Semiconductor device having strings

Abstract

A semiconductor device includes a peripheral circuit structure and cell structures stacked on the peripheral circuit structure, the cell structures including gate electrodes spaced apart from each other in a vertical direction; a channel structure disposed within a channel hole extending in a vertical direction by passing through the gate electrode, the channel structure including a channel layer and a back gate electrode spaced apart from the channel layer, and including a first end portion disposed adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion; a common source layer connected to the channel layer at a second end of the channel structure; an upper insulating layer on the common source layer; and a back gate contact disposed within a first back contact hole passing through the upper insulating layer and the common source layer, and connected to the back gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0149280 filed on November 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having memory strings arranged in a vertical direction. Background Art

[0004] Semiconductor devices capable of storing high-capacity data are used in electronic systems with data storage. In a method of increasing the data storage capacity of a semiconductor device, the semiconductor device includes three-dimensionally arranged storage cells instead of two-dimensionally arranged storage cells. In addition, in some semiconductor devices, a portion of the semiconductor device is formed on a first substrate, the other portion of the semiconductor device is formed on a second substrate, and the first substrate and the second substrate are bonded to each other. Summary of the invention

[0005] The present disclosure provides a semiconductor device having high operating characteristics and improved integration.

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a peripheral circuit structure and a unit structure stacked on the peripheral circuit structure, wherein the unit structure includes: gate electrodes spaced apart from each other in a vertical direction; a channel structure arranged in a channel hole extending in a vertical direction by passing through the gate electrode, the channel structure including a channel layer and a back gate electrode spaced apart from the channel layer, and including a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion; a common source layer arranged to be connected to the channel layer at the second end portion of the channel structure; an upper insulating layer on the common source layer; and a back gate contact portion arranged in a first back contact hole passing through the upper insulating layer and the common source layer, and connected to the back gate electrode.

[0007] According to another aspect of the present disclosure, a semiconductor device includes: a peripheral circuit structure and a unit structure stacked on the peripheral circuit structure, wherein the unit structure includes: gate electrodes spaced apart from each other in a vertical direction; a channel structure arranged in a channel hole extending in a vertical direction by passing through the gate electrode, the channel structure including a channel layer and a back gate electrode spaced apart from the channel layer, and including a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion; a bit line arranged adjacent to the first end portion of the channel structure and electrically connected to the channel layer; a common source layer arranged adjacent to the second end portion of the channel structure and connected to the channel layer; a back gate contact portion arranged adjacent to the second end portion of the channel structure and connected to the back gate electrode; and a first back wiring layer arranged on the back gate contact portion and electrically connected to the back gate contact portion.

[0008] According to another aspect of the present disclosure, a semiconductor device includes: a peripheral circuit structure including a substrate and a peripheral circuit transistor arranged on the substrate; gate electrodes spaced apart from each other in a vertical direction on the peripheral circuit structure; a channel layer arranged in a channel hole extending in a vertical direction by passing through the gate electrode; a back gate electrode arranged in the channel hole and electrically insulated from the channel layer by an insulating liner; a bit line arranged adjacent to a first end of the channel layer and electrically connected to the channel layer; a common source layer arranged adjacent to a second end of the channel layer and connected to the channel layer, the second end being opposite to the first end; an upper insulating layer disposed at the common source; a back gate contact arranged adjacent to the second end of the channel layer and connected to the back gate electrode by passing through the upper insulating layer and the common source layer; a common source contact connected to the common source layer by passing through the upper insulating layer; a first spacer arranged between the upper insulating layer and the back gate contact and between the common source layer and the back gate contact; a second spacer arranged between the upper insulating layer and the common source contact; a first back wiring layer arranged on the upper insulating layer and electrically connected to the back gate contact; and a second back wiring layer spaced apart from the first back wiring layer on the upper insulating layer and electrically connected to the common source contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of an example of a semiconductor device.

[0010] Figure 2 is a circuit diagram showing an example of a memory cell array.

[0011] Figure 3 is a perspective view showing representative components of an example of a semiconductor device.

[0012] Figure 4 is a plan layout diagram of an example of a semiconductor device.

[0013] Figure 5 yes Figure 4 An enlarged layout diagram of portion A.

[0014] Figure 6 is along Figure 5 A cross-sectional view taken along line BB'.

[0015] Figure 7 yes Figure 6 An enlarged view of a portion of CX1.

[0016] Figure 8 yes Figure 6 An example layout diagram of a common source contact and a back gate contact.

[0017] Fig. 9 is a layout diagram showing an example of a semiconductor device.

[0018] Fig.10 is a cross-sectional view of an example of a semiconductor device.

[0019] Fig.11 yes Fig.10 An enlarged view of a portion of CX1.

[0020] Fig.12 is a cross-sectional view of an example of a semiconductor device.

[0021] Fig.13 yes Fig.12 An enlarged view of a portion of CX1.

[0022] Fig.14 is a cross-sectional view of an example of a semiconductor device.

[0023] Fig.15 is a cross-sectional view of an example of a semiconductor device.

[0024] Figures 16 to 29 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0025] Figure 30 to Figure 33 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0026] Figure 34 to Figure 36 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0027] Fig.37 is a diagram schematically showing an example of a data storage system including a semiconductor device.

[0028] Fig.38 is a perspective view schematically showing an example of a data storage system including a semiconductor device.

[0029] Fig.39 is a cross-sectional view schematically showing an example of a semiconductor package. DETAILED DESCRIPTION

[0030] Figure 1 is a block diagram of an example of a semiconductor device 10 .

[0031] refer to Figure 1 , the semiconductor device 10 includes a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, ..., and BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, ..., and BLKn may be connected to the peripheral circuit 30 through a bit line BL, a word line WL, a string selection line SSL, and a ground selection line GSL.

[0032] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output circuit 36, and a control logic 38. Figure 1 Although not shown, the peripheral circuit 30 may further include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, and the like.

[0033] The memory cell array 20 may be connected to the page buffer 34 through the bit line BL, and may be connected to the row decoder 32 through the word line WL, the string selection line SSL and the ground selection line GSL. In the memory cell array 20, each of the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, ... and BLKn may be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected to a plurality of word lines WL vertically stacked on a substrate.

[0034] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 10 , and may transmit and receive data DATA to and from a device outside the semiconductor device 10 .

[0035] The row decoder 32 may select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKn in response to an address ADDR from the outside, and may select a word line WL, a string selection line SSL, and a ground selection line GSL of the selected memory cell block. The row decoder 32 may send a voltage for performing a storage operation to the word line WL of the selected memory cell block.

[0036] The page buffer 34 may be connected to the memory cell array 20 through the bit line BL. The page buffer 34 may operate as a write driver during a program operation to apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20, and may operate as a sense amplifier during a read operation to detect the data DATA stored in the memory cell array 20. The page buffer 34 may operate according to the control signal PCTL provided by the control logic 38.

[0037] The data input / output circuit 36 ​​may be connected to the page buffer 34 through the data line DL. The data input / output circuit 36 ​​may receive data DATA from a memory controller (not shown) during a program operation, and may provide the program data DATA to the page buffer 34 based on the column address C_ADDR provided by the control logic 38. During a read operation, the data input / output circuit 36 ​​may provide the read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided by the control logic 38.

[0038] The data input / output circuit 36 ​​may send an input address or command to the control logic 38 or the row decoder 32. The peripheral circuit 30 may further include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0039] The control logic 38 may receive a command CMD and a control signal CTRL from a memory controller. The control logic 38 may provide a row address R_ADDR to the row decoder 32 and a column address C_ADDR to the data input / output circuit 36. The control logic 38 may generate various types of internal control signals used within the semiconductor device 10 in response to the control signal CTRL. For example, the control logic 38 may adjust the voltage levels provided to the word lines WL and the bit lines BL when performing a memory operation (e.g., a program operation or an erase operation).

[0040] Figure 2 is a circuit diagram showing an example of a memory cell array MCA.

[0041] refer to Figure 2 , the memory cell array MCA may include memory cell strings MCS11 to MCS33 , word lines WL1 to WL8 , ground selection lines GSL1 to GSL3 , string selection lines SSL1 to SSL3 , and a common source line CSL.

[0042] The memory cell strings MCS11, MCS21 and MCS31 may be arranged between the first bit line BL1, the first back gate line BGL1 and the common source line CSL. The memory cell strings MCS12, MCS22 and MCS32 may be arranged between the second bit line BL2, the second back gate line BGL2 and the common source line CSL. The memory cell strings MCS13, MCS23 and MCS33 may be arranged between the third bit line BL3, the third back gate line BGL3 and the common source line CSL. Each of the memory cell strings (e.g., MCS11) may include a string selection transistor SST, a plurality of memory cells MCT1 to MCT8 and a ground selection transistor GST, which are connected in series.

[0043] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MCT1 to MCT8 may be connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1 to BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0044] exist Figure 2 In the example of , word lines (eg, WL1, etc.) of the same height may be commonly connected to each other, string selection lines SSL1 to SSL3 may be separated from each other, and ground selection lines GSL1 to GSL3 may also be separated from each other. Figure 2 It is shown that three string selection lines (eg, SSL1 to SSL3) share a word line at the same height, but the present disclosure is not limited thereto. For example, two string selection lines may share a word line at the same height. As another example, four string selection lines may share a word line at the same height.

[0045] Figure 3 is a perspective view showing representative components of an example of the semiconductor device 100 . Figure 4 is a plan layout diagram of the semiconductor device 100, and Figure 5 yes Figure 4 An enlarged layout diagram of portion A. Figure 6 is along Figure 5 A cross-sectional view taken along line BB'. Figure 7 yes Figure 6 An enlarged view of a portion of CX1, and Figure 8 yes Figure 6 An example layout diagram of a common source contact and a back gate contact.

[0046] refer to Figures 3 to 8 , the semiconductor device 100 may include a cell structure CS and a peripheral circuit structure PS overlapping each other in a vertical direction Z. The cell structure CS may include a reference Figure 1The memory cell array 20 described above and the peripheral circuit structure PS may include reference Figure 1 The peripheral circuit 30 is described.

[0047] The cell structure CS may include a plurality of memory cell blocks BLK1 , BLK2 , . . . , and BLKn. Each of the plurality of memory cell blocks BLK1 , BLK2 , . . . , and BLKn may include three-dimensionally arranged memory cells.

[0048] The peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 arranged on the substrate 50. An active region AC may be defined in the substrate 50 by a device isolation layer 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. Each of the plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and a source / drain region 62 arranged in a portion of the substrate 50 on both sides of the peripheral circuit gate 60G. In the embodiments shown herein, the phrase "source / drain region" may be understood to mean a source terminal region and / or a drain terminal region of a transistor.

[0049] The substrate 50 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium. The substrate 50 may also be provided as a bulk wafer or an epitaxial layer. In an embodiment, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0050] The peripheral circuit wiring structure 70 includes a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wiring layers 74. An interlayer insulating layer 80 covering the peripheral circuit transistor 60TR and the peripheral circuit wiring structure 70 may be arranged on the substrate 50. The plurality of peripheral circuit wiring layers 74 may have a multilayer structure including a plurality of metal layers arranged at different vertical levels. A connection pad 90 may be arranged on the interlayer insulating layer 80, and the peripheral circuit structure PS and the cell structure CS may be electrically connected and bonded to each other through the connection pad 90.

[0051] The cell structure CS may include a cell region MCR, a connection region CON, and a peripheral circuit connection region PRC. The cell region MCR may be a region in which a memory cell block BLK including a plurality of memory cell strings extending in a vertical direction Z is arranged. A common source layer 110, a plurality of gate electrodes 120, and a channel structure 130 may be arranged in the cell region MCR, and the channel structure 130 extends in the vertical direction Z and is connected to the common source layer 110 by passing through the gate electrode 120. An extension portion 120E and a pad portion 120P connected to the plurality of gate electrodes 120, and a first plug CP1 electrically connected to the pad portion 120P by passing through the extension portion 120E and the pad portion 120P may be arranged in the connection region CON. A second plug CP2 extending in the vertical direction Z and electrically connected to the peripheral circuit wiring structure 70 may be arranged in the peripheral circuit connection region PCR.

[0052] The cell structure CS may include a first surface CS_1 connected to the peripheral circuit structure PS and a second surface CS_2 opposite to the first surface CS_1 . Figure 6 It is shown that the first surface CS_1 of the unit structure CS is arranged at the lower side of the unit structure CS, and the second surface CS_2 of the unit structure CS is arranged at the upper side of the unit structure CS. Here, for convenience, as shown in the figure, when the component is arranged close to the first surface CS_1 of the unit structure CS, the component is arranged at a lower vertical level (e.g., the lower side of the unit structure CS), and when the component is arranged close to the second surface CS_2 of the unit structure CS, the component is arranged at a higher vertical level (e.g., the upper side of the unit structure CS).

[0053] The gate electrodes 120 may be arranged spaced apart from each other along the vertical direction Z in the cell region MCR, and the gate electrodes 120 may be arranged alternately with the mold insulating layer 122. The gate electrode 120 may extend to the connection region CON, and the portion of the gate electrode 120 arranged in the connection region CON may be referred to as an extension 120E. The extension 120E may have a gradually increasing horizontal length in a direction toward the second surface CS_2 of the cell structure CS (e.g., an upward direction in the figure). The extension 120E may have a stepped shape, and the pad portion 120P may be connected to the end of the extension 120E. The pad portion 120P may have a greater thickness in the vertical direction Z than the extension 120E.

[0054] like Figure 7As shown, each of the gate electrodes 120 may include a buried conductive layer 120A and a conductive barrier layer 120B surrounding the upper surface, the lower surface, and the side surface of the buried conductive layer 120A. For example, the buried conductive layer 120A may include a metal (e.g., tungsten, nickel, cobalt, or tantalum), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide), doped polysilicon, or a combination thereof. In some embodiments, the conductive barrier layer 120B may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0055] In some embodiments, the gate electrode 120 may correspond to a Figure 2 The memory cell strings MCS11 to MCS33 of the present invention may include ground selection lines GSL1 to GSL3, word lines WL1 to WL8, and at least one string selection line SSL1 to SSL3. For example, the uppermost gate electrode 120 may be used as the ground selection lines GSL1 to GSL3, the lowermost two gate electrodes 120 may be used as the string selection lines SSL1 to SSL3, and the remaining gate electrodes 120 may be used as the word lines WL1 to WL8. Therefore, a memory cell string MCS11 to MCS33 in which the ground selection transistors GST, the string selection transistors SST, and the memory cell transistors MCT1 to MCT8 therebetween are connected in series may be provided. In some embodiments, at least one of the gate electrodes 120 may be used as a dummy word line, but is not limited thereto.

[0056] The stack isolation insulating layer WLI may be arranged within the stack isolation opening WLH extending in the vertical direction Z by passing through the gate electrode 120 and the mold insulation layer 122. The stack isolation insulating layer WLI may have an upper surface arranged at a higher vertical level than the uppermost gate electrode 120 and may protrude upward from the uppermost gate electrode 120. In some embodiments, the gate electrodes 120 arranged between a pair of stack isolation openings WLH may constitute one block BLK. In addition, within one block BLK, at least one gate electrode 120 (for example, the lowermost gate electrode 120) may be separated into two gate electrodes 120 by a string isolation opening SSLH. The string isolation insulating layer SSLI may be arranged within the string isolation opening SSLH.

[0057] The stacked insulating layer 124 may be arranged to surround the gate electrode 120, the extension portion 120E, and the pad portion 120P in the connection region CON and the peripheral circuit connection region PCR. From a plan view, the stacked insulating layer 124 may be arranged to surround the gate electrode 120, and may have an upper surface arranged at the same level as the uppermost gate electrode 120 in the peripheral circuit connection region PCR.

[0058] The channel structure 130 may be arranged in a channel hole 130H extending in a vertical direction Z by passing through the gate electrode 120 and the mold insulating layer 122. The channel structure 130 may include a gate insulating layer 132, a channel layer 134, an insulating liner 136, a drain region 138, and a back gate electrode BG. The gate insulating layer 132, the channel layer 134, the insulating liner 136, and the back gate electrode BG may be sequentially arranged on the inner wall of the channel hole 130H.

[0059] The channel structure 130 may include a first end portion 130x disposed adjacent to the peripheral circuit structure PS and a second end portion 130y opposite to the first end portion 130x. In some embodiments, the channel structure 130 may have an inclined sidewall such that a width of the first end portion 130x is greater than a width of the second end portion 130y.

[0060] A drain region 138 may be arranged at a first end portion 130x of the channel structure 130, and the drain region 138 is electrically connected to the channel layer 134. The drain region 138 may be connected to a bit line contact BLC, and the channel layer 134 may be electrically connected to the bit line BL through the drain region 138 and the bit line contact BLC. At a second end portion 130y of the channel structure 130, a portion of a side surface of the channel layer 134 may not be covered by the gate insulating layer 132, and the common source layer 110 may be connected to a portion of the side surface of the channel layer 134. The back gate electrode BG may be connected to the back gate contact 144 at the second end portion 130y of the channel structure 130.

[0061] like Figure 7 As shown, the gate insulating layer 132 may have a structure including a tunnel dielectric layer 132A, a charge storage layer 132B, and a blocking dielectric layer 132C sequentially on the outer wall of the channel layer 134. The relative thicknesses of the tunnel dielectric layer 132A, the charge storage layer 132B, and the blocking dielectric layer 132C constituting the gate insulating layer 132 are not limited to Figure 7 The relative thicknesses are shown and may be modified in various ways.

[0062] The tunnel dielectric layer 132A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like.

[0063] The charge storage layer 132B may be a region storing electrons passing through the tunnel dielectric layer 132A from the channel layer 134, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer 132C may include silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0064] In some embodiments, the charge storage layer 132B may include a ferroelectric dielectric material. In this case, the charge storage layer 132B may include a metal oxide having ferroelectric material properties. For example, the charge storage layer 132B may include a ferroelectric material that is capable of storing data through a hysteresis behavior caused by a voltage applied to the charge storage layer 132B. In some embodiments, the charge storage layer 132B may include at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0065] The back gate electrode BG may extend in the vertical direction Z within the channel hole 130H. The back gate electrode BG may have a vertical column shape, and the insulating liner 136 may be arranged on the sidewall of the back gate electrode BG. The back gate electrode BG may be electrically insulated from the channel layer 134 by the insulating liner 136 located between the back gate electrode BG and the channel layer 134. At the first end 130x of the channel structure 130, the bottom surface of the back gate electrode BG may be covered by the insulating liner 136, and the insulating liner 136 may be located between the bottom surface of the back gate electrode BG and the drain region 138. At the second end 130y of the channel structure 130, the upper surface of the back gate electrode BG may not be covered by the insulating liner 136, and the back gate contact 144 may be arranged on the upper surface of the back gate electrode BG.

[0066] In some embodiments, the back gate electrode BG may include a doped polysilicon layer, but the material selection is not limited thereto. Figure 2 When the memory cells MCT1 to MCT8 perform data writing, reading or erasing operations, the Figure 2 The back gate lines BGL1 to BGL3 apply a specific voltage (or signal) to the back gate electrode BG.

[0067] The etch stop layer 112 may be disposed on the uppermost gate electrode 120, and the etch stop layer 112 may include polysilicon. In some embodiments, the etch stop layer 112 may be omitted.

[0068] The common source layer 110 may be conformally formed on the etch stop layer 112 to be connected to the second end 130y of the channel structure 130 and to cover the upper surface of the stacked isolation insulating layer WLI. From a plan view, the common source layer 110 may be arranged above the entire area of ​​the cell region MCR. The portion of the common source layer 110 in contact with the etch stop layer 112 may have an upper surface that is arranged at a different vertical level from the portion of the common source layer 110 in contact with the second end 130y of the channel structure 130. In addition, in some embodiments, the portion of the common source layer 110 in contact with the stacked isolation insulating layer WLI may have an upper surface that is arranged at a different vertical level from the portion of the common source layer 110 in contact with the second end 130y of the channel structure 130.

[0069] In some embodiments, Figure 7 As shown, the common source layer 110 may conformally cover the upper surface of the channel layer 134 and the upper surface of the gate insulating layer 132. For example, the gate insulating layer 132 may be arranged at a level lower than the upper surface of the channel layer 134, so that the upper surface and part of the sidewall of the channel layer 134 may be covered by the common source layer 110 to ensure sufficient contact area between the channel layer 134 and the common source layer 110. In some embodiments, as Figure 7 As shown, the upper surface of the charge storage layer 132B can be arranged at the same level as the upper surfaces of the tunneling dielectric layer 132A and the blocking dielectric layer 132C, so that the gate insulating layer 132 can have a flat level. In some embodiments, the charge storage layer 132B can be arranged so that its upper surface protrudes more upward than the upper surfaces of the tunneling dielectric layer 132A and the blocking dielectric layer 132C.

[0070] In some embodiments, the first end portion CP1x of the first plug CP1 may be disposed at a position adjacent to the peripheral circuit structure PS, and the second portion CP1y of the first plug CP1 may be disposed opposite to the first end portion CP1x. The first plug CP1 may have an inclined sidewall such that the width of the first end portion CP1x is greater than the width of the second end portion CP1y.

[0071] In some embodiments, the first plug CP1 may include a metal such as tungsten, nickel, cobalt or tantalum; a metal nitride such as titanium nitride, tantalum nitride or tungsten nitride; a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide or tantalum silicide; doped polysilicon; or a combination thereof.

[0072] In the peripheral circuit connection region PRC, the second plug CP2 may be arranged to pass through the stacked insulating layer 124. The shape and constituent material of the second plug CP2 may be similar to those of the first plug CP1.

[0073] The connection via 152, the connection wiring layer 154, and the interlayer insulating layer 156 surrounding the connection via 152 and the connection wiring layer 154 may be arranged between the stacked insulating layer 124 and the peripheral circuit structure PS. The connection via 152 and the connection wiring layer 154 may constitute a multilayer to be arranged at a plurality of vertical levels, and the bit line BL, the first plug CP1, and the second plug CP2 may be electrically connected to the peripheral circuit structure PS through the connection pad 90.

[0074] The upper insulating layer 142 may be disposed on the common source layer 110. The upper insulating layer 142 may have a flat upper surface in the cell region MCR and the connection region CON. The upper insulating layer 142 may be disposed to cover an upper surface of the common source layer 110 and an upper surface of the first plug CP1.

[0075] The back gate contact 144 may be disposed in a first back contact hole 144H passing through the upper insulating layer 142 and the common source layer 110. The back gate contact 144 may be disposed at a position vertically overlapping each channel structure 130. Figure 8 As shown, the back gate contact 144 may be arranged to be offset in the first horizontal direction X and the second horizontal direction Y. The spacer 148 may be arranged on the inner wall of the first back contact hole 144H, and the spacer 148 may surround the sidewall of the back gate contact 144. The sidewall of the back gate contact 144 may be surrounded by the spacer 148, and thus, the back gate contact 144 may be electrically isolated from the common source layer 110.

[0076] like Figure 7 As shown, the bottom of the first back contact hole 144H may extend into the second end 130y of the channel structure 130, and the bottom of the first back contact hole 144H may be surrounded by the end of the channel layer 134. For example, at the bottom of the first back contact hole 144H, the bottom surface of the back gate contact 144 may contact the upper surface of the back gate electrode BG, and the bottom of the back gate contact 144 may be surrounded by the channel layer 134, with the spacer 148 interposed between the back gate contact 144 and the channel layer 134. The upper surface of the back gate contact 144 may be arranged at the same vertical level as the upper surface of the upper insulating layer 142.

[0077] The common source contact 146 may be arranged in a second back contact hole 146H passing through the upper insulating layer 142. The second back contact hole 146H may pass through the upper insulating layer 142 but not through the common source layer 110, and the upper surface of the common source layer 110 may be arranged at the bottom of the second back contact hole 146H. The second back contact hole 146H may be arranged to be spaced apart from the first back contact hole 144H in the horizontal direction, for example, the common source contact 146 may be arranged at a position vertically overlapping with the stack isolation opening WLH or the stack isolation insulating layer WLI. For example, as Figure 8 As shown, the common source contacts 146 may be arranged in a row along the first horizontal direction X. As shown in FIG.

[0078] Spacers 148 may be disposed on inner walls of second back contact holes 146H, and spacers 148 may surround sidewalls of common source contacts 146. In some embodiments, an upper surface of common source contacts 146 may be disposed at the same vertical level as an upper surface of upper insulating layer 142.

[0079] In some embodiments, a portion of the spacer 148 arranged on the inner wall of the second back contact hole 146H can be formed in the same process as a portion of the spacer 148 arranged on the inner wall of the first back contact hole 144H, and the common source contact 146 arranged in the second back contact hole 146H can be formed in the same process as the back gate contact 144 arranged in the first back contact hole 144H.

[0080] In some embodiments, the back gate contact 144 and the common source contact 146 may include a metal, such as tungsten, nickel, cobalt, or tantalum; a metal nitride, such as titanium nitride, tantalum nitride, or tungsten nitride; a metal silicide, such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide; or a combination thereof. In some embodiments, the spacer 148 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0081] A first backside wiring layer 164 and a second backside wiring layer 166 may be disposed on the upper insulating layer 142. The first backside wiring layer 164 may be electrically connected to the back gate contact 144, and the second backside wiring layer 166 may be disposed to be spaced apart from the first backside wiring layer 164 in a horizontal direction and may be electrically connected to the common source contact 146. For example, Figure 8As shown, the second backside wiring layer 166 may be located at a position vertically overlapping with the stack isolation opening WLH, and may be electrically connected to the common source layer 110 through the common source contact 146. The first backside wiring layer 164 may be arranged in a region between two adjacent stack isolation openings WLH, for example, at a position vertically overlapping with the channel structure 130. The first backside wiring layer 164 may be electrically connected in common to the back gate electrodes BG of the plurality of channel structures 130 arranged between the two adjacent stack isolation openings WLH (or between the two adjacent stack isolation insulating layers WLI).

[0082] The passivation layer 168 may be disposed on the first back side wiring layer 164 and the second back side wiring layer 166, and the opening OP of the passivation layer 168 may be disposed to expose at least one of a portion of the upper surface of the first back side wiring layer 164 and a portion of the upper surface of the second back side wiring layer 166. The first back side wiring layer 164 may be configured to apply a back gate voltage from an external connection terminal to the back gate electrode BG in the channel structure 130 through the back gate contact 144, and / or the first back side wiring layer 164 may be configured to apply a back gate voltage from an external connection terminal to the back gate electrode BG in the channel structure 130 through the back gate contact 144. Figure 5 The second plug CP2 is electrically connected to the peripheral circuit structure PS. The second back wiring layer 166 may be configured to apply a common source voltage to the common source layer 110 from an external connection terminal through the common source contact 146, and / or the second back wiring layer 166 may be configured to apply a common source voltage to the common source layer 110 through the common source contact 146 from the external connection terminal. Figure 5 The second plug CP2 is electrically connected to the peripheral circuit structure PS.

[0083] In some embodiments, a back gate electrode BG may be included in the channel structure 130. For example, when the back gate electrode BG is included in the channel structure 130, for a programming operation, a back gate voltage may be applied to the back gate electrode BG, a programming voltage may be applied to a selected word line, and a relatively low pass voltage (e.g., 0V) may be applied to an unselected word line. Therefore, in the disclosed semiconductor device, when a relatively high pass voltage is applied to an unselected word line, interference with data storage in an unselected memory cell may be prevented or minimized.

[0084] In addition, the back gate contact 144 and the first back wiring layer 164 for providing electrical connection to the back gate electrode BG may be disposed on the second surface CS_2 of the cell structure CS, and therefore, the area and degree of freedom of arrangement of the back gate contact 144 and the first back wiring layer 164 may be increased. In addition, the back gate contact 144 and the first back wiring layer 164 may be formed simultaneously in the manufacturing process for forming the common source contact 146 and the second back wiring layer 166, respectively, and therefore, the process for forming the back gate contact 144 and the first back wiring layer 164 may not be increased.

[0085] Fig. 9is a layout diagram showing an example of a semiconductor device 100A.

[0086] refer to Fig. 9 , the second backside wiring layer 166 may be arranged at a position vertically overlapping with the stack isolation opening WLH, and the second backside wiring layer 166 may have a linear planar shape extending along the first horizontal direction X. The first backside wiring layer 164 may be arranged in an area between two adjacent stack isolation openings WLH, for example, Figure 6 The common source contact 146 may include a first group 146_1 and a second group 146_2, the first group 146_1 being arranged in a row in the first horizontal direction X at a position vertically overlapping with the second backside wiring layer 166, and the second group 146_2 being spaced apart from the first group 146_1 in the second horizontal direction Y and arranged in a row in the first horizontal direction X.

[0087] In some embodiments, the common source contact 146 may further include an additional group spaced apart from the first group 146_1 and the second group 146_2 in the second horizontal direction Y and arranged in a row in the first horizontal direction X at a position vertically overlapping one second back-side wiring layer 166 .

[0088] Fig.10 is a cross-sectional view of an example of a semiconductor device 100B. Fig.11 yes Fig.10 An enlarged view of a portion of CX1.

[0089] refer to Fig.10 and Fig.11 , a portion of the channel layer 134 has a shape extending in a horizontal direction at the second end portion 130y of the channel structure 130. For example, an extension portion 134T of the channel layer 134 disposed at a higher vertical level than the etch stop layer 112 may have a greater width than a portion of the channel layer 134 disposed at a lower vertical level than the etch stop layer 112 (e.g., a portion of the channel layer 134 disposed at the same vertical level as the gate electrode 120 and surrounded by the gate electrode 120). The insulating liner 136 may be formed to have a conformal thickness within the extension portion 134T of the channel layer 134.

[0090] A portion of the back gate electrode BG may have a shape extending in the horizontal direction at the second end portion 130y of the channel structure 130. For example, the extension portion BGT of the back gate electrode BG disposed at a vertical level higher than the etch stop layer 112 may have a greater width than a portion of the back gate electrode BG disposed at a vertical level lower than the etch stop layer 112.

[0091] The back gate contact 144 can be arranged on the upper surface of the extension portion BGT of the back gate electrode BG, and therefore, the back gate contact 144 can be formed to have a relatively large width and / or a relatively large contact area between the back gate contact 144 and the upper surface of the extension portion BGT of the back gate electrode BG can be ensured.

[0092] A portion of the stacked isolation insulating layer WLI disposed at a higher vertical level than the etch stop layer 112 may have a shape extending in a horizontal direction. For example, an extension portion WLIT of the stacked isolation insulating layer WLI disposed at a higher vertical level than the etch stop layer 112 may have a greater width than a portion of the stacked isolation insulating layer WLI disposed at a lower vertical level than the etch stop layer 112.

[0093] The second end portion CP1y of the first plug CP1 may further include a landing pad portion CP1P. The landing pad portion CP1P may have a shape extending in a horizontal direction to have a greater width than a portion of the first plug CP1 surrounded by the gate electrode 120.

[0094] Fig.12 is a cross-sectional view of an example of a semiconductor device 100C. Fig.13 yes Fig.12 An enlarged view of a portion of CX1.

[0095] refer to Fig.12 and Fig.13 , the stacked isolation insulating layer WLI has an upper surface arranged at a level lower than the second end portion 130y of the channel structure 130. For example, the upper surface of the stacked isolation insulating layer WLI may be arranged at a vertical level higher than the etch stop layer 112, and may be arranged at a vertical level lower than an upper surface of the channel layer 134 of the channel structure 130 or an upper surface of the back gate electrode BG.

[0096] Fig.14 is a cross-sectional view of an example of a semiconductor device 100D.

[0097] refer to Fig.14 , spacer 148 is disposed on the inner wall of first back contact hole 144H, but spacer 148 may not be disposed on the inner wall of second back contact hole 146H. Common source contact 146 may be disposed on the inner wall of second back contact hole 146H, and the sidewall of common source contact 146 may be surrounded by upper insulating layer 142 and may be in contact with upper insulating layer 142.

[0098] Fig.15 is a cross-sectional view of an example of a semiconductor device 100E.

[0099] refer to Fig.15, the upper conductive layer 110M may also be arranged on the upper surface of the common source layer 110. The upper conductive layer 110M may include a metal nitride, such as titanium nitride, tantalum nitride, or tungsten nitride; a metal, such as tungsten, molybdenum, chromium, nickel, cobalt, or tantalum; a metal silicide, such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide; or a combination thereof. In some embodiments, the upper conductive layer 110M may be formed as a stacked structure of two or more different material layers.

[0100] The first back contact hole 144H may extend in a vertical direction by passing through the upper insulating layer 142, the upper conductive layer 110M, and the common source layer 110, the spacer 148 may be arranged on the inner wall of the first back contact hole 144H, and the back gate contact 144 may be arranged inside the first back contact hole 144H. The back gate contact 144 may be electrically isolated from the upper conductive layer 110M and the common source layer 110 by the spacer 148.

[0101] Figures 16 to 29 is a cross-sectional view illustrating an example of a method of manufacturing the semiconductor device 100 .

[0102] refer to Fig.16 , a buffer insulating layer 220 is formed on the unit substrate 210 , and an etch stop layer 112 may be formed on the buffer insulating layer 220 .

[0103] In some embodiments, the unit substrate 210 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The buffer insulating layer 220 may be formed by using silicon oxide. In some embodiments, the etch stop layer 112 may be formed by using polysilicon.

[0104] refer to Fig.17 , the gate electrode 120 and the mold insulating layer 122 are alternately formed in the cell region MCR and the connection region CON, and the extension portion 120E and the pad portion 120P connected to the gate electrode 120 may be formed in the connection region CON. In addition, a channel structure 130 extending in a vertical direction Z by passing through the gate electrode 120 and a bit line BL connected to the channel structure 130 may be formed in the cell region MCR. In addition, a first plug CP1 passing through the extension portion 120E and the pad portion 120P may be formed in the connection region CON, and a first plug CP1 may be formed in the connection region CON. Figure 4 The peripheral circuit connection region PRC is formed through the stacked insulating layer 124. Figure 5 The second plug CP2.

[0105] In some embodiments, during the formation of the gate electrode 120 and the pad portion 120P, a mold stack may be formed in the cell region MCR and the connection region CON, the mold stack alternately including a sacrificial layer (not shown) on the etch stop layer 112 and a mold insulating layer 122. A portion of the mold stack may be patterned in the connection region CON to form a preliminary pad portion (not shown), and then the sacrificial layer and the preliminary pad portion may be removed. The gate electrode 120 and the pad portion 120P may be formed in the space where the sacrificial layer and the preliminary pad portion are removed.

[0106] In some embodiments, during the process of forming the channel structure 130, a channel hole 130H passing through the mold stack can be formed in the unit region MCR, a gate insulation layer 132, a channel layer 134, an insulating liner 136 and a back gate electrode BG can be sequentially formed on the inner wall of the channel hole 130H, and a drain region 138 can be formed at the entrance of the channel hole 130H.

[0107] In some embodiments, the back gate electrode BG may be surrounded by an insulating liner 136 to be electrically insulated from the channel layer 134 and the drain region 138. In some embodiments, a liner portion of the insulating liner 136 covering the channel layer 134 may be first formed on the sidewall and bottom of the channel hole 130H, and then a back gate electrode BG filling the remaining portion of the channel hole 130H may be formed on the portion of the insulating liner 136, a portion of the back gate electrode BG disposed at the entrance of the channel hole 130H may be removed, and another portion of the insulating liner 136 may be formed on the upper surface of the back gate electrode BG. Subsequently, the drain region 138 filling the entrance of the channel hole 130H may be formed on the other portion of the insulating liner 136.

[0108] The first end portion 130 x of the channel structure 130 may be disposed at a higher vertical level than the second end portion 130 y , and the second end portion 130 y may be formed to pass through the etch stop layer 112 and extend into the unit substrate 210 .

[0109] In some embodiments, in the process of forming the first plug CP1, the first end CP1x of the first plug CP1 may be formed to have a greater width than the second end CP1y, and the second end CP1y of the first plug CP1 may be formed to have a greater height to pass through the etch stop layer 112 and extend into the unit substrate 210. In some embodiments, a first plug hole CP1H passing through the mold stack may be formed in the connection region CON, a portion of the sacrificial layer exposed on the sidewall of the first plug hole CP1H may be removed by lateral etching, and an insulating pattern 126 may be formed in the portion where the sacrificial layer is removed. Subsequently, the first plug CP1 may be formed in the first plug hole CP1H.

[0110] refer to Fig.18 A connection via 152 electrically connected to the bit line BL and the first plug CP1, a connection wiring layer 154, and an interlayer insulating layer 156 are formed. A connection pad 90_U may be formed on an upper surface of the interlayer insulating layer 156.

[0111] refer to Fig.19 , providing a peripheral circuit structure PS. The peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 arranged on the substrate 50. The active region AC may be defined by the device isolation layer 52 in the substrate 50, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. Each of the plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and a source / drain region 62 arranged in a portion of the substrate 50 on both sides of the peripheral circuit gate 60G.

[0112] Subsequently, the peripheral circuit structure PS may be attached to the cell structure CS. The peripheral circuit structure PS and the cell structure CS may be attached to each other by a metal oxide hybrid bonding method through the connection pad 90 and the interlayer insulating layers 80 and 156, but the method of attaching the peripheral circuit structure PS and the cell structure CS is not limited thereto.

[0113] Subsequently, the structure in which the peripheral circuit structure PS and the cell structure CS are attached to each other may be turned over so that the unit substrate 210 faces upward.

[0114] refer to Fig. 20 , you can remove Fig.18 The unit substrate 210 may be removed by a grinding process and a subsequent etching process, and the unit substrate 210 may be exposed. Fig.18 A buffer insulating layer 220 is formed.

[0115] Subsequently, the buffer insulating layer 220 may be removed and the upper surface of the etch stop layer 112 may be exposed. The buffer insulating layer 220 may be removed and thus, the second end 130y of the channel structure 130 and the second end CP1y of the first plug CP1 may protrude from the upper surface of the etch stop layer 112.

[0116] The unit substrate 210 and the buffer insulating layer 220 may be removed, and thus, an upper side of the stacked isolation insulating layer WLI may also be exposed and protrude above the etch stop layer 112 .

[0117] refer to Fig.21, a portion of the gate insulating layer 132 exposed at the second end portion 130y of the channel structure 130 may be removed to expose an upper surface of the channel layer 134. The process of removing the gate insulating layer 132 may be performed such that an upper surface of the etch stop layer 112 is exposed in the process of removing the gate insulating layer 132. In some embodiments, an upper side 132 of the gate insulating layer may be removed such that the gate insulating layer 132 is disposed at a level lower than an upper surface of the channel layer 134 and portions of an upper surface and sidewalls of the channel layer 134 are exposed.

[0118] refer to Fig. 22 , a common source layer 110 may be formed on the cell region MCR, the connection region CON, and the peripheral circuit connection region PRC. The common source layer 110 may be formed by using polysilicon. For example, the common source layer 110 may be formed by using polysilicon doped with n-type impurities. In the cell region MCR, the common source layer 110 may be conformally formed on the exposed upper surfaces of the etch stop layer 112 and the channel layer 134. In the connection region CON, the common source layer 110 may cover the second end portion CP1y of the first plug CP1.

[0119] refer to Fig.23 , portions of the common source layer 110 disposed in the connection region CON and the peripheral circuit connection region PRC and portions of the etch stop layer 112 disposed in the connection region CON and the peripheral circuit connection region PRC may be removed.

[0120] In some embodiments, a mask pattern may be formed on the common source layer 110 in the cell region MCR, and portions of the common source layer 110 and the etch stop layer 112 arranged in the connection region CON and the peripheral circuit connection region PRC may be removed by using the mask pattern as an etching mask. The common source layer 110 and the etch stop layer 112 arranged in the connection region CON and the peripheral circuit connection region PRC may be removed so that the second end portion CP1y of the first plug CP1 and the uppermost mold insulation layer 122 may be exposed again.

[0121] refer to Fig.24 , an upper insulating layer 142 may be formed on the common source layer 110 and the uppermost mold insulating layer 122 in the cell region MCR, the connection region CON, and the peripheral circuit connection region PRC. The upper insulating layer 142 may be formed to have a sufficiently large height to cover the common source layer 110 and the second end portion CP1y of the first plug CP1, and to have a flat upper surface level.

[0122] refer to Fig.25, a mask pattern may be formed on the upper insulating layer 142 , and the second back contact hole 146H may be formed by removing a portion of the upper insulating layer 142 using the mask pattern as an etching mask.

[0123] In some embodiments, the second back contact hole 146H may be formed at a position vertically overlapping the stacked isolation insulating layer WLI. An upper surface of the common source layer 110 may be disposed on a bottom of the second back contact hole 146H.

[0124] refer to Fig.26 A mask pattern is formed on the upper insulating layer 142, and a first back contact hole 144H is formed by removing a portion of the upper insulating layer 142 and a portion of the common source layer 110 using the mask pattern as an etching mask.

[0125] In some embodiments, the first back contact hole 144H may be formed at a position vertically overlapping with the channel structure 130. In the process of forming the first back contact hole 144H, a horizontally extending portion of the channel layer 134 disposed at the second end 130y of the channel structure 130 may be removed, and then a liner horizontally extending portion of the insulating liner 136 disposed below the horizontally extending portion of the channel layer 134 may be removed. After removing the horizontally extending portion of the channel layer 134 and the horizontally extending portion of the insulating liner 136, the upper surface of the back gate electrode BG may be exposed on the bottom of the first back contact hole 144H.

[0126] refer to Fig. 27 , a spacer 148 may be formed on the sidewalls of the first back contact hole 144H and the second back contact hole 146H. In some embodiments, the spacer 148 may be arranged on the sidewall of the first back contact hole 144H, for example, the spacer 148 may cover the sidewalls of the common source layer 110 and the channel layer 134. At least a portion of the upper surface of the back gate electrode BG may be exposed at the bottom of the first back contact hole 144H without being covered by the spacer 148. In addition, the spacer 148 may be arranged on the sidewall of the second back contact hole 146H, and the upper surface of the common source layer 110 may be exposed at the bottom of the second back contact hole 146H.

[0127] refer to Fig.28 , a back gate contact 144 and a common source contact 146 may be formed in the first back contact hole 144H and the second back contact hole 146H, respectively.

[0128] In some embodiments, the back gate contact 144 and the common source contact 146 may be formed by forming a conductive layer in the first back contact hole 144H and the second back contact hole 146H using a metal such as tungsten, nickel, cobalt, or tantalum, a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide, or a combination thereof and planarizing an upper portion of the conductive layer. Therefore, the back gate contact 144 and the common source contact 146 may include an upper surface disposed at the same vertical level as an upper surface of the upper insulating layer 142.

[0129] refer to Fig.29 , a first back side wiring layer 164 and a second back side wiring layer 166 may be formed on the upper insulating layer 142. The first back side wiring layer 164 may be electrically connected to the back gate contact 144, and the second back side wiring layer 166 may be electrically connected to the common source contact 146. For example, the first back side wiring layer 164 and the second back side wiring layer 166 may be spaced apart from each other in the horizontal direction.

[0130] Subsequently, a passivation layer 168 covering the first and second back side wiring layers 164 and 166 may be formed on the upper insulating layer 142 , and an opening OP may be formed in the passivation layer 168 to expose upper surfaces of the first and second back side wiring layers 164 and 166 .

[0131] In some embodiments, the back gate contact 144 and the first back wiring layer 164 for providing electrical connection to the back gate electrode BG may be disposed on the second surface CS_2 of the cell structure CS, and thus, the area and degree of freedom of arrangement of the back gate contact 144 and the first back wiring layer 164 may be increased. In addition, the back gate contact 144 and the first back wiring layer 164 may be formed simultaneously in the manufacturing process for forming the common source contact 146 and the second back wiring layer 166, respectively, and thus, the back gate contact 144 and the first back wiring layer 164 may be formed without adding a process step.

[0132] Figure 30 to Figure 33 is a cross-sectional view illustrating an example of a method of manufacturing the semiconductor device 100B.

[0133] refer to Fig.30 , a buffer insulating layer 220 may be formed on the unit substrate 210, and an opening 230H and a landing pad opening 232H may be formed by removing a portion of the unit substrate 210 and the buffer insulating layer 220. Subsequently, a sacrificial layer 230 may be formed within the opening 230H, and a landing pad portion CP1P may be formed within the landing pad opening 232H.

[0134] In some embodiments, the sacrificial layer 230 and the landing pad portion CP1P may be formed by using a metal such as tungsten, nickel, cobalt or tantalum, a metal nitride such as titanium nitride, tantalum nitride or tungsten nitride, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide or tantalum silicide, or a combination thereof. In some embodiments, the sacrificial layer 230 and the landing pad portion CP1P may be formed by using the same material, but in some embodiments, the sacrificial layer 230 and the landing pad portion CP1P may be formed by using different materials.

[0135] Subsequently, an etch stop layer 112 covering the sacrificial layer 230 and the landing pad portion CP1P may be formed on the buffer insulating layer 220 .

[0136] refer to Fig.31 , gate electrodes 120 and mold insulating layers 122 are alternately formed in the cell region MCR and the connection region CON, and an extension portion 120E and a pad portion 120P connected to the gate electrode 120 may be formed in the connection region CON. In addition, a channel structure 130 extending in a vertical direction by passing through the gate electrode 120 and a bit line BL connected to the channel structure 130 may be formed in the cell region MCR.

[0137] In some embodiments, during the formation of the channel structure 130, a mold stack alternately including a sacrificial layer (not shown) on the etch stop layer 112 and a mold insulating layer 122 may be formed in the cell region MCR and the connection region CON, and a channel hole 130H passing through the mold stack may be formed in the cell region MCR. The channel hole 130H may be formed to pass through the etch stop layer 112 and expose the channel hole 130H disposed in the opening 230H. Fig.30 Subsequently, the sacrificial layer 230 may be removed, the gate insulating layer 132, the channel layer 134, the insulating liner 136, and the back gate electrode BG may be sequentially formed on the inner wall of the channel hole 130H and the inner wall of the opening 230H, and the drain region 138 may be formed at the entrance of the channel hole 130H.

[0138] In some embodiments, the opening 230H may be formed to have a greater width in the horizontal direction than the channel hole 130H, and thus, the portion of the back gate electrode BG disposed within the opening 230H may be formed to have a greater width in the horizontal direction than the portion of the back gate electrode BG disposed within the channel hole 130H. Here, the portion of the back gate electrode BG disposed within the opening 230H of the channel hole 130H may be referred to as an extension portion BGT.

[0139] In addition, a first plug CP1 passing through the extension portion 120E and the pad portion 120P may be formed in the connection region CON. In some embodiments, a first plug hole CP1H passing through the mold stack may be formed in the connection region CON. The upper surface of the landing pad portion CP1P may be exposed at the bottom of the first plug hole CP1H. Subsequently, a portion of the sacrificial layer exposed on the sidewall of the first plug hole CP1H may be removed by lateral etching, and an insulating pattern 126 may be formed in the portion where the sacrificial layer is removed. Subsequently, a first plug CP1 may be formed in the first plug hole CP1H.

[0140] Subsequently, by executing the reference Figures 18 to 20 According to the described process, the cell structure CS and the peripheral circuit structure PS may be bonded to each other, and the second end portion 130 y and the landing pad portion CP1P of the channel structure 130 may be exposed by removing the cell substrate 210 .

[0141] refer to Fig.32 The upper surface of the channel layer 134 is exposed by removing a portion of the gate insulating layer 132 exposed at the second end 130y of the channel structure 130. The process of removing the gate insulating layer 132 may be performed such that the upper surface of the etch stop layer 112 is exposed during the process of removing the gate insulating layer 132.

[0142] In some embodiments, the upper side of the gate insulating layer 132 may be removed so that the gate insulating layer 132 is disposed at a level lower than the upper surface of the channel layer 134 and exposes portions of the upper surface and sidewalls of the channel layer 134. The gate insulating layer 132 may be removed and an extension 134T of the channel layer 134 may be exposed at a vertical level higher than the etch stop layer 112.

[0143] Subsequently, you can reference Figure 23 to Figure 28 The described process is used to form the first back contact hole 144H and the second back contact hole 146H through the upper insulating layer 142.

[0144] refer to Fig.33 , spacers 148 may be formed on inner walls of the first back contact hole 144H and the second back contact hole 146H. Subsequently, a back gate contact 144 and a common source contact 146 may be formed in the first back contact hole 144H and the second back contact hole 146H, respectively.

[0145] Subsequently, you can reference Fig.29 The described process is used to completely form the semiconductor device 100B.

[0146] In some embodiments, the extension 134T of the channel layer 134 may be disposed at the second end 130y of the channel structure 130, and thus, the contact area between the channel layer 134 and the common source layer 110 may be increased. In addition, the extension BGT of the back gate electrode BG may be disposed at the second end 130y of the channel structure 130, and thus, the first back contact hole 144H may be formed to have a larger width, the contact area between the extension BGT of the back gate electrode BG and the back gate contact 144 may be increased, and / or a misalignment defect occurring during the formation of the first back contact hole 144H may be prevented or reduced.

[0147] Figure 34 to Figure 36 is a cross-sectional view illustrating an example of a method of manufacturing the semiconductor device 100D.

[0148] You can reference it by executing Figures 16 to 25 According to the described process, an upper insulating layer 142 is formed on the common source layer 110 .

[0149] refer to Fig.34 , the second back contact hole 146H may be formed by removing a portion of the upper insulating layer 142. The common source layer 110 may be exposed at the bottom of the second back contact hole 146H.

[0150] refer to Fig.35 , a common source contact portion 146 may be formed on the inner wall of the second back contact hole 146H.

[0151] In some embodiments, common source contact 146 may be formed using a metal such as tungsten, nickel, cobalt or tantalum, a metal nitride such as titanium nitride, tantalum nitride or tungsten nitride, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide or tantalum silicide, or a combination thereof.

[0152] In some embodiments, Figures 16 to 29 Unlike the manufacturing method, the spacer 148 may not be formed on the inner wall of the second back contact hole 146H. Therefore, the common source contact 146 may be surrounded by the upper insulating layer 142 and may be in contact with the upper insulating layer 142 .

[0153] Subsequently, a first back contact hole 144H may be formed by removing a portion of the upper insulating layer 142 and a portion of the common source layer 110. In the process of forming the first back contact hole 144H, a horizontally extending portion of the channel layer 134 disposed at the second end portion 130y of the channel structure 130 may be removed, and then a horizontally extending portion of the insulating liner 136 disposed below the horizontally extending portion of the channel layer 134 may be removed. After removing the horizontally extending portion of the channel layer 134 and the horizontally extending portion of the insulating liner 136, the upper surface of the back gate electrode BG may be exposed at the bottom of the first back contact hole 144H.

[0154] refer to Fig.36 , a spacer 148 may be formed on a sidewall of the first back contact hole 144H.

[0155] In some embodiments, the spacer 148 may be disposed on the sidewalls of the first back contact hole 144H. For example, the spacer 148 may cover the sidewalls of the common source layer 110 and the channel layer 134 .

[0156] Subsequently, a back gate contact 144 may be formed in the first back contact hole 144H.

[0157] The semiconductor device 100D may be completely formed by performing the above-mentioned processes.

[0158] Fig.37 is a diagram schematically illustrating an example of a data storage system 1000 including a semiconductor device.

[0159] refer to Fig.37 , the data storage system 1000 includes one or more semiconductor devices 1100 and a storage controller 1200 electrically connected to the semiconductor devices 1100. The data storage system 1000 may be, for example, a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including at least one semiconductor device 1100.

[0160] The semiconductor device 1100 may be a nonvolatile semiconductor device. For example, the semiconductor device 1100 may be a NAND flash memory semiconductor device including a reference Figures 1 to 15 The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may be a peripheral circuit structure including a row decoder 1110, a page buffer 1120, and a logic circuit 1130.

[0161] The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a plurality of word lines WL, a first string selection line UL1 and a second string selection line UL2, a first ground selection line LL1 and a second ground selection line LL2, and a plurality of memory cell strings CSTR between the bit line BL and the common source line CSL.

[0162] In the second structure 1100S, each of the plurality of memory cell strings CSTR may include ground selection transistors LT1 and LT2 adjacent to a common source line CSL, string selection transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT arranged between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of the ground selection transistors LT1 and LT2 and the number of the string selection transistors UT1 and UT2 may be variously modified.

[0163] In some embodiments, a plurality of ground selection lines LL1 and LL2 may be connected to gate electrodes of ground selection transistors LT1 and LT2, respectively. A word line WL may be connected to gate electrodes of memory cell transistors MCT. A plurality of string selection lines UL1 and UL2 may be connected to gate electrodes of string selection transistors UT1 and UT2, respectively.

[0164] A common source line CSL, a plurality of ground selection lines LL1 and LL2, a plurality of word lines WL, and a plurality of string selection lines UL1 and UL2 may be connected to the row decoder 1110. A plurality of bit lines BL may be electrically connected to the page buffer 1120.

[0165] The semiconductor device 1100 may communicate with the memory controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130.

[0166] The memory controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the memory controller 1200 may control the plurality of semiconductor devices 1100 .

[0167] The processor 1210 may control the overall operation of the data storage system 1000 including the storage controller 1200. The processor 1210 may operate according to a specific firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be written into a plurality of memory cell transistors MCT of the semiconductor device 1100, data to be read from a plurality of memory cell transistors MCT of the semiconductor device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0168] Fig.38 is a perspective view schematically illustrating an example of a data storage system 2000 including a semiconductor device.

[0169] refer to Fig.38 , a data storage system 2000 according to an embodiment may include a main substrate 2001, a memory controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the memory controller 2002 through a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0170] The main substrate 2001 includes a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host according to any of interfaces such as USB, Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. In some embodiments, the data storage system 2000 may be operated by power provided from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes the power provided by the external host to the storage controller 2002 and the semiconductor package 2003.

[0171] The memory controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operation speed of the data storage system 2000 .

[0172] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data in the control operation of the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the storage controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0173] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 arranged on a lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a mold layer 2500 covering the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0174] The package substrate 2100 may be a printed circuit board including a plurality of package pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may be connected to a Fig.37 Each of the plurality of semiconductor chips 2200 may include a reference Figures 1 to 15 At least one of the semiconductor devices 10 , 100 , 100A, 100B, 100C, and 100D described.

[0175] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other in a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV), rather than being electrically connected to each other through the connection structure 2400 in a bonding wire method.

[0176] In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In an embodiment, the memory controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the memory controller 2002 and the plurality of semiconductor chips 2200 may be connected to each other through wires formed on the interposer substrate.

[0177] Fig.39 is a cross-sectional view schematically showing an example of a semiconductor package 2003 . Fig.39 is along Fig.38 A cross-sectional view taken along line II-II'.

[0178] refer to Fig.39 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, a Fig.38 A plurality of upper package pads 2130, a plurality of lower pads 2125 arranged on the lower surface of the package substrate body 2120 or exposed through the lower surface, and an electrically connected Fig.38 The plurality of package upper pads 2130 and the plurality of internal wirings 2135 of the plurality of lower pads 2125 inside the package substrate body 2120. Fig.38 As shown, the plurality of package pads 2130 may be electrically connected to the plurality of connection structures 2400. Fig.38 As shown, the plurality of lower pads 2125 may be connected to the Fig.38 The data storage system 2000 is shown as having a plurality of wiring patterns 2005 on a main substrate 2001. Each of the plurality of semiconductor chips 2200 may include a reference Figures 1 to 15 At least one of the semiconductor devices 10 , 100 , 100A, 100B, 100C, and 100D described.

[0179] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. On the contrary, different features described in the context of a single embodiment can also be implemented in multiple embodiments separately, or in appropriate sub-combinations. In addition, although features can be described above as working in certain combinations and even initially claimed as such, one or more features from the combination can be deleted from the combination in some cases, and the combination can be for sub-combinations or variants of sub-combinations.

[0180] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Peripheral circuit structure; as well as A unit structure, stacked on the peripheral circuit structure, wherein the unit structure comprises: gate electrodes spaced apart from each other in a vertical direction; a channel structure arranged in a channel hole extending through the gate electrode in the vertical direction, the channel structure comprising a channel layer and a back gate electrode spaced apart from the channel layer, and comprising a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion; a common source layer connected to the channel layer at the second end of the channel structure; an upper insulating layer, disposed on the common source layer; and A back gate contact portion is arranged in the first back contact hole, extends through the upper insulating layer and the common source layer, and is connected to the back gate electrode.

2. The semiconductor device according to claim 1, wherein The unit structure further includes a spacer disposed on an inner wall of the first back contact hole.

3. The semiconductor device according to claim 2, wherein: The spacer is located between the back gate contact and the common source layer.

4. The semiconductor device according to claim 1, wherein: The cell structure further includes a common source contact portion, which is arranged in a second back contact hole extending through the upper insulating layer and connected to the common source layer, and Wherein, an upper surface of the common source contact is arranged at the same level as an upper surface of the back gate contact.

5. The semiconductor device according to claim 4, wherein: The cell structure further includes a spacer disposed within the second back contact hole and surrounding a sidewall of the common source contact.

6. The semiconductor device according to claim 4, wherein: The unit structure also includes: a first backside wiring layer disposed on the upper insulating layer and electrically connected to the back gate contact; and A second back-side wiring layer is disposed on the upper insulating layer, is spaced apart from the first back-side wiring layer, and is electrically connected to the common source contact.

7. The semiconductor device according to claim 6, wherein: The cell structure further includes a stacked isolation insulating layer extending through the gate electrode in the vertical direction, wherein the second backside wiring layer is arranged at a position vertically overlapping with the stacked isolation insulating layer, and The first backside wiring layer is arranged at a position vertically overlapping with the channel structure.

8. The semiconductor device according to claim 1, wherein The back gate electrode includes an extension portion at the second end portion of the channel structure, and the back gate contact portion is arranged on an upper surface of the extension portion of the back gate electrode.

9. The semiconductor device according to claim 8, wherein: The channel layer includes an extension portion at the second end portion of the channel structure, and a horizontal width of the extension portion of the channel layer is greater than a horizontal width of a portion of the channel layer surrounded by the gate electrode.

10. The semiconductor device according to claim 1, wherein The unit structure also includes: a bit line contact electrically connected to the channel layer at the first end of the channel structure; and A bit line is electrically connected to the bit line contact.

11. The semiconductor device according to claim 1, wherein The channel structure further includes: a gate insulating layer disposed on a sidewall of the channel hole and located between the channel layer and the gate electrode; and an insulating liner, located between the channel layer and the back gate electrode, The insulating liner and the gate insulating layer have a cylindrical shape extending in the vertical direction.

12. The semiconductor device according to claim 11, wherein The back-gate electrode has a column shape extending in the vertical direction, and a bottom surface of the back-gate electrode is covered by the insulating liner at the first end portion of the channel structure.

13. A semiconductor device comprising: Peripheral circuit structure; as well as A unit structure, stacked on the peripheral circuit structure, wherein the unit structure comprises: gate electrodes spaced apart from each other in a vertical direction; a channel structure arranged in a channel hole extending through the gate electrode in the vertical direction, the channel structure comprising a channel layer and a back gate electrode spaced apart from the channel layer, and comprising a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion; a bit line disposed adjacent to the first end of the channel structure and electrically connected to the channel layer; a common source layer disposed adjacent to the second end of the channel structure and connected to the channel layer; a back gate contact disposed adjacent to the second end of the channel structure and connected to the back gate electrode; and The first back-side wiring layer is disposed on the back gate contact portion and is electrically connected to the back gate contact portion.

14. The semiconductor device according to claim 13, wherein: The unit structure also includes: an upper insulating layer disposed on the common source layer and surrounding the back gate contact; and A spacer is located between the back gate contact and the upper insulating layer and between the back gate contact and the common source layer.

15. The semiconductor device according to claim 14, wherein: The unit structure also includes: a common source contact extending through the upper insulating layer and connected to the common source layer; and A second back-side wiring layer is disposed on the upper insulating layer, is spaced apart from the first back-side wiring layer, and is electrically connected to the common source contact.

16. The semiconductor device according to claim 15, wherein: An upper surface of the common source contact is arranged at the same level as an upper surface of the upper insulating layer, and an upper surface of the back gate contact is arranged at the same level as the upper surface of the upper insulating layer.

17. The semiconductor device according to claim 15, wherein: The cell structure further includes a stacked isolation insulating layer extending through the gate electrode in the vertical direction, wherein the second backside wiring layer is arranged at a position vertically overlapping with the stacked isolation insulating layer, and The first backside wiring layer is arranged at a position vertically overlapping with the channel structure.

18. A semiconductor device comprising: A peripheral circuit structure, comprising a substrate and a peripheral circuit transistor arranged on the substrate; gate electrodes spaced apart from each other in a vertical direction on the peripheral circuit structure; a channel layer arranged in a channel hole extending through the gate electrode in the vertical direction; a back gate electrode, arranged in the channel hole and electrically insulated from the channel layer by an insulating liner; a bit line disposed adjacent to a first end portion of the channel layer and electrically connected to the channel layer; a common source layer disposed adjacent to and connected to a second end portion of the channel layer, the second end portion being opposite to the first end portion; an upper insulating layer, on the common source layer; a back gate contact portion, arranged adjacent to the second end portion of the channel layer, the back gate contact portion extending through the upper insulating layer and the common source layer and connected to the back gate electrode; a common source contact extending through the upper insulating layer and connected to the common source layer; a first spacer disposed between the upper insulating layer and the back gate contact and between the common source layer and the back gate contact; a second spacer disposed between the upper insulating layer and the common source contact; a first backside wiring layer disposed on the upper insulating layer and electrically connected to the back gate contact; as well as A second back-side wiring layer is spaced apart from the first back-side wiring layer on the upper insulating layer and is electrically connected to the common source contact.

19. The semiconductor device according to claim 18, wherein: An upper surface of the common source contact is arranged at the same level as an upper surface of the upper insulating layer, and an upper surface of the back gate contact is arranged at the same level as the upper surface of the upper insulating layer.

20. The semiconductor device according to claim 18, further comprising a gate insulating layer arranged on a sidewall of the channel hole and between the channel layer and the gate electrode, in, The insulating liner is located between the channel layer and the back gate electrode, Wherein, the insulating liner and the gate insulating layer have a cylindrical shape extending in the vertical direction, Wherein, the back gate electrode has a column shape extending in the vertical direction, Wherein, a bottom surface of the back gate electrode disposed adjacent to the first end portion of the channel layer is covered by the insulating liner.

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