Method for preparing SONOS storage device

Abstract

The present application provides a method for preparing a SONOS memory device. In the preparation method, before and after a wet cleaning process is performed on a semiconductor structure after an ion implantation process in a control gate region, a pre-thickness value, a post-thickness value, and a thickness difference of a shallow trench isolation structure are obtained. Subsequently, before forming an ONO film layer, a pre-cleaning process is performed based on the STI thickness difference to remove a second thickness of the STI so that the final thickness of the STI is equal to its preset depth value. In the pre-cleaning process, based on the STI etching amount in the wet cleaning process, the STI etching amount in the pre-cleaning process is dynamically adjusted. If the first thickness etched is too little, the pre-cleaning process increases the etching; if the first thickness etched is too much, the pre-cleaning process reduces the etching, ensuring that the final depth of the STI is equal to the preset depth value, thereby avoiding the problem of the STI being too high or too low, and solving the problem of linear pattern defects occurring within the wafer surface causing device failure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a SONOS memory device. Background Art

[0002] SONOS memory devices have become a post-era application of traditional Flash memory (flash memory devices) due to their advantages such as low power consumption, low programming and erase voltage, no coupling rate issues and excellent anti-interference ability. In particular, with the continuous advancement and development of 3D-Flash technology in recent years, the advantages of charge trap memory have become more prominent.

[0003] However, after large-scale mass production, some SONOS memory devices have experienced line pattern defects on some wafers, leading to device failure. Line pattern defects typically appear in four directions in the MAP (mapping diagram) of chip probing, resulting in yield losses of 0.5% to 3%. This chip failure can have a serious impact on sales profits.

[0004] According to the results of CP feedback, it was found that the main failure BIN in line pattern failure was Chip CBKD failure. When operating any memory cell in the SONOS memory device, under normal circumstances, the storage state of the unoperated control gate adjacent to the operated control gate (CG) should all be "1". However, due to a certain amount of polysilicon remaining during polysilicon etching and not being completely removed by wet cleaning, it eventually led to conduction between the control gates, causing line pattern failure. The chip test results also fed back: Chip CBKD failure. Based on this, the line pattern area was analyzed for failure (Failure Analysis) using transmission electron microscopy. The electron microscope image showed that there was a certain amount of polysilicon residue between adjacent control gates. Summary of the Invention

[0005] The present application provides a method for preparing a SONOS memory device, which can solve the problem that a certain amount of polysilicon residue exists between adjacent control gates of the SONOS memory device, causing linear pattern defects on the wafer and resulting in device failure.

[0006] The present invention provides a method for manufacturing a SONOS memory device, comprising:

[0007] Providing a substrate, the substrate comprising a control gate region and a select gate region adjacent to the control gate region, a shallow trench isolation structure for isolating the control gate region from the select gate region formed in the substrate, and a sacrificial oxide layer formed on a surface of the substrate;

[0008] coating a photoresist layer on the sacrificial oxide layer;

[0009] Opening the photoresist layer in the control gate region by a photolithography process to expose the sacrificial oxide layer in the control gate region to form a patterned photoresist layer;

[0010] Using the patterned photoresist layer as a mask, an ion implantation process is performed on the substrate in the control gate region to adjust the threshold voltage of the control gate;

[0011] Obtaining a previous value of the thickness of the shallow trench isolation structure on the control gate region side;

[0012] Performing a wet cleaning process on the semiconductor structure after the ion implantation process in the control gate region to remove the sacrificial oxide layer on the active area surface of the control gate region and the shallow trench isolation structure of the first thickness on the side of the control gate region;

[0013] Obtaining a thickness value of the shallow trench isolation structure on the control gate region side;

[0014] Obtaining an actual thickness difference of the shallow trench isolation structure according to a previous thickness value of the shallow trench isolation structure and a subsequent thickness value of the shallow trench isolation structure;

[0015] performing a pre-cleaning process on the semiconductor structure after the wet cleaning process, based on the actual thickness difference of the shallow trench isolation structure, to remove the sacrificial oxide layer on the surface of the active area of ​​the select gate region and the shallow trench isolation structure of the second thickness on the side of the control gate region, wherein after removing the shallow trench isolation structure of the second thickness, the remaining thickness of the shallow trench isolation structure is equal to the preset depth value of the shallow trench isolation structure;

[0016] An ONO film layer is formed, where the ONO film layer covers the substrate of the control gate region, the substrate of the select gate region, and the remaining thickness of the shallow trench isolation structure.

[0017] Optionally, in the method for preparing the SONOS memory device, the pre-cleaning process is used to dynamically adjust the second thickness of the shallow trench isolation structure removed so that the final thickness of the shallow trench isolation structure after removing the second thickness is equal to a preset depth value of the shallow trench isolation structure.

[0018] Optionally, in the method for preparing the SONOS memory device, the pre-cleaning process is a wet etching process.

[0019] Optionally, in the method for preparing the SONOS memory device, the ONO film layer includes: a tunneling oxide layer, a silicon nitride layer, and a top silicon oxide layer stacked in sequence.

[0020] Optionally, in the method for manufacturing the SONOS memory device, a thickness monitoring machine is used to obtain a thickness before and a thickness after of the shallow trench isolation structure in the control gate region.

[0021] Optionally, in the method for preparing the SONOS memory device, after obtaining the thickness value of the shallow trench isolation structure in the control gate region and before performing a pre-cleaning process on the semiconductor structure after the wet cleaning process, the method for preparing the SONOS memory device further includes:

[0022] The patterned photoresist layer is removed.

[0023] Optionally, in the method for preparing the SONOS memory device, after forming the ONO film layer, the method for preparing the SONOS memory device further comprises:

[0024] Etching and removing the ONO film layer in the select gate region;

[0025] forming a gate oxide layer, wherein the gate oxide layer covers a portion of the substrate in the select gate region;

[0026] forming a polysilicon layer, wherein the polysilicon layer covers the shallow trench isolation structure, the gate oxide layer of the select gate region, and the ONO film layer of the control gate region;

[0027] The polysilicon layer above the shallow trench isolation structure is removed by etching to form a control gate and a select gate, wherein the control gate covers the ONO film layer, and the select gate covers the gate oxide layer.

[0028] The technical solution of this application has at least the following advantages:

[0029] The present application provides a method for fabricating a SONOS memory device. In the fabrication method, before and after a wet cleaning process is performed on a semiconductor structure following an ion implantation process in a control gate region, a pre-thickness value, a post-thickness value, and a thickness difference of a shallow trench isolation (STI) structure are obtained. Subsequently, before forming an ONO film layer, a pre-cleaning process is performed based on the thickness difference of the shallow trench isolation structure to remove a second thickness of the shallow trench isolation structure. After removing the second thickness of the shallow trench isolation structure, a remaining thickness of the shallow trench isolation structure is equal to a preset depth value of the shallow trench isolation structure. In the pre-cleaning process, the etching amount of the shallow trench isolation structure in the pre-cleaning process is dynamically adjusted based on the etching amount of the shallow trench isolation structure in the wet cleaning process. If the first etching thickness is too little, the pre-cleaning process increases etching compensation; if the first etching thickness is too much, the pre-cleaning process reduces etching to ensure that the final depth of the shallow trench isolation structure is equal to the preset depth value, thereby avoiding the problem that the shallow trench isolation structure is too high and affects the coupling coefficient of the ONO film layer thereon. At the same time, it also avoids the problem that the shallow trench isolation structure is too short, resulting in residual polysilicon on the surface of the shallow trench isolation structure during subsequent polysilicon gate etching, thereby solving the problem of device failure caused by linear graphic defects on the wafer surface and greatly improving the product yield.

[0030] Furthermore, the method for preparing the SONOS memory device provided in the present application can maintain process stability in actual mass production, thereby improving economic benefits and device stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 is a flow chart of a method for preparing a SONOS memory device according to an embodiment of the present invention;

[0033] Figure 2-Figure 7 1 is a schematic diagram of a semiconductor structure in each process step of preparing a SONOS memory device according to an embodiment of the present invention;

[0034] The description of the accompanying drawings is as follows:

[0035] 10-substrate, 11-shallow trench isolation structure, 20-sacrificial oxide layer, 30-photoresist layer, 31-patterned photoresist layer, 40-ONO film layer. DETAILED DESCRIPTION

[0036] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0037] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0039] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0040] The inventors have found that the polysilicon residue is caused by the wet etching process after the ion implantation process in the control gate region for adjusting the control gate threshold voltage. The wet etching process is used to remove the sacrificial layer on the substrate surface. However, since the shallow trench isolation structure is usually higher than the substrate surface, the wet cleaning also needs to remove a certain thickness of the shallow trench isolation structure. If the shallow trench isolation structure is removed too thick or too thin, it will cause a step between the shallow trench isolation structure and the substrate. Among them, if the shallow trench isolation structure is removed too thick (too much), the final shallow trench isolation structure will be lower than the substrate surface, and the ONO film layer that continues to be deposited on the surface of the shallow trench isolation structure will cause the residual polysilicon residue to be higher than the substrate surface. The thickness of the polysilicon material is also lower than that of the ONO film layer and polysilicon material on the surface of other substrates, so the subsequent removal of the polysilicon on the shallow trench isolation structure between adjacent control gates will cause certain residues in the polysilicon etching process. The polysilicon residue on the shallow trench isolation structure causes the control gates (different control gates) in adjacent storage cells to be interconnected, and the corresponding storage states of the adjacent storage cells are changed through the polysilicon interconnection, which will eventually cause the chip test to fail. In addition, if the removed shallow trench isolation structure is too thin (too little), the final shallow trench isolation structure will be higher than the substrate surface, which will have an adverse effect on the coupling coefficient of the ONO film layer subsequently deposited thereon.

[0041] Based on the above findings, the present invention provides a method for preparing a SONOS memory device. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a SONOS memory device according to an embodiment of the present invention, wherein the method for preparing a SONOS memory device comprises:

[0042] First, perform step S1: refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after coating a photoresist layer according to an embodiment of the present application. A substrate 10 is provided. The substrate 10 includes a control gate region and a select gate region adjacent to the control gate region. A plurality of shallow trench isolation structures 11 are formed in the substrate 10. The shallow trench isolation structures 11 are used to isolate the control gate region from the select gate region, and are also used to isolate adjacent control gate regions and adjacent select gate regions. A sacrificial oxide layer 20 is formed on the surface of the substrate 10. The upper surface of the shallow trench isolation structure 11 is higher than the surface of the substrate 10.

[0043] Then, proceed to step S2: continue with reference Figure 2 , a photoresist layer 30 is coated on the sacrificial oxide layer 20 .

[0044] Next, execute step S3: refer to Figure 3 , Figure 33 is a schematic diagram of a semiconductor structure after a patterned photoresist layer is formed in an embodiment of the present application. The photoresist layer 30 in the control gate region is opened by a photolithography process to expose the sacrificial oxide layer 20 in the control gate region to form a patterned photoresist layer 31.

[0045] Further, step S4 is performed: refer to Figure 4 , Figure 4 This is a schematic diagram of a semiconductor structure in which an ion implantation process is performed on the substrate in the control gate region using the patterned photoresist layer as a mask according to an embodiment of the present application. The ion implantation process is performed on the substrate 10 in the control gate region using the patterned photoresist layer 31 as a mask to adjust the threshold voltage of the control gate.

[0046] Next, step S5 is performed: obtaining a previous value of the thickness of the shallow trench isolation structure 11 on the control gate region side.

[0047] Preferably, the previous thickness value of the shallow trench isolation structure 11 in the control gate region can be obtained by a thickness monitoring machine, that is, the thickness value of the shallow trench isolation structure 11 between adjacent control gate regions before step S6 can be obtained by a thickness monitoring machine.

[0048] Further, step S6 is performed: refer to Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after a wet cleaning process is performed on the semiconductor structure after the ion implantation process in the control gate region according to an embodiment of the present application. A wet cleaning process is performed on the semiconductor structure after the ion implantation process in the control gate region to remove the sacrificial oxide layer 20 on the surface of the active area of ​​the control gate region and the shallow trench isolation structure 11 of the first thickness on the side of the control gate region.

[0049] Specifically, this embodiment can use an acidic solution to perform a wet cleaning process on the semiconductor structure after the ion implantation process in the control gate region to remove the sacrificial oxide layer 20 on the surface of the active area of ​​the control gate region. At the same time, the shallow trench isolation structure 11 of the first thickness on the side of the control gate region is inevitably removed.

[0050] Next, step S7 is performed: obtaining a thickness value of the shallow trench isolation structure 11 on the control gate region side.

[0051] Preferably, the thickness value of the shallow trench isolation structure 11 in the control gate region can be obtained by a thickness monitoring machine, that is, the thickness value of the shallow trench isolation structure 11 between adjacent control gate regions after step S6 can be obtained by a thickness monitoring machine.

[0052] Furthermore, step S8 is performed: obtaining an actual thickness difference of the shallow trench isolation structure 11 according to the previous thickness value of the shallow trench isolation structure 11 and the subsequent thickness value of the shallow trench isolation structure 11 .

[0053] Specifically, based on the thickness value of the shallow trench isolation structure 11 before step S6 and the thickness value of the shallow trench isolation structure 11 before step S6, the actual thickness difference of the shallow trench isolation structure 11 is obtained to monitor the etching thickness of the shallow trench isolation structure 11 in the wet cleaning process of step S6.

[0054] Furthermore, after obtaining the thickness value of the shallow trench isolation structure 11 in the control gate region and before performing a pre-cleaning process on the semiconductor structure after the wet cleaning process, the method for preparing the SONOS memory device may further include: removing the patterned photoresist layer 31 .

[0055] Then, execute step S9: refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the wet cleaning process is performed on the semiconductor structure after the pre-cleaning process is performed in an embodiment of the present application, and the sacrificial oxide layer on the surface of the active area of ​​the selection gate region and the shallow trench isolation structure of the second thickness on the control gate region side are removed. According to the actual thickness difference of the shallow trench isolation structure 11, a pre-cleaning process is performed on the semiconductor structure after the wet cleaning process is performed to remove the sacrificial oxide layer 20 on the surface of the active area of ​​the selection gate region and the shallow trench isolation structure 11 of the second thickness on the control gate region side, wherein after removing the shallow trench isolation structure of the second thickness, the remaining thickness of the shallow trench isolation structure 11 is equal to the preset depth value of the shallow trench isolation structure 11.

[0056] Preferably, after executing step S9 , the upper surface of the final shallow trench isolation structure 11 is flush with the substrate surface.

[0057] In the pre-cleaning process, the etching amount of the shallow trench isolation structure in the pre-cleaning process is dynamically adjusted based on the etching thickness (etching amount) of the shallow trench isolation structure in the wet cleaning process. If the first etching thickness is too little, the pre-cleaning process increases etching compensation; if the first etching thickness is too much, the pre-cleaning process reduces etching. It can be seen that the pre-cleaning process is used to dynamically adjust the second thickness of the shallow trench isolation structure 11 removed, so that the final thickness of the shallow trench isolation structure 11 after removing the second thickness is equal to the preset depth value of the shallow trench isolation structure 11.

[0058] Preferably, the pre-cleaning process is a wet etching process.

[0059] In the present application, in the pre-cleaning process, the etching amount of the shallow trench isolation structure in the pre-cleaning process is dynamically adjusted based on the etching thickness (etching amount) of the shallow trench isolation structure in the wet cleaning process. If the first etching thickness is too little, the pre-cleaning process increases the etching compensation; if the first etching thickness is too much, the pre-cleaning process reduces the etching to ensure that the final depth of the shallow trench isolation structure is equal to the preset depth value, thereby avoiding the problem that the final shallow trench isolation structure is too high, affecting the coupling coefficient of the subsequent ONO film layer deposited thereon. At the same time, it also avoids the problem that the final shallow trench isolation structure is too short, resulting in the problem of residual polysilicon on the surface of the shallow trench isolation structure during the subsequent polysilicon gate etching, thereby solving the problem of linear pattern defects on the wafer surface causing device failure and greatly improving the product yield. In addition, the preparation method of the SONOS memory device provided by the present application can maintain process stability in actual mass production, thereby improving economic benefits and device stability.

[0060] Finally, execute step S10: refer to Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the ONO film layer is formed in an embodiment of the present application, wherein the ONO film layer 40 is formed, and the ONO film layer 40 covers the substrate 10 of the control gate region, the substrate 10 of the select gate region, and the remaining thickness of the shallow trench isolation structure 11.

[0061] In this embodiment, the ONO film layer 40 includes a tunneling oxide layer, a silicon nitride layer, and a top silicon oxide layer (not shown) stacked in sequence.

[0062] Furthermore, after forming the ONO film layer, the method for preparing the SONOS memory device may further include:

[0063] Step S11: etching and removing the ONO film layer 40 in the select gate region;

[0064] Step S12: forming a gate oxide layer, wherein the gate oxide layer covers a portion of the substrate in the select gate region;

[0065] Step S13: forming a polysilicon layer, wherein the polysilicon layer covers the shallow trench isolation structure, the gate oxide layer in the select gate region, and the ONO film layer in the control gate region;

[0066] Step S14: etching and removing the polysilicon layer above the shallow trench isolation structure to form a control gate and a select gate, wherein the control gate covers the ONO film layer, and the select gate covers the gate oxide layer.

[0067] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing a SONOS memory device, characterized in that: include: Providing a substrate, the substrate comprising a control gate region and a select gate region adjacent to the control gate region, a shallow trench isolation structure for isolating the control gate region from the select gate region formed in the substrate, and a sacrificial oxide layer formed on a surface of the substrate; coating a photoresist layer on the sacrificial oxide layer; Opening the photoresist layer in the control gate region by a photolithography process to expose the sacrificial oxide layer in the control gate region to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, an ion implantation process is performed on the substrate in the control gate region to adjust the threshold voltage of the control gate; Obtaining a previous value of the thickness of the shallow trench isolation structure on the control gate region side; Performing a wet cleaning process on the semiconductor structure after the ion implantation process in the control gate region to remove the sacrificial oxide layer on the active area surface of the control gate region and the shallow trench isolation structure of the first thickness on the side of the control gate region; Obtaining a thickness value of the shallow trench isolation structure on the control gate region side; Obtaining an actual thickness difference of the shallow trench isolation structure according to a previous thickness value of the shallow trench isolation structure and a subsequent thickness value of the shallow trench isolation structure; performing a pre-cleaning process on the semiconductor structure after the wet cleaning process, based on the actual thickness difference of the shallow trench isolation structure, to remove the sacrificial oxide layer on the surface of the active area of ​​the select gate region and the shallow trench isolation structure of the second thickness on the side of the control gate region, wherein after removing the shallow trench isolation structure of the second thickness, the remaining thickness of the shallow trench isolation structure is equal to the preset depth value of the shallow trench isolation structure; An ONO film layer is formed, where the ONO film layer covers the substrate of the control gate region, the substrate of the select gate region, and the remaining thickness of the shallow trench isolation structure.

2. The method for preparing a SONOS memory device according to claim 1, wherein: The pre-cleaning process is used to dynamically adjust the second thickness of the shallow trench isolation structure removed, so that the final thickness of the shallow trench isolation structure after removing the second thickness is equal to a preset depth value of the shallow trench isolation structure.

3. The method for preparing a SONOS memory device according to claim 1, wherein: The pre-cleaning process is a wet etching process.

4. The method for preparing a SONOS memory device according to claim 1, wherein: The ONO film layer includes: a tunneling oxide layer, a silicon nitride layer and a top silicon oxide layer stacked in sequence.

5. The method for preparing a SONOS memory device according to claim 1, wherein: The thickness monitoring machine is used to obtain a thickness front value and a thickness back value of the shallow trench isolation structure in the control gate region.

6. The method for preparing a SONOS memory device according to claim 1, wherein: After obtaining the thickness value of the shallow trench isolation structure in the control gate region and before performing a pre-cleaning process on the semiconductor structure after the wet cleaning process, the method for preparing the SONOS memory device further includes: The patterned photoresist layer is removed.

7. The method for preparing a SONOS memory device according to claim 1, wherein: After forming the ONO film layer, the method for preparing the SONOS memory device further includes: Etching and removing the ONO film layer in the select gate region; forming a gate oxide layer, wherein the gate oxide layer covers a portion of the substrate in the select gate region; forming a polysilicon layer, wherein the polysilicon layer covers the shallow trench isolation structure, the gate oxide layer of the select gate region, and the ONO film layer of the control gate region; The polysilicon layer above the shallow trench isolation structure is removed by etching to form a control gate and a select gate, wherein the control gate covers the ONO film layer, and the select gate covers the gate oxide layer.

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