Semiconductor package

Abstract

A semiconductor chip includes: a substrate; a plurality of upper pads on the substrate, the plurality of upper pads including a first set of upper pads and a second set of upper pads; a buffer layer covering a side surface of the first group of upper pads; and an insulating layer on the substrate surrounding side surfaces of the second set of upper pads and side surfaces of the buffer layer, where the buffer layer includes a first material having a first Young's modulus less than a second Young's modulus of a second material of the plurality of upper pads.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0152083 filed in the Korean Intellectual Property Office on November 6, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package. Background Art

[0003] As the demand for high capacity, thinness, and miniaturization of electronic products continues to grow, various types of semiconductor packages have been developed. Recently, in order to integrate more components (e.g., semiconductor chips) into a package structure, a direct bonding technology has been developed that can bond semiconductor chips to each other without an adhesive film (e.g., a non-conductive film (NCF)) or a connection bump (e.g., a solder ball). Summary of the invention

[0004] A semiconductor package is provided which can achieve semiconductor chip stacking with a bonding interface of improved quality and can have improved reliability.

[0005] According to one aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip, including: a first substrate, a plurality of first upper pads on the first substrate, wherein the plurality of first upper pads include a first group of first upper pads and a second group of first upper pads, a first buffer layer surrounding side surfaces of the first group of first upper pads, a first insulating layer surrounding side surfaces of the second group of first upper pads and side surfaces of the first buffer layer, and a plurality of through electrodes penetrating the first substrate, the plurality of through electrodes being respectively connected to the plurality of first upper pads; and a second semiconductor chip on the first semiconductor chip, including: a second substrate, a plurality of second lower pads under the second substrate, wherein the plurality of second lower pads include a first group of second lower pads and a second group of second lower pads, a second buffer layer surrounding side surfaces of the first group of second lower pads, and a second insulating layer surrounding side surfaces of the second group of second lower pads and side surfaces of the second buffer layer, wherein the first group of first upper pads are respectively in contact with the first group of second lower pads, and wherein the second group of first upper pads are respectively in contact with the second group of second lower pads.

[0006] According to one aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip and a second semiconductor chip stacked in a vertical direction, wherein the first semiconductor chip includes: a plurality of first upper pads, including: a first upper conductive layer, and a first upper seed layer surrounding the side surface of the first upper conductive layer and the lower surface of the first upper conductive layer; a first buffer layer extending along at least one periphery of the first upper pad in the first group of multiple first upper pads; and a first insulating layer surrounding the first upper pad and the first buffer layer in the second group of multiple first upper pads, wherein the second semiconductor chip includes: a plurality of second lower pads, including: a second lower conductive layer, and a second lower seed layer surrounding the side surface of the second lower conductive layer and the upper surface of the second lower conductive layer, the second lower conductive layer being electrically connected to the plurality of first upper pads; a second buffer layer extending along at least one periphery of the second lower pad in the first group of multiple second lower pads; and a second insulating layer surrounding the second lower pad and the second buffer layer in the second group of multiple second lower pads, wherein the first buffer layer and the second buffer layer include a polymer or a porous metal.

[0007] According to one aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip including a plurality of upper solder pads; and a second semiconductor chip including: a plurality of lower solder pads, including a first group of lower solder pads and a second group of lower solder pads in contact with upper surfaces of the plurality of upper solder pads, a connecting conductor in contact with the upper surface of the first group of lower solder pads, an internal insulating layer surrounding the side surfaces of the connecting conductor, a buffer insulating layer in contact with the side surfaces of the first group of lower solder pads and the upper surfaces of the second group of lower solder pads, and an external insulating layer surrounding the side surfaces of the first group of lower solder pads and the side surfaces of the second group of lower solder pads under the buffer insulating layer, wherein the first group of lower solder pads includes: a layer portion surrounded by the external insulating layer, and an extension portion extending from the upper surface of the layer portion, penetrating the buffer insulating layer and contacting the lower surface of the connecting conductor.

[0008] According to one aspect of the present disclosure, a semiconductor chip includes: a substrate; a plurality of upper pads on the substrate, the plurality of upper pads including a first group of upper pads and a second group of upper pads; a buffer layer covering side surfaces of the first group of upper pads; and an insulating layer surrounding side surfaces of the second group of upper pads and side surfaces of the buffer layer on the substrate, wherein the buffer layer includes a first material having a first Young's modulus that is less than a second Young's modulus of a second material in the plurality of upper pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view showing a semiconductor package according to an example embodiment of the present disclosure;

[0011] Figure 2A It is shown Figure 1 A magnified view of the middle area “A”;

[0012] Figure 2B is shown along Figure 2A A plan view of a section taken along line II' in FIG.

[0013] Figures 3 to 15 is shown with Figure 2A A plan view of a modified example related to area "A" in FIG.

[0014] FIG. 16A to FIG. 16C It is shown Fig.14 and Fig.15 perspective views of modified examples in and graphs indicating experimental data;

[0015] Fig.17 and Fig.18 is shown with Figure 2A A plan view of an example related to area "A" in FIG.

[0016] Fig.19 is a cross-sectional view showing a semiconductor package according to an example embodiment of the present disclosure;

[0017] Fig. 20A is a plan view showing a semiconductor package according to an example embodiment of the present disclosure;

[0018] Fig. 20B is shown along Fig. 20A A cross-sectional view of a section taken along line II-II' in FIG.

[0019] Figures 21A to 21E It shows the manufacturing Figure 2A A cross-sectional view of a semiconductor packaging process;

[0020] Figures 22A to 22C It shows the manufacturing Figure 4 A cross-sectional view of a process of semiconductor packaging in FIG.

[0021] Figures 23A to 23C It shows the manufacturing Fig.14 A cross-sectional view of a process of semiconductor packaging. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments in the present exemplary embodiment will be described as follows with reference to the drawings.

[0023] This description merely illustrates the principles of the present disclosure. Those skilled in the art will be able to design one or more arrangements that embody the principles of the present disclosure, although not explicitly described herein. In addition, all examples cited herein are primarily and explicitly used only for explanatory purposes to help the reader understand the principles of the present disclosure and the concepts contributed by the inventors to improve the prior art, and should be interpreted as not being limited to these specifically cited examples and conditions. In addition, all statements cited herein for the principles, aspects, embodiments, and specific examples thereof of the present disclosure are intended to include equivalents of the present disclosure.

[0024] The terms used in the present disclosure are only used to describe specific embodiments, and are not intended to limit the scope of another embodiment. Unless clearly expressed differently in the context, singular expressions may include plural expressions. The terms used herein (including technical or scientific terms) may have the same meanings as those generally understood by those of ordinary skill in the technical field described in the present disclosure. Among the terms used in the present disclosure, the terms defined in general dictionaries may be interpreted as meanings identical or similar to the contextual meanings of the relevant technology, unless clearly defined in the present disclosure, otherwise they will not be interpreted with ideal or overly formal meanings. In some cases, even the terms defined in the present disclosure may not be interpreted as excluding embodiments of the present disclosure.

[0025] In one or more embodiments of the present disclosure described below, a hardware method is described as an example. However, since one or more embodiments of the present disclosure include technologies using both hardware and software, various embodiments of the present disclosure do not exclude software-based methods.

[0026] In addition, in the present disclosure, in order to determine whether a specific condition is satisfied or achieved, the expression of greater than or less than can be used, but this is only a description of an expression example, and does not exclude the description of greater than or equal to or less than or equal to. The condition described as "greater than or equal to" can be replaced with "greater than", the condition described as "less than or equal to" can be replaced with "less than", and the condition described as "greater than or equal to and less than" can be replaced with "greater than and less than or equal to". In addition, hereinafter, "A" to "B" means at least one of the elements from A (including A) to B (including B).

[0027] The terms "include" and "comprising" and their derivatives refer to inclusion rather than limitation. The term "or" is an inclusive term, meaning "and / or". The phrase "associated with..." and its derivatives refer to including, being included, interconnected with, containing, being contained within, connected to or connected with, coupled to or coupled with, communicable with, cooperating with, interlaced, juxtaposed, close to, bound to or bound with, having, having the property of, having a relationship to or with, etc. The term "controller" refers to any device, system or part thereof that controls at least one operation. The functions associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, "at least one of A, B, and C" includes any combination of: A, B, C, A and B, A and C, B and C, A and B and C, and any variation thereof. The expression "at least one of a, b, or c" may mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. Similarly, the term "set" means one or more. Thus, a set of items may be a single item or a set of two or more items.

[0028] Figure 1 is a cross-sectional view illustrating a semiconductor package 10 according to example embodiments. Figure 2A It is shown Figure 1 Magnified view of area "A" in the middle. Figure 2B is shown along Figure 2A A plan view of a cross section taken along line II'.

[0029] refer to Figure 1 The semiconductor package 10 in the example embodiment may include a plurality of semiconductor chips stacked in a vertical direction (eg, a Z-axis direction). For example, the plurality of semiconductor chips include a first semiconductor chip 100 and a second semiconductor chip 200 .

[0030] In the first semiconductor chip 100 and the second semiconductor chip 200, the upper surface of the first semiconductor chip 100 and the lower surface of the second semiconductor chip 200 can be directly bonded and coupled to each other (for example, referred to as "hybrid bonding" or "direct bonding") without a connection member such as a metal bump. The first insulating layer 140 and the plurality of first upper pads 150 (providing the upper surface of the first semiconductor chip 100) can be bonded and coupled to the second insulating layer 240 and the plurality of second lower pads 250 (providing the lower surface of the second semiconductor chip 200), respectively. The first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected to the plurality of first upper pads 150 and the plurality of second lower pads 250 directly bonded to each other.

[0031] In the following, reference will be made to Figure 2A and Figure 2B Components of the first semiconductor chip 100 and the second semiconductor chip 200 are described in more detail.

[0032] Hereinafter, the “first insulating layer 140” may be referred to as a “first upper insulating layer” or a “first rear surface insulating layer”, respectively, to distinguish the positions of components in the first semiconductor chip 100. The “second insulating layer 240” may be referred to as a “second lower insulating layer” or a “second front surface insulating layer” to distinguish the positions of components in the second semiconductor chip 200. In addition, the “first upper pad 150” may be referred to as a “first pad” or a “first rear surface pad”, and the “second lower pad 250” may be referred to as a “second pad” or a “second front surface pad”.

[0033] The first semiconductor chip 100 may include a first substrate 110, a first circuit layer 120, a plurality of first through electrodes 130, a first insulating layer 140, a plurality of first upper pads 150, and a first buffer layer 160. The plurality of first upper pads 150 may include a first group of first upper pads 150a and a second group of first upper pads 150b.

[0034] The first substrate 110 may be a semiconductor wafer substrate having a front surface FR and a back surface BA facing each other. For example, the first substrate 110 may be a semiconductor wafer including semiconductor elements such as silicon and germanium or including compounds such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The front surface FR may be an active surface having an active region doped with impurities. The back surface BA may be an inactive surface disposed opposite to the front surface FR with respect to the first substrate 110.

[0035] The first circuit layer 120 may be disposed on the front surface FR of the first substrate 110, and may include a first wiring structure connected to the active area and a first interlayer insulating layer surrounding the first wiring structure. The first wiring structure may form an integrated circuit in which various devices are formed on the active surface of the first substrate 110. A first lower pad 182 electrically connected to the wiring structure may be disposed below the first circuit layer 120. The first lower pad 182 may be a pad structure electrically connected to the wiring structure. A connecting bump 186 may be disposed below the first lower pad 182. The connecting bump 186 may be a conductive bump structure including, for example, a solder ball or a copper (Cu) column. The first circuit layer 120 may have a Figure 2A Therefore, the first wiring structure, the first interlayer insulating layer and the respective devices described above may have similar characteristics to the second wiring structure 225, the second interlayer insulating layer 221 and the respective devices 215 of the second circuit layer 220 to be described later.

[0036] A plurality of through electrodes 130 (or "a plurality of first through electrodes") may penetrate the first substrate 110, and may electrically connect each of the first upper pads 150 to the first lower pad 182. The plurality of through electrodes 130 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by an electroplating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. A side surface insulating film may be formed between one through electrode (of the plurality of through electrodes 130) and the first substrate 110, the side surface insulating film including an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., high aspect ratio process (HARP) oxide).

[0037] The first insulating layer 140 (or "first upper insulating layer") may be disposed on the back surface BA of the first substrate 110. The first insulating layer 140 may include an insulating material bonded and coupled to the second insulating layer 240 (or "second lower insulating layer") below the second semiconductor chip 200. For example, the first insulating layer 140 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN). That is, at least a portion of the first insulating layer 140 may be bonded to the second insulating layer 240, and a "bonding interface" may be formed that bonds and couples the first semiconductor chip 100 to the second semiconductor chip 200. In addition, the first insulating layer 140 may be formed to surround a plurality of first upper pads 150 arranged on an upper surface of the first insulating layer 140. The upper surface of the first insulating layer 140 may be substantially coplanar with the upper surfaces of the plurality of first upper pads 150.

[0038] The plurality of first upper pads 150 may be disposed on the back surface BA of the first substrate 110, may be bonded to the second lower pads 250 of the second semiconductor chip 200, and may physically and electrically couple the first semiconductor chip 100 to the second semiconductor chip 200. The plurality of first upper pads 150 may include a first group of first upper pads 150a and a second group of first upper pads 150b. In an embodiment, as shown in FIG. Figure 2A As shown, in a direction parallel to the upper surface of the first substrate 110 (e.g., the X direction or the Y direction), the first width W1 of the first group of first upper pads 150a may be greater than the second width W2 of the second group of first upper pads 150b. The side surfaces and the lower surface of the first group of first upper pads 150a may be covered by the first buffer layer 160, and the side surfaces of the second group of first upper pads 150b may be in direct contact with the first insulating layer 140. Figure 2B As shown, the plurality of first upper pads 150 may have a circular shape on a plane (XY plane), and the first buffer layer 160 may have a shape surrounding the first group of first upper pads 150a. The embodiments of the present disclosure are not limited to the above-described embodiments.

[0039] Each first upper pad 150 may include a first upper conductive layer 155a and 155b and a first seed layer 153a and 153b. The first seed layer 153a and 153b may cover the side surface and the lower surface of the first upper conductive layer 155a and 155b. The first upper conductive layer 155a and 155b may include at least one of copper (Cu), nickel (Ni), gold (Au) and silver (Ag). The first seed layer 153a and 153b may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN).

[0040] The first buffer layer 160 may cover side surfaces and lower surfaces of a first group of first upper pads 150a among the plurality of first upper pads 150. The first buffer layer 160 may relieve expansion of the first group of first upper pads 150a during a thermal compression process for bonding and coupling the first and second semiconductor chips 100 and 200.

[0041] When the first width W1 of the first group of first upper pads 150a is greater than the second width W2 of the second group of second upper pads 150b, the expansion characteristics of the first group of first upper pads 150a during the hot pressing process may be greater than the expansion rate (expansion characteristics) of the second group of first upper pads 150b. When there are differences in the expansion characteristics of the plurality of first upper pads 150 during the bonding process, the reliability of direct bonding may be reduced. The first buffer layer 160 may improve the reliability of direct bonding by alleviating the expansion characteristics of the first group of first upper pads 150a, where the first group of first upper pads 150a may have greater expansion characteristics.

[0042] The first buffer layer 160 may include a material having a Young's modulus lower than that of the material in the plurality of first upper pads 150. The Young's modulus is a coefficient indicating how the relative length of an elastic object changes in response to stress, and is also referred to as an elastic modulus. Alternatively, the Young's modulus of the first buffer layer 160 may be lower than that of each of the plurality of first upper pads 150.

[0043] For example, the first buffer layer 160 may include a porous metal. Porosity may refer to a state in which a plurality of small voids (pores) are present in or on a surface of a solid object. A porous metal may have voids so that the Young's modulus of the porous metal may be lower than that of a metal without voids. For example, when the first upper pad 150 includes copper (Cu) and the first buffer layer 160 is formed of porous copper (Cu), even if the first upper pad 150 and the first buffer layer 160 include the same material copper (Cu), the Young's modulus of the first buffer layer 160 may be lower than that of the first upper pad 150. For the convenience of description in the present disclosure, the Young's modulus of a material described as a "porous metal" may be lower than that of a general "metal" material. For example, the Young's modulus of porous copper (Cu) may be lower than that of copper (Cu). In example embodiments, the first buffer layer 160 may include porous copper (Cu) or porous silver (Ag). Since the first buffer layer 160 includes a conductive material such as a porous metal, the first group of first upper pads 150 a may be electrically connected to at least one of the plurality of through electrodes 130 through the first buffer layer 160 .

[0044] The second semiconductor chip 200 may be disposed on the first semiconductor chip 100, and may include a second substrate 210, a second circuit layer 220, a second insulating layer 240, and a plurality of second lower pads 250. The second semiconductor chip 200 may have a flat lower surface corresponding to the lower surfaces of the second insulating layer 240 and the plurality of second lower pads 250. For example, the lower surface of the second insulating layer 240 and the lower surface of the second lower pads 250 exposed from the second insulating layer 240 may be substantially coplanar with each other. Since the first semiconductor chip 100 and the second semiconductor chip 200 may have substantially the same or similar structures, the same or similar components may be represented by the same or similar reference numerals, and repeated descriptions of the same components may be omitted below. For example, the second substrate 210 may have substantially the same characteristics as the first substrate 110 as described above.

[0045] The second circuit layer 220 may be disposed on the front surface or active surface of the second substrate 210 , and may include a second wiring structure 225 connected to the active region and a second interlayer insulating layer 221 surrounding the second wiring structure 225 .

[0046] The second interlayer insulating layer 221 may include flowable oxide (FOX), tonn SilaZen (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), flowable CVD (FCVD) oxide or a combination thereof. At least a portion of the region surrounding the second wiring structure 225 of the second interlayer insulating layer 221 may be formed as a low-k layer. The second interlayer insulating layer 221 may be formed using CVD, a flowable CVD process or a spin coating process.

[0047] The second wiring structure 225 can be formed into a multilayer structure, including, for example, a wiring pattern and a through hole, the wiring pattern including aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W) or a combination thereof. A barrier film including titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN) can be provided between the wiring pattern and / or the through hole and the second interlayer insulating layer 221. The various devices 215 in the integrated circuit can be provided on the front surface of the second substrate 210. In this case, the second wiring structure 225 can be electrically connected to the various devices 215 through an interconnection portion (e.g., a contact plug). The individual devices 215 may include: field effect transistors (FETs), such as planar FETs and FinFETs; memory devices, such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) and resistive random access memory (RRAM); logic devices, such as AND, OR, NOT; and various active and / or passive devices, such as system large scale integration (LSI), complementary metal oxide semiconductor (CMOS) image sensor (CIS), microelectromechanical system (MEMS).

[0048] The second insulating layer 240 (or "second lower insulating layer") may be disposed below the second substrate 210 or the second circuit layer 220, and may be formed to surround a plurality of second lower pads 250. The second insulating layer 240 may include an insulating material bonded and coupled to the first insulating layer 140 of the first semiconductor chip 100. For example, the second insulating layer 240 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN). That is, at least a portion of the second insulating layer 240 may be bonded to the first insulating layer 140, and may form a "bonding interface" that bonds and couples the first semiconductor chip 100 to the second semiconductor chip 200. The lower surface of the second insulating layer 240 may be substantially coplanar with the lower surfaces of the plurality of second lower pads 250. The second insulating layer 240 may have similar properties to the first insulating layer 140.

[0049] The plurality of second lower pads 250 may be bonded to the first upper pads 150 of the first semiconductor chip 100, thereby physically and electrically coupling the first semiconductor chip 100 to the second semiconductor chip 200. The plurality of second lower pads 250 may include a first group of second lower pads 250a and a second group of second lower pads 250b. Figure 3 As shown, the width of the first group of second lower pads 250a in a direction parallel to the upper surface of the second substrate 210 (e.g., the X direction or the Y direction) may be substantially equal to the first width W1 of the first group of first upper pads 150a. The width of the second group of second lower pads 250b may be substantially the same as the width of the second group of first upper pads 150b. For example, Figure 3 As shown, the first width W1 of the first group of second lower pads 250a may be greater than the second width W2 of the second group of second lower pads 250b. The side surface and the upper surface of the first group of second lower pads 250a may be covered by the second buffer layer 260. The side surface of the second group of second lower pads 250b may be in direct contact with the second insulating layer 240. Each second lower pad 250 may include a second seed layer 253a and 253b (covering the side surface and the upper surface of the second lower conductive layer 253a and 253b) and a second lower conductive layer 255a and 255b. The second lower conductive layer 255a and 255b may include at least one of copper (Cu), nickel (Ni), gold (Au) and silver (Ag). The second seed layer 253a and 253b may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN). The plurality of second lower pads 250 may have similar characteristics to the plurality of first upper pads 150.

[0050] The second buffer layer 260 may cover the side surfaces and the upper surface of the first group of second lower pads 250a in the plurality of second lower pads 250. The second buffer layer 260 may alleviate the expansion of the first group of second lower pads 250a during the thermal compression process of bonding and coupling the first semiconductor chip 100 to the second semiconductor chip 200. The second buffer layer 260 may improve the reliability of direct bonding by alleviating the expansion characteristics of the first group of second lower pads 250a. The second buffer layer 260 may have the same or similar characteristics as the above-mentioned first buffer layer 160. The first group of second lower pads 250a may be electrically connected to the second wiring structure 225 through the second buffer layer 260.

[0051] The bonding and coupling of the first semiconductor chip 100 and the second semiconductor chip 200 may be performed through the following operations.

[0052] First, a flat surface may be formed by applying a polishing process to an upper surface of the first insulating layer 140 and a lower surface of the second insulating layer 240. The polishing process may include a chemical mechanical polishing (CMP) process.

[0053] Thereafter, the upper surface of the first insulating layer 140 and the lower surface of the second insulating layer 240 may be disposed to face each other, and pressure may be applied to form coupling by a force (eg, van der Waals force).

[0054] Subsequently, through a low temperature annealing process, the upper surface of the first insulating layer 140 and the lower surface of the second insulating layer 240 may be coupled to each other and the coupling may be strengthened. The low temperature annealing process may be performed at, for example, about 100° C. to 200° C. The embodiments of the present disclosure are not limited to the above embodiments.

[0055] After the upper surface of the first insulating layer 140 and the lower surface of the second insulating layer 240 are coupled to each other, the upper surfaces of the plurality of first upper pads 150 and the lower surfaces of the plurality of second lower pads 250 may be coupled to each other through interdiffusion through a high temperature annealing process performed at about 200° C. to 400° C. The embodiments of the present disclosure are not limited to the above-described embodiments.

[0056] Since the width of the first group of first upper pads 150a and the first group of second lower pads 250a is greater than the width of the second group of first upper pads 150b and the second group of second lower pads 250b, the expansion characteristics of the first group of pads during heat treatment may be greater than the second group of pads, which may hinder the stability of coupling. In example embodiments, by including the first buffer layer 160 and the second buffer layer 260 surrounding the first group of pads, the expansion characteristics of the first group of pads may be mitigated, and a bond with improved reliability may be obtained.

[0057] exist Figure 2AIn the embodiment, both the first buffer layer 160 and the second buffer layer 260 may exist, but in example embodiments, only the first buffer layer 160 or only the second buffer layer 260 may exist.

[0058] After bonding, the interface of the first insulating layer 140 and the second insulating layer 240 may not be obvious. The interface of the plurality of first upper pads 150 and the plurality of second lower pads 250 may also not be obvious. In example embodiments, "the first insulating layer 140 and the second insulating layer 240", "the plurality of first upper pads 150 and the plurality of second lower pads 250", "the first buffer layer 160 and the second buffer layer 260" may each be described as an integrated component. For example, the first insulating layer 140 and the second insulating layer 240 may be referred to as an integrated bonding insulating layer 140 and 240. The plurality of first upper pads 150 and the plurality of second lower pads 250 may be referred to as a plurality of bonding pads 150 and 250. The first buffer layer 160 and the second buffer layer 260 may be referred to as a bonding buffer layer 160 and 260.

[0059] References Figures 1 to 2B The description relates to an example embodiment of a semiconductor package. In some embodiments, in the portion where the first semiconductor chip 100 and the second semiconductor chip 200 are bonded to each other, the number and shape of the plurality of first upper pads 150 and the plurality of second lower pads 250 and the spacing therebetween may vary, and some of the pads may be dummy pads that are not electrically connected to other components.

[0060] In the following description, references to Figures 1 to 2B Description of duplicate description.

[0061] Figures 3 to 15 is shown with Figure 2A A plan view of a modified example related to the area "A" in FIG. Figures 3 to 15 The descriptions herein relate to example embodiments, and the bonding and coupling between the first semiconductor chip 100 and the second semiconductor chip 200 may vary. Figures 3 to 15 Modification Examples of the Embodiments Applied to the First Semiconductor Chip 100 and the Second Semiconductor Chip 200 may be varied. For example, the region “A” on the first semiconductor chip 100 may have Figure 4 and the area “A” under the second semiconductor chip 200 may have Figure 5 That is, various modification examples for the first semiconductor chip 100 and the second semiconductor chip 200 may be mixed within a compatible range.

[0062] refer to Figure 3, there may be a bonding film BF between the first insulating layer 140 and the second insulating layer 240. The bonding film BF may include a material that facilitates bonding and coupling between the first semiconductor chip 100 and the second semiconductor chip 200. The bonding film BF may include the same or different materials as the first insulating layer 140 and the second insulating layer 240. For example, the bonding film BF may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0063] refer to Figure 4 , the first buffer layer 160 may surround the side surface of the first group of first upper pads 150a. The lower surface of the first group of first upper pads 150a may be in direct contact with at least one of the plurality of through electrodes 130. Figure 2A and Figure 2B Similar to the described example, the first buffer layer 160 may cover the side surface of the first group of first upper pads 150a, thereby reducing the expansion characteristics of the first group of first upper pads 150a during heat treatment. As in the example embodiment, when the first group of first upper pads 150a are in direct contact with at least one of the plurality of through electrodes 130, the first buffer layer 160 may use an insulating material (e.g., a polymer or a porous metal). The Young's modulus of the polymer contained in the first buffer layer 160 may be lower than the Young's modulus of the conductive material in the first upper pad 150a. Similarly, the second buffer layer 260 may surround the side surface of the first group of second lower pads 250a. The upper surface of the first group of second lower pads 250a may be in direct contact with the second circuit layer 220 and may be directly electrically connected to the second wiring structure 225.

[0064] refer to Figure 5 , the first buffer layer 160 may cover the side surface and the lower surface of the first group of first upper pads 150a. The first group of first upper pads 150a may penetrate the lower surface of the first buffer layer 160, and may be directly in contact with and electrically connected to at least one of the plurality of through electrodes 130. The first buffer layer 160 may include a conductive material (e.g., a porous metal) and an insulating material (e.g., a polymer). Similarly, the first group of second lower pads 250a penetrate the upper surface of the second buffer layer 260, and may be in direct contact with the second circuit layer 220, and may be electrically connected to the second wiring structure 225.

[0065] refer to Figure 6 , the plurality of first upper pads 150 and the plurality of second lower pads 250 may contact each other and be offset from each other. For example, the plurality of first upper pads 150 and the plurality of second lower pads 250 may be offset from each other in a horizontal direction (e.g., X direction) by a predetermined distance L. At least a portion of the upper surface of the first upper pad 150 may contact at least a portion of the lower surface of the second lower pad 250.

[0066] refer to Figure 7 The first semiconductor chip 100 may further include a first connection conductor 170. The first connection conductor 170 may be disposed between the plurality of first upper pads 150 and the first substrate 110 in the first insulating layer 140. The first connection conductor 170 may be connected to the upper surface (or Figure 1 The first buffer layer 160 is in direct contact with the rear surface BA shown, and at least one of the plurality of through electrodes 130 may be electrically connected to the first upper pad 150. Even in this case, the first buffer layer 160 may alleviate the expansion characteristics of the first group of first upper pads 150a during the bonding process. Therefore, even when the first width W1 of the first group of first upper pads 150a is greater than the second width W2 of the second group of first upper pads 150b, the reliability of the bonding may be improved. The width of the first connecting conductor 170 in the horizontal direction (e.g., the X direction) may be greater than the first width W1 and the second width W2. The first connecting conductor 170 may include at least one of the following: aluminum (Al), copper (Cu), or an alloy of these components. The embodiments of the present disclosure are not limited to the above-described embodiments.

[0067] The second semiconductor chip 200 may include a second connection conductor 270 in contact with the upper surface of the plurality of second lower pads 250 under the second substrate 210. In an example embodiment, the second connection conductor 270 may exist only on the first group of second lower pads 250a, or may exist only on the second group of second lower pads 250b. The second connection conductor 270 may have the same or similar properties as the first connection conductor 170 of the first semiconductor chip 100. The second connection conductor 270 may be disposed between the plurality of second lower pads 250 and the second circuit layer 220 in the second insulating layer 240. The second connection conductor 270 may be in direct contact with the lower surface of the second circuit layer 220, and the second wiring structure 225 may be electrically connected to the second lower pads 250.

[0068] refer to Figure 8, the second group of first upper pads 150b and the second group of second lower pads 250b may be dummy pads that are not electrically connected to the surrounding components. The first connecting conductor 170 may be electrically connected and directly contacted with at least one of the plurality of through electrodes 130 below the first group of first upper pads 150a. The second connecting conductor 270 may be electrically connected and directly contacted with the second wiring structure 225 on the first group of second lower pads 250a. The first connecting conductor 170 may increase the expansion characteristics of the adjacent first group of first upper pads 150a when they are joined. Therefore, even when the first width W1 of the first group of first upper pads 150a is substantially the same as the second width W2 of the second group of second upper pads 150b, the expansion characteristics of the first group of first upper pads 150a may be greater. The first buffer layer 160 covering the side surface and the lower surface of the first group of first upper pads 150a reduces the expansion characteristics of the first group of first upper pads 150a and can improve the reliability of the joining. Similarly, the second buffer layer 260 may alleviate the expansion characteristics of the adjacent first group of second lower pads 250 a and may improve the reliability of bonding.

[0069] refer to Fig. 9 , the first group of first upper pads 150a may penetrate the first buffer layer 160 and may directly contact the first connection conductor 170. Therefore, the first buffer layer 160 may include an insulating material and may also include a conductive material. The first group of second lower pads 250a may penetrate the second buffer layer 260 and may directly contact the second connection conductor 270, and the second buffer layer 260 may include an insulating material and may also include a conductive material. Fig. 9 Each component in can have a Figure 8 Each corresponding component is described with the same or similar features.

[0070] refer to Fig.10 ,and Figure 8 and Fig. 9 Unlike the example embodiments in the embodiment of the present invention, the first buffer layer 160 may cover the side surfaces of the first group of first upper pads 150a, and the lower surfaces of the first group of first upper pads 150a may be in direct contact with the first connecting conductor 170. Similarly, the second buffer layer 260 may cover the side surfaces of the first group of second lower pads 250a, and the upper surfaces of the first group of second lower pads 250a may be in direct contact with the lower surface of the second circuit layer 220 and may be electrically connected to the second wiring structure 225.

[0071] refer to Fig.11, the first buffer layer 160 may cover the side surface of the first group of first upper pads 150a, and may also cover the side surface of the second group of first upper pads 150b. The first buffer layer 160 may reduce the expansion of the adjacent plurality of first upper pads 150 during bonding, and may improve the reliability of bonding. The second buffer layer 260 may also cover the side surface of the first group of second lower pads 250a and the second group of second lower pads 250b, and may improve the reliability of bonding. The embodiment in which the first buffer layer 160 and the second buffer layer 260 cover the plurality of first upper pads 150 and the second lower pads 250 is not limited thereto, and may be varied as in the above-described example embodiments.

[0072] refer to Fig.12 In addition to the configuration that the second group of first upper pads 150b may be spaced apart from the upper surface of the first substrate 110 by the thickness of the first connection conductor 170, the second group of first upper pads 150b may have the same Figure 8 The second group of second lower pads 250 b may be spaced apart from the second circuit layer 220 by the thickness of the second connecting conductor 270 .

[0073] refer to Fig.13 , the second width W2 of the second group of first upper pads 150b may be greater than the first width W1 of the first group of first upper pads 150a. The first buffer layer 160 may cover the side surfaces of the second group of first upper pads 150b and the first group of first upper pads 150a. The first buffer layer 160 (adjacent to the first group of first upper pads 150a) may alleviate the expansion characteristics of the first group of first upper pads 150a increased by the first connecting conductor 170. The first buffer layer 160 (adjacent to the second group of first upper pads 150b) may alleviate the increased expansion characteristics of the second group of first upper pads 150b having the second width W2. In example embodiments, the width of the first buffer layer 160 (covering the first group of first upper pads 150a) and the width of the first buffer layer 160 (covering the second group of second upper pads 150b) may be the same or different.

[0074] For example, when the expansion of the first group of first upper pads 150a needs to be further reduced, the width of the first buffer layer 160 (in contact with the first group of first upper pads 150a) may be greater than the width of the first buffer layer 160 in contact with the second group of first upper pads 150b. The second buffer layer 260 of the second semiconductor chip 200 may have the same or similar properties as the first buffer layer 160 of the first semiconductor chip 100.

[0075] refer to Fig.14, the first semiconductor chip 100 may include a first buffer insulating layer 165 that divides the first insulating layer 140 into a first inner insulating layer 140_1 and a first outer insulating layer 140_2. The first inner insulating layer 140_1 may surround the side surface of the first connecting conductor 170 on the first substrate 110. The first buffer insulating layer 165 may be disposed on the first inner insulating layer 140_1 and the first connecting conductor 170, and may contact the side surface of the first group of first upper pads 150a and the lower surface of the second group of first upper pads 150b. The first group of first upper pads 150a may include a first layer portion 150aL on the first buffer insulating layer 165 and an extension portion 150aV extending from the lower surface of the first layer portion 150aL, the extension portion 150aV penetrating the first buffer insulating layer 165 and contacting the first connecting conductor 170. The first outer insulating layer 140_2 may surround the first layer portion 150aL on the first buffer insulating layer 165.

[0076] Since the first layer portion 150aL is spaced apart from the first connection conductor 170, the expansion of the first group of first upper pads 150a (increased due to the first connection conductor 170) can be reduced, and therefore, the reliability of the bonding can be improved. The second semiconductor chip 200 may include a second connection conductor 270 (having similar characteristics to the first connection conductor 170) and a second buffer insulating layer 265 (having similar characteristics to the first buffer insulating layer 165). The second connection conductor 270 may contact the upper surface of the first group of second lower pads 250a below the second circuit layer 220. The second inner insulating layer 240_1 may surround the side surface of the second lower pad 250a. The second buffer insulating layer 265 may surround the first group of second lower pads 250a below the second inner insulating layer 240_1, and may contact the upper surface of the second group of second lower pads 250b. The second outer insulating layer 240_2 may surround the first group of second lower pads 250a and the second group of second lower pads 250b below the second buffer insulating layer 265.

[0077] refer to Fig.15 , the first semiconductor chip 100 may further include a first buffer layer 160 covering the side surface of the first group of first upper pads 150a. Therefore, even when the first width W1 of the first group of first upper pads 150a in contact with the first connecting conductor 170 is greater than the second width W2 of the second group of second upper pads 150b, the expansion characteristics of the first group of first upper pads 150a may be alleviated and the bonding reliability may be improved. The second semiconductor chip 200 may include a second buffer layer 260. The description of the above elements will be omitted.

[0078] FIG. 16A to FIG. 16C It is shown Fig.14 and Fig.15Perspective diagram of the modified example in and a graph indicating experimental data. FIG. 16A to FIG. 16C The description will refer to Figure 14 to Figure 15 conduct.

[0079] Fig.16A The image in may represent a conductive structure including a layer portion and an extension portion, and Fig.16A The UBM1, UBM2 and LB in the image can be respectively Figure 14 to Figure 15 UBM1 may correspond to the first extension portion 150aV or the second extension portion 250aV, UBM2 may correspond to the first layer portion 150aL or the second layer portion 250aL, and LB may correspond to the first connection conductor 170 or the second connection conductor 270. Fig. 16B It shows that as the thickness h of UBM1 decreases from 2.8 μm to 0.5 μm, UBM2 expands more significantly during the heat treatment. Fig. 16C The figure in also shows that the average expansion value of UBM2 increases with temperature when the thickness of UBM1 changes from 0.5μm to 2.8μm.

[0080] The UMB2 electrically connected to the LB may have a greater expansion characteristic during the bonding heat treatment process. As the thickness of the UBM1 increases, that is, the distance between the UBM2 and the LB increases, the expansion characteristic may be mitigated. For example, when the thickness of the UBM1 is 0.5 μm, during the heat treatment at 300°C, the average expansion value of the UBM2 may be 220 angstroms. and 240 Angstroms However, when the thickness of UBM1 is 2.8 μm, the average expansion value of UBM2 can be between 160 Å and 2.8 μm. and 180 Angstroms Since the first group of first upper pads 150a are in contact with the first connection conductor 170, even if the upper pads 150a expand more significantly than the second group of first upper pads 150b during the heat treatment, the expansion of the first layer portion 150aL can be mitigated by ensuring a sufficient thickness of the first extension portion 150aV. Fig.15 As shown, by including the first buffer layer 160 in contact with the first layer portion 150aL, the expansion characteristics of the first layer portion 150aL can be further alleviated, and hybrid coupling can be stably performed by heat treatment. The description of the first group of second lower pads 250a, the second connecting conductor 270, and the second buffer layer 260 overlapping with the above description will not be provided.

[0081] refer to Fig.17, the first group of first upper pads 150a (surrounded by the first buffer layer 160) may be dummy pads that are not electrically connected to other components. The first width W1 of the first group of first upper pads 150a as dummy pads may be greater than the second width W2 of the second group of second upper pads 150b electrically connected to other components. The first buffer layer 160 may surround at least a portion of the side surface and the lower surface of the first group of first upper pads 150a. In addition to including a conductive material (e.g., a porous metal), the first buffer layer 160 may also include an insulating material (e.g., a polymer). The first group of second lower pads 250a surrounded by the second buffer layer 260 may have the same or similar properties as the first group of first upper pads 150a. The second buffer layer 260 may cover at least a portion of the side surface and the upper surface of the first group of second lower pads 250a, and may have the same or similar properties as the first buffer layer 160.

[0082] refer to Fig.18 , the first group of first upper pads 150a and the second group of first upper pads 150b may be dummy pads that are not electrically connected to other components. Fig.18 In a sub-region of region "A" in , there may be a third group of pads that electrically connect the first semiconductor chip 100 to the second semiconductor chip 200. In a direction perpendicular to the upper surface of the first substrate 110 (e.g., the Z direction), the first thickness H1 of the first group of first upper pads 150a may be greater than the second thickness H2 of the second group of second upper pads 150b. Even when the first width W1 of the first upper pads 150a is substantially the same as the second width W2 of the second group of first upper pads 150b, during the bonding process, the expansion characteristics of the first group of first upper pads 150a may be greater than the expansion characteristics of the second group of first upper pads 150b. The first buffer layer 160 may surround at least a portion of the side surface and the lower surface of the first group of first upper pads 150a, and may mitigate the expansion characteristics of the first group of first upper pads 150a. The first group of second lower pads 250a, the second group of second lower pads 250b, and the second buffer layer 260 have the same or similar characteristics as the first group of first upper pads 150a, the second group of first upper pads 150b, and the first buffer layer 160, respectively.

[0083] refer to Fig.19 The semiconductor package 10B in the example embodiment may have the same configuration as the reference 1 except that the first semiconductor chip 100 includes a plurality of second semiconductor chips 200A, 200B, 200C, and 200D stacked in a vertical direction (Z-axis direction) and a molding member 290. Figures 1 to 18 Examples of the description have the same or similar features.

[0084] For example, the first semiconductor chip 100 may include a plurality of first upper pads 150. The plurality of first upper pads 150 may include reference Figures 2A to 18 The first group of first upper pads 150a and the second group of first upper pads 150b are described. Each of the plurality of second semiconductor chips 200A, 200B, 200C, and 200D may include a plurality of second lower pads 250. The plurality of second lower pads 250 may include reference Figures 2A to 18 The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may include a plurality of second upper pads 255 and a second upper insulating layer 245 having the same or similar properties as the plurality of first upper pads 150 and the first insulating layer 140, respectively.

[0085] The second lower insulating layer 240 is bonded to the second upper insulating layer 245, and a bonding interface where a plurality of second lower pads 250 are bonded to a plurality of second upper pads 255 may be formed between the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may be electrically connected to each other through the second lower pads 250 and the second upper pads 255 bonded to each other. Among the plurality of second semiconductor chips 200A, 200B, 200C, and 200D, the lowermost second semiconductor chip 200A may be electrically connected to the first semiconductor chip 100 through the plurality of second lower pads 250 and the plurality of first upper pads 150 of the first semiconductor chip 100.

[0086] In addition to the configuration that may further include the second through-electrode 230 to form a mutual electrical connection path, the plurality of second semiconductor chips 200A, 200B, 200C, and 200D may have the same configuration as the reference Figures 1 to 18 The second semiconductor chip 200D may have the same or similar characteristics as described above. However, the uppermost second semiconductor chip 200D may not have the second through electrode 230. In example embodiments, the uppermost second semiconductor chip 200D may have a relatively large thickness. Therefore, in example embodiments, more or fewer semiconductor chips than the example shown in the figure may be stacked on the first semiconductor chip 100. For example, less than three or more than five semiconductor chips may be stacked on the first semiconductor chip 100.

[0087] As an example, the first semiconductor chip 100 may be a buffer chip or a control chip including a plurality of logic devices or memory devices. The first semiconductor chip 100 may transmit signals from a plurality of second semiconductor chips 200A, 200B, 200C, and 200D stacked on top to an external entity, and may also transmit signals and power from an external entity to the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may be memory chips including volatile memory devices such as DRAM and SRAM or non-volatile memory devices such as PRAM, MRAM, FeRAM, or RRAM.

[0088] The molding member 290 may be disposed on the first semiconductor chip 100 and may encapsulate at least a portion of each of the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The molding member 290 may be formed to expose the upper surface of the uppermost second semiconductor chip 200D. However, in an example embodiment, the molding member 290 may be formed to cover the upper surface of the uppermost second semiconductor chip 200D. The molding member 290 may include, for example, epoxy molding compound (EMC), but the material of the molding member 290 is not limited to any specific example.

[0089] Fig. 20A is a plan view illustrating a semiconductor package according to example embodiments. Fig. 20B is shown along Fig. 20A A cross-sectional view of a section taken along line II-II' in FIG.

[0090] refer to Fig. 20A and Fig. 20B , the semiconductor package 10C in the example embodiment may include a package substrate 600, an interposer substrate 700, and at least one package structure PS. In addition, the semiconductor package 10C may further include a logic chip (or processor chip) 800, which is disposed adjacent to the package structure PS on the interposer substrate 700. The package structure PS may have the same Figures 1 to 18 The package structure PS can be implemented as Fig.19 The semiconductor package 10B shown. The embodiments of the present disclosure are not limited to the above-described embodiments.

[0091] The package substrate 600 may be a support substrate on which the interposer substrate 700, the logic chip 800, and the package structure PS are mounted, and may be a semiconductor package substrate including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring substrate, etc. The package substrate 600 may include a lower pad 612, an upper pad 611, and a wiring circuit 613 electrically connecting the lower pad 612 to the upper pad 611. Depending on the type of substrate, the body of the package substrate 600 may include different materials. For example, when the package substrate 600 is a printed circuit board, the package substrate 600 may be a main copper-clad laminate, or may be a wiring layer additionally stacked on one or both surfaces of the copper-clad laminate. The upper pad 611, the lower pad 612, and the wiring circuit 613 may form an electrical path connecting the lower surface and the upper surface of the package substrate 600 to each other. The external connection bump 620 connected to the lower pad 612 may be provided on the lower surface of the package substrate 600. The external connection bump 620 may include, for example, a solder ball.

[0092] The interposer substrate 700 may include a substrate 701, a lower protective layer 703, a lower pad 705, an interconnect structure 710, a conductive bump 720, and a through-hole 730. The package structure PS and the processor chip 800 may be stacked on the package substrate 600 using the interposer substrate 700. The interposer substrate 700 may electrically connect the package structure PS and the processor chip 800 to each other.

[0093] The substrate 701 may be formed of at least one of, for example, silicon, organic matter, plastic, and glass substrates. When the substrate 701 is a silicon substrate, the interposer substrate 700 may be referred to as a silicon interposer. In some embodiments, when the substrate 701 is an organic substrate, the interposer substrate 700 may be referred to as a panel interposer.

[0094] The lower protective layer 703 may be disposed on the lower surface of the substrate 701, and the lower pad 705 may be disposed on the lower protective layer 703. The lower pad 705 may be connected to the through hole 730. The package structure PS and the processor chip 800 may be electrically connected to the package substrate 600 through the conductive bump 720 disposed on the lower pad 705.

[0095] The interconnection structure 710 is disposed on the upper surface of the substrate 701 and may include an interlayer insulating layer 711 and a single-layer wiring structure 712 or a multi-layer wiring structure 712. When the interconnection structure 710 is formed as a multi-layer wiring structure, wiring patterns on different layers may be connected to each other through contact vias. An upper pad 704 connected to the wiring structure 712 may be disposed on the interconnection structure 710. The package structure PS and the processor chip 800 may be connected to the upper pad 704 through a connection bump 139.

[0096] The via 730 may extend from the upper surface to the lower surface of the substrate 701 and may penetrate the substrate 701. For example, the via 730 may extend into the interconnect structure 710 and may be electrically connected to the wiring of the interconnect structure 710. When the substrate 701 is silicon, the via 730 may be referred to as a TSV.

[0097] The interposer substrate 700 may be used to convert or transmit input electrical signals between the package substrate 600 and the package structure PS or the processor chip 800. Therefore, the interposer substrate 700 may not include devices such as active devices or passive devices. Therefore, in example embodiments, the interconnect structure 710 may be disposed below the substrate 701.

[0098] The conductive bumps 720 may be disposed on the lower surface of the interposer substrate 700 and may be electrically connected to the wiring of the interconnect structure 710. The interposer substrate 700 may be mounted on the package substrate 600 through the conductive bumps 720. For example, a portion of the lower pads 705 for power or ground may be integrated and connected together to the conductive bumps 720, so that the number of the lower pads 705 may be greater than the number of the conductive bumps 720.

[0099] The logic chip or processor chip 800 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, and an application-specific semiconductor (ASIC). Depending on the type of integrated circuit included in the logic chip 800, the semiconductor package 10B may be referred to as a server-oriented semiconductor package or a mobile-oriented semiconductor package. Therefore, in an example embodiment, the number of logic chips 800 and / or package structures PS mounted on the interposer substrate 700 may be greater or less than the example shown in the figure.

[0100] FIG. 21A to FIG. 21E is manufactured in order as shown Figure 2A A cross-sectional view of the process of some components of a semiconductor package.

[0101] refer to Fig.21A , a plurality of recessed regions RS1 and RS2 having different widths may be formed on the first insulating layer 140 on the first substrate 110. The plurality of recessed regions RS1 and RS2 may be formed using a photosensitive material layer and a photolithography process. The width of the first recessed region RS1 may be greater than the width of the second recessed region RS2.

[0102] refer to Fig.21B, an initial first buffer layer 160' covering the upper surface of the first insulating layer 140 and the side surface of the first insulating layer 140 exposed by the plurality of recessed regions RS1 and RS2, and an initial first buffer layer 160' covering the upper surface of the first substrate 110 and the upper surface of at least one of the plurality of through electrodes 130 may be formed. The initial first buffer layer 160' may include a porous metal and may be formed using an electroplating process. The voids contained in the porous metal of the initial first buffer layer 160' may be formed, for example, by forming a mixed metal of copper (Cu) and zinc (Zn) using an electroplating process and selectively etching only zinc (Zn).

[0103] refer to Fig. 21C , the first buffer layer 160' may be formed by removing the remaining portion of the initial first buffer layer 160' except for the portion formed in the first recessed region RS1. The removal of the initial first buffer layer 160' may be performed, for example, using a photolithography process. After forming the first buffer layer 160', the first width W1 of the first recessed region RS1 may be greater than the second width W2 of the second recessed region RS2.

[0104] refer to Fig.21D , an initial first seed layer 153' may be formed to cover the first insulating layer 140, the first buffer layer 160, the upper surface of the first substrate 110 exposed by the second recessed region RS2, and the upper surface of at least one of the plurality of through electrodes 130. The initial first seed layer 153' may be formed using, for example, an electroplating process, a PVD process, or a CVD process.

[0105] refer to Fig.21E , an initial first upper conductive layer 155' may be formed on the initial first seed layer 153'. The initial first upper conductive layer 155' may be formed by, for example, an electroplating process, a PVD process, or a CVD process. Figure 2A , through the planarization process, the initial first upper conductive layer 155' and the initial first seed layer 153' at a level higher than the upper surface of the first insulating layer 140 may be removed, and a plurality of first upper pads 150 may be formed. FIG. 21A to FIG. 21E The described manufacturing process may also be applied to the second insulating layer 240 and the plurality of second lower pads 250 of the second semiconductor chip 200 .

[0106] In the following description of the manufacturing method, reference will no longer be made to FIG. 21A to FIG. 21E The descriptions overlap the descriptions.

[0107] FIG. 22A to FIG. 22C is manufactured in order as shown Figure 4 A cross-sectional view of the process of some components of a semiconductor package.

[0108] refer to Fig.22A, a plurality of recessed regions RS1 and RS2 may be formed by patterning the first insulating layer 140, and an initial first buffer layer 160' may be formed. The initial first buffer layer 160' may include a porous metal and a polymer. When the initial first buffer layer 160' includes a polymer, the initial first buffer layer 160' may be formed using, for example, a PVD process or a CVD process. When the initial first buffer layer 160' includes a porous metal, the same method as in reference may be used. Fig.21B The initial first buffer layer 160 ′ is formed in the same manner as described above.

[0109] refer to Fig. 22B , the first buffer layer 160 may be formed by removing a portion of the preliminary first buffer layer 160 ′ except for a side surface portion exposed by the first recess region RS1 .

[0110] refer to Fig. 22C , an initial first seed layer 153' may be formed to cover the first insulating layer 140, the first buffer layer 160, the upper surface of the first substrate 110 exposed by the plurality of recessed regions RS1 and RS2, and the upper surface of at least one of the plurality of through electrodes 130. An initial first upper conductive layer 155' may be formed on the initial first seed layer 153'. Thereafter, referring to Figure 4 , the preliminary first upper conductive layer 155 ′ and the preliminary first seed layer 153 ′ at a level higher than the upper surface of the first insulating layer 140 may be removed, and a plurality of first upper pads 150 may be formed.

[0111] FIG. 23A to FIG. 23C It shows the manufacturing Fig.14 A cross-sectional view of the process of some components of a semiconductor package.

[0112] refer to Fig.23A , a first connection conductor 170 contacting the through electrode 130 on the first substrate 110 and a first inner insulating layer 140_1 surrounding the side surface of the first connection conductor 170 may be formed on the first substrate 110. In addition, a first buffer insulating layer 165 may be formed on the first inner insulating layer 140_1, and a first outer insulating layer 140_2 may be formed on the first buffer insulating layer 165. The first buffer insulating layer 165 and the first outer insulating layer 140_2 may be formed using, for example, a PVD process, a CVD process, or a spin coating process.

[0113] refer to Fig. 23B The first recessed region RS1 may be formed by etching a portion of the first outer insulating layer 140_2 and the first buffer insulating layer 165 to expose a portion of the upper surface of the first connecting conductor 170. In addition, the second recessed region RS2 having a second width W2 substantially the same as the first width W1 of the first recessed region RS1 may be formed.

[0114] refer to Fig.23C , an initial first seed layer 153' covering the upper surface of the first outer insulating layer 140_2 and the portions exposed by the plurality of recessed regions RS1 and RS2 may be formed, and an initial first upper conductive layer 155' may be formed on the initial first seed layer 153'. Thereafter, referring back to Fig.14 , the preliminary first upper conductive layer 155 ′ and the preliminary first seed layer 153 ′ at a level higher than the upper surface of the first outer insulating layer 140_2 may be removed, and a plurality of first upper pads 150 may be formed.

[0115] According to the above-described example embodiments, by including a buffer layer surrounding a portion of a pad, stacking of semiconductor chips having a high-quality bonding interface may be achieved, and a semiconductor package having improved reliability may be provided.

[0116] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the example embodiments as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip comprising: The first substrate, a plurality of first upper pads on the first substrate, wherein the plurality of first upper pads include a first group of first upper pads and a second group of first upper pads, a first buffer layer surrounding the side surfaces of the first group of first upper pads, a first insulating layer surrounding side surfaces of the second group of first upper pads and side surfaces of the first buffer layer, and a plurality of through electrodes penetrating the first substrate, the plurality of through electrodes being respectively connected to the plurality of first upper pads; and A second semiconductor chip, on the first semiconductor chip, comprises: The second substrate, a plurality of second lower pads, under the second substrate, wherein the plurality of second lower pads include a first group of second lower pads and a second group of second lower pads, a second buffer layer surrounding the side surfaces of the first group of second lower pads, and a second insulating layer surrounding a side surface of the second group of second lower pads and a side surface of the second buffer layer, wherein the first group of first upper pads are in contact with the first group of second lower pads respectively, and The second group of first upper pads are in contact with the second group of second lower pads respectively.

2. The semiconductor package according to claim 1, wherein The first buffer layer includes a first material having a first Young's modulus that is lower than a second Young's modulus of a second material in the plurality of first upper pads, and The second buffer layer includes a third material, the third material has a third Young's modulus, and the third Young's modulus is lower than a fourth Young's modulus of a fourth material in the plurality of second lower pads.

3. The semiconductor package according to claim 1, wherein: In a direction parallel to the upper surface of the first semiconductor chip, a first width of the first group of first upper pads is greater than a second width of the second group of first upper pads.

4. The semiconductor package according to claim 1, wherein: In a direction perpendicular to an upper surface of the first semiconductor chip, a first thickness of the first group of first upper pads is greater than a second thickness of the second group of first upper pads. 5 . The semiconductor package according to claim 1 , further comprising a bonding film between the first insulating layer and the second insulating layer. 6 . The semiconductor package according to claim 1 , further comprising a second connecting conductor contacting upper surfaces of the first group of second lower pads under the second substrate.

7. The semiconductor package according to claim 6, further comprising: a second buffer insulating layer configured to divide the second insulating layer into a second inner insulating layer and a second outer insulating layer, wherein the second inner insulating layer is configured to surround a side surface of the second connecting conductor below the second substrate, wherein the second buffer insulating layer contacts the side surfaces of the first group of second lower pads and the upper surfaces of the second group of second lower pads below the second inner insulating layer and the second connecting conductor, and The second outer insulating layer is configured to surround side surfaces of the first group of second lower pads and side surfaces of the second group of second lower pads under the second buffer insulating layer.

8. The semiconductor package according to claim 7, wherein: The first group of second lower pads comprises: a second layer portion below the second buffer insulating layer, and The second extending portion extends from the upper surface of the second layer portion, penetrates the second buffer insulating layer, and contacts the second connecting conductor.

9. The semiconductor package according to claim 8, wherein: The width of the second extension portion decreases toward the second connecting conductor.

10. The semiconductor package according to claim 7, wherein: The second buffer insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

11. The semiconductor package according to claim 6, wherein: The second connection conductor includes at least one of the following: aluminum Al, copper Cu, and an alloy of Al and Cu.

12. The semiconductor package according to claim 1, wherein The first buffer layer comprises a polymer or a porous metal, and Wherein, the second buffer layer includes the polymer or the porous metal.

13. The semiconductor package according to claim 1, wherein The first insulating layer and the second insulating layer include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

14. A semiconductor package, comprising: A first semiconductor chip and a second semiconductor chip are stacked in a vertical direction, Wherein, the first semiconductor chip comprises: A plurality of first upper pads, comprising: a first upper conductive layer, and a first upper seed layer surrounding a side surface of the first upper conductive layer and a lower surface of the first upper conductive layer; a first buffer layer extending along at least one periphery of a first upper pad in a first group of first upper pads in the plurality of first upper pads; and a first insulating layer surrounding the first upper pads in the second group of first upper pads in the plurality of first upper pads and the first buffer layer, Wherein, the second semiconductor chip comprises: A plurality of second lower pads, including: a second lower conductive layer, and a second lower seed layer surrounding a side surface of the second lower conductive layer and an upper surface of the second lower conductive layer, the second lower conductive layer being electrically connected to the plurality of first upper pads; a second buffer layer extending along at least one periphery of a second lower pad in a first group of second lower pads in the plurality of second lower pads; and a second insulating layer surrounding the second lower pads in the second group of second lower pads in the plurality of second lower pads and the second buffer layer, Wherein, the first buffer layer and the second buffer layer include polymer or porous metal.

15. The semiconductor package according to claim 14, wherein: At least one of the plurality of first upper pads is in direct contact with at least one of the plurality of second lower pads.

16. The semiconductor package according to claim 14, wherein: The first upper conductive layer and the second lower conductive layer include copper (Cu), and Wherein, the first upper seed layer and the second lower seed layer include at least one of titanium Ti, titanium nitride TiN, tantalum Ta and tantalum nitride TaN.

17. A semiconductor package, comprising: A first semiconductor chip including a plurality of upper pads; as well as The second semiconductor chip comprises: a plurality of lower pads, including a first group of lower pads and a second group of lower pads contacting upper surfaces of the plurality of upper pads, a connecting conductor in contact with the upper surface of the first group of lower pads, an inner insulating layer, surrounding the side surface of the connecting conductor, a buffer insulating layer in contact with side surfaces of the first group of lower pads and upper surfaces of the second group of lower pads, and an outer insulating layer surrounding side surfaces of the first group of lower pads and side surfaces of the second group of lower pads below the buffer insulating layer, Wherein, the first group of lower pads includes: layer portion, surrounded by the outer insulating layer, and The extension portion extends from the upper surface of the layer portion, penetrates the buffer insulating layer and contacts the lower surface of the connection conductor.

18. The semiconductor package according to claim 17, wherein: The buffer insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride. 19 . The semiconductor package according to claim 17 , further comprising a buffer layer covering the layer portion in the outer insulating layer.

20. The semiconductor package according to claim 19, wherein In a direction perpendicular to the lower surface of the connection conductor, a thickness of the first group of lower pads is greater than a thickness of the second group of lower pads.

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