Funnel type silicon capacitor

Abstract

The invention discloses a funnel type silicon capacitor, and aims to solve the problem that the performance of the capacitor is reduced due to the fact that the existing silicon capacitor adopts a deep groove with a high depth-to-width ratio, and the deep groove is invalid due to hollowness caused by opening blockage in the hole filling process. The structure comprises a silicon substrate, a first electrode layer, a first dielectric layer, a second electrode layer, an insulating layer, a through hole lead and two surface bonding pads, a deep groove is formed in the top surface of the silicon substrate, the aperture of the deep groove is gradually reduced in the direction from the top surface of the silicon substrate to the bottom surface of the silicon substrate to form a funnel shape, and the surface bonding pads are arranged on the bottom surface of the silicon substrate. A continuous forming surface is formed on the silicon substrate and the side wall and the bottom surface of the deep groove, and the first electrode layer, the first dielectric layer, the second electrode layer and the insulating layer are sequentially formed on the forming surface and fill and level up the deep groove. By arranging the funnel-shaped deep groove with the large upper part and the small lower part, the probability that the performance of the silicon capacitor is influenced by hollowness caused by blockage of the groove opening of the deep groove is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a funnel-shaped silicon capacitor. Background Art

[0002] Silicon capacitors are mainly used in communications, military and automobiles, and can play the role of bypass, filtering, coupling and decoupling. Silicon capacitors use semiconductor manufacturing technology to prepare deep trenches with high aspect ratios on silicon substrates, and deposit capacitor stacking structures in the deep trenches. The biggest advantage of silicon capacitors is that they have very high capacitance density. The higher the capacitance density, the higher the capacitance per unit area, and the more miniaturized and micro-miniaturized the device can be.

[0003] The aspect ratio of deep trenches with high aspect ratio is as high as 20:1, and the hole filling technology is relatively difficult.

[0004] A silicon capacitor with a publication number of CN116646341A discloses a silicon capacitor, comprising: a first electrode and a second electrode arranged opposite to each other, both of which are made of silicon material; a dielectric layer arranged between the first electrode and the second electrode; a metal layer sandwiched between the dielectric layer and the first electrode and / or the second electrode, and an ohmic contact is formed between the metal layer and the first electrode and / or the second electrode. In this application, the deep trench with a high aspect ratio is easily blocked during the hole filling process, resulting in a hollow interior of the trench, which affects the performance of the capacitor. Summary of the invention

[0005] The present invention overcomes the disadvantage that the existing silicon capacitors use deep trenches with high aspect ratios, which cause the deep trenches to become hollow due to blocking of the openings during the hole filling process, making the deep trenches ineffective and thus reducing the performance of the capacitors, and provides a funnel-shaped silicon capacitor that can reduce the hollowness of the deep trenches, thereby improving the efficiency of the silicon capacitors.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions: A funnel-shaped silicon capacitor comprises a silicon substrate, a first electrode layer, a first dielectric layer, a second electrode layer, an insulating layer, a through-hole lead and two surface pads, wherein a deep groove is provided on the top surface of the silicon substrate, and the diameter of the deep groove gradually decreases along the direction from the top surface to the bottom surface of the silicon substrate to form a funnel shape, and the silicon substrate, the sidewall and the bottom surface of the deep groove form a continuous formation surface, and the first electrode layer, the first dielectric layer, the second electrode layer and the insulating layer are successively formed on the formation surface and fill the deep groove.

[0007] The deep groove is wide at the top and narrow at the bottom, forming a funnel shape. During the forming process of the first electrode layer, the first dielectric layer, the second electrode layer, and the insulating layer, it is not easy to block the notch of the deep groove, resulting in the deep groove being hollow, thereby reducing the performance of the silicon capacitor. The inclined sidewalls of the deep groove also make it easier for the first electrode layer, the first dielectric layer, the second electrode layer, and the insulating layer to adhere and form. The funnel-shaped deep groove makes the transition between the silicon substrate, the sidewalls, and the bottom surface of the deep groove more friendly to deposition than the transition of the vertical groove of the BOSCH process, and the first electrode layer, the first dielectric layer, the second electrode layer, and the insulating layer are not easy to break and cause failure.

[0008] Preferably, the deep trench includes an upper opening trench and a lower opening trench, the etching angle of the upper opening trench is 40°~70°, the etching angle of the lower opening trench is 70°~80°, the bottom opening of the upper opening trench and the top opening of the lower opening trench are of the same size and connected. The etching angle of the upper opening trench is smaller than the etching angle of the lower opening trench, wherein the sidewall of the lower opening trench is close to vertical, so that the distance between the first electrode layer and the second electrode layer between the upper and lower sides of the lower opening trench is close, and the performance is close to the performance of silicon capacitors brought by the vertical trench process.

[0009] Preferably, the upper opening groove is obtained by anisotropic etching or angled dry etching.

[0010] Preferably, the small opening groove is obtained by angled deep reactive ion dry etching.

[0011] Preferably, the deep groove array is arranged on the top surface of the silicon substrate. The array arrangement includes a horizontal row arrangement and a concentric ring arrangement. In the horizontal row arrangement, each deep groove arranged horizontally is arranged at an equal distance, and each deep groove arranged vertically is arranged at an equal distance. In the concentric ring arrangement, each deep groove in the same ring is arranged at an equal distance. In some possible implementations, adjacent rings are arranged at an equal distance. In some possible implementations, the ring body is circular, elliptical or polygonal.

[0012] Preferably, the top shape of the upper opening groove is circular or polygonal, the top opening diameter of the deep groove is 0.5 μm to 5 μm, and the depth of the deep groove is 5 μm to 50 μm.

[0013] Preferably, the first electrode layer is formed by doping produced by a solid source diffusion process, and the solid source diffusion process causes the diffusion ions in the dopant to diffuse toward the formation surface to form doping, and the doping depth is 10nm~1200nm, wherein if the silicon substrate is P-type, the diffusion ions are phosphorus, and if the silicon substrate is N-type, the diffusion ions are boron.

[0014] Preferably, the first dielectric layer comprises a combination of one or more of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide. The first dielectric layer covers the surface of the first electrode layer and has a thickness of 1 nm to 2000 nm.

[0015] Preferably, the second electrode layer comprises one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride or titanium nitride, and the second electrode layer covers the silicon groove on the surface of the first dielectric layer and has a thickness of 10nm~2000nm.

[0016] Preferably, the insulating layer includes a combination of one or more of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide. The insulating layer covers the surface of the third electrode layer. Its main purpose is to isolate the electrical connection between the three electrode layers. The thickness is 5nm~2000nm.

[0017] Preferably, the through-hole lead comprises one of metal gold, metal aluminum, metal copper, tantalum nitride or titanium nitride.

[0018] Preferably, the surface pad comprises one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium, is located on the insulating layer, is connected to the internal through-hole lead, and has a thickness of 200nm~1000nm.

[0019] Preferably, the through-hole lead comprises a first through-hole lead and a second through-hole lead, the first through-hole lead electrically connects the first electrode layer and a surface pad, the second through-hole lead electrically connects the second electrode layer and another surface pad, and the side walls of the through-hole lead are provided with an insulating sheath.

[0020] Preferably, a second dielectric layer and a third electrode layer are further included, the material of the second dielectric layer is the same as that of the first dielectric layer, and the material of the third electrode layer is the same as that of the second electrode layer.

[0021] Preferably, the first through-hole lead connects the first electrode layer and the third electrode layer.

[0022] Compared with the prior art, the present invention has the following beneficial effects: (1) By setting a funnel-shaped deep groove that is larger at the top and smaller at the bottom, the probability of the deep groove being blocked, resulting in hollowness and affecting the performance of the silicon capacitor, is reduced; (2) The inclined deep trench sidewalls also make it easier for the first electrode layer, the first dielectric layer, the second electrode layer, and the insulating layer to adhere and form, thereby reducing the process difficulty and improving the reliability of the silicon capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a cross-sectional view of the present invention; Figure 2is a schematic diagram of a deep trench of the present invention; Figure 3 is a cross-sectional view of another embodiment of the present invention; In the figure: Silicon substrate 1, first electrode layer 2, first dielectric layer 3, second electrode layer 4, insulating layer 5, surface pad 6, deep trench 7, upper open trench 8, lower open trench 9, first through hole lead 10, second through hole lead 11, second dielectric layer 12, third electrode layer 13. DETAILED DESCRIPTION

[0024] The present disclosure is further described below in conjunction with the accompanying drawings and embodiments.

[0025] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0026] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0027] In the present disclosure, terms such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "side", "bottom" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are relational words determined only for the convenience of describing the structural relationships of the various parts or elements of the present disclosure, and do not specifically refer to any part or element in the present disclosure and should not be understood as limitations on the present disclosure.

[0028] In the present disclosure, terms such as "fixed connection", "connected", "connection", etc. should be understood in a broad sense, indicating that it can be fixedly connected, integrally connected or detachably connected; it can be directly connected or indirectly connected through an intermediate medium. For relevant scientific research or technical personnel in this field, the specific meanings of the above terms in the present disclosure can be determined according to specific circumstances, and they cannot be understood as limitations on the present disclosure.

[0029] Example: A funnel-shaped silicon capacitor, Figure 1As shown, the capacitor includes a silicon substrate 1, a first electrode layer 2, a first dielectric layer 3, a second electrode layer 4, an insulating layer 5, a through-hole lead and two surface pads 6. A deep groove 7 is provided on the top surface of the silicon substrate 1, and the diameter of the deep groove 7 gradually decreases and is funnel-shaped along the direction from the top surface to the bottom surface of the silicon substrate 1. The deep groove 7 does not penetrate the silicon substrate 1, so that the deep groove 7 has a side wall and a bottom surface.

[0030] The silicon substrate 1 and the sidewalls and bottom surface of the deep trench 7 form a continuous formation surface. The structure is composed of semiconductor thin film deposition. The materials of the first electrode layer 2, the first dielectric layer 3, the second electrode layer 4, and the insulating layer 5 can be evenly deposited on the formation surface to form a continuous functional layer.

[0031] The specific functional layers include a first electrode layer 2, a first dielectric layer 3, a second electrode layer 4, and an insulating layer 5. Among them, the first dielectric layer 3 is between the first electrode layer 2 and the second electrode layer 4. When the capacitor is connected to an external circuit, the electrode layer is responsible for conducting charges and establishing an electric field on both sides of the dielectric layer, which is the basis for the capacitor to store electrical energy. The dielectric layer is located between the two electrode layers, and its core function is to isolate charges and prevent charges from passing directly, thereby avoiding short circuits. At the same time, the dielectric layer can maintain the electric field between the electrodes to ensure that the capacitor can store electrical energy stably. The two work together to enable silicon capacitors to efficiently store and release electrical energy. The insulating layer 5 covers the surface of the second electrode layer 4, electrically isolating the second electrode layer 4 from the outside world.

[0032] The first electrode layer 2, the first dielectric layer 3, the second electrode layer 4, and the insulating layer 5 are successively formed on the formation surface and fill the deep groove 7. The successive formation means that the first dielectric layer 3 is formed on the upper surface of the first electrode layer 2, the second electrode layer 4 is formed on the upper surface of the first dielectric layer 3, and the insulating layer 5 is formed on the surface of the second electrode layer 4 to play an insulating role and electrically isolate the second electrode layer 4 from the outside.

[0033] Specifically, for a silicon capacitor that realizes a capacitance function by means of a first electrode layer 2, a first dielectric layer 3, a second electrode layer 4, and an insulating layer 5, the portion of the second electrode layer 4 located in the deep trench 7 is columnar and located in the middle of the deep trench 7. The top of the second electrode layer 4 forms a plane, and the insulating layer 5 covers the top of the second electrode layer 4.

[0034] Ginseng Figure 2As shown, the deep trench 7 includes an upper opening trench 8 and a lower opening trench 9, the etching angle of the upper opening trench 8 is 40°~70°, the etching angle of the lower opening trench 9 is 70°~80°, and the bottom opening of the upper opening trench 8 and the top opening of the lower opening trench 9 are of the same size and connected. The etching angle of the upper opening trench 8 is smaller than the etching angle of the lower opening trench 9, wherein the sidewall of the lower opening trench 9 is close to vertical, so that the distance between the first electrode layer 2 and the second electrode layer 4 between the upper and lower sides of the lower opening trench 9 is close, and the efficiency is close to the silicon capacitor performance brought by the vertical trench process.

[0035] Wherein, the upper opening groove 8 is obtained by anisotropic corrosion or angled dry etching. The small opening groove is obtained by angled deep reactive ion dry etching. The top shape of the upper opening groove 8 is circular or polygonal, the top opening diameter of the deep groove 7 is 0.5μm~5μm, and the depth of the deep groove 7 is 5μm~50μm. Wherein, the deep groove 7 array is arranged on the top surface of the silicon substrate 1. Wherein, the array arrangement includes a horizontal row mode and a concentric ring mode. In the horizontal row mode, each deep groove 7 arranged horizontally is arranged at an equal distance, and each deep groove 7 arranged longitudinally is arranged at an equal distance; in the concentric ring mode, each deep groove 7 in the same ring is arranged at an equal distance. In some possible implementation methods, adjacent rings are equally spaced. In some possible methods, the ring body is circular, elliptical or polygonal.

[0036] The first electrode layer 2 and the second electrode layer 4 are both good electrical conductors. The first electrode layer 2 is formed by doping produced by a solid source diffusion process, and the solid source diffusion process causes the diffusion ions in the dopant to diffuse to the formation surface to form doping, and the doping depth is 10nm~1200nm, wherein if the silicon substrate 1 is P-type, the diffusion ions are phosphorus, and if the silicon substrate 1 is N-type, the diffusion ions are boron.

[0037] The second electrode layer 4 includes heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride or titanium nitride. The second electrode layer 4 covers the silicon groove on the surface of the first dielectric layer 3 and has a thickness of 10nm-2000nm.

[0038] The first dielectric layer 3 includes one or more combinations of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide. The first dielectric layer 3 covers the surface of the first electrode layer 2 and has a thickness of 1 nm to 2000 nm.

[0039] The insulating layer 5 includes one or more combinations of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide. The insulating layer 5 covers the surface of the second electrode layer 4. The main purpose is to isolate the second electrode layer from the external electrical connection to avoid leakage. The thickness is 5nm~2000nm.

[0040] The through-hole lead includes a first through-hole lead 10 and a second through-hole lead 11. The first through-hole lead 10 is electrically connected to the first electrode layer 2 and a surface pad 6, and the second through-hole lead 11 is electrically connected to the second electrode layer 4 and another surface pad 6, so that the corresponding functional layer is electrically connected to the through-hole lead. Specifically, the first through-hole lead 10 and the second through-hole lead 11 are both vertically buried in the functional layer, and their height is greater than the thickness of any functional layer. The outer wall of the first through-hole lead at the corresponding second electrode layer 4 has an insulating layer, which is connected to the first electrode layer 2. The end of the second through-hole lead 11 is located in the second electrode layer 4.

[0041] In some embodiments, the insulating layer of the outer wall of the through-hole conductor is formed by extending the insulating layer 5 .

[0042] The surface pad 6 is connected to the insulating layer 5 and is used to connect to the external circuit. The through-hole lead includes one of metal gold, metal aluminum, metal copper, tantalum nitride or titanium nitride. The surface pad 6 includes one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium, is located on the insulating layer 5, is connected to the internal through-hole lead, and has a thickness of 200nm~1000nm.

[0043] The deep groove 7 is wide at the top and narrow at the bottom, forming a funnel shape. During the forming process of the first electrode layer 2, the first dielectric layer 3, the second electrode layer 4, and the insulating layer 5, it is not easy to block the notch of the deep groove 7, causing the deep groove 7 to be hollow, thereby reducing the efficiency of the silicon capacitor. The inclined sidewalls of the deep groove 7 also make it easier for the first electrode layer 2, the first dielectric layer 3, the second electrode layer 4, and the insulating layer 5 to adhere and form. The funnel-shaped deep groove 7 makes the transition between the sidewalls and the bottom surface of the silicon substrate 1, the deep groove 7 more friendly to deposition than the transition of the vertical groove of the BOSCH process, and the first electrode layer 2, the first dielectric layer 3, the second electrode layer 4, and the insulating layer 5 are not easy to break and cause failure.

[0044] Ginseng Figure 3 As shown, in some embodiments, a second dielectric layer 12 and a third electrode layer 13 are further included, the material of the second dielectric layer 12 is the same as the material of the first dielectric layer 3, and the material of the third electrode layer 13 is the same as the material of the second electrode layer 4. The same means that the second dielectric layer 12 also includes a combination of one or more of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide, and the third electrode layer 13 is also heavily doped with polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride, or titanium nitride.

[0045] In this embodiment, the second electrode layer 4 does not completely fill the deep trench 7 to form a columnar structure, but the third electrode layer 13 fills the deep trench 7 and finally presents a columnar shape. The functional layers on the silicon substrate 1 include the first electrode layer 2, the first dielectric layer 3, the second electrode layer 4, the second dielectric layer 12, the third electrode layer 13, and the insulating layer 5. The above-mentioned functional layers are formed step by step, and different functional layers can only be electrically connected through through-hole leads.

[0046] The first through-hole lead 10 connects a surface pad 6, the first electrode layer 2 and the third electrode layer 13 and avoids the second electrode layer 4, wherein the avoidance method includes setting an insulating layer at the corresponding second electrode layer 4 to avoid the current flow between the first through-hole lead 10 and the second electrode layer 4. This limitation allows the charge introduced by the external circuit to be uniformly conducted between the first electrode layer 2 and the third electrode layer 13. The second electrode layer 4 is located between the first electrode layer 2 and the third electrode layer 13 in a "hamburger-style" manner. The first electrode layer 2 and the second electrode layer 4 establish an electric field on both sides of the first dielectric layer 3, and the second electrode layer 4 and the third electrode layer 13 establish an electric field on both sides of the second dielectric layer 12 to achieve the function of a capacitor. The second through-hole lead 11 connects the second electrode layer 4 and another surface pad 6. The second through-hole lead 11 is provided with an insulating layer at the corresponding third electrode layer 13 to avoid the electrical connection between the second through-hole lead 11 and the third electrode layer 13. The end of the second through-hole lead 11 is located in the second electrode layer 4.

[0047] The embodiments described above are only preferred solutions of the present invention and are not intended to limit the present invention in any form. Other variations and modifications are possible without exceeding the technical solutions described in the claims.

Claims

1. A funnel-shaped silicon capacitor, characterized in that: The capacitor comprises a silicon substrate, a first electrode layer, a first dielectric layer, a second electrode layer, an insulating layer, a through-hole lead and two surface pads, wherein a deep groove is provided on the top surface of the silicon substrate, and the diameter of the deep groove gradually decreases from the top surface to the bottom surface of the silicon substrate to form a funnel shape, and a continuous formation surface is formed on the silicon substrate, the sidewall and the bottom surface of the deep groove, and the first electrode layer, the first dielectric layer, the second electrode layer and the insulating layer are successively formed on the formation surface and the deep groove is filled.

2. A funnel-shaped silicon capacitor according to claim 1, characterized in that: The deep trench includes an upper opening trench and a lower opening trench, the etching angle of the upper opening trench is 40°~70°, the etching angle of the lower opening trench is 70°~80°, and the bottom opening of the upper opening trench and the top opening of the lower opening trench have the same size and are connected.

3. A funnel-shaped silicon capacitor according to claim 2, characterized in that: The upper opening groove is obtained by anisotropic etching or angled dry etching, the lower opening groove is obtained by angled deep reactive ion dry etching, and the deep groove array is arranged on the top surface of the silicon substrate.

4. The funnel-shaped silicon capacitor according to claim 3, characterized in that: The top shape of the upper opening groove is circular or polygonal, the top opening diameter of the deep groove is 0.5 μm to 5 μm, and the depth of the deep groove is 5 μm to 50 μm.

5. The funnel-shaped silicon capacitor according to claim 1, characterized in that: The first electrode layer is formed by doping produced by a solid source diffusion process. The solid source diffusion process causes the diffusion ions in the dopant to diffuse toward the formation surface to form doping. The doping depth is 10nm~1200nm. If the silicon substrate is P-type, the diffusion ions are phosphorus, and if the silicon substrate is N-type, the diffusion ions are boron.

6. The funnel-shaped silicon capacitor according to claim 1, characterized in that: The first dielectric layer includes one or more of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide. The first dielectric layer covers the surface of the first electrode layer and has a thickness of 1 nm to 2000 nm.

7. The funnel-shaped silicon capacitor according to claim 1, characterized in that: The second electrode layer includes one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride or titanium nitride. The second electrode layer covers the silicon groove on the surface of the first dielectric layer and has a thickness of 10nm~2000nm.

8. The funnel-shaped silicon capacitor according to claim 1, characterized in that: The insulating layer includes one or more combinations of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide. The insulating layer covers the surface of the third electrode layer. Its main purpose is to isolate the electrical connection between the three electrode layers. The thickness is 5nm~2000nm.

9. The funnel-shaped silicon capacitor according to claim 1, characterized in that: The through-hole lead includes one of metal gold, metal aluminum, metal copper, tantalum nitride or titanium nitride.

10. The funnel-shaped silicon capacitor according to claim 1, characterized in that: The surface pad includes one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium, is located on the insulating layer, is connected to the internal through-hole lead, and has a thickness of 200nm~1000nm.

11. A funnel-shaped silicon capacitor according to claim 1 or 9, characterized in that: The through-hole leads include a first through-hole lead and a second through-hole lead, the first through-hole lead is electrically connected to the first electrode layer and a surface pad, and the second through-hole lead is electrically connected to the second electrode layer and another surface pad.

12. The funnel-shaped silicon capacitor according to claim 1, characterized in that: It also includes a second dielectric layer and a third electrode layer. The material of the second dielectric layer is the same as that of the first dielectric layer, and the material of the third electrode layer is the same as that of the second electrode layer. The second dielectric layer and the third electrode layer are successively formed on the second electrode layer, and the insulating layer is located at the outermost layer. The first through-hole lead connects the first electrode layer and the third electrode layer.

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