Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: providing a substrate which comprises a first region where a first gate structure is formed and a second region where a second gate structure is formed; forming a first patterned mask to cover the substrate, the first gate structure and the second gate structure, and exposing a part of height of the second gate structure; executing an etching process to remove a part of height of the hard mask layer on the second gate structure, so that a first height difference exists between the first gate structure and the second gate structure; forming a second patterned mask to cover the substrate and the first gate structure, and exposing the second gate structure and the surface of the substrate on the two sides of the second gate structure; performing source-drain ion implantation on the substrate on two sides of the second gate structure; epitaxial structures are formed in the substrate on the two sides of the first gate structure, and a second height difference exists between the first gate structure and the second gate structure and is smaller than the first height difference. According to the invention, the leveling step between the gate structures is optimized, and the leveling effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] With the development of semiconductor technology, the size of MOS (Metal-Oxide-Semiconductor) transistors continues to shrink, and the mobility of P-type particles decreases faster than that of N-type particles. For this reason, a germanium-silicon epitaxial structure is used as a source-drain structure at both ends of the P-type channel to improve its carrier mobility.

[0003] Take the preparation process of a semiconductor device as an example. The semiconductor device includes a P-type core region, an N-type core region, a P-type peripheral region and an N-type peripheral region. A corresponding gate structure is formed on each region. When an epitaxial structure is formed on both sides of the gate structure of the P-type core region as a source-drain structure, it is necessary to open the P-type core region and the source-drain regions on both sides thereof (substrate surface) separately, and to form a groove in the source-drain region so as to form an epitaxial structure in the groove, so that the gate structure of the P-type core region is consumed in the above-mentioned opening process and becomes lower (there is a significant height difference with other gate structures). For this reason, it is necessary to level the gate structure (the height difference between them). In the related art, the steps may include: forming an etching stop layer to cover all gate structures, then using a mask layer to cover the gate structure and expose the higher part thereof, etching the higher part of the gate structure to achieve the purpose of leveling the gate structure, and then removing the etching stop layer.

[0004] However, in practice, since the sizes (widths) and distribution densities of the multiple gate structures are different, the load effect generated during the etching process does not effectively reduce the height difference between the gate structures. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing a semiconductor device, which optimizes the leveling step between gate structures and improves the leveling effect.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:

[0007] Providing a substrate, which includes a first region and a second region, wherein a first gate structure is formed on the first region, a second gate structure is formed on the second region, and the tops of the first gate structure and the second gate structure both include a hard mask layer;

[0008] An epitaxial structure is formed in the substrate on both sides of the first gate structure, and the height of the first gate structure is

[0009] Forming a first patterned mask to cover the substrate, the first gate structure and the second gate structure, and to expose a portion of the height of the second gate structure;

[0010] Using the first patterned mask, an etching process is performed to remove a portion of the hard mask layer above the second gate structure, so that a first height difference exists between the first gate structure and the second gate structure;

[0011] Removing the first patterned mask to form a second patterned mask to cover the substrate and the first gate structure and expose the second gate structure and the substrate surfaces on both sides thereof;

[0012] Using the second patterned mask, performing source and drain ion implantation on the substrate at both sides of the second gate structure;

[0013] An epitaxial structure is formed in the substrate at both sides of the first gate structure, and a second height difference exists between the first gate structure and the second gate structure, and the second height difference is smaller than the first height difference.

[0014] Optionally, the first region includes a P-type core region, and the epitaxial structure includes a P-type silicon-germanium epitaxial structure, which serves as a source-drain structure of the first region.

[0015] Optionally, the material of the first patterned mask includes photoresist, and the height of the second gate structure exposed by the first patterned mask is greater than or equal to the first height difference.

[0016] Optionally, the step of forming the first patterned mask includes:

[0017] Forming a photoresist layer to cover the substrate and fill the first gate structure and the second gate structure;

[0018] A photolithography process is performed to remove part of the photoresist layer on the second gate structure and on both sides thereof to expose a partial height of the second gate structure, and the photoresist layer covering the first gate structure and the remaining height of the second gate structure is used as the first patterned mask.

[0019] Optionally, the hard mask layer includes a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer, and the first patterned mask at least exposes the silicon oxide layer on the second gate structure.

[0020] Optionally, the first patterned mask and the second patterned mask are formed using the same mask.

[0021] Optionally, the exposure intensity when forming the first patterned mask is lower than the exposure intensity when forming the second patterned mask, and / or the development intensity when forming the first patterned mask is lower than the development intensity when forming the second patterned mask.

[0022] Optionally, the step of forming the epitaxial structure includes:

[0023] forming a third patterned mask to cover the second gate structure and the substrate on both sides thereof, and to expose the first gate structure and the substrate on both sides thereof;

[0024] Etching the substrate and the first gate structure using the third patterned mask to form source-drain trenches in the substrate at both sides of the first gate structure, and making a second height difference between the first gate structure and the second gate structure smaller than the first height difference;

[0025] The third patterned mask is removed, and an epitaxial process is performed to form the epitaxial structure in the source / drain trench.

[0026] Optionally, the first height difference is 200 angstroms to 400 angstroms, and the second height difference is less than or equal to 50 angstroms.

[0027] Optionally, the second region includes an N-type core region, an N-type IO region and a P-type IO region. After the etching process and corresponding source and drain ion implantation are performed on the second gate structures of the N-type core region, the N-type IO region and the P-type IO region respectively, the epitaxial structure is formed on both sides of the first gate structure.

[0028] In summary, the present invention forms a first patterned mask covering the substrate, the first gate structure and the second gate structure, and exposes a portion of the height of the second gate structure; uses the first patterned mask to perform an etching process to remove a portion of the height of the hard mask layer on the second gate structure, so that the height of the second gate structure becomes lower, and there is a first height difference between the second gate structure and the first gate structure, and then removes the first patterned mask to form a second patterned mask covering the substrate and the first gate structure, and exposes the second gate structure and the substrate surfaces on both sides thereof; then uses the second patterned mask to perform source and drain ion implantation on the substrate on both sides of the second gate structure, and then forms an epitaxial structure in the substrate on both sides of the first gate structure, so that the height of the first gate structure becomes lower, and the second height difference between the second gate structure and the second gate structure is smaller than the first height difference. In the above process, before the epitaxial structure is formed in the substrate on both sides of the first gate structure, during the process of forming the source-drain structure (source-drain ion implantation) in the second gate structure, the height of the second gate structure is lowered in advance, so that the second height difference between the second gate structure and the first gate structure after the epitaxial structure is formed is smaller than the first height difference, thereby combining the leveling of the gate structure with the step of forming the source-drain structure on both sides of the second gate structure, thereby optimizing the step of performing the same leveling on all gate structures, and correspondingly reducing one layer of mask and etching stop layer. Moreover, since the source-drain structures on both sides of different second gate structures need to be formed separately, the different second gate structures are leveled at the same time, thereby avoiding the load effect caused by the simultaneous leveling of gate structures of different sizes and different distribution densities in the related art, and then more accurately controlling the height difference between the gate structures to achieve a better leveling effect of the height difference between the gate structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0030] Figure 1 is a flow chart of a method for preparing a semiconductor device provided in this embodiment;

[0031] Figure 2a to Figure 2h This is a schematic structural diagram corresponding to the corresponding steps of the method for preparing a semiconductor device provided in this embodiment.

[0032] In the attached figure:

[0033] 10-substrate; 11-first region; 12-second region; AA-N type core region; BB-N type peripheral region; CC-P type peripheral region; 21-first gate structure; 22-second gate structure; 23-hard mask layer; 23a-silicon oxide layer; 23b-silicon nitride layer; 24-etching stop layer; 31-first patterned mask; 32-second patterned mask; 33-source-drain structure; 34-third patterned mask; 35-source-drain trench; 36-epitaxial structure. DETAILED DESCRIPTION

[0034] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0035] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0036] Figure 1 A flow chart of a method for preparing a semiconductor device provided in this embodiment.

[0037] like Figure 1 As shown, the method for preparing a semiconductor device provided in this embodiment includes:

[0038] S01: providing a substrate, which comprises a first region and a second region, wherein a first gate structure is formed on the first region, and a second gate structure is formed on the second region, and the tops of the first gate structure and the second gate structure both comprise a hard mask layer;

[0039] S02: forming a first patterned mask to cover the substrate, the first gate structure and the second gate structure, and to expose a portion of the height of the second gate structure;

[0040] S03: using the first patterned mask, performing an etching process to remove a portion of the hard mask layer above the second gate structure, so that a first height difference exists between the first gate structure and the second gate structure;

[0041] S04: removing the first patterned mask to form a second patterned mask to cover the substrate and the first gate structure and expose the second gate structure and the substrate surfaces on both sides thereof;

[0042] S05: performing source-drain ion implantation on the substrate at both sides of the second gate structure using the second patterned mask;

[0043] S06: forming an epitaxial structure in the substrate on both sides of the first gate structure, wherein a second height difference exists between the first gate structure and the second gate structure, and the second height difference is smaller than the first height difference.

[0044] Figure 2a to Figure 2h The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. Next, Figure 2a to Figure 2h The method for preparing the semiconductor device is described in detail.

[0045] First, please refer to Figure 2a , perform step S01, provide a substrate 10, which includes a first area 11 and a second area 12, a first gate structure 21 is formed on the first area 11, a second gate structure 22 is formed on the second area 12, and the tops of the first gate structure 21 and the second gate structure 22 both include a hard mask layer 23.

[0046] The material of the substrate 10 may include any suitable base material known to those skilled in the art, for example, it may be at least one of the following materials: silicon, glass, quartz, plastic, etc.

[0047] The first region 11 and the second region 12 may be regions with different electrical properties or different functions. The main difference between the first region 11 and the second region 12 is that an epitaxial structure 36 will be formed in the substrate 10 on both sides of the first gate structure 21 in the first region 11 as a source-drain structure 33, while no epitaxial structure 36 is formed in the substrate 10 on both sides of the second gate structure 22 in the second region 12 (for example, ion implantation forms the corresponding source-drain structure). The first region 11 and the second region 12 may be any one or more of an N-type core region AA, a P-type core region, an N-type peripheral region BB, and a P-type peripheral region CC. Figure 2aIn the example shown, the first region 11 may include a P-type core region, and the second region 12 may include an N-type core region AA, a P-type peripheral region CC, and an N-type peripheral region BB. In addition, only a portion of the gate structure in the functional region of a certain electrical property will form an epitaxial structure 36 on both sides thereof, and the portion of the functional region where the epitaxial structure 36 is to be formed is the first region 11, and the rest of the functional region is the second region 12.

[0048] The steps of forming the first gate structure 21 and the second gate structure 22 on the first area 11 and the second area 12 respectively include: forming a gate oxide layer, a gate material layer and a hard mask material layer in sequence on the first area 11 and the second area 12 of the substrate 10, the hard mask material layer may include a silicon nitride layer 23b and a silicon oxide layer 23a formed in sequence, the thickness of the silicon oxide layer 23a is greater than the thickness of the silicon nitride layer 23b; performing a patterning process, etching the above materials in sequence, so as to form a first gate structure 21 in the first area 11 and a second gate structure 22 in the second area 12, the first gate structure 21 and the second gate structure 22 may include a hard mask layer 23 (composed of the remaining hard mask material layer) located on the top thereof, and the first gate structure 21 and the second gate structure 22 have the same or nearly the same height. In addition, sidewalls may be formed on the sidewalls of the first gate structure 21 and the second gate structure 22.

[0049] It should be noted that the gate structure of this embodiment (including the first gate structure 21 and the second gate structure 22) may also be a virtual gate structure, or part of it may be a virtual gate structure, and the virtual gate structure may be used to form a metal gate structure later.

[0050] Next, please refer to Figure 2b , step S02 is performed to form a first patterned mask 31 to cover the substrate 10 , the first gate structure 21 and the second gate structure 22 , and to expose a portion of the height of the second gate structure 22 .

[0051] Specifically, the sidewalls of the first gate structure 21 and the second gate structure 22 can be removed first to form an etch stop layer 24 covering the outer walls of the substrate 10, the first gate structure 21 and the second gate structure 22; then, a mask material layer is formed to cover the surface of the substrate 10, the etch stop layer on the outer walls of the epitaxial structure 36 of the first gate structure 21 and the second gate structure 22, and fill it above the second gate structure 22 (or the first gate structure 21). The material of the mask material layer can be photoresist, and when filling it above the second gate structure 22, the better fluidity of the photoresist can be used to form a surface that is as flat as possible.

[0052] Next, a photolithography process is performed to remove a portion of the thickness of the mask material layer in the second area 12, exposing a portion of the height of the second gate structure 22, and using the remaining mask material layer as the first patterned mask 31. In one example, when performing the exposure step using a mask plate, the exposure energy or exposure time can be reduced so that only a portion of the depth of the mask material layer in the first area 11 is exposed, and then the exposed mask material layer is removed by development, thereby exposing only a portion of the height of the second gate structure 22. In another example, when developing the mask material layer in the first area 11 after exposure, the intensity of the development can be reduced so that only a portion of the thickness of the exposed mask material layer in the first area 11 is removed by development, thereby exposing only a portion of the height of the second gate structure 22.

[0053] In this embodiment, the first patterned mask 31 at least exposes the silicon oxide layer 23b (including the corresponding etching stop layer 24) on the second gate structure 22 to facilitate subsequent etching. In addition, if the second region 12 may include multiple regions with different electrical properties and different functions, the source-drain structures 33 of the multiple regions with different electrical properties and different functions are different. Therefore, the second gate structures 22 of different second regions 12 need to be processed similarly. This embodiment is described by taking the N-type core region AA of the second region 12 as an example.

[0054] It should be noted that the mask used to perform the photolithography process can be the mask for subsequent ion implantation (second patterned mask), and no additional mask is required. Moreover, most process conditions of the photolithography process can be similar to the photolithography process conditions for forming the second patterned mask, so that the photolithography process has lower cost and better operability.

[0055] Next, please refer to Figure 2c , executing step S03 , using the first patterned mask 31 , performing an etching process to remove a portion of the hard mask layer 23 on the second gate structure 22 , so that a first height difference ΔH1 exists between the first gate structure 21 and the second gate structure 22 .

[0056] A dry etching process is performed on the etch stop layer and the hard mask layer 23 on the exposed second gate structure 22 to remove a portion of the height of the etch stop layer and the hard mask layer 23 (the silicon oxide layer 23a on it), so that there is a first height difference ΔH1 between the hard mask layer 23 on the first gate structure 21 and the hard mask layer 23 on the second gate structure 22, wherein the first height difference ΔH1 may be the height of the first gate structure 21 lost in the subsequent formation of the epitaxial structure. By reducing the height of the second gate structure by the first height difference ΔH1 in advance, the large height difference between the gate structures is prevented from affecting the electrical stability of the semiconductor device, which is beneficial to improving the performance and reliability of the semiconductor device. In this embodiment, the first height difference ΔH1 may be 200 angstroms to 300 angstroms.

[0057] Compared with the related art in which gate structures of different sizes and distribution densities are etched simultaneously, the present embodiment only etches the second gate structure of the same area and the same size (the area with the same electrical properties and the same function in the second area), thereby avoiding the load effect in the related art, thereby more accurately controlling the height of the second gate structure to achieve a better leveling effect for the height difference between the gate structures, that is, minimizing the height difference between the gate structures.

[0058] Next, please refer to Figure 2d , perform step S04 to remove the first patterned mask 31 and form a second patterned mask 32 to cover the substrate 10 and the first gate structure 21 and expose the second gate structure 22 and the surfaces of the substrate 10 on both sides thereof.

[0059] The material of the second patterned mask 32 may be the same as that of the first patterned mask 31, such as photoresist. The substrate 10 regions on both sides of the second gate structure 22 exposed by the second patterned mask 32 may be source and drain regions corresponding to the second gate structure 22. Of course, what is exposed by the photolithography process is the etch stop layer 24 on the surface of the source and drain regions, so a dry etching process may also be performed to remove the etch stop layer 24 on the surface of the source and drain regions to expose the surface of the substrate 10.

[0060] Next, please refer to Figure 2e , executing step S05 , using the second patterned mask 32 , performing source-drain ion implantation on the substrate 10 at both sides of the second gate structure 22 .

[0061] The source-drain ion implantation performed on the source-drain region on both sides of the second gate structure 22 may include multiple ion implantations, and the concentrations of the multiple ion implantations may be different, for example, including light LDD doping and heavy source-drain doping, etc. Thus, while the source-drain structure 33 is formed in the N-type core area AA of the second region 12, the second gate structure 22 thereon and the first gate structure 21 of the first region 11 have a first height difference ΔH1.

[0062] In addition, please refer to Figure 2f Similarly, similar methods may be used to perform the above processing on the P-type peripheral region CC and the N-type peripheral region BB of the second region 12 to form corresponding source-drain structures 33 , and to provide a first height difference ΔH1 between the second gate structure 22 and the first gate structure 21 thereon.

[0063] Next, step S06 is performed to form an epitaxial structure 36 in the substrate 10 on both sides of the first gate structure 21 . A second height difference ΔH2 exists between the first gate structure 21 and the second gate structure 22 . The second height difference ΔH2 is smaller than the first height difference ΔH1 .

[0064] Specifically, the steps of forming the epitaxial structure 36 may include: Figure 2g , a third patterned mask 34 is formed to cover the first area 11 and the second area 12, the opening of the third patterned mask 34 exposes the first gate structure 21 and the surface of the substrate 10 on both sides thereof (as source and drain regions), and an etching process is performed using the third patterned mask 34 to form source and drain trenches 35 in the substrate 10 (source and drain regions) on both sides of the first gate structure 21.

[0065] Please refer to Figure 2h , perform an epitaxial process to form a protruding epitaxial structure 36 in the source-drain trench 35, and then remove the third patterned mask 34. In this embodiment, the first region 11 may be a P-type core region, and the epitaxial structure 36 may be a P-type germanium silicon epitaxial structure. It should be noted that in the process of opening the first gate structure 21 and the substrate 10 on both sides thereof and etching to form the source-drain trench 35, the hard mask layer 23 (the silicon oxide layer 23a therein) on the top of the first gate structure 21 will be consumed (etched) to a large extent, so that the height of the first gate structure 21 is reduced (for example, the first height difference ΔH1 is reduced), so that the second height difference ΔH2 between the first gate structure 21 and the second gate structure 22 is smaller, that is, the second height difference ΔH2 is at least smaller than the first height difference ΔH1. Of course, the smaller the second height difference ΔH2, the better. In one example, the first height difference ΔH1 may be 200 angstroms to 300 angstroms, and the second height difference ΔH2 is less than or equal to 50 angstroms.

[0066] In summary, the present invention forms a first patterned mask covering the substrate, the first gate structure and the second gate structure, and exposes a portion of the height of the second gate structure; uses the first patterned mask to perform an etching process to remove a portion of the height of the hard mask layer on the second gate structure, so that the height of the second gate structure becomes lower, and there is a first height difference between the second gate structure and the first gate structure, and then removes the first patterned mask to form a second patterned mask covering the substrate and the first gate structure, and exposes the second gate structure and the substrate surfaces on both sides thereof; then uses the second patterned mask to perform source and drain ion implantation on the substrate on both sides of the second gate structure, and then forms an epitaxial structure in the substrate on both sides of the first gate structure, so that the height of the first gate structure becomes lower, and the second height difference between the second gate structure and the second gate structure is smaller than the first height difference. In the above process, before the epitaxial structure is formed in the substrate on both sides of the first gate structure, during the process of forming the source-drain structure (source-drain ion implantation) in the second gate structure, the height of the second gate structure is lowered in advance, so that the second height difference between the second gate structure and the first gate structure after the epitaxial structure is formed is smaller than the first height difference, thereby combining the leveling of the gate structure with the step of forming the source-drain structure on both sides of the second gate structure, thereby optimizing the step of performing the same leveling on all gate structures, and correspondingly reducing one layer of mask and etching stop layer. Moreover, since the source-drain structures on both sides of different second gate structures need to be formed separately, the different second gate structures are leveled at the same time, thereby avoiding the load effect caused by the simultaneous leveling of gate structures of different sizes and different distribution densities in the related art, and then more accurately controlling the height difference between the gate structures to achieve a better leveling effect of the height difference between the gate structures.

[0067] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, which includes a first region and a second region, wherein a first gate structure is formed on the first region, a second gate structure is formed on the second region, and the tops of the first gate structure and the second gate structure both include a hard mask layer; Forming a first patterned mask to cover the substrate, the first gate structure and the second gate structure, and to expose a portion of the height of the second gate structure; Using the first patterned mask, an etching process is performed to remove a portion of the hard mask layer above the second gate structure, so that a first height difference exists between the first gate structure and the second gate structure; Removing the first patterned mask to form a second patterned mask to cover the substrate and the first gate structure and expose the second gate structure and the substrate surfaces on both sides thereof; Using the second patterned mask, performing source and drain ion implantation on the substrate at both sides of the second gate structure; An epitaxial structure is formed in the substrate at both sides of the first gate structure, and a second height difference exists between the first gate structure and the second gate structure, and the second height difference is smaller than the first height difference.

2. The method for preparing a semiconductor device according to claim 1, wherein: The first region includes a P-type core region, and the epitaxial structure includes a P-type silicon-germanium epitaxial structure, which serves as a source-drain structure of the first region.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The material of the first patterned mask includes photoresist, and the height of the second gate structure exposed by the first patterned mask is greater than or equal to the first height difference.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of forming the first patterned mask comprises: Forming a photoresist layer to cover the substrate and fill the first gate structure and the second gate structure; A photolithography process is performed to remove part of the photoresist layer on the second gate structure and on both sides thereof to expose a partial height of the second gate structure, and the photoresist layer covering the first gate structure and the remaining height of the second gate structure is used as the first patterned mask.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The hard mask layer includes a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer, and the first patterned mask at least exposes the silicon oxide layer on the second gate structure.

6. The method for preparing a semiconductor device according to claim 4, characterized in that: The first patterned mask and the second patterned mask are formed by using the same mask plate.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The exposure intensity when forming the first patterned mask is lower than the exposure intensity when forming the second patterned mask, and / or the development intensity when forming the first patterned mask is lower than the development intensity when forming the second patterned mask.

8. The method for preparing a semiconductor device according to claim 1, characterized in that: The steps of forming the epitaxial structure include: forming a third patterned mask to cover the second gate structure and the substrate on both sides thereof, and to expose the first gate structure and the substrate on both sides thereof; Etching the substrate and the first gate structure using the third patterned mask to form source-drain trenches in the substrate at both sides of the first gate structure, and making a second height difference between the first gate structure and the second gate structure smaller than the first height difference; The third patterned mask is removed, and an epitaxial process is performed to form the epitaxial structure in the source / drain trench.

9. The method for preparing a semiconductor device according to claim 1, wherein: The first height difference is 200 angstroms to 400 angstroms, and the second height difference is less than or equal to 50 angstroms.

10. The method for preparing a semiconductor device according to any one of claims 1 to 9, characterized in that: The second region includes an N-type core region, an N-type IO region and a P-type IO region. After the etching process and corresponding source and drain ion implantation are performed on the second gate structures of the N-type core region, the N-type IO region and the P-type IO region respectively, the epitaxial structure is formed on both sides of the first gate structure.

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