Preparation method of semiconductor device
By using an etch stop layer and a hard mask layer during the preparation of the semiconductor device, adjusting the height difference between the first gate structure and the second gate structure, the problem of the gate structure being consumed when opening the source and drain regions is solved, and the effect of simplifying the process, reducing costs and improving device performance is achieved.
Patent Information
- Application Number
- CN202311429713.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-31
- Publication Date
- 2025-05-06
AI Technical Summary
During the preparation of semiconductor devices, the gate structure of the P-type core region is easily consumed when opening the source and drain region, resulting in inconsistent gate structures and affecting device performance.
By forming an etch stop layer and a hard mask layer on the substrate, more hard mask layers of the second gate structure are exposed using the mask layer, an etching process is performed to make the height difference between the first gate structure and the second gate structure less than or equal to a preset value, and the remaining hard mask layer and the etch stop layer are used as hard protection layers.
Effective adjustment of the height difference between the first gate structure and the second gate structure is achieved, the process flow is simplified, the manufacturing cost is reduced, and the performance and reliability of the semiconductor device is improved.
Smart Images
Figure CN119947149A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art
[0002] With the development of semiconductor technology, the size of MOS (Metal-Oxide-Semiconductor) transistors continues to shrink, and the mobility of P-type particles decreases faster than that of N-type particles. For this reason, a germanium-silicon epitaxial structure is used as a source-drain structure at both ends of the P-type channel to improve its mobility.
[0003] Take the preparation process of a semiconductor device as an example. The semiconductor device includes a P-type core region, an N-type core region, a P-type peripheral region and an N-type peripheral region. A corresponding gate structure is formed on each region. When an epitaxial structure is formed on both sides of the gate structure of the P-type core region as a source-drain structure, the gate structure of the P-type core region is consumed and becomes lower during the above-mentioned opening process because the P-type core region and the source-drain regions on both sides thereof (substrate surface) need to be opened separately. For this reason, it is necessary to level the higher gate structures of other regions (etching to make them lower). In the related art, the steps may include: forming an etching stop layer (photolithography barrier layer) to cover all gate structures, then using a mask layer to etch the higher gate structure, then removing the etching stop layer, and forming a grinding stop layer to cover the leveled gate structure (as a hard protective layer). Summary of the invention
[0004] The object of the present invention is to provide a method for preparing a semiconductor device, which is used to optimize the preparation process of an etch stop layer and a hard protective layer of a gate structure.
[0005] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:
[0006] Providing a substrate, which includes a first region and a second region, wherein a first gate structure is formed on the first region, a second gate structure is formed on the second region, and a hard mask layer is disposed on top of the first gate structure and the second gate structure;
[0007] forming an epitaxial structure in the substrate on both sides of the first gate structure;
[0008] forming an etch stop layer to cover the surface of the substrate, the first gate structure, the second gate structure and the outer wall of the epitaxial structure;
[0009] Forming a mask layer to cover the substrate and the etch stop layer and to expose at least a portion of the hard mask layer of the second gate structure, wherein the exposed height of the second gate structure is greater than the exposed height of the first gate structure;
[0010] The mask layer is used to perform an etching process to etch the etching stop layer and a portion of the hard mask layer of the first gate structure and the second gate structure, so that the height difference between the remaining first gate structure and the second gate structure is less than or equal to a preset value.
[0011] Optionally, the first region includes a P-type core region, and the second region includes an N-type core region and / or a peripheral region.
[0012] Optionally, the epitaxial structure includes a P-type silicon-germanium epitaxial structure.
[0013] Optionally, the sidewalls of the first gate structure and the second gate structure are further provided with sidewalls, and the sidewalls are removed after forming the epitaxial structure and before forming the etching stop layer.
[0014] Optionally, the step of forming the mask layer includes:
[0015] Forming a mask material layer to cover the surface of the substrate, the first gate structure, the second gate structure, and the outer wall of the epitaxial structure, and to fill the upper part of the second gate structure;
[0016] Perform photolithography and dry etching processes to remove a portion of the mask material layer so that the height of the hard mask layer exposed by the second gate structure is greater than the height of the hard mask layer exposed by the first gate structure, and use the remaining mask material layer as the mask layer.
[0017] Optionally, the mask material layer is made of photoresist, and the photolithography process is a maskless photolithography process.
[0018] Optionally, the hard mask layer includes a silicon nitride layer covering the first gate structure and the second gate structure and a silicon oxide layer covering the silicon nitride layer. After the epitaxial structure is formed in the substrate on both sides of the first gate structure, the thickness of the silicon oxide layer on the second gate structure is greater than the thickness of the silicon oxide layer on the first gate structure.
[0019] Optionally, when the etching process is performed using the mask layer, the silicon oxide layer on the first gate structure and the second gate structure is etched away, and the etching stops at the silicon nitride layer on the first gate structure and the second gate structure.
[0020] Optionally, when performing the etching process, an etching rate of the silicon oxide layer is greater than etching rates of the silicon nitride layer and the etch stop layer.
[0021] Optionally, the preset value is less than or equal to 50 angstroms.
[0022] To summarize, after forming a first gate structure and a second gate structure with a height difference, the present invention forms an etch stop layer to cover the surface of the substrate, the first gate structure, the second gate structure and the outer wall of the epitaxial structure; forms a mask layer to cover the substrate and the etch stop layer, and at least exposes a portion of the hard mask layer of the second gate structure, and the exposed height of the second gate structure is greater than the exposed height of the first gate structure; uses the mask layer to perform an etching process to etch the etch stop layer and the hard mask layer of the first gate structure and the second gate structure, so that the height difference between the remaining first gate structure and the second gate structure is less than or equal to a preset value, and uses the remaining hard mask layer and the etch stop layer as hard protection layers for the first gate structure and the second gate structure. In the above process, it is only necessary to form an etch stop layer to cover the surface of the substrate, the outer walls of the first gate structure and the second gate structure before leveling the gate structure, and then form a mask layer to expose the second gate structure at a height greater than the height of the first gate structure. Then, the first gate structure and the second gate structure are etched using the mask layer and the etching stops at the hard mask layer. The etching speed of the second gate structure with more exposure is greater than the etching speed of the first gate structure with less exposure, thereby achieving the purpose of leveling the first gate structure and the second gate structure, and the remaining hard mask layer and the etch stop layer are used as hard protection layers for the first gate structure and the second gate structure, thereby achieving the effect of simplifying the process and saving manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0024] Figure 1 is a flow chart of a method for preparing a semiconductor device provided in this embodiment;
[0025] Figure 2a to Figure 2h This is a schematic structural diagram corresponding to the corresponding steps of the method for preparing a semiconductor device provided in Example 1.
[0026] In the attached figure:
[0027] 10-substrate; 11-first region; 12-second region; AA-N type core region; BB-N type peripheral region; CC-P type peripheral region; 21-first gate structure; 22-second gate structure; 23-hard mask layer; 23a-silicon oxide layer; 23b-silicon nitride layer; 24-side wall; 25-epitaxial structure; 26-etching stop layer; 27a-mask material layer; 27-mask layer. DETAILED DESCRIPTION
[0028] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0029] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0030] This embodiment provides a method for manufacturing a semiconductor device.
[0031] Figure 1 A flow chart of a method for preparing a semiconductor device provided in this embodiment.
[0032] like Figure 1 As shown, the method for preparing a semiconductor device provided in this embodiment includes:
[0033] S01: providing a substrate, which includes a first region and a second region, wherein a first gate structure is formed on the first region, and a second gate structure is formed on the second region, and a hard mask layer is disposed on top of the first gate structure and the second gate structure;
[0034] S02: forming an epitaxial structure in the substrate on both sides of the first gate structure;
[0035] S03: forming an etch stop layer to cover the surface of the substrate, the first gate structure, the second gate structure and the outer wall of the epitaxial structure;
[0036] S04: forming a mask layer to cover the substrate and the etch stop layer and to expose at least a portion of the hard mask layer of the second gate structure, wherein the exposed height of the second gate structure is greater than the exposed height of the first gate structure;
[0037] S05: Using the mask layer, performing an etching process to etch the etching stop layer and a portion of the hard mask layer of the first gate structure and the second gate structure, so that the height difference between the remaining first gate structure and the second gate structure is less than or equal to a preset value.
[0038] Figure 2a to Figure 2h The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in Example 1 is shown below. Figure 2a to Figure 2h The method for preparing the semiconductor device is described in detail.
[0039] First, please refer to Figure 2a , perform step S01, provide a substrate 10, which includes a first area 11 and a second area 12, a first gate structure 21 is formed on the first area 11, a second gate structure 22 is formed on the second area 12, and a hard mask layer 23 is provided on the top of the first gate structure 21 and the second gate structure 22.
[0040] The material of the substrate 10 may include any suitable base material known to those skilled in the art, for example, it may be at least one of the following materials: silicon, glass, quartz, plastic, etc.
[0041] The first region 11 and the second region 12 are regions with different electrical properties or functions. The main difference between the first region 11 and the second region 12 is that an epitaxial structure 25 is formed in the substrate 10 on both sides of the first gate structure 21 in the first region 11 as a source-drain structure, while no epitaxial structure 25 is formed in the substrate 10 on both sides of the second gate structure 22 in the second region 12 (for example, ion implantation forms the corresponding source-drain structure). The first region 11 and the second region 12 can be any one or more of an N-type core region AA, a P-type core region, an N-type peripheral region BB, and a P-type peripheral region CC. Figure 2a In the example shown, the first region 11 may include a P-type core region, and the second region 12 may include an N-type core region AA, a P-type peripheral region CC, and an N-type peripheral region BB. In addition, only a portion of the functional region of a certain electrical property will form an epitaxial structure 25 on both sides of the gate structure, then the portion of the functional region where the epitaxial structure 25 is to be formed is the first region 11, and the rest of the functional region is the second region 12.
[0042] The steps of forming the first gate structure 21 and the second gate structure 22 on the first area 11 and the second area 12 respectively include: forming a gate oxide layer, a gate material layer and a hard mask material layer in sequence on the first area 11 and the second area 12 of the substrate 10, the hard mask material layer may include a silicon nitride layer 23b and a silicon oxide layer 23a formed in sequence, the thickness of the silicon oxide layer 23a is greater than the thickness of the silicon nitride layer 23b; performing a patterning process, etching the above materials in sequence, so as to form a first gate structure 21 in the first area 11 and a second gate structure 22 in the second area 12, the first gate structure 21 and the second gate structure 22 may include a hard mask layer 23 (composed of the remaining hard mask material layer) located on the top thereof, and the first gate structure 21 and the second gate structure 22 have the same or nearly the same height. In addition, a sidewall 24 may be formed on the sidewalls of the first gate structure 21 and the second gate structure 22.
[0043] It should be noted that the gate structure of this embodiment (including the first gate structure 21 and the second gate structure 22) may also be a virtual gate structure, or part of it may be a virtual gate structure, and the virtual gate structure may be used to form a metal gate structure later.
[0044] Next, please refer to Figure 2b , step S02 is performed to form an epitaxial structure 25 in the substrate 10 on both sides of the first gate structure 21 . At this time, the height of the first gate structure 21 is lower than the height of the second gate structure 22 .
[0045] Specifically, the step of forming the epitaxial structure 25 may include: forming a patterned mask to cover the first region 11 and the second region 12, the opening of the patterned mask exposing the first gate structure 21 and the surface of the substrate 10 on both sides thereof (as source and drain regions); performing an etching process using the patterned mask to form source and drain grooves in the substrate 10 (source and drain regions) on both sides of the first gate structure 21; performing an epitaxial process to form an epitaxial structure 25 protruding from the source and drain grooves in the source and drain grooves, and then removing the patterned mask. In this embodiment, the first region 11 is a P-type core region, and the epitaxial structure 25 may be a P-type silicon-germanium epitaxial structure 25.
[0046] It should be noted that, in the process of opening the first gate structure 21 and the substrate 10 on both sides thereof and etching to form source and drain trenches, the hard mask layer 23 (the silicon oxide layer 23a therein) on the top of the first gate structure 21 will be greatly consumed, so that the exposed height of the second gate structure 22 is greater than the exposed height of the first gate structure 21, that is, the thickness of the silicon oxide layer 23a on the second gate structure 22 is greater than the thickness of the silicon oxide layer 23a on the first gate structure 21. In one example, the height difference may be 200 angstroms to 300 angstroms.
[0047] Next, step S03 is performed to form an etch stop layer 26 to cover the surface of the substrate 10 , the first gate structure 21 , the second gate structure 22 and the outer wall of the epitaxial structure 25 .
[0048] For details, please refer to Figure 2c , a wet process may be used to first remove the sidewall spacers 24 of the first gate structure 21 and the second gate structure 22. In some examples, the sidewall spacers 24 may include a silicon oxide layer and a silicon nitride layer formed sequentially, and only the outer silicon nitride layer may be removed.
[0049] Please refer to Figure 2d , an etch stop layer 26 is formed to conformally cover the surface of the substrate 10, the first gate structure 21, the second gate structure 22 and the outer wall of the epitaxial structure 25. The material of the etch stop layer is different from the material of the upper layer (a layer away from the substrate 10) of the hard mask layer 23, and its material may include silicon nitride, silicon oxynitride, etc., and is preferably the same as the material of the lower layer (a layer close to the substrate 10) of the hard mask layer 23. In addition, after the etch stop layer 26 is formed, the etch stop layer 26 may be treated with oxygen to facilitate the adhesion of the mask material.
[0050] It should be noted that, in this embodiment, the parameter requirements of the etch stop layer in this step can also refer to the parameter requirements of the hard protective layer that eventually covers the outer wall of the gate structure (after leveling the gate structure), for example, the parameter requirements of the hard protective layer used in the subsequent grinding process. In one example, compared with the thickness of the silicon nitride layer that is usually only used for etching stop, which is about 50 angstroms to 100 angstroms, the thickness of the etch stop layer 26 (taking silicon nitride as an example) in this embodiment can be 200 angstroms to 300 angstroms, and can be adjusted by the process to have a larger stress (such as compressive stress) so as to provide corresponding stress for the gate structure (or the channel under the gate structure) to adjust the corresponding carrier mobility.
[0051] Next, step S04 is performed to form a mask layer 27 to cover the substrate 10 and the etch stop layer 26 and expose at least a portion of the hard mask layer 23 of the second gate structure 22 . The exposed height of the second gate structure 22 is greater than the exposed height of the first gate structure 21 .
[0052] For details, please refer to Figure 2e A mask material layer 27a can be formed to cover the surface of the substrate 10, the first gate structure 21, the second gate structure 22, and the etch stop layer 26 on the outer wall of the epitaxial structure 25, and fill the second gate structure 22. The mask material layer 27a can be made of photoresist, and when filling the second gate structure 22, the better fluidity of the photoresist is used to form a surface as flat as possible.
[0053] Please refer to Figure 2f, perform a photolithography process and an etching process to remove a portion of the thickness of the mask material layer 27a, and expose the second gate structure 22 (including the hard mask layer 23 and the etch stop layer 26) to a height greater than the height of the first gate structure 21, and use the remaining mask material layer 27a as the mask layer 27. The photolithography process may be an exposure without a mask (or a blank mask) to harden the photoresist layer; the etching process may include dry etching the mask material layer 27a on the first area 11 and the second area 12 to remove a portion of the thickness of the mask material layer 27a, and expose a portion of the height of the hard mask layer 23 of the first gate structure 21, a portion of the height of the hard mask layer 23 of the second gate structure 22, and a corresponding portion of the etch stop layer 26. Since the height of the second gate structure 22 (the hard mask layer 23) itself is higher than the height of the first gate structure 21 (the hard mask layer 23), the height of the second gate structure 22 exposing the hard mask layer 23 is greater than the height of the first gate structure 21 exposing the hard mask layer 23. On the other hand, the first gate structure 21 and the second gate structure 22 covered by the mask layer 27 have the same or nearly the same height. Of course, the height of the mask layer 27 may be higher than the silicon nitride layer 23b (lower layer) of the hard mask layer 23 on the first gate structure 21 and the second gate structure 22.
[0054] In addition, in other examples of this embodiment, only the hard mask layer 23 on the top of the second gate structure 22 may be exposed through an etching process.
[0055] Next, step S05 is executed, and an etching process is performed using the mask layer 27 to etch the etch stop layer 26 and a portion of the hard mask layer 23 of the first gate structure 21 and the second gate structure 22, so that the height difference between the remaining first gate structure 21 and the second gate structure 22 is less than or equal to a preset value, and the remaining hard mask layer 23 and the etch stop layer 26 are used as hard protection layers for the first gate structure 21 and the second gate structure 22.
[0056] For details, please refer to Figure 2gThe silicon oxide layer 23a and the corresponding etch stop layer 26 can be etched using a dry etching process in which the upper layer of the hard mask layer 23 (for example, the silicon oxide layer 23a) has a higher etching selectivity relative to the lower layer of the hard mask layer 23 (including the etch stop layer 26), and the mask layer 27 is etched simultaneously until the etching stops at the lower layer of the hard mask layer 23, that is, the silicon nitride layer 23b in the hard mask layer 23 is exposed. Since the etch stop layer 26 and the hard mask layer 23 on the second gate structure 22 are more exposed, and the etching rate of the upper layer of the hard mask layer 23 is greater than the etching rate of the lower layer of the etch stop layer 26 and the hard mask layer 23, the etching amount of the etch stop layer 26 and the hard mask layer 23 on the second gate structure 22 is greater than that of the etch stop layer 26 and the hard mask layer 23 on the first gate structure 21, and under the action (blocking) of the mask layer 27 and the lower layer of the hard mask layer 23, the height difference between the first gate structure 21 and the second gate structure 22 after the etching is stopped can be reduced, for example, less than or equal to a preset value, thereby preventing the large height difference between the gate structures from affecting the electrical stability of the semiconductor device, which is beneficial to improving the performance and reliability of the semiconductor device. In this embodiment, the preset value can be less than or equal to 50 angstroms. Of course, the smaller the height difference between the two, the better.
[0057] Please refer to Figure 2h , remove the remaining mask layer 27, and use the remaining hard mask layer 23 and the etch stop layer 26 as hard protection layers for the first gate structure 21 and the second gate structure 22. The remaining hard mask layer 23 covers the top walls of the first gate structure 21 and the second gate structure 22, and the remaining etch stop layer 26 covers the surface of the substrate 10, the outer wall of the epitaxial structure 25, and the side walls of the first gate structure 21 and the second gate structure 22.
[0058] Compared with the process of forming a photolithography stop layer, removing the photolithography stop layer and forming a grinding stop layer in the related art, in the above process provided in this embodiment, it is only necessary to form an etch stop layer to cover the surface of the substrate, the first gate structure and the outer wall of the second gate structure, so as to complete the gate structure (including the first gate structure and the second gate structure) and form a hard protective layer to cover the gate structure, thereby achieving the purpose of simplifying the process and saving manufacturing costs.
[0059] To summarize, after forming a first gate structure and a second gate structure with a height difference, the present invention forms an etch stop layer to cover the surface of the substrate, the first gate structure, the second gate structure and the outer wall of the epitaxial structure; forms a mask layer to cover the substrate and the etch stop layer, and at least exposes a portion of the hard mask layer of the second gate structure, and the exposed height of the second gate structure is greater than the exposed height of the first gate structure; uses the mask layer to perform an etching process to etch the etch stop layer and the hard mask layer of the first gate structure and the second gate structure, so that the height difference between the remaining first gate structure and the second gate structure is less than or equal to a preset value, and uses the remaining hard mask layer and the etch stop layer as hard protection layers for the first gate structure and the second gate structure. In the above process, it is only necessary to form an etch stop layer to cover the surface of the substrate, the outer walls of the first gate structure and the second gate structure before leveling the gate structure, and then form a mask layer to expose the second gate structure at a height greater than the height of the first gate structure. Then, the first gate structure and the second gate structure are etched using the mask layer and the etching stops at the hard mask layer. The etching speed of the second gate structure with more exposure is greater than the etching speed of the first gate structure with less exposure, thereby achieving the purpose of leveling the first gate structure and the second gate structure, and the remaining hard mask layer and the etch stop layer are used as hard protection layers for the first gate structure and the second gate structure, thereby achieving the effect of simplifying the process and saving manufacturing costs.
[0060] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, which includes a first region and a second region, wherein a first gate structure is formed on the first region, a second gate structure is formed on the second region, and a hard mask layer is disposed on top of the first gate structure and the second gate structure; forming an epitaxial structure in the substrate on both sides of the first gate structure; forming an etch stop layer to cover the surface of the substrate, the first gate structure, the second gate structure and the outer wall of the epitaxial structure; Forming a mask layer to cover the substrate and the etch stop layer and to expose at least a portion of the hard mask layer of the second gate structure, wherein the exposed height of the second gate structure is greater than the exposed height of the first gate structure; The mask layer is used to perform an etching process to etch the etching stop layer and a portion of the hard mask layer of the first gate structure and the second gate structure, so that the height difference between the remaining first gate structure and the second gate structure is less than or equal to a preset value.
2. The method for preparing a semiconductor device according to claim 1, wherein: The first region includes a P-type core region, and the second region includes an N-type core region and / or a peripheral region.
3. The method for preparing a semiconductor device according to claim 2, characterized in that: The epitaxial structure includes a P-type silicon-germanium epitaxial structure.
4. The method for preparing a semiconductor device according to claim 1, wherein: The sidewalls of the first gate structure and the second gate structure are further provided with sidewalls, and the sidewalls are removed after forming the epitaxial structure and before forming the etching stop layer.
5. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming the mask layer comprises: Forming a mask material layer to cover the surface of the substrate, the first gate structure, the second gate structure, and the outer wall of the epitaxial structure, and to fill the upper part of the second gate structure; Perform photolithography and dry etching processes to remove a portion of the mask material layer so that the height of the hard mask layer exposed by the second gate structure is greater than the height of the hard mask layer exposed by the first gate structure, and use the remaining mask material layer as the mask layer.
6. The method for preparing a semiconductor device according to claim 5, characterized in that: The material of the mask material layer includes photoresist, and the photolithography process is a maskless photolithography process.
7. The method for preparing a semiconductor device according to claim 1, characterized in that: The hard mask layer includes a silicon nitride layer covering the first gate structure and the second gate structure and a silicon oxide layer covering the silicon nitride layer. After the epitaxial structure is formed in the substrate on both sides of the first gate structure, the thickness of the silicon oxide layer on the second gate structure is greater than the thickness of the silicon oxide layer on the first gate structure.
8. The method for preparing a semiconductor device according to claim 7, characterized in that: When the etching process is performed using the mask layer, the silicon oxide layer on the first gate structure and the second gate structure is removed by etching, and the etching stops at the silicon nitride layer on the first gate structure and the second gate structure.
9. The method for preparing a semiconductor device according to claim 8, characterized in that: When the etching process is performed, an etching rate of the silicon oxide layer is greater than etching rates of the silicon nitride layer and the etching stop layer.
10. The method for preparing a semiconductor device according to claim 1, characterized in that: The preset value is less than or equal to 50 angstroms.