Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench extending downward from a top surface of the substrate, the trench having sidewalls and a bottom surface, an included angle between the sidewalls and the bottom surface being greater than or equal to 90 degrees, forming a well on the top surface of the substrate and the sidewalls and the bottom surface of the trench, forming a source region on the bottom surface of the trench, and forming a drain region on the bottom surface of the trench. The method includes forming a trench on a substrate, forming a body contact region on a bottom surface of the trench, the body contact region being adjacent to the source region, forming a gate structure along a top surface of the substrate and sidewalls and the bottom surface of the trench, and forming a source contact in the trench to penetrate the gate structure and electrically connect the source region and the body contact region. The semiconductor device disclosed by the invention can provide a larger current under the condition of the same area, so that a smaller on-resistance can be provided.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Metal oxide semiconductor field effect transistors (MOS FETs) can be divided into horizontal channel MOSFETs and vertical channel MOSFETs according to their channel direction. Among them, vertical channel MOSFETs can provide the same current in a smaller area and obtain a smaller on-resistance (Rdson), which can greatly reduce production costs. How to further improve the efficiency of vertical channel MOSFETs has also become one of the important issues. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising forming a groove in a substrate, the groove extending downward from the top surface of the substrate, and the groove having side walls and a bottom surface, and the angle between the side walls and the bottom surface is greater than or equal to 90 degrees, forming a well on the top surface of the substrate and the side walls and bottom surface of the groove, forming a source region on the bottom surface of the groove, forming a body contact region on the bottom surface of the groove, and the body contact region is adjacent to the source region, forming a gate structure along the top surface of the substrate and the side walls and bottom surface of the groove, and forming a source contact in the groove to penetrate the gate structure and electrically connect the source region and the body contact region.

[0004] In some embodiments, the groove is an inverted trapezoidal groove.

[0005] In some embodiments, forming the trench in the substrate includes forming a plurality of stepped dielectric layer stacks on the substrate, and etching the substrate to form the trench using the stepped dielectric layer stacks as a mask.

[0006] In some embodiments, forming a stepped dielectric layer stack on a substrate includes forming a dielectric layer stack on the substrate, the dielectric layer stack including a plurality of first dielectric layers and a plurality of second dielectric layers that are cross-stacked, the first dielectric layer being made of a first material, and the second dielectric layer being made of a second material different from the first material, and patterning the dielectric layer stack multiple times through a mask to form a stepped dielectric layer stack.

[0007] In some embodiments, when etching a substrate using the stepped dielectric layer stack as a mask, the stepped dielectric layer stack and the substrate are etched at the same etching rate.

[0008] In some embodiments, the angle between the sidewall and the bottom surface is determined according to the lattice arrangement direction of the substrate.

[0009] Some embodiments of the present disclosure provide a semiconductor device, including a substrate, a gate structure, a source contact, and a drain electrode. The substrate has a groove extending downward from the top surface of the substrate, the groove has a sidewall and a bottom surface, and the angle between the sidewall and the bottom surface is greater than or equal to 90 degrees. The gate structure is on the substrate and along the top surface of the substrate, the sidewall and the bottom surface of the groove. The source contact is in the groove of the substrate and penetrates the gate structure to electrically connect the source region of the substrate. The drain electrode is under the substrate.

[0010] In some embodiments, the groove is an inverted trapezoidal groove.

[0011] In some embodiments, the source region is at the bottom of the trench, and the substrate further includes a well and a body contact region. The well is along the top surface of the substrate, the sidewalls and the bottom surface of the trench. The body contact region is at the bottom of the trench and adjacent to the source region.

[0012] In some embodiments, the extension direction of the sidewall of the trench is the same as the lattice arrangement direction of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 6 A cross-sectional view of a semiconductor device formed in some embodiments of the present disclosure is shown.

[0014] Figure 7 Cross-sectional views of semiconductor devices according to other embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0015] Some embodiments of the present disclosure are directed to forming a power semiconductor device with a vertical channel. The power semiconductor device with a vertical channel can provide a larger current with the same area, and thus can provide a smaller on-resistance.

[0016] Figures 1 to 6 FIG. 1 is a cross-sectional view of a semiconductor device formed in some embodiments of the present disclosure. Figure 1 , providing a substrate 110. The substrate 110 may be any suitable semiconductor substrate. For example, the substrate 110 may be a silicon substrate or a silicon carbide substrate. In some embodiments, the substrate 110 is a lightly doped region having a first conductivity type, for example, the substrate 110 may be an N-type lightly doped region and include N-type dopants, such as arsenic, phosphorus, and nitrogen.

[0017] Next, a dielectric layer stack is formed on the substrate 110, the dielectric layer stack comprising a plurality of cross-stacked first dielectric layers 210 and a plurality of second dielectric layers 220, the first dielectric layer 210 being made of a first material, and the second dielectric layer 220 being made of a second material different from the first material. In some embodiments, the first dielectric layer 210 may be made of silicon oxide, and the second dielectric layer 220 may be made of silicon nitride. In some embodiments, the thickness of the first dielectric layer 210 and the second dielectric layer 220 may be between 0.1 micrometers and 0.5 micrometers. In some embodiments, the dielectric layer stack may comprise 2 to 10 layers of the first dielectric layer 210 and the second dielectric layer 220. In the following description, the present disclosure takes the dielectric layer stack comprising 3 layers of the first dielectric layer 210A, 210B and 210C and the second dielectric layer 220A, 220B and 220C as an example.

[0018] Next, a first patterning process is performed by using a photomask to pattern the dielectric layer stack, and the dielectric layer stack has a first sidewall S1. Specifically, a first photoresist layer may be formed on the dielectric layer stack, and the first photoresist layer may be patterned by using a photomask, and then all dielectric layers in the dielectric layer stack may be patterned by using the first photoresist layer. At this time, the photomask is located at a first position.

[0019] Next, the mask is moved in the first direction D1, and a second patterning process is performed through the mask to partially pattern the dielectric layer stack, so that the dielectric layer stack has a first side wall S1 and a second side wall S2 offset in the first direction D1, and the second side wall S1 is on the first side wall S1. Specifically, a second photoresist layer can be formed on the dielectric layer stack, and the mask is moved along the first direction D1 based on the first position, so that the mask is located at the second position, and the second photoresist layer is patterned through the mask. Among them, the second photoresist layer is offset along the first direction D1 compared to the first photoresist layer. Next, the second photoresist layer is first used as a mask, and the first gas is used to etch the second dielectric layer 220C, and then the second dielectric layer 220C is used as a mask, and the second gas is used to etch the first dielectric layer 210C. Since the second dielectric layer 220 and the first dielectric layer 210 are made of different materials, different etching gases can be selected to etch the first dielectric layer 210 and the second dielectric layer 220 respectively. In the present disclosure, the first gas may be defined as a gas having a higher etching rate for the second dielectric layer 220 than for the first dielectric layer 210. The second gas may be defined as a gas having a higher etching rate for the first dielectric layer 210 than for the second dielectric layer 220.

[0020] Next, the mask is moved in the first direction, and a third patterning process is performed through the mask to partially pattern the dielectric layer stack, so that the dielectric layer stack also has a third sidewall S3, and the third sidewall S3 is offset in the first direction D1 compared to the second sidewall S2, and the third sidewall S3 is on the second sidewall S2. Specifically, a third photoresist layer can be formed on the dielectric layer stack, and the mask is moved along the first direction D1 based on the second position, so that the mask is located at the third position, and the third photoresist layer is patterned through the mask. Among them, the third photoresist layer is offset along the first direction D1 compared to the second photoresist layer. Next, the photoresist layer and the first dielectric layer 210C are used as masks respectively, and the first gas is used to etch the second dielectric layer 220C and the second dielectric layer 220B respectively. Next, the second dielectric layer 220C and the second dielectric layer 220B are used as masks respectively, and the second gas is used to etch the first dielectric layer 210C and the first dielectric layer 210B in the middle respectively.

[0021] Next, the mask is moved in the first direction D1, and a fourth patterning process is performed through the mask to partially pattern the dielectric layer stack, so that the dielectric layer stack also has a fourth side wall S4, and compared with the third side wall S3, the fourth side wall S4 is offset in the first direction, and the fourth side wall S4 is on the third side wall S3. Specifically, a fourth photoresist layer can be formed on the dielectric layer stack, and the mask is moved along the first direction based on the third position, so that the mask is located at the fourth position, and the fourth photoresist layer is patterned through the mask. Among them, the fourth photoresist layer is offset along the first direction D1 compared to the third photoresist layer. Next, the fourth photoresist layer, the first dielectric layer 210C and the first dielectric layer 210B are used as masks, and the second dielectric layer 220C, the second dielectric layer 220B and the second dielectric layer 220A are etched respectively using the first gas. At this point, the side wall of one side of the dielectric layer stack is formed into a stepped shape.

[0022] Next, in a similar manner to the above, the sidewall of the other side of the dielectric layer stack is also formed into a step shape (for example, the above-mentioned mask is moved from the first position to the second direction D2), so that a plurality of stepped dielectric layer stacks 200 can be formed on the substrate 110. In the present disclosure, the dielectric layer stack can be patterned by the mask PM to form the stepped dielectric layer stack 200. The shape of the sidewall of the stepped dielectric layer stack 200 can be determined by the amplitude of each movement of the mask PM. In addition, the offset distance of the second photoresist layer, the third photoresist layer, and the fourth photoresist layer corresponds to the amplitude of each movement of the mask. The stepped dielectric layer stack 200 includes sidewalls S1, S2, S3, and S4 that are sequentially retracted. In some embodiments, the horizontal distance between two adjacent sidewalls (for example, the horizontal distance between the sidewalls S1 and S2, the horizontal distance between the sidewalls S2 and S3, and the horizontal distance between the sidewalls S3 and S4) is approximately between 0.1 microns and 0.5 microns. The stepped dielectric layer stack 200 includes a plurality of first dielectric layers 210 and a plurality of second dielectric layers 220 stacked crosswise, wherein the first dielectric layer 210 is made of a first material, and the second dielectric layer 220 is made of a second material different from the first material. In some embodiments, the first dielectric layer 210 may be made of silicon oxide, and the second dielectric layer 220 may be made of silicon nitride. In some embodiments, the thickness of the first dielectric layer 210 and the second dielectric layer 220 may be between 0.1 micrometers and 0.5 micrometers. In some embodiments, the dielectric layer stack may include 2 to 10 layers of the first dielectric layer 210 and the second dielectric layer 220, respectively.

[0023] refer to Figure 2 , a trench T is formed in the substrate 110. Specifically, the substrate 110 can be etched with the stepped dielectric layer stack 200 as a mask to form the trench T. When etching the substrate 110 with the stepped dielectric layer stack 200 as a mask, the stepped dielectric layer stack 200 and the substrate 110 are etched at the same etching rate until the stepped dielectric layer stack 200 is completely etched. Therefore, a stepped trench T can be formed in the substrate 110.

[0024] After forming the stepped groove T, the surface of the substrate 110 may be smoothed so that the surface of the groove T of the substrate 110 becomes smooth. Figure 3 , the substrate 110 may be subjected to an oxidation process to form an oxide layer 111 on the surface of the substrate 110, and then Figure 4 , removing the oxide layer 111, so that the surface of the trench T of the substrate 110 becomes smooth. After the smoothing process, the trench T extends downward from the top surface 112 of the substrate 110, and the trench T has a sidewall 114 and a bottom surface 116, and the angle between the sidewall 114 and the bottom surface 116 is greater than 90 degrees. In other words, the trench T is an inverted trapezoidal trench.

[0025] refer to Figure 5 , a first ion implantation process is performed on the substrate 110 to form a well 122 on the top surface 112 of the substrate 110 and the sidewalls 114 and bottom surface 116 of the trench T. Specifically, when performing the first ion implantation process, a second conductive type dopant may be implanted into the substrate 110 to form a well 122 with the second conductive type on the top surface 112 of the substrate 110 and the sidewalls 114 and bottom surface 116 of the trench T. In some embodiments, the well 122 may be a lightly doped region of the second conductive type, for example, the well 122 may be a lightly doped region of the P type and include P type dopant, such as boron, gallium and aluminum. The remaining region not implanted with the second conductive type dopant still remains as a doped region of the first semiconductor type, and this doped region with the first semiconductor type may be referred to as a drift region 121. The doping concentration of the well 122 is higher than the doping concentration of the drift region 121.

[0026] Next, a second ion implantation process is performed on the substrate 110 to form a source region 124 on the bottom surface 116 of the trench T. Specifically, when the second ion implantation process is performed, a first conductive type dopant may be implanted into the substrate 110 to form a first conductive type source region 124 on the bottom surface 116 of the trench T. In some embodiments, the source region 124 may be a heavily doped region of the first conductive type, and the doping concentration of the source region 124 is higher than the doping concentration of the well 122. For example, the source region 124 may be an N-type heavily doped region and include N-type dopant, such as arsenic, phosphorus, and nitrogen.

[0027] After forming the source region 124, a junction field-effect transistor (JFET) region 126 may also be formed on the top surface 112 of the substrate 110, so that the JFET region 126 has the same conductivity type and doping concentration as the source region 124. In some embodiments, the JFET region 126 may be a heavily doped region of a first conductivity type, for example, the JFET region 126 may be an N-type heavily doped region and include N-type dopants, such as arsenic, phosphorus, and nitrogen.

[0028] Next, a third ion implantation process is performed on the substrate 110 to form a body contact region 128 on the bottom surface 116 of the trench T, and the body contact region 128 is adjacent to the source region 124. Specifically, when performing the third ion implantation process, a second conductive type dopant may be implanted into the substrate 110 to form a body contact region 128 having the second conductive type on the bottom surface 116 of the trench T. In some embodiments, the body contact region 128 may be a heavily doped region of the second conductive type, and the doping concentration of the body contact region 128 is higher than the doping concentration of the well 122. For example, the body contact region 128 may be a heavily doped region of the P type and include a P type dopant, such as boron, gallium, and aluminum.

[0029] Next, a gate structure 130 is formed along the top surface 112 of the substrate 110 and the sidewalls 114 and bottom surface 116 of the trench T. In some embodiments, the gate structure 130 may have a first horizontal portion located on the top surface 112 of the substrate 110, an inclined portion located on the sidewalls 114 of the trench T, and a second horizontal portion located on the bottom surface 116 of the trench T. Specifically, a gate dielectric layer 132 may be first formed on the substrate 110 and along the top surface 112 of the substrate 110, the sidewalls 114 and bottom surface 116 of the trench T. Next, a gate layer 134 is formed on the gate dielectric layer 132. The gate dielectric layer 132 and the gate layer 134 may be collectively referred to as a gate structure 130. Next, an opening may be formed in the gate structure 130 to expose the body contact region 128 and a portion of the source region 124. In some embodiments, the gate dielectric layer 132 may be made of silicon oxide, and the gate layer 134 may be made of polysilicon.

[0030] refer to Figure 6 , a dielectric layer 140 is formed on the substrate 110 and in the trench T. The dielectric layer 140 also fills the opening of the gate structure 130. Next, a source contact 150 is formed in the trench T to penetrate the gate structure 130 and contact the source region 124 and the body contact region 128. Specifically, an opening exposing the source region 124 and the body contact region 128 may be first formed in the dielectric layer 140, and then a contact material is formed in the opening to form the source contact 150. Therefore, the source contact 150 penetrates the dielectric layer 140 and the gate structure 130 at the same time and contacts the source region 124 and the body contact region 128, and the dielectric layer 140 surrounds the source contact 150. Next, a drain electrode 160 is formed under the substrate 110.

[0031] In this way, we can get Figure 6The semiconductor device may include a substrate 110, a gate structure 130, a source contact 150, and a drain electrode 160. The substrate 110 has a trench T extending downward from the top surface 112 of the substrate 110, the trench T has a sidewall 114 and a bottom surface 116, and the angle between the sidewall 114 and the bottom surface 116 is greater than 90 degrees. The substrate 110 includes a drift region 121, a well 122, a JFET region 126, a body contact region 128, and a source region 124. The well 122 is on the drift region 121, and the well 122 is along the top surface 112 of the substrate 110, the sidewall 114 and the bottom surface 116 of the trench T. The JFET region 126 is on the top surface 112 of the substrate 110. The source region 124 is on the bottom surface 116 of the trench T. The body contact region 128 is on the bottom surface 116 of the trench T and is adjacent to the source region 124. The gate structure 130 is on the substrate 110 and along the top surface 112 of the substrate 110, the sidewalls 114 and the bottom surface 116 of the trench T. The source contact 150 is in the trench T of the substrate 110 and penetrates the gate structure 130 and electrically connects the source region 124 and the body contact region 128 to contact the substrate 110. The drain electrode 160 is under the substrate 110.

[0032] The semiconductor device disclosed in the present invention has a vertical channel, and the vertical channel is a well 122 along the sidewall 114 of the trench T. When the semiconductor device has a vertical channel, for example, when the angle between the sidewall 114 and the bottom surface 116 of the trench T is greater than 90 degrees, a larger current can be provided under the same area, and thus a smaller on-resistance can be provided. In addition, the angle between the sidewall 114 and the bottom surface 116 can be determined according to the lattice arrangement direction of the substrate 110. Specifically, the angle between the sidewall 114 and the bottom surface 116 can determine the extension direction of the well 122 along the sidewall 114 of the trench, that is, the direction of the channel. When the direction of the channel is the same as the arrangement direction of the substrate 110, the carrier can have the maximum carrier mobility in the channel. In other words, the angle between the sidewall 114 and the bottom surface 116 can be determined according to the lattice arrangement direction of the substrate 110 to ensure that the carrier can have the maximum carrier mobility in the channel and have the maximum current (for example, when the extension direction of the sidewall 114 of the trench is the same as the lattice arrangement direction of the substrate 110). Since a portion of the gate structure 130 is formed along the sidewall 114 of the trench, when the extension direction of the sidewall 114 of the trench is the same as the lattice arrangement direction of the substrate 110 , the extension direction of the gate structure 130 on the sidewall 114 of the trench is also the same as the lattice arrangement direction of the substrate 110 .

[0033] Figure 7 Cross-sectional views of semiconductor devices according to other embodiments of the present disclosure are shown. Figure 7 Semiconductor devices and Figure 6 The semiconductor devices are similar to Figure 7The angle between the sidewall 114 and the bottom surface 116 of the trench of the semiconductor device is 90 degrees. Figure 7 When the semiconductor device is Figure 1 In the step of replacing the stepped dielectric layer stack with a hard mask layer having vertical sidewalls, and using the hard mask layer having vertical sidewalls to etch the substrate 110. Figures 2 to 6 The steps to form Figure 7 When the angle between the sidewall 114 and the bottom surface 116 of the trench of the semiconductor device is 90 degrees, the semiconductor device can also provide a larger current under the condition of the same area, and thus can provide a smaller on-resistance.

[0034] The above descriptions are only some embodiments of the present disclosure, not all embodiments. Any equivalent changes made to the technical solution of the present disclosure by ordinary technicians in this field after reading the specification of the present disclosure are covered by the claims of the present disclosure.

[0035]

Explanation of symbols

[0036] 110: Substrate

[0037] 111: Oxide layer

[0038] 112: Top

[0039] 114: Sidewall

[0040] 116: Bottom

[0041] 121: Drift Zone

[0042] 122: Trap

[0043] 124: Source region

[0044] 126: Junction Field Effect Transistor Region / JFET Region

[0045] 128: Body contact area

[0046] 130: Gate structure

[0047] 132: Gate dielectric layer

[0048] 134: Gate layer

[0049] 140: Dielectric layer

[0050] 150: Source contact

[0051] 160: Drain electrode

[0052] 210: First dielectric layer

[0053] 220: Second dielectric layer

[0054] S1, S2, S3, S4: Sidewall

[0055] T: Groove.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: A groove is formed in the substrate, the groove extending downward from the top surface of the substrate, and the groove has a side wall and a bottom surface, and the angle between the side wall and the bottom surface is greater than or equal to 90 degrees; forming a well on the top surface of the substrate and the sidewalls and bottom surface of the trench; forming a source region on the bottom surface of the trench; forming a body contact region on the bottom surface of the trench, wherein the body contact region is adjacent to the source region; forming a gate structure along the top surface of the substrate and the sidewalls and bottom surface of the trench; A source contact is formed in the trench to penetrate the gate structure and electrically connect the source region and the body contact region.

2. The method according to claim 1, characterized in that The groove is an inverted trapezoidal groove.

3. The method according to claim 2, characterized in that Forming the trench in the substrate comprises: forming a plurality of stepped dielectric layer stacks on the substrate; and The substrate is etched using the plurality of stepped dielectric layer stacks as masks to form the trenches.

4. The method according to claim 3, characterized in that Forming the plurality of stepped dielectric layer stacks on the substrate comprises: forming a dielectric layer stack on the substrate, the dielectric layer stack comprising a plurality of first dielectric layers and a plurality of second dielectric layers that are cross-stacked, the plurality of first dielectric layers being made of a first material, and the plurality of second dielectric layers being made of a second material different from the first material; and The dielectric layer stack is patterned multiple times by a photomask to form the multiple stepped dielectric layer stacks.

5. The method according to claim 3, characterized in that: When the substrate is etched using the plurality of stepped dielectric layer stacks as masks, the plurality of stepped dielectric layer stacks and the substrate are etched at the same etching rate.

6. The method according to any one of claims 1 to 5, characterized in that: The angle between the side wall and the bottom surface is determined according to the lattice arrangement direction of the substrate.

7. A semiconductor device, characterized in that: Include: A substrate having a groove extending downward from a top surface of the substrate, the groove having a side wall and a bottom surface, and an angle between the side wall and the bottom surface is greater than or equal to 90 degrees; a gate structure on the substrate and along the top surface of the substrate, the sidewalls of the trench and the bottom surface; a source contact in the trench of the substrate and extending through the gate structure to electrically connect to a source region of the substrate; as well as A drain electrode is under the substrate.

8. The semiconductor device according to claim 7, wherein: The groove is an inverted trapezoidal groove.

9. The semiconductor device according to any one of claims 7 to 8, characterized in that The source region is located at the bottom surface of the trench, and the substrate further comprises: a well along the top surface of the substrate, the sidewalls of the trench and the bottom surface; and A body contact region is located at the bottom surface of the trench and adjacent to the source region.

10. The semiconductor device according to any one of claims 7 to 8, characterized in that The extending direction of the sidewall of the groove is the same as the lattice arrangement direction of the substrate.

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