Groove type super junction field effect transistor and preparation method thereof

Abstract

According to the trench type super junction field effect transistor and the preparation method thereof, the conductive column is formed in the first trench through an epitaxial filling method, the depth-to-width ratio of the conductive column formed through filling is reduced, the formed conductive column has a small pitch size, and the reliability of the trench type super junction field effect transistor is improved. And then forming a third epitaxial layer with a plurality of sub-epitaxial layers on the second epitaxial layer through a multi-layer epitaxial process, and etching while extending so as to form well regions in the plurality of sub-epitaxial layers, thereby greatly reducing thermal budget and photoetching cost in the forming process of the super junction field effect transistor. A well region formed in a sub-epitaxial layer in the third epitaxial layer also has a small pitch size, and the combination of the processes enables a formed P-type conductive column to be narrow and an N-type epitaxial layer where the P-type conductive column is located to be wide. Therefore, when the device is used up and unfolded, the switching speed of a body diode region formed by the P-type well region, the P-type conductive column and the N-type epitaxial layer is slowed down, the abrupt change capacitance is reduced, and the EMI performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a trench type super junction field effect transistor and a preparation method thereof. Background Art

[0002] As an advanced power MOS device technology, the trench superjunction field effect transistor (Super Junction Trench MOSFET) combines the advantages of trench structure and superjunction technology. The trench structure makes the device have higher current density and lower resistance, and the superjunction technology enables the device to maintain a higher breakdown voltage while reducing the on-resistance, so it is widely used in the modern electronic field of medium and high voltage.

[0003] In the prior art, the SJ-MOSFET device cell region obtained by the trench filling method, the P-type conductive column is formed by deep trench etching the N-type epitaxial layer and then filling the P-type epitaxial layer. The process of super junction switching is to charge and discharge the parasitic capacitance of the MOS device to open and close the channel of the MOS device. The P-type well region of the super junction, the P-type conductive column and the N-type epitaxial layer form a body diode, which plays the role of a freewheeling diode in the process of super junction switching. However, since the charging and discharging process of the parasitic capacitance of the MOS device will resonate with the inductance and capacitance in the application topology, the gate voltage of the MOS device will be out of control, thereby causing the MOS device to fail. It can be seen from this that the EMI performance of the super junction MOS can be improved by improving the parasitic capacitance of the MOS device. However, when reducing the pitch size to improve the parasitic capacitance of the MOS device, it is not easy to reduce the pitch size using the traditional deep trench filling technology, and it is difficult to improve the parasitic capacitance of the MOS device using the multi-layer epitaxial technology due to the thermal budget and lithography cost.

[0004] Therefore, how to provide a trench superjunction field effect transistor that can both reduce the pitch size and improve the EMI performance of the superjunction MOS has become a problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a trench type super junction field effect transistor and a preparation method thereof, so as to solve the problem in the prior art that the pitch size of the trench type super junction field effect transistor is difficult to reduce and the resulting EMI performance cannot be improved.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a trench superjunction field effect transistor, the method comprising: providing a semiconductor substrate having a first conductivity type, and sequentially forming a first epitaxial layer of the first conductivity type, a second epitaxial layer of the first conductivity type, and a first hard mask layer on a surface of the semiconductor substrate from bottom to top;

[0007] Patterning the first hard mask layer, and etching the first epitaxial layer and the second epitaxial layer to form a plurality of first trenches in the first epitaxial layer and the second epitaxial layer;

[0008] Filling a conductive column having a second conductivity type in the first trench, and removing the first hard mask layer;

[0009] forming a third epitaxial layer of the first conductivity type on the second epitaxial layer, and performing ion implantation at a preset depth on the surface of the third epitaxial layer to form a well region of the second conductivity type;

[0010] forming a body region of a second conductivity type on the third epitaxial layer and forming a second hard mask layer on the body region;

[0011] Patterning the second hard mask layer, etching the body region and the third epitaxial layer, forming a plurality of second trenches in the body region and the third epitaxial layer, and removing the second hard mask layer;

[0012] forming a first interlayer dielectric layer on the inner wall of the second trench, and forming a first polysilicon filling the second trench on the first interlayer dielectric layer, wherein the first polysilicon, the first interlayer dielectric layer and the body region have flush surfaces;

[0013] forming a source region having a first conductivity type and a second interlayer dielectric layer on the body region, and forming a first electrode contact hole penetrating the second interlayer dielectric layer and exposing the body region at the bottom, and a second electrode contact hole exposing the first polysilicon;

[0014] The first electrode contact hole and the second electrode contact hole are filled with metal to form a front metal layer.

[0015] Optionally, the doping concentration of the conductive column is 0.6E15 NA / cm 3 ~1.5E15 NA / cm 3 , the width of the conductive pillar is 2-5 μm, and the depth of the conductive pillar in the first groove is 15-25 μm.

[0016] Optionally, the third epitaxial layer includes a plurality of sub-epitaxial layers formed sequentially, the number of the sub-epitaxial layers is 3 to 6, the well regions formed in each sub-epitaxial layer have the same width, and the width of the well regions is greater than 20% to 80% of the width of the conductive column.

[0017] Optionally, the method for forming the conductive column includes: based on a CVD process, introducing epitaxial gas, doping gas and etching gas to deposit the conductive column in the first groove, and performing a chemical mechanical polishing process on the conductive column so that the conductive column, the second epitaxial layer and the first groove have a flush surface.

[0018] Optionally, the first interlayer dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer, or a stacked combination; the second interlayer dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer, or a stacked combination.

[0019] Optionally, after forming the front metal layer, the following steps are also included: forming a photoresist layer on the upper surface of the front metal layer and patterning the photoresist layer; etching the front metal layer based on the patterned photoresist layer to form a plurality of first isolation grooves, wherein the first isolation grooves isolate the source region from the front metal layer on the first polysilicon to form the source electrode on the source region, forming a gate electrode on the first polysilicon, and removing the remaining photoresist layer.

[0020] Optionally, after forming the source electrode, the following steps are also included: forming a passivation layer on the upper surface of the front metal layer, and photolithography and etching the passivation layer to form a plurality of pad windows to expose the source electrode and the gate electrode; thinning the back side of the substrate layer to form a drain electrode; and performing a back gold process on the lower surface of the drain electrode to form a back metal layer.

[0021] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0022] The present invention also provides a trench type super junction field effect transistor, the trench type super junction field effect transistor comprising:

[0023] A semiconductor substrate of a first conductivity type, and a first epitaxial layer of the first conductivity type, a second epitaxial layer of the first conductivity type, and a first hard mask layer located on a surface of the semiconductor substrate;

[0024] a first trench located in the first epitaxial layer and the second epitaxial layer;

[0025] A conductive column of the second conductive type is located in the first trench and completely fills the first trench, and the conductive column, the second epitaxial layer and the first trench have flush surfaces;

[0026] A third epitaxial layer of the first conductivity type, located on the second epitaxial layer;

[0027] A well region of the second conductivity type, located in the third epitaxial layer and connected to the conductive pillar;

[0028] A body region of the second conductivity type, located on the third epitaxial layer;

[0029] a second trench located in the third epitaxial layer and the body region;

[0030] A first interlayer dielectric layer, located on an inner wall of the second trench;

[0031] A first polysilicon layer is located on the first interlayer dielectric layer and fills the second trench;

[0032] a source region, located on the body region and having a flush surface with the first interlayer dielectric layer and the first polysilicon;

[0033] A second interlayer dielectric layer is located on the source region and has a first electrode contact hole exposing the source region and a second electrode contact hole exposing the first polysilicon;

[0034] A front metal layer, wherein the front metal layer fills the first electrode contact hole and the second electrode contact hole and has a first isolation groove therein, wherein the first isolation groove isolates the source region from the front metal layer on the first polysilicon, so that the front metal layer on the source region forms a source electrode, and the front metal layer on the first polysilicon forms a gate electrode;

[0035] The drain is located on the back side of the semiconductor substrate and a back metal layer is disposed on the lower surface of the drain.

[0036] Optionally, the third epitaxial layer includes a plurality of sub-epitaxial layers and the number of layers of the sub-epitaxial layers is 3 to 6.

[0037] Optionally, the width of the conductive pillar is 2-5 μm, and the width of the well region is greater than 20%-80% of the width of the conductive pillar.

[0038] Optionally, the trench superjunction field effect transistor further includes: a passivation layer located on the front metal layer, and the passivation layer has a plurality of pad windows, and the pad windows expose the source and the gate.

[0039] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0040] As described above, the present invention provides a trench-type superjunction field effect transistor and a preparation method thereof, which have the following beneficial effects: the aspect ratio of the first trench formed by etching and filling the epitaxial layer is reduced by the method of epitaxial deep trench filling, so that the conductive pillars formed in the first epitaxial layer and the second epitaxial layer have a smaller pitch size, and the number of sub-epitaxial layers in the third epitaxial layer is subsequently controlled by a multi-layer epitaxial process to greatly reduce the thermal budget and lithography cost in the formation process of the superjunction field effect transistor, so that the well region formed in the sub-epitaxial layer in the third epitaxial layer also has a smaller pitch size. The combination of the above processes makes the conductive pillars formed narrower and the area where the well region is located wider, so that the switching speed of the body diode area formed by the P-type well region, the P-type conductive pillar and the N-type epitaxial layer when the device is depleted and expanded is slowed down, thereby reducing the mutation capacitance and improving the EMI performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic flow chart of the method for preparing the trench type super junction field effect transistor of the present invention.

[0042] Figure 2 It is a schematic diagram of the cross-sectional structure after forming a first epitaxial layer, a second epitaxial layer and a first hard mask layer on a semiconductor substrate according to the present invention.

[0043] Figure 3 It is a schematic diagram of the cross-sectional structure after the first groove is formed in the present invention.

[0044] Figure 4 It is a schematic diagram of the cross-sectional structure after the conductive pillar is formed according to the present invention.

[0045] Figure 5 It is a schematic diagram of the cross-sectional structure after forming the third epitaxial layer and the well region according to the present invention.

[0046] Figure 6 It is a schematic diagram of the cross-sectional structure after the body region and the second hard mask layer are formed according to the present invention.

[0047] Figure 7 It is a schematic diagram of the cross-sectional structure after the second groove is formed in the present invention.

[0048] Figure 8 It is a schematic diagram of the cross-sectional structure after forming the first interlayer dielectric layer and the first polysilicon according to the present invention.

[0049] Fig. 9 It is a schematic diagram of the cross-sectional structure after the source region and the second interlayer dielectric layer are formed according to the present invention.

[0050] Fig.10 It is a schematic diagram of the cross-sectional structure after the first electrode contact hole and the second electrode contact hole are formed according to the present invention.

[0051] Fig.11 It is a schematic diagram of the cross-sectional structure after the front metal layer, the first isolation groove, the gate and the source are formed in the present invention.

[0052] Fig.12 It is a schematic diagram of the cross-sectional structure after the passivation layer and the pad window are formed according to the present invention.

[0053] Fig.13 It is a schematic diagram showing the cross-sectional structure of forming the drain electrode and the back metal layer according to the present invention.

[0054] Component number description

[0055] 111, semiconductor substrate; 112, first epitaxial layer; 113, second epitaxial layer; 12, first trench; 13, first hard mask layer; 131, first silicon dioxide layer; 132, first silicon nitride layer; 133, second silicon dioxide layer; 14, conductive pillar; 15, third epitaxial layer; 151, first sub-epitaxial layer; 152, second sub-epitaxial layer; 153, third sub-epitaxial layer; 16, well region; 17, body region; 18, second hard mask layer; 181, third silicon dioxide layer; 182, second silicon nitride layer; 183, third Four silicon dioxide layers; 19, second trench; 201, first interlayer dielectric layer; 202, first polysilicon; 21, source region; 22, second interlayer dielectric layer; 221, fifth silicon oxide layer; 222, silicon phosphate glass layer; 231, first electrode contact hole; 232, second electrode contact hole; 24, front metal layer; 241, gate; 242, source; 25, first isolation groove; 26, passivation layer; 261, silicon nitride layer; 262, polyimide layer; 27, drain; 28, back metal layer; S1~S9, steps. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0058] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0059] See also Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0060] Example 1

[0061] This embodiment provides a method for preparing a trench type super junction field effect transistor. Figure 1 , shown as a process flow chart of the preparation method, comprising the following steps:

[0062] S1: providing a semiconductor substrate 111 having a first conductivity type, and sequentially forming a first epitaxial layer 112 of the first conductivity type, a second epitaxial layer 113 of the first conductivity type, and a first hard mask layer 13 on the surface of the semiconductor substrate 111 from bottom to top;

[0063] S2: patterning the first hard mask layer 13, and etching the first epitaxial layer 112 and the second epitaxial layer 113 to form a plurality of first trenches 12 in the first epitaxial layer 112 and the second epitaxial layer 113;

[0064] S3: filling the first trench 12 with a conductive pillar 14 of the second conductivity type, and removing the first hard mask layer 13;

[0065] S4: forming a third epitaxial layer 15 of the first conductivity type on the second epitaxial layer 113 , and performing ion implantation of a preset depth on the surface of the third epitaxial layer 15 to form a well region 16 of the second conductivity type;

[0066] S5: forming a body region 17 of a second conductivity type on the third epitaxial layer 15 and forming a second hard mask layer 18 on the body region 17;

[0067] S6: patterning the second hard mask layer 18, etching the body region 17 and the third epitaxial layer 15, forming a plurality of second trenches 19 in the body region 17 and the third epitaxial layer 15, and removing the second hard mask layer 18;

[0068] S7: forming a first interlayer dielectric layer 201 on the inner wall of the second trench 19, and forming a first polysilicon 202 filling the second trench 19 on the first interlayer dielectric layer 201, wherein the first polysilicon 202, the first interlayer dielectric layer 201 and the body region 17 have flush surfaces;

[0069] S8: forming a source region 21 having a first conductivity type and a second interlayer dielectric layer 22 on the body region 17, and forming a first electrode contact hole 231 penetrating through the second interlayer dielectric layer 22 and exposing the body region 17 at the bottom, and a second electrode contact hole 232 exposing the first polysilicon 202;

[0070] S9: filling the first electrode contact hole 231 and the second electrode contact hole 232 with metal to form a front metal layer 24 .

[0071] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type, for example, the first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type. In this embodiment, the first conductivity type is N type and the second conductivity type is P type as an example for explanation. In addition, the N-type doping ions can be pentavalent ions such as nitrogen, phosphorus, arsenic, and antimony, and the P-type doping ions can be trivalent ions such as boron, aluminum, gallium, and indium, which are selected according to actual needs and are not excessively restricted here.

[0072] The method for preparing the trench super junction field effect transistor of this embodiment is described in detail below with reference to the specific drawings.

[0073] like Figure 2 As shown, step S1 is performed to provide a semiconductor substrate 111 having a first conductivity type, and a first epitaxial layer 112 of the first conductivity type, a second epitaxial layer 113 of the first conductivity type and a first hard mask layer 13 are sequentially formed on the surface of the semiconductor substrate 111 from bottom to top.

[0074] Specifically, Figure 2, which is a schematic diagram of a cross-sectional structure of the semiconductor substrate 111 , wherein the semiconductor substrate 111 is of a first conductivity type, and a first epitaxial layer 112 and a second epitaxial layer 113 of the first conductivity type are sequentially formed on the front side of the semiconductor substrate 111 .

[0075] Optionally, the doping concentrations of the semiconductor substrate 111 and the first epitaxial layer 112 and the second epitaxial layer 113 may be sequentially reduced, and the semiconductor substrate 111 may be an N+-type doped silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc., and the first epitaxial layer 112 and the second epitaxial layer 113 are lightly doped single crystal silicon epitaxial layers. In this embodiment, the semiconductor substrate 111 is selected as an N+-type doped silicon substrate, and the first epitaxial layer 112 and the second epitaxial layer 113 are selected as N-type single crystal silicon epitaxial layers. Before performing subsequent processes, the semiconductor substrate 111 may be cleaned first, for example, by sequentially using an organic solvent such as acetone and deionized water to remove pollutants on the surface of the semiconductor substrate 111, and then drying, or first using a dilute acid solution to remove the natural oxide layer on the surface of the semiconductor substrate 111, then using deionized water for cleaning, and finally drying, or using the aforementioned cleaning methods for multiple cleanings.

[0076] Furthermore, a first hard mask layer 13 is formed on the surface of the second epitaxial layer 113, which helps to improve the etching accuracy. The structure of the first hard mask layer 13 can be a single silicon oxide layer with a certain thickness, or can include a combination layer of silicon oxide-silicon nitride-silicon oxide stacked from bottom to top. Preferably, in this embodiment, the first hard mask layer includes a first silicon dioxide layer 131, a first silicon nitride layer 132 and a second silicon dioxide layer 133 from bottom to top, and the thickness of the second silicon dioxide layer 133 is generally greater than the thickness of the first silicon dioxide layer 131. The structural layers of the first hard mask layer can be formed in sequence by chemical vapor deposition process, or by thermal oxidation process to form the first silicon dioxide layer 131, and the first silicon nitride layer 132 and the second silicon dioxide layer 133 can be formed by chemical vapor deposition process. The first silicon dioxide layer 131 serves as a buffer layer to buffer the stress between the first silicon nitride layer 132 and the second epitaxial layer 113, and the first silicon nitride layer 132 serves as an etching stop layer for the second silicon dioxide layer 133. After the first groove 12 is defined in the first hard mask layer 13, the second silicon dioxide layer 133 will be consumed as a hard mask when etching the first groove 12 in the second epitaxial layer 113. Therefore, the first hard mask layer with silicon oxide-silicon nitride-silicon oxide structure can not only help to improve the etching accuracy, but also help to protect the semiconductor substrate 111.

[0077] like Figure 3As shown, step S2 is performed to pattern the first hard mask layer 13 , and to etch the first epitaxial layer 112 and the second epitaxial layer 113 to form a plurality of first trenches 12 in the first epitaxial layer 112 and the second epitaxial layer 113 .

[0078] Specifically, the first hard mask layer 13 is used to define the regional position of the first groove 12 to be prepared through a patterned photolithography process, thereby etching the required first groove 12, wherein the depth of the first groove 12 in the first epitaxial layer 112 and the second epitaxial layer 113 is 15 to 25 μm. The specific implementation of the patterned photolithography and etching process can be implemented by conventional means known to those skilled in the art, and is not specifically limited here.

[0079] like Figure 4 As shown, step S3 is performed to fill the first trench 12 with a conductive pillar 14 having a second conductivity type, and remove the hard mask layer.

[0080] As a preferred example, the process method for preparing the conductive pillar 14 is: based on the chemical vapor deposition (CVD) process, in order to make the epitaxial layer fill the entire deep trench and avoid premature sealing during epitaxial growth, the etching gas will be introduced at the same time as the epitaxial gas and the doping gas, and by adjusting the flow rate of the etching gas, for example, increasing it to about 1800sccm, the method of etching while depositing is adopted to reduce the overall epitaxial growth rate, and the side wall of the deep trench is almost not long, and the epitaxy grows only from the bottom to the top. The epitaxial gas can be selected as needed, for example, when it is silicon epitaxy, the epitaxial gas can be silane, if it is germanium epitaxy, the epitaxial gas can be germane, the doping gas can be N-containing gas or B-containing gas when depositing an N-type epitaxial layer, and the etching gas can be hydrogen chloride gas.

[0081] The specific method is: first use the above-mentioned process method to introduce epitaxial gas, doping gas and etching gas to form a conductive column 14 with the second conductive type extending from bottom to top to be flush with the top of the second epitaxial layer inside the first groove 12, and adjust the gas flow of the doping gas so that the doping concentration of the portion of the conductive column 14 flush with the top of the second epitaxial layer is the same as the doping concentration of the second epitaxial layer.

[0082] As an example, the top of the formed conductive pillar 14 is generally higher than the top of the second epitaxial layer. Therefore, after the conductive pillar 14 is formed, the surface of the conductive pillar 14 can be planarized by using methods including but not limited to chemical mechanical polishing to remove the epitaxial material of the conductive pillar 14 on the surface of the second epitaxial layer 113 outside the first trench 12 to expose the second epitaxial layer 113, so that the surface of the conductive pillar 14 is flush with the surface of the second epitaxial layer 113. The chemical mechanical polishing process combines the effects of mechanical grinding and chemical etching to form a smooth and flat surface on the second epitaxial layer 113, providing a good surface foundation for subsequent processes, and after the surface of the conductive pillar 14 is planarized, the residual first hard mask layer is removed by using methods including but not limited to etching processes.

[0083] As an example, the doping concentration of the conductive pillar 14 is 0.6E15 NA / cm3 to 1.5E15 NA / cm3, the width of the conductive pillar 14 is 2 to 5 μm, and the depth of the conductive pillar 14 in the first groove 12 is 15 to 25 μm. Preferably, in this embodiment, the doping concentration of the conductive pillar 14 is selected to be 1.00E15 NA / cm3, the width of the conductive pillar 14 is 3 μm, and the depth of the conductive pillar 14 in the first groove 12 is 20 μm. By reasonably setting the thickness of the first epitaxial layer 112 and the second epitaxial layer 113, the influence on the Rsp performance of the device is reduced or even avoided, thereby reducing or even avoiding the influence on the conductive efficiency, power loss, switching speed and withstand voltage of the device caused by the above.

[0084] like Figure 5 As shown, step S4 is performed to form a third epitaxial layer 15 of the first conductivity type on the second epitaxial layer 113 , and ion implantation of a preset depth is performed on the surface of the third epitaxial layer 15 to form a well region 16 of the second conductivity type.

[0085] As an example, the third epitaxial layer 15 includes a plurality of sub-epitaxial layers formed in sequence, the number of the sub-epitaxial layers is 3 to 6, the well region 16 formed in each sub-epitaxial layer has the same width, and the width of the well region 16 is greater than 20% to 80% of the width of the conductive column 14.

[0086] Specifically, a first sub-epitaxial layer 151 of the first conductive type third epitaxial layer 15 is formed on the second epitaxial layer 113 by a chemical vapor deposition process, and an implantation region of P-type ions is defined by photolithography, and then an ion implantation process is used to form a well region 16 of the second conductive type at a preset depth in the first sub-epitaxial layer 151 by high temperature, and an electrical connection is formed between the well region 16 and the conductive column 14 in the first trench 12, and then a chemical vapor deposition process is continued to be used to continue to form a second sub-epitaxial layer 152 of the first conductive type third epitaxial layer 15 on the surface of the first sub-epitaxial layer 151, and an ion implantation process is simultaneously performed. The well region 16 of the second conductivity type is formed in the second sub-epitaxial layer 152 by the process. A plurality of sub-epitaxial layers can be formed by continuing to adopt the same process steps. The number of layers of the sub-epitaxial layers is 3 to 6, for example, 3, 4, 5 or 6 layers, and the well region 16 formed in each layer of the sub-epitaxial layer by the process has the same width. The width of the well region 16 is greater than 20% to 80% of the width of the conductive column 14. For example, when the width of the conductive column 14 is 3μm, the width of the well region 16 can be 3.6μm, 4.5μm or 5.4μm. The specific selection is based on actual needs and is not excessively restricted here.

[0087] like Figure 6 As shown, step S5 is performed to form a body region 17 of the second conductivity type on the third epitaxial layer 15 and to form a second hard mask layer 18 on the body region 17 .

[0088] As an example, the body region 17 includes a P-type body region 17, and the method for forming the body region 17 includes ion implantation. For example, ion implantation can be used to implant P-type impurities into the top sub-epitaxial layer in the third epitaxial layer 15. In other examples, photolithography is used to define the implantation area as needed. After the body region 17 is formed, a second hard mask layer 18 is formed on the surface of the body region 17, wherein the structure of the second hard mask layer 18 can be a separate silicon oxide layer with a certain thickness, or can include a combination layer of silicon oxide-silicon nitride-silicon oxide stacked from bottom to top. Preferably, in this embodiment, the second hard mask layer 18 includes, from bottom to top, a third silicon dioxide layer 181, a second silicon nitride layer 182 and a fourth silicon dioxide layer 183. The structural layers of the second hard mask layer 18 can be formed sequentially by a chemical vapor deposition process, or the third silicon dioxide layer 181 can be formed by a thermal oxidation process, and the second silicon nitride layer 182 and the fourth silicon dioxide layer 183 can be formed by a chemical vapor deposition process. The second hard mask layer 18 with a silicon oxide-silicon nitride-silicon oxide structure helps to improve etching accuracy and protect the semiconductor substrate 111.

[0089] like Figure 7As shown, step S6 is performed to pattern the second hard mask layer 18, etch the body region 17 and the third epitaxial layer 15, form a plurality of second trenches 19 in the body region 17 and the third epitaxial layer 15, and remove the second hard mask layer 18.

[0090] Specifically, the second hard mask layer 18 is used to define the regional position of the second groove 19 to be prepared through a patterned photolithography process, so as to etch the required second groove 19 in the body region 17 and the third epitaxial layer 15. The specific implementation of the patterned photolithography and etching process can be implemented by conventional means known to those skilled in the art, and is not specifically limited here. After the second groove 19 is formed, the residual second hard mask layer 18 is removed by including but not limited to an etching process.

[0091] like Figure 8 As shown, step S7 is performed to form a first interlayer dielectric layer 201 on the inner wall of the second trench 19, and to form a first polysilicon 202 filling the second trench 19 on the first interlayer dielectric layer 201, wherein the first polysilicon 202, the first interlayer dielectric layer 201 and the body region 17 have a flush surface.

[0092] Specifically, the first interlayer dielectric layer 201 is formed by generally using a furnace tube and a CVD process to grow a certain thickness of the first interlayer dielectric layer 201 on the surface of the body region 17 and the sidewall of the second trench 19. Optionally, the first interlayer dielectric layer 201 includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer 261, and a silicon phosphate glass layer 222. Preferably, the first interlayer dielectric layer 201 in this embodiment includes a silicon oxide layer.

[0093] Further, the first polysilicon 202 filling the second trench 19 is formed on the first interlayer dielectric layer 201 on the sidewall of the second trench 19, and the first polysilicon 202 is first planarized to expose the surface of the first interlayer dielectric layer 201, and then the first polysilicon 202 and the first interlayer dielectric layer 201 are subjected to a surface planarization process until the first polysilicon 202, the first interlayer dielectric layer 201 and the body region 17 have a flush surface. The surface planarization process may include mechanical grinding or CMP, which is not excessively limited here.

[0094] like Fig. 9As shown, step S8 is performed to form a source region 21 having a first conductivity type and a second interlayer dielectric layer 22 on the body region 17, and to form a first electrode contact hole 231 that penetrates the second interlayer dielectric layer 22 and exposes the body region 17 at the bottom, and a second electrode contact hole 232 that exposes the first polysilicon 202.

[0095] Specifically, N-type impurities are implanted on the body region 17 by an ion implantation process to form a source region 21 with a first conductivity type, so that the source region 21 has a flush surface with the first interlayer dielectric layer 201 and the first polysilicon 202, and a second interlayer dielectric layer 22 is formed on the source region 21 by a PECVD process. Optionally, the second interlayer dielectric layer 22 includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer 261, and a silicon phosphate glass layer 222. Preferably, in this embodiment, the second interlayer dielectric layer 22 includes a fifth silicon oxide layer 221 located on the source region 21 and a silicon phosphate glass layer 222 located on the fifth silicon oxide layer 221.

[0096] Furthermore, electrode contact holes are etched in the second interlayer dielectric layer 22 to form a first electrode contact hole 231 that penetrates the second interlayer dielectric layer 22 and the source region 21 and exposes the body region 17 on the bottom surface, and a second electrode contact hole 232 that penetrates the second interlayer dielectric layer 22 and the source region 21 and exposes the first polysilicon 202 on the bottom surface.

[0097] Specifically, a photoresist masking layer is formed on the second interlayer dielectric layer 22, and the photoresist masking layer is exposed using masks with different critical sizes, and the first electrode contact hole 231 and the second electrode contact hole 232 areas are defined in the developed photoresist masking layer; a dry etching process is used to penetrate the second interlayer dielectric layer 22 and the source region 21 to form the first electrode contact hole 231 and the second electrode contact hole 232 of different critical sizes, the bottom of the first electrode contact hole 231 exposes the body region 17, the bottom of the second electrode contact hole 232 exposes the first polysilicon 202, and the depth of the first electrode contact hole 231 in the body region 17 is equal to the depth of the second electrode contact hole 232 in the first polysilicon 202.

[0098] like Fig.10 As shown, step S9 is performed to fill the first electrode contact hole 231 and the second electrode contact hole 232 with metal to form a front metal layer 24 .

[0099] Specifically, in order to ensure good metal connection between the first electrode contact hole 231 and the second electrode contact hole 232, the present embodiment uses metal to fill the first electrode contact hole 231 and the second electrode contact hole 232, and thins them to form metal connection pillars. In order to avoid metallization of the first polysilicon 202, a chemical vapor deposition process can be used to form a barrier layer covering the inner walls of the first electrode contact hole 231 and the second electrode contact hole 232. Preferably, the material of the barrier layer includes Ti / TiN, and the material of the metal includes tungsten.

[0100] Further, such as Fig.11 As shown, the front metal layer 24 is formed on the surface of the second interlayer dielectric layer 22 and is connected to the metal connection pillars in the first electrode contact hole 231 and the second electrode contact hole 232 .

[0101] Further, such as Fig.11 As shown, after the front metal layer 24 is formed, a photoresist layer is formed on the upper surface of the front metal layer 24, and the photoresist layer is patterned; based on the patterned photoresist layer, the front metal layer 24 is etched to form a plurality of first isolation grooves 25, and the first isolation grooves 25 isolate the source region 21 from the front metal layer 24 on the first polysilicon 202, thereby forming a gate 241 on the first polysilicon 202, forming the source electrode 242 on the source region 21, and then removing the residual photoresist layer.

[0102] Furthermore, if Fig.12 As shown, a passivation layer 26 is formed on the upper surface of the front metal layer 24, and the passivation layer 26 is photoetched to form a plurality of pad windows to expose the source 242 and the gate 241; Fig.13 As shown, the back side of the substrate layer is thinned to form a drain electrode 27 ; and a back-gold process is performed on the lower surface of the drain electrode 27 to form a back metal layer 28 .

[0103] As an example, the passivation layer 26 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 26 can include only a silicon nitride layer 261, or it can include a silicon nitride layer 261 and a polymer layer located on the silicon nitride layer 261. Preferably, in this embodiment, the passivation layer 26 includes a silicon nitride layer 261 and a polyimide layer 262. The silicon nitride layer 261 can be formed by a chemical vapor deposition process, and the polyimide layer 262 can be formed by a spin coating process, so that the passivation layer 26 can better protect the underlying structure, and then etching is performed to form a pad window exposing the source 242 and the gate 241.

[0104] As an example, the back metal layer 28 can be at least one of a copper layer, a gold layer, a nickel layer and other material layers, and there can also be an adhesion layer between the back metal layer 28 and the drain electrode 27, such as a titanium layer and / or a titanium nitride layer, to enhance the adhesion between the back metal layer 28 and the drain electrode 27.

[0105] The method for preparing a trench super junction field effect transistor proposed in this embodiment reduces the aspect ratio of the first trench 12 formed by etching and filling the epitaxial layer by a method of epitaxial deep trench filling, so that the conductive pillars 14 formed in the first epitaxial layer 112 and the second epitaxial layer 113 have a smaller pitch size. Subsequently, the number of sub-epitaxial layers in the third epitaxial layer 15 is controlled by a multi-layer epitaxial process to greatly reduce the thermal budget and lithography cost in the formation process of the super junction field effect transistor, so that the well region 16 formed in the sub-epitaxial layer in the third epitaxial layer 15 also has a smaller pitch size. The combination of the above processes makes the formed conductive pillar 14 narrower and the area where the conductive pillar 14 is located wider, so that the switching speed of the body diode area formed by the P-type well region 16, the P-type conductive pillar 14 and the N-type epitaxial layer is slowed down when the device is depleted and expanded, thereby reducing the mutation capacitance and improving the EMI performance of the device.

[0106] Example 2

[0107] This embodiment provides a trench type super junction field effect transistor, the trench type super junction field effect transistor comprising:

[0108] A semiconductor substrate 111 of the first conductivity type, and a first epitaxial layer 112 of the first conductivity type, a second epitaxial layer 113 of the first conductivity type, and a first hard mask layer 13 located on a surface of the semiconductor substrate 111;

[0109] A first trench 12, located in the first epitaxial layer 112 and the second epitaxial layer 113;

[0110] A conductive pillar 14 of the second conductivity type is located in the first trench 12 and completely fills the first trench 12 , and the conductive pillar 14 , the second epitaxial layer 113 and the first trench 12 have flush surfaces;

[0111] A third epitaxial layer 15 of the first conductivity type, located on the second epitaxial layer 113;

[0112] A well region 16 of the second conductivity type, located in the third epitaxial layer 15 and connected to the conductive pillar 14;

[0113] A body region 17 of the second conductivity type, located on the third epitaxial layer 15;

[0114] A second trench 19, located in the third epitaxial layer 15 and the body region 17;

[0115] A first interlayer dielectric layer 201, located on the inner wall of the second trench 19;

[0116] A first polysilicon 202, located on the first interlayer dielectric layer 201 and filling the second trench 19;

[0117] A source region 21, located on the body region 17 and having a flush surface with the first interlayer dielectric layer 201 and the first polysilicon 202;

[0118] A second interlayer dielectric layer 22 is located on the source region 21 and has a first electrode contact hole 231 exposing the source region 21 and a second electrode contact hole 232 exposing the first polysilicon 202;

[0119] A front metal layer 24, wherein the front metal layer 24 fills the first electrode contact hole 231 and the second electrode contact hole 232 and has a first isolation groove 25 therein, wherein the first isolation groove 25 isolates the source region 21 from the front metal layer 24 on the first polysilicon 202, so that the front metal layer 24 on the source region 21 forms a source 242, and the front metal layer 24 on the first polysilicon 202 forms a gate 241;

[0120] The drain electrode 27 is located on the back side of the semiconductor substrate 111 and a back side metal layer 28 is disposed on the lower surface of the drain electrode 27 .

[0121] In this embodiment, the first conductivity type includes N type and P type, the second conductivity type includes P type and N type, and the first conductivity type is different from the second conductivity type, for example, the first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type. In this embodiment, the first conductivity type is N type and the second conductivity type is P type. In addition, the N-type doping ions can be pentavalent ions such as nitrogen, phosphorus, arsenic, and antimony, and the P-type doping ions can be trivalent ions such as boron, aluminum, gallium, and indium. The selection is based on actual needs and is not excessively limited here.

[0122] As an example, the third epitaxial layer 15 includes a plurality of sub-epitaxial layers and the number of the sub-epitaxial layers is 3 to 6. Specifically, the number of the sub-epitaxial layers is 3 to 6, for example, 3, 4, 5 or 6 layers.

[0123] As an example, the width of the conductive pillar 14 is 2 to 5 μm, and the width of the well region 16 is greater than 20% to 80% of the width of the conductive pillar 14. Specifically, the width of the conductive pillar 14 may be 2 μm, 3 μm, 4 μm or 5 μm, and the width of the well region 16 in the third epitaxial layer 15 is greater than 20% to 80% of the width of the conductive pillar 14. For example, when the width of the conductive pillar 14 is 3 μm, the width of the well region 16 may be 3.6 μm, 4.5 μm or 5.4 μm, which is selected according to actual needs and is not excessively limited here.

[0124] As an example, the trench superjunction field effect transistor further includes: a passivation layer 26 located on the front metal layer 24 , and the passivation layer 26 has a plurality of pad windows, and the pad windows expose the source 242 and the gate 241 .

[0125] Specifically, the passivation layer 26 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 26 can include only a silicon nitride layer 261, or it can include a silicon nitride layer 261 and a polymer layer located on the silicon nitride layer 261. Preferably, in this embodiment, the passivation layer 26 is selected to include a silicon nitride layer 261 and a polyimide layer 262, so that the passivation layer 26 can better protect the underlying structure, and the passivation layer 26 has a plurality of pad windows, and the pad windows reveal the source 242 and the gate 241.

[0126] In summary, the present invention provides a trench-type superjunction field effect transistor and a preparation method thereof, wherein a conductive column is formed in a first trench by an epitaxial deep trench filling method, the depth-to-width ratio of the conductive column formed by etching and epitaxial layer filling is reduced, and the conductive column formed in the first epitaxial layer and the second epitaxial layer has a smaller pitch size, and a third epitaxial layer having multiple sub-epitaxial layers is subsequently formed on the second epitaxial layer by a multi-layer epitaxial process, and a well region is formed in the multiple sub-epitaxial layers by epitaxial and etching, thereby greatly reducing the thermal budget and photolithography cost in the formation process of the superjunction field effect transistor, so that the well region formed in the sub-epitaxial layer in the third epitaxial layer also has a smaller pitch size, and the combination of the above processes makes the formed P-type conductive column narrower and the N-type epitaxial layer where the P-type conductive column is located wider, so that the switching speed of the body diode region formed by the P-type well region, the P-type conductive column and the N-type epitaxial layer when the device is depleted and expanded is slowed down, thereby reducing the mutation capacitance and improving the EMI performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a trench superjunction field effect transistor, characterized in that: The preparation method comprises: Providing a semiconductor substrate having a first conductivity type, and sequentially forming a first epitaxial layer of the first conductivity type, a second epitaxial layer of the first conductivity type, and a first hard mask layer on a surface of the semiconductor substrate from bottom to top; Patterning the first hard mask layer, and etching the first epitaxial layer and the second epitaxial layer to form a plurality of first trenches in the first epitaxial layer and the second epitaxial layer; Filling a conductive column having a second conductivity type in the first trench, and removing the first hard mask layer; forming a third epitaxial layer of the first conductivity type on the second epitaxial layer, and performing ion implantation of a preset depth on the surface of the third epitaxial layer to form a well region of the second conductivity type; forming a body region of a second conductivity type on the third epitaxial layer and forming a second hard mask layer on the body region; Patterning the second hard mask layer, etching the body region and the third epitaxial layer, forming a plurality of second trenches in the body region and the third epitaxial layer, and removing the second hard mask layer; forming a first interlayer dielectric layer on the inner wall of the second trench, and forming a first polysilicon filling the second trench on the first interlayer dielectric layer, wherein the first polysilicon, the first interlayer dielectric layer and the body region have flush surfaces; forming a source region having a first conductivity type and a second interlayer dielectric layer on the body region, and forming a first electrode contact hole penetrating the second interlayer dielectric layer and exposing the body region at the bottom, and a second electrode contact hole exposing the first polysilicon; The first electrode contact hole and the second electrode contact hole are filled with metal to form a front metal layer.

2. The method for preparing a trench type super junction field effect transistor according to claim 1, characterized in that: The doping concentration of the conductive column is 0.6E15 NA / cm 3 ~1.5E15 NA / cm 3 , the width of the conductive pillar is 2 to 5 μm, and the depth of the conductive pillar in the first groove is 15 to 25 μm.

3. The method for preparing a trench type super junction field effect transistor according to claim 2, characterized in that: The third epitaxial layer includes a plurality of sub-epitaxial layers formed in sequence, the number of the sub-epitaxial layers is 3 to 6, the well regions formed in each sub-epitaxial layer have the same width, and the width of the well regions is greater than 20% to 80% of the width of the conductive column.

4. The method for preparing a trench type super junction field effect transistor according to claim 1, characterized in that: The method for forming the conductive column includes: based on the CVD process, introducing epitaxial gas, doping gas and etching gas to deposit the conductive column in the first groove, and performing a chemical mechanical polishing process on the conductive column so that the conductive column, the second epitaxial layer and the first groove have a flush surface.

5. The method for preparing a trench type super junction field effect transistor according to claim 1, characterized in that: The first interlayer dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer, or a stacked combination thereof; the second interlayer dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer, or a stacked combination thereof.

6. The method for preparing a trench superjunction field effect transistor according to claim 1, characterized in that: After forming the front metal layer, the following steps are also included: forming a photoresist layer on the upper surface of the front metal layer and patterning the photoresist layer; etching the front metal layer based on the patterned photoresist layer to form a plurality of first isolation grooves, wherein the first isolation grooves isolate the source region from the front metal layer on the first polysilicon to form the source electrode on the source region, forming a gate electrode on the first polysilicon, and removing the remaining photoresist layer.

7. The method for preparing a trench type super junction field effect transistor according to claim 6, characterized in that: After forming the source electrode, the following steps are also included: forming a passivation layer on the upper surface of the front metal layer, and photolithographically etching the passivation layer to form a plurality of pad windows to expose the source electrode and the gate electrode; thinning the back side of the substrate layer to form a drain electrode; A back-metal process is performed on the lower surface of the drain electrode to form a back metal layer.

8. A trench superjunction field effect transistor, characterized in that: The trench type super junction field effect transistor comprises: A semiconductor substrate of a first conductivity type, and a first epitaxial layer of the first conductivity type, a second epitaxial layer of the first conductivity type, and a first hard mask layer located on a surface of the semiconductor substrate; a first trench located in the first epitaxial layer and the second epitaxial layer; A conductive column of the second conductive type is located in the first trench and completely fills the first trench, and the conductive column, the second epitaxial layer and the first trench have flush surfaces; A third epitaxial layer of the first conductivity type, located on the second epitaxial layer; A well region of the second conductivity type, located in the third epitaxial layer and connected to the conductive pillar; A body region of the second conductivity type, located on the third epitaxial layer; a second trench located in the third epitaxial layer and the body region; A first interlayer dielectric layer, located on an inner wall of the second trench; A first polysilicon layer is located on the first interlayer dielectric layer and fills the second trench; a source region, located on the body region and having a flush surface with the first interlayer dielectric layer and the first polysilicon; A second interlayer dielectric layer is located on the source region and has a first electrode contact hole exposing the source region and a second electrode contact hole exposing the first polysilicon; A front metal layer, wherein the front metal layer fills the first electrode contact hole and the second electrode contact hole and has a first isolation groove therein, wherein the first isolation groove isolates the source region from the front metal layer on the first polysilicon, so that the front metal layer on the source region forms a source electrode, and the front metal layer on the first polysilicon forms a gate electrode; The drain is located on the back side of the semiconductor substrate and a back metal layer is disposed on the lower surface of the drain.

9. The trench type super junction field effect transistor according to claim 8, characterized in that: The third epitaxial layer includes a plurality of sub-epitaxial layers, and the number of layers of the sub-epitaxial layers is 3 to 6.

10. The trench type super junction field effect transistor according to claim 8, characterized in that: The width of the conductive column is 2-5 μm, and the width of the well region is greater than 20%-80% of the width of the conductive column.

11. The trench type super junction field effect transistor according to claim 9, characterized in that: The trench type super junction field effect transistor further includes: a passivation layer located on the front metal layer, and the passivation layer has a plurality of pad windows, and the pad windows expose the source and the gate.

12. The trench type super junction field effect transistor according to any one of claims 8 to 11, characterized in that: The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.

Images