Super-junction MOS device and preparation method thereof
By forming a first body region and a second body region with different doping concentrations in the superjunction MOS device, opening the first body region conductive channel in advance and using the second body region to dissipate heat, the problem of thermal failure during the device opening process is solved, and the performance and tolerance of the device are improved.
Patent Information
- Application Number
- CN202510009908.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-05-06
AI Technical Summary
Existing superjunction MOS devices are prone to thermal failure during the turn-on process, resulting in high power consumption and rising temperatures.
By forming a first body region and a second body region communicating below each and having a different doping concentration in the semiconductor structure, the doping concentration of the first body region is similar to that of the column region. The second body region forms a high doping concentration by doping again to ensure that the opening voltage of the first body region conductive channel is lower than the second body region, so that the first body region conductive channel is opened in advance when the device is turned on, reducing heat generation, and helping the device to dissipate heat through the second body region.
It effectively reduces the current density and heat generation during the device opening process, avoids thermal failure. At the same time, when all cells are turned on, the reduction in the doping concentration of the first body region does not affect the on-resistance, and improves the device's tolerance and performance.
Smart Images
Figure CN119947155A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a super junction MOS device and a preparation method thereof. Background Art
[0002] As an advanced power MOSFET device technology, Super Junction MOSFET (SJ MOS) introduces a P-type column to deplete it with the N-column, optimizes the internal electric field, and enhances the device's ability to withstand breakdown voltage, so that the N-type column and the P-type column in the SJ MOS can achieve a higher doping concentration, and then achieve a lower on-resistance. However, under the same on-resistance, the chip area of the SJ MOS will be much smaller than that of the vertical double diffused MOS (VDMOS), resulting in its safe operating area (SOA) capability being weaker than that of ordinary VDMOS. During the SJ MOS turn-on process, as the gate-source voltage rises, the current is small at this time, but because the drain-source voltage does not drop at this time, the SJ MOS will generate huge power consumption, which is much greater than the dissipated power, and the temperature of the SJ MOS will rise, and then it is easy to cause thermal failure.
[0003] Therefore, there is an urgent need to find a method for preparing a super junction MOS device that can avoid thermal failure during the device startup process. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a super junction MOS device and a preparation method thereof, so as to solve the problem in the prior art that the super junction MOS device is prone to thermal failure during the turn-on process.
[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a super junction MOS device, comprising the following steps:
[0006] A semiconductor structure is provided, the semiconductor structure comprising a gate structure and a first conductive type substrate and a first conductive type epitaxial layer stacked in sequence, a plurality of second conductive type column regions spaced apart in an X direction and having a bottom surface spaced apart from a bottom surface of the epitaxial layer by a preset distance are formed in the epitaxial layer, the column region is spaced apart from an upper surface of the epitaxial layer by a preset distance, and the gate structure is located above a region between two adjacent column regions;
[0007] A plurality of second conductivity type first body regions and second conductivity type second body regions are formed on the upper surface layer of the epitaxial layer above each of the column regions, which are alternately arranged in the X direction and have different doping concentrations, and the first body regions and the second body regions are respectively connected to the column regions below them;
[0008] forming a first conductive type source region located on the upper surface layer of the first body region and the second body region at two opposite sides of the gate structure along the X direction;
[0009] A source electrode electrically connected to the source region, a gate electrode electrically connected to the gate structure, and a drain electrode electrically connected to the substrate are formed.
[0010] Optionally, the doping concentration of the epitaxial layer is lower than the doping concentration of the substrate.
[0011] Optionally, the gate structure is located on the upper surface of the epitaxial layer in the area between two adjacent column regions, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, the two ends of the gate conductive layer in the X direction respectively extend to directly above two adjacent first body regions and the second body region, and the gate conductive layer is electrically connected to the gate; or the gate structure is embedded in the upper surface layer of the epitaxial layer in the area between two adjacent column regions, the gate structure includes a trench, a gate dielectric layer covering the inner wall of the trench, and a gate conductive layer at least filling the upper part of the trench, the first body region and the second body region are respectively located on the upper surface of the epitaxial layer on both sides of the gate structure along the X direction and the side walls are adjacent to the side walls of the gate structure, the gate dielectric layer at least wraps the side walls of the gate conductive layer, the source regions in the first body region and the second body region are respectively adjacent to the two side walls of the trench oppositely arranged in the X direction, and the bottom surface of the gate conductive layer is lower than the bottom surfaces of the first body region and the second body region.
[0012] Optionally, the doping concentration of the first body region is less than the doping concentration of the second body region, and the doping concentration of the first body region is not less than the doping concentration of the column region.
[0013] Optionally, forming the first body region and the second body region comprises the following steps:
[0014] A plurality of first body regions and second conductive type doped regions are formed on the upper surface layer of the epitaxial layer above each of the pillar regions, and are alternately arranged in sequence along the X direction, wherein the first body regions and the doped regions are respectively connected to the pillar regions below them;
[0015] The doped region is doped again to obtain the second body region.
[0016] Optionally, a doping dose for forming the first body region and the doping region is not less than a doping dose for re-doping the doping region.
[0017] Optionally, a maximum ion implantation energy for re-doping the doping region is less than a maximum ion implantation energy for forming the first body region and the doping region.
[0018] Optionally, after forming the first body region and the second body region and before forming the source, the method further includes forming a second conductive type contact region located on the upper surface of the first body region and the second body region, wherein the contact region is electrically connected to the source.
[0019] Optionally, before forming the source electrode and the gate electrode and after forming the source region, the step of forming an interlayer dielectric layer covering the exposed upper surface of the semiconductor structure is also included, the source electrode penetrates the interlayer dielectric layer and is electrically connected to the source region, and the gate electrode penetrates the interlayer dielectric layer and is electrically connected to the gate structure.
[0020] The present invention also provides a super junction MOS device, which is manufactured by using the above-mentioned method for manufacturing the super junction MOS device.
[0021] As described above, the super junction MOS device and preparation method of the present invention are as follows: after forming the first body region and the doping region which are connected to each other below and alternately arranged in sequence along the X direction, the doping concentration of the first body region is close to the doping concentration of the column region, and then the doping region is doped again to form the second body region, so that the turn-on voltage of the conductive channel in the first body region is lower than the turn-on voltage of the conductive channel in the second body region. In the process of forward conduction of the device, the cells with the first body region as the conductive channel are turned on in advance, which can reduce the current density during the device turn-on process and reduce the heat generated during the device turn-on process. At the same time, the cells with the second body region as the conductive channel in the device help the device to dissipate heat, so that the device quickly passes the thermal instability stage, avoiding thermal failure during the device turn-on process. Moreover, when all cells in the device are turned on, the reduction of the doping concentration of the first body region has no effect on the on-resistance of the device after it is fully turned on, thereby reducing the influence of the parasitic transistor in the device on the device, improving the tolerance of the device, and improving the performance of the device, and having a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a process flow chart of a method for preparing a super junction MOS device of the present invention.
[0023] Figure 2 The cross-sectional structure schematic diagram shows the semiconductor structure of the method for preparing the super junction MOS device of the present invention.
[0024] Figure 3 It is a schematic diagram showing the cross-sectional structure of the method for preparing a super junction MOS device of the present invention after forming the first body region and the doping region.
[0025] Figure 4 It is a schematic diagram showing the cross-sectional structure after forming the first body region and the second body region in the method for preparing the super junction MOS device of the present invention.
[0026] Figure 5 The schematic diagram of the cross-sectional structure of the method for preparing the super junction MOS device of the present invention after forming the source region is shown.
[0027] Figure 6 It is a schematic diagram showing the cross-sectional structure after forming an interlayer dielectric layer in the method for preparing a super junction MOS device of the present invention.
[0028] Figure 7 It is a schematic diagram showing the cross-sectional structure after forming the source and drain of the method for preparing the super junction MOS device of the present invention.
[0029] Description of Figure Numbers
[0030] 1 Semiconductor structure
[0031] 11 Substrate
[0032] 12 Epitaxial layer
[0033] 13 Gate structure
[0034] 131 gate dielectric layer
[0035] 132 gate conductive layer
[0036] 14 Column Area
[0037] 15. First body region
[0038] 151 Doping region
[0039] 16. Second body area
[0040] 17 Source Area
[0041] 2 Interlayer dielectric layer
[0042] 3 Source
[0043] 4 Drain DETAILED DESCRIPTION
[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0045] See also Figures 1 to 7It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0046] Embodiment 1
[0047] This embodiment provides a method for preparing a super junction MOS device, such as Figure 1 FIG. 1 is a process flow chart of the method for preparing the super junction MOS device, comprising the following steps:
[0048] S1: A semiconductor structure is provided, the semiconductor structure comprising a gate structure and a first conductive type substrate and a first conductive type epitaxial layer stacked in sequence, a plurality of second conductive type column regions spaced apart in an X direction and having a bottom surface spaced apart from a bottom surface of the epitaxial layer by a preset distance are formed in the epitaxial layer, the column region is spaced apart from an upper surface of the epitaxial layer by a preset distance, and the gate structure is located above a region between two adjacent column regions;
[0049] S2: forming a plurality of first body regions of the second conductivity type and second body regions of the second conductivity type on the upper surface layer of the epitaxial layer above each of the pillar regions, which are alternately arranged in the X direction and have different doping concentrations, wherein the first body regions and the second body regions are respectively connected to the pillar regions below them;
[0050] S3: forming a first conductive type source region located on the upper surface layer of the first body region and the second body region at two opposite sides of the gate structure along the X direction;
[0051] S4: forming a source electrode electrically connected to the source region, a gate electrode electrically connected to the gate structure, and a drain electrode electrically connected to the substrate.
[0052] See also Figures 2 to 4 , perform step S1 and step S2: provide a semiconductor structure 1, the semiconductor structure 1 includes a gate structure 13 and a first conductive type substrate 11 and a first conductive type epitaxial layer 12 stacked in sequence, a plurality of second conductive type column regions 14 arranged at intervals along the X direction and having a preset distance between the bottom surface and the bottom surface of the epitaxial layer 12 are formed in the epitaxial layer 12, the column region 14 is spaced at a preset distance from the upper surface of the epitaxial layer 12, and the gate structure 13 is located on the upper surface of the epitaxial layer 12 between two adjacent column regions 14; a plurality of second conductive type first body regions 15 and second conductive type second body regions 16 arranged alternately and spaced in sequence along the X direction and having different doping concentrations are formed on the upper surface of the epitaxial layer 12 above each column region 14, and the first body region 15 and the second body region 16 are respectively connected to the column region 14 below them. The X direction here refers to any direction parallel to the upper surface of the epitaxial layer 12.
[0053] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.
[0054] Specifically, Figure 2 , which is a schematic cross-sectional structural diagram of a semiconductor structure 1. Usually, the semiconductor structure 1 is a structure of a body region of a super junction MOS device to be manufactured, that is, a structure after forming a column region 14 and a gate structure 13 of the super junction MOS device.
[0055] As an example, the doping concentration of the epitaxial layer 12 is lower than the doping concentration of the substrate 11 .
[0056] Specifically, since the substrate 11 is usually required to form an ohmic contact with the drain 4 formed later, the substrate 11 is usually a heavily doped region, while the epitaxial layer 12 is a region for ensuring the voltage resistance of the device, which is usually a lightly doped region.
[0057] It should be noted that, usually, the epitaxial layer 12 is formed by epitaxy on the upper surface of the substrate 11, and is formed by multiple epitaxies. After the epitaxial layer 12 is formed to a preset thickness, ion implantation is performed on the corresponding area of the column area 14, and then the epitaxy and ion implantation processes are repeated. After the column area 14 of a preset height is formed, epitaxy is continued until an epitaxial layer 12 of a preset thickness is formed.
[0058] Specifically, while ensuring device performance, the number of epitaxial growths to form the epitaxial layer 12 can be selected based on actual conditions; the number of ion implantations to form the column region 14 and the distance between the column region 14 and the upper surface of the substrate 11, the distance between the column region 14 and the upper surface of the epitaxial layer 12, and the distance between two adjacent column regions 14 can be selected based on actual conditions.
[0059] As an example, the gate structure 13 is located on the upper surface of the epitaxial layer 12 in the area between two adjacent column regions 14. The gate structure 13 includes a gate dielectric layer 131 and a gate conductive layer 132 stacked in sequence. The gate conductive layer 132 extends at both ends in the X direction to directly above the two adjacent first body regions 15 and the second body region 16, respectively. The gate conductive layer 132 is electrically connected to the gate, that is, the manufactured device is a planar gate super junction MOS device.
[0060] Specifically, the gate structure 13 is located on the upper surface of the epitaxial layer 12 in the area between two adjacent column regions 14, and the formation of the gate structure 13 includes the following steps: forming a gate dielectric material layer and a gate conductive material layer stacked in sequence to expose the upper surface of the covering epitaxial layer 12; forming a patterned first shielding layer on the upper surface of the gate conductive material layer, and etching the gate conductive material layer based on the patterned first shielding layer to obtain the gate structure 13.
[0061] Specifically, the method of forming the gate dielectric material layer includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods; the method of forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0062] Specifically, the method for forming the patterned first shielding layer is a mask patterning method or a photoresist patterning method commonly used in the photolithography process, which will not be described in detail here.
[0063] Specifically, the method of etching the gate conductive material layer based on the patterned first shielding layer includes dry etching, wet etching or other suitable methods.
[0064] It should be noted that, in the process of etching the gate conductive material layer to form the gate structure 13, the gate dielectric material layer below the area of the etched gate conductive material layer can be removed, or the gate dielectric material layer below the area of the etched gate conductive material layer can be retained, and the remaining gate dielectric material layer after etching serves as the gate dielectric layer 131, and the remaining gate conductive material layer serves as the gate conductive layer 132.
[0065] Specifically, after the gate structure 13 is formed, a step of removing the first shielding layer is also included. The method for removing the first shielding layer is usually a commonly used mask layer or photoresist layer removal method, which will not be described in detail here.
[0066] Specifically, while ensuring device performance, the size and shape of the gate structure 13 can be selected according to actual conditions; the distance between two adjacent gate structures 13 can be selected according to actual conditions.
[0067] Specifically, the material of the gate dielectric layer 131 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials; the material of the gate conductive layer 132 includes polysilicon or other suitable conductive materials.
[0068] As an example, the gate structure 13 is embedded in the upper surface layer of the epitaxial layer 12 in the area between two adjacent column regions 14. The gate structure 13 includes a trench, a gate dielectric layer covering the inner wall of the trench, and a gate conductive layer at least filling the upper portion of the trench. The first body region 15 and the second body region 16 are respectively located on the upper surface layer of the epitaxial layer 12 on both sides of the gate structure 13 along the X direction, and the side walls are adjacent to the side walls of the gate structure 13. The gate dielectric layer at least wraps the side walls of the gate conductive layer. The source regions in the first body region 15 and the second body region 16 are respectively adjacent to the two side walls of the trench that are oppositely arranged in the X direction. The bottom surface of the gate conductive layer is lower than the bottom surfaces of the first body region 15 and the second body region 16, that is, the device is a trench gate super junction MOS device.
[0069] It should be noted that the trench gate structure 13 is usually formed by a commonly used trench gate forming method, which will not be described in detail here.
[0070] Specifically, when the gate structure 13 is embedded in the upper surface layer of the epitaxial layer 12 between two adjacent column regions 14, the gate dielectric layer covers the inner wall and bottom surface of the trench and wraps the side wall and bottom surface of the gate conductive layer, then the gate structure 13 is an ordinary trench gate, and the device is an ordinary trench gate super junction MOS device in the trench gate super junction MOS device.
[0071] Specifically, when the gate structure 13 is embedded in the upper surface layer of the epitaxial layer 12 between two adjacent column regions 14, the gate dielectric layer only covers the inner wall of the upper part of the groove, and the gate dielectric layer only wraps the side wall of the gate conductive layer. Then the gate structure 13 also includes a thick insulating layer, a shielding gate layer and an isolation dielectric layer. The thick insulating layer covers the inner wall and bottom surface of the bottom of the groove, the shielding gate layer fills the bottom of the groove, the thick insulating layer wraps the side wall and bottom surface of the shielding gate layer, the isolation dielectric layer covers the gate conductive layer and the exposed upper surface of the thick insulating layer, the bottom surface of the gate conductive layer is flush with the upper surface of the isolation dielectric layer, the bottom surface of the gate dielectric layer is flush with the upper surface of the isolation dielectric layer, the shielding gate layer is electrically connected to the source formed subsequently, and the device is a shielded gate trench super junction MOS device in a trench gate super junction MOS device.
[0072] As an example, the doping concentration of the first body region 15 is less than that of the second body region 16 , and the doping concentration of the first body region 15 is not less than that of the pillar region 14 . In this embodiment, the doping concentration of the first body region 15 is slightly greater than that of the pillar region 14 .
[0073] Specifically, by making the doping concentration of the first body region 15 lower than the doping concentration of the second body region 16 , conductive channels with different turn-on voltages, ie, cells of super junction MOS with different thresholds, can be formed.
[0074] As an example, Figure 3 and Figure 4 As shown, they are schematic diagrams of the cross-sectional structure after the first body region 15 and the doped region 151 are formed, and schematic diagrams of the cross-sectional structure after the first body region 15 and the second body region 16 are formed, respectively. The formation of the first body region 15 and the second body region 16 includes the following steps: forming a plurality of first body regions 15 and second conductive type doped regions 151 alternately arranged in sequence along the X direction on the upper surface layer of the epitaxial layer 12 above each column region 14, the first body region 15 and the doped region 151 are respectively connected to the column region 14 thereunder; and re-doping the doped region 151 to obtain the second body region 16.
[0075] Specifically, before forming the first body region 15 and the doping region 151, a step of forming a patterned second shielding layer on the upper surface of the semiconductor structure 1 is also included. The first body region 15 and the doping region 151 are formed by ion implantation based on the patterned second shielding layer. The method of usually forming the patterned second shielding layer is the mask patterning or photoresist patterning method commonly used in the photolithography process, which will not be repeated here.
[0076] Specifically, after forming the first body region 15 and the doping region 151, before re-doping the doping region 151, it is necessary to remove the second shielding layer and form a patterned third shielding layer. The method for removing the second shielding layer is a commonly used mask layer or photoresist layer removal method, which will not be repeated here; the method for forming the patterned third shielding layer is a mask patterning or photoresist patterning method commonly used in common photolithography processes, which will not be repeated here.
[0077] It should be noted that the doped region 151 is usually re-doped based on the patterned third shielding layer, and after the second body region 16 is formed, the third shielding layer needs to be removed before the subsequent process. The method for removing the third shielding layer is a commonly used mask layer or photoresist layer removal method, which will not be repeated here.
[0078] As an example, the doping dose for forming the first body region 15 and the doping region 151 is not less than the dose for re-doping the doping region 151 to avoid the doping concentration of the formed second body region 16 being too high, thereby affecting the turn-on voltage of the conductive channel in the second body region 16 .
[0079] Specifically, the doping dosage range of forming the first body region 15 and the doping region 151 is 1×10 13 / cm 2 ~5×10 13 / cm 2 , for example, it can be 1×10 13 / cm 2 , 2×10 13 / cm 2 , 3×10 13 / cm 2 , 4×10 13 / cm 2 , 5×10 13 / cm 2 .
[0080] Specifically, the doping dosage range of the doping region 151 is 6×10 12 / cm 2 ~3×10 13 / cm 2 , for example, it can be 6×10 12 / cm 2 ,9×10 13 / cm 2 , 1×10 13 / cm 2 , 2×10 13 / cm 2 , 3×10 13 / cm 2 .
[0081] Specifically, the ion implantation dose of the first body region 15 and the doping region 151 is 1×10 13 / cm 2 ~5×10 13 / cm 2 , so as to obtain a region with lower doping concentration and then a conductive channel with lower turn-on voltage.
[0082] As an example, the maximum ion implantation energy for re-doping the doping region 151 is less than the maximum ion implantation energy for forming the first body region 15 and the doping region 151 .
[0083] It should be noted that, during the ion implantation process, the higher the energy of the implanted ions, the deeper the ion implantation depth is usually. Since the first body region 15 has a certain thickness, multiple ion implantations with different energies are usually required to ensure that the doping concentrations of the first body region 15 and the doping region 151 are relatively uniform. Generally, the ion implantation energy for forming the first body region 15 and the doping region 151 is in the range of 60KeV to 120KeV, and the ion implantation energy of multiple ion implantations is within this range.
[0084] Specifically, in the process of re-doping the doping region 151, multiple ion implantation processes with different energies are usually required. In order to avoid uneven concentration distribution of the formed second body region 16 and excessive size difference with the first body region 15, the re-doping ion implantation energy needs to be controlled between 80KeV and 100KeV.
[0085] Specifically, while ensuring device performance, the size, shape and thickness of the first body region 15 can be selected according to actual conditions; the size, shape and thickness of the second body region 16 can be selected according to actual conditions. Preferably, the first body region 15 and the second body region 16 have the same thickness.
[0086] Specifically, the gate structure 13 is located on the upper surface of the epitaxial layer 12 between two adjacent column regions 14, and the two ends of the gate conductive layer 132 in the X direction extend to directly above the adjacent first body region 15 and the second body region 16 respectively. While ensuring the device performance, the distance between the end of the gate conductive layer 132 directly above the first body region 15 and the side wall of the first body region 15 adjacent thereto can be selected according to actual conditions; the distance between the end of the gate conductive layer 132 directly above the second body region 16 and the side wall of the second body region 16 adjacent thereto can be selected according to actual conditions.
[0087] Specifically, the gate structure 13 is embedded in the upper surface of the epitaxial layer 12 between two adjacent column regions 14. While ensuring device performance, the distance between the bottom surface of the gate conductive layer and the bottom surfaces of the first body region 15 and the second body region 16 can be selected according to actual conditions.
[0088] It should be noted that, generally, the doping concentration of the second body region 16 is similar to the doping concentration of the body region in a normal device.
[0089] See also Figures 5 to 7 , perform step S3 and step S4: form a first conductive type source region 17 on the upper surface layer of the first body region 15 and the second body region 16; form a source electrode 3 electrically connected to the source region 17, a gate electrode electrically connected to the gate structure 13, and a drain electrode 4 electrically connected to the substrate 11.
[0090] Specifically, Figure 5 , which is a schematic diagram of the cross-sectional structure after the source region 17 is formed. The formation of the source region 17 includes the following steps: forming a patterned fourth shielding layer on the upper surface of the semiconductor structure 1 after the first body region 15 and the second body region 16 are formed; forming the source region 17 located on the upper surface of the first body region 15 and the second body region 16 respectively based on the patterned fourth shielding layer, and removing the fourth shielding layer.
[0091] Specifically, the method for forming the fourth shielding layer is a mask patterning method or a photoresist patterning method commonly used in a common photolithography process, which will not be described in detail here.
[0092] Specifically, the method of forming the source region 17 includes ion implantation or other suitable methods.
[0093] Specifically, in the first body region 15, the source region 17 extends close to the side wall of the first body region 15 in the X direction to directly below the gate structure 13, and the side wall of the source region 17 close to the first body region 15 in the X direction is spaced apart from the side wall of the first body region 15 by a preset distance; in the second body region 16, the source region 17 extends close to the side wall of the second body region 16 in the X direction to directly below the gate structure 13, and the side wall of the source region 17 close to the second body region 16 in the X direction is spaced apart from the side wall of the second body region 16 by a preset distance.
[0094] Specifically, the contact type between the source region 17 and the subsequently formed source electrode 3 is an ohmic contact. Under the condition of ensuring the device performance, the size, shape, thickness and doping concentration of the source region 17 can be selected according to the actual situation; the distance between the side wall of the source region 17 close to the side wall of the first body region 15 in the X direction and the side wall of the first body region 15 can be selected according to the actual situation; the distance between the side wall of the source region 17 close to the side wall of the second body region 16 in the X direction and the side wall of the second body region 16 can be selected according to the actual situation. The thickness here refers to the distance between the upper surface and the lower surface of the source region 17.
[0095] Specifically, the method for removing the fourth shielding layer is a commonly used method for removing a mask layer or a photoresist layer, which will not be described in detail here.
[0096] It should be noted that, usually, two source regions 17 are formed on the upper surface layers of the first body region 15 and the second body region 16. Under the condition of ensuring device performance, the distance between the two source regions 17 in the first body region 15 and the distance between the two source regions 17 in the second body region 16 can be selected according to actual conditions; only one source region 17 can also be formed in the first body region 15, and only one source region 17 can also be formed in the second body region 16.
[0097] As an example, after forming the first body region 15 and the second body region 16 and before forming the source 3 , a step of forming a second conductive type contact region located on the upper surface of the first body region 15 and the second body region 16 is also included, and the contact region is electrically connected to the source 3 .
[0098] Specifically, the contact region is usually used to form an ohmic contact between the first body region 15 and the second body region 16 and the subsequently formed source 3. Under the condition of ensuring device performance, the doping concentration, thickness, size and shape of the contact region can be selected according to actual conditions.
[0099] Specifically, the method of forming the contact region includes ion implantation or other suitable methods.
[0100] As an example, before forming the source 3 and the gate and after forming the source region 17, the step of forming an interlayer dielectric layer 2 covering the exposed upper surface of the semiconductor structure 1 is also included, the source 3 penetrates the interlayer dielectric layer 2 and is electrically connected to the source region 17, and the gate penetrates the interlayer dielectric layer 2 and is electrically connected to the gate structure 13.
[0101] Specifically, Figure 6 , which is a schematic diagram of a cross-sectional structure after the interlayer dielectric layer 2 is formed. The method of forming the interlayer dielectric layer 2 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0102] Specifically, the interlayer dielectric layer 2 is usually used for insulation between the source 3 and the gate of the device and protects the epitaxial layer 12 and the gate structure 13 of the device. The thickness of the interlayer dielectric layer 2 can be selected according to actual conditions while ensuring the performance of the device.
[0103] Specifically, after forming the interlayer dielectric layer 2 and before forming the source 3 and the gate, the step of forming a source contact hole and a gate contact hole penetrating the interlayer dielectric layer 2 is also included, and the bottom surface of the source contact hole exposes the source region 17. When a contact region is formed in the first body region 15 and the second body region 16, the bottom surface of the source contact hole also exposes the contact region, and the bottom surface of the gate contact hole exposes the gate conductive layer 132.
[0104] It should be noted that a contact region is formed in the first body region 15 and the second body region 16, which can be adjacent to the source region 17. When the source contact hole penetrates the source region 17, it can be formed in the first body region 15 and the second body region 16 exposed at the bottom of the source contact hole after the source contact hole is formed.
[0105] Specifically, the source electrode 3 fills the source contact hole and is electrically connected to the source region 17 , the gate electrode fills the gate contact hole, and the gate conductive layer 132 is electrically connected to the gate electrode.
[0106] It should be noted that the opening size and opening shape of the source contact hole can be selected according to actual conditions; the opening size and opening shape of the gate contact hole can be selected according to actual conditions.
[0107] Specifically, Figure 7 As shown, it is a schematic diagram of the cross-sectional structure after the drain 4 is formed. The contact type between the drain 4 and the bottom surface of the substrate 11 is an ohmic contact. The method for forming the source 3 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the drain 4 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods. Preferably, after the source contact hole and the gate contact hole are formed, the source 3 and the gate are formed simultaneously.
[0108] Specifically, after forming the first body region 15 and the doping region 151 respectively connected to the column region 14 below them, the doping region 151 is continuously doped to form the second body region 16 having a doping concentration higher than that of the first body region 15, and the doping concentration of the first body region 15 is similar to the doping concentration of the column region 14, so that the turn-on voltage of the conductive channel of the first body region 15 is lower than the turn-on voltage of the conductive channel in the second body region 16. Subsequently, during the device startup process, since the turn-on voltage of the conductive channel in the first body region 15 is relatively low, the conductive channels of some cells are turned on in advance, thereby reducing the current density when the device is turned on and reducing the heat generated during the device startup process. At the same time, the cells whose conductive channels are not turned on help the device to dissipate heat, so that the device quickly exits the thermal instability zone.
[0109] Specifically, after the conductive channel in the first body region 15 is turned on, when the gate-source voltage of the device reaches the turn-on voltage of the conductive channel in the second body region 16, all cells in the device are turned on, and the doping concentration of the device epitaxial layer 12 and the column region 14 is not reduced. Therefore, the overall on-resistance of the device will not be affected by the reduction in the doping concentration of the first body region 15. At the same time, the influence of the parasitic transistor in the device on the device is reduced, and the tolerance of the device is improved.
[0110] The preparation method of the super junction MOS structure of the present embodiment first forms a first body region 15 and a doping region 151 which are respectively connected to the column region 14 below each other and have a doping concentration similar to that of the column region 14, and then continues to dope the doping region 151 to obtain a second body region 16 with a doping concentration higher than that of the first body region 15, so that the turn-on voltage of the conductive channel in the first body region 15 is lower than the turn-on voltage of the conductive channel in the second body region 16, and then in the process of forward conduction of the device, some cells are turned on in advance to reduce the heat generated during the device turn-on process, and at the same time, another part of the unturned cells of the device help the device to dissipate heat, so that the device quickly overheats and is unstable, avoiding thermal failure during the device turn-on process, and when the gate-source voltage of the device reaches the turn-on voltage of the conductive channel in the second body region 16, all cells in the device are turned on, and the reduction of the doping concentration of the first body region 15 has no effect on the on-resistance of the device after it is fully turned on, thereby reducing the influence of the parasitic transistor in the device on the device and improving the tolerance of the device.
[0111] Embodiment 2
[0112] This embodiment also provides a super junction MOS device, such as Figure 7 , which is a schematic diagram of the cross-sectional structure of the super junction MOS device, and the super junction MOS device is manufactured using the preparation method of the super junction MOS device described in Example 1.
[0113] Specifically, the super junction MOS device includes a semiconductor structure 1, a second conductive type first body region 15, a second conductive type second body region 16, a first conductive type source region 17, a source electrode 3, a gate electrode and a drain electrode 4, wherein the semiconductor structure 1 includes a first conductive type substrate 11, a first conductive type epitaxial layer 12 and a gate structure 13 stacked in sequence, a plurality of second conductive type column regions 14 are formed in the epitaxial layer 12 and are arranged at intervals along the X direction and the bottom surface of the epitaxial layer 12 is spaced apart by a preset distance, and the column region 14 is spaced apart from the upper surface of the epitaxial layer 12 by a preset distance. The gate structure 13 is located above the area between two adjacent column regions 14; the first body region 15 and the second body region 16 are alternately arranged in the X direction on the upper surface of the epitaxial layer 12 directly above each column region 14, and the first body region 15 and the second body region 16 have different doping concentrations and are respectively connected to the column region 14 directly below them; the source region 17 is located on the upper surface of the first body region 15 and the second body region 16 on the opposite sides of the gate structure 13 along the X direction; the source 3 is electrically connected to the source region 17, the gate is electrically connected to the gate structure 13, and the drain 4 is electrically connected to the substrate 11.
[0114] Specifically, while ensuring device performance, the doping concentration, size, shape and thickness of the substrate 11 can be selected according to actual conditions; the thickness and doping concentration of the epitaxial layer 12 can be selected according to actual conditions.
[0115] Specifically, a vertical PN junction is usually formed between the column region 14 and the epitaxial layer 12, and a depletion region is formed when the device is reverse biased to provide the device with voltage resistance. Under the condition of ensuring the device performance, the size, shape and height of the column region 14 can be selected according to actual conditions. The height here refers to the distance between the upper surface and the lower surface of the column region 14.
[0116] Specifically, the doping concentration of the first body region 15 is less than the doping concentration of the second body region 16 and not less than the doping concentration of the pillar region 14 , and the doping concentration of the first body region 15 is similar to the doping concentration of the pillar region 14 .
[0117] Specifically, the source region 17 is spaced apart from the upper surface layer of the first body region 15 and the upper surface layer of the second region, and the side of the source region 17 close to the side wall of the first body region 15 is spaced apart from the side wall of the first body region 15 , and the side of the source region 17 close to the side wall of the second body region 16 is spaced apart from the side wall of the second body region 16 .
[0118] Specifically, the upper surface layers of the first body region 15 and the second body region 16 are further provided with second conductive type contact regions, and the contact regions are electrically connected to the source 3 to achieve electrical connection between the source 3 and the first body region 15 and the second body region 16 .
[0119] Specifically, the gate structure 13 is located on the upper surface of the epitaxial layer 12 in the region between the two adjacent column regions 14, and the gate structure 13 includes a gate dielectric layer 131 and a gate conductive layer 132 stacked in sequence, and the two ends of the gate structure 13 in the X direction extend to the source region 17 in the first body region 15 and the source region 17 in the second body region 16, respectively, that is, the two ends of the gate conductive layer 132 in the X direction are respectively located in the first body region 15 and the source region 17 in the second body region 16. The gate structure 13 is embedded in the epitaxial layer in the region between the two adjacent column regions 14. The gate structure 13 includes a trench, a gate dielectric layer covering the inner wall of the trench and a gate conductive layer filling at least the upper part of the trench, the first body region 15 and the second body region 16 are respectively located on the upper surface of the epitaxial layer 12 on both sides of the gate structure 13 along the X direction and the side walls are adjacent to the side walls of the gate structure 13, the gate dielectric layer at least wraps the side walls of the gate conductive layer, the source regions 17 in the first body region 15 and the second body region 16 are respectively adjacent to the two side walls of the trench oppositely arranged in the X direction, and the bottom surface of the gate conductive layer is lower than the bottom surfaces of the first body region 15 and the second body region 16.
[0120] Specifically, when the gate structure 13 is embedded in the upper surface of the epitaxial layer 12 between two adjacent column regions 14 , the source region 17 is adjacent to the two side walls of the trench oppositely disposed in the X direction and the lower surface is spaced a preset distance from the lower surfaces of the first body region 15 and the second body region 16 .
[0121] Specifically, the device is also provided with an interlayer dielectric layer 2 covering the exposed upper surfaces of the first body region 15, the second body region 16 and the source region 17 and the exposed surface of the semiconductor structure 1, and a source contact hole and a gate contact hole penetrating the interlayer dielectric layer 2 are provided in the interlayer dielectric layer 2, and the bottom surface of the source contact hole exposes the source region 17. When a contact region is provided in the first body region 15 and the second body region 16, the bottom surface of the source contact hole also exposes the contact region, and the bottom surface of the gate contact hole exposes the gate conductive layer 132.
[0122] Specifically, the source electrode 3 fills the source contact hole and forms an ohmic contact with the source region 17 , the gate electrode fills the gate contact hole and is electrically connected to the gate conductive layer 132 , and the drain electrode 4 covers the bottom surface of the substrate 11 and forms an ohmic contact with the substrate 11 .
[0123] Specifically, the material of the source electrode 3 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the gate electrode includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the drain electrode 4 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.
[0124] Specifically, by adopting the super junction MOS preparation method described in Example 1 to manufacture a super junction MOS device, the current density when the device is turned on is reduced, the heat generated during the device turning on process is reduced, thermal failure during the device turning on process is avoided, and the performance of the device is improved.
[0125] The super junction MOS device of this embodiment is manufactured by the super junction MOS device manufacturing method described in the first embodiment, which reduces the current density when the device is turned on, avoids thermal failure during the device turning on process, and improves the performance of the device.
[0126] In summary, the super junction MOS device and its preparation method of the present invention improve the manufacturing process of the device, after forming the first body region and the doping region which are connected to each other below and alternately arranged in the X direction, the doping region is doped again to form the second body region, so that the doping concentration of the second body region is higher than the doping concentration of the first body region, and the doping concentration of the first body region is similar to the doping concentration of the column region, and then the turn-on voltage of the conductive channel in the first body region is lower than the turn-on voltage of the conductive channel in the second body region, and in the process of forward conduction of the device, the cell with the first body region as the conductive channel is turned on in advance, which reduces the current density in the process of turning on the device, and reduces the heat generated in the process of turning on the device, and at the same time, the cell with the second body region as the conductive channel in the device helps the device to dissipate heat, so that the device quickly passes the thermal instability stage, and avoids thermal failure in the process of turning on the device, and at the same time, when all cells in the device are turned on, the reduction of the doping concentration of the first body region has no effect on the on-resistance of the device after it is fully turned on, which reduces the influence of the parasitic transistor in the device on the device and improves the tolerance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0127] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a super junction MOS device, characterized in that: The following steps are involved: A semiconductor structure is provided, the semiconductor structure comprising a gate structure and a first conductive type substrate and a first conductive type epitaxial layer stacked in sequence, a plurality of second conductive type column regions spaced apart in an X direction and having a bottom surface spaced apart from a bottom surface of the epitaxial layer by a preset distance are formed in the epitaxial layer, the column region is spaced apart from an upper surface of the epitaxial layer by a preset distance, and the gate structure is located above a region between two adjacent column regions; A plurality of second conductivity type first body regions and second conductivity type second body regions are formed on the upper surface layer of the epitaxial layer above each of the column regions, which are alternately arranged in the X direction and have different doping concentrations, and the first body regions and the second body regions are respectively connected to the column regions below them; forming a first conductive type source region located on the upper surface layer of the first body region and the second body region at two opposite sides of the gate structure along the X direction; A source electrode electrically connected to the source region, a gate electrode electrically connected to the gate structure, and a drain electrode electrically connected to the substrate are formed.
2. The method for preparing a super junction MOS device according to claim 1, characterized in that: The doping concentration of the epitaxial layer is lower than the doping concentration of the substrate.
3. The method for preparing a super junction MOS device according to claim 1, characterized in that: The gate structure is located on the upper surface of the epitaxial layer in the area between two adjacent column regions, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, the two ends of the gate conductive layer in the X direction respectively extend to directly above the two adjacent first body regions and the second body region, and the gate conductive layer is electrically connected to the gate; or the gate structure is embedded in the upper surface layer of the epitaxial layer in the area between two adjacent column regions, the gate structure includes a trench, a gate dielectric layer covering the inner wall of the trench, and a gate conductive layer at least filling the upper part of the trench, the first body region and the second body region are respectively located on the upper surface of the epitaxial layer on both sides of the gate structure along the X direction and the side walls are adjacent to the side walls of the gate structure, the gate dielectric layer at least wraps the side walls of the gate conductive layer, the source regions in the first body region and the second body region are respectively adjacent to the two side walls of the trench arranged opposite to each other in the X direction, and the bottom surface of the gate conductive layer is lower than the bottom surfaces of the first body region and the second body region.
4. The method for preparing a super junction MOS device according to claim 1, characterized in that: The doping concentration of the first body region is less than the doping concentration of the second body region, and the doping concentration of the first body region is not less than the doping concentration of the column region.
5. The method for preparing a super junction MOS device according to claim 1, characterized in that: Forming the first body region and the second body region comprises the following steps: A plurality of first body regions and second conductive type doped regions are formed on the upper surface layer of the epitaxial layer above each of the pillar regions, and are alternately arranged in sequence along the X direction, wherein the first body regions and the doped regions are respectively connected to the pillar regions below them; The doped region is doped again to obtain the second body region.
6. The method for preparing a super junction MOS device according to claim 5, characterized in that: The doping dose for forming the first body region and the doping region is not less than the dose for re-doping the doping region.
7. The method for preparing a super junction MOS device according to claim 5, characterized in that: A maximum ion implantation energy for re-doping the doping region is less than a maximum ion implantation energy for forming the first body region and the doping region.
8. The method for preparing a super junction MOS device according to claim 1, characterized in that: After forming the first body region and the second body region and before forming the source, the method further includes forming a second conductive type contact region located on the upper surface of the first body region and the second body region, wherein the contact region is electrically connected to the source.
9. The method for preparing a super junction MOS device according to claim 1, characterized in that: Before forming the source electrode and the gate electrode and after forming the source region, the method further includes forming an interlayer dielectric layer covering the exposed upper surface of the semiconductor structure, wherein the source electrode penetrates the interlayer dielectric layer and is electrically connected to the source region, and the gate electrode penetrates the interlayer dielectric layer and is electrically connected to the gate structure.
10. A super junction MOS device, characterized in that: The super junction MOS device is manufactured by using the method for manufacturing a super junction MOS device according to any one of claims 1 to 9.