Method for reducing input capacitance of power MOSFET
By reducing the overlap area of the source injection region and gate and increasing the thickness of the oxide layer, the problem of excessive high input capacitance of the power MOSFET is solved, and the input capacitance is reduced and the device switching performance is improved.
Patent Information
- Application Number
- CN202510105514.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-06
AI Technical Summary
In the prior art, the input capacitance of the power MOSFET is too high, which affects the device's turn-on and turn-off delay.
The input capacitance is reduced by reducing the overlap area of the source injection region and the gate adjacent to the trench and increasing the thickness of the oxide layer between the source injection region and the gate.
It effectively reduces the input capacitance and improves the switching performance of the device, which is specifically manifested as a 28.46% reduction in the input capacitance Ciss.
Smart Images
Figure CN119947159A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for reducing the input capacitance of a power MOSFET. Background Art
[0002] The gate electrode input capacitance Ciss has a direct impact on the turn-on and turn-off delays of power devices.
[0003] See also Figure 1 The input capacitor consists of two parts, the gate-drain capacitor Cgd and the gate-source capacitor Cgs. The gate-source capacitor Cgs is an important component of the input capacitor.
[0004] The gate-source capacitance Cgs is determined by the gate oxide thickness (GOX thickness) and the area of the source implant region and the gate overlap region.
[0005] How to reduce the input capacitance of power MOSFET in the prior art needs to be solved urgently.
[0006] In order to solve the above problems, it is necessary to propose a new method for reducing the input capacitance of the power MOSFET. Summary of the invention
[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing the input capacitance of a power MOSFET, so as to solve the problem of excessively high input capacitance of the power MOSFET in the prior art.
[0008] To achieve the above object and other related objects, the present invention provides a method for reducing the input capacitance of a power MOSFET, comprising:
[0009] Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a deep trench in the cell region and the gate lead-out region on the epitaxial layer, forming a first gate dielectric layer at the bottom of the deep trench and a source polysilicon layer located on the first gate dielectric layer, an isolation dielectric layer on the first gate dielectric layer and the source polysilicon layer, forming a second gate dielectric layer on the remaining sidewalls of the deep trench and the substrate, and forming a gate polysilicon layer filling the remaining deep trench;
[0010] Step 2, etching the gate polysilicon layer to a preset thickness to form an opening pattern, and then removing the exposed second gate dielectric layer;
[0011] Step 3: forming a thermal oxide layer by thermal oxidation, wherein the thermal oxide layer is located on the surface of the epitaxial layer and the opening pattern, and the corner of the upper surface of the gate polysilicon layer is consumed by oxidation, so that the oxide layer between the gate and the source is thickened;
[0012] Step 4: forming a body region and a source region on the upper surface of the epitaxial layer by ion implantation;
[0013] Step 5: using a self-alignment process to increase the angled source implantation to form an ion implantation region along the sidewall of the opening pattern;
[0014] Step 6: Form a pre-metal dielectric layer, form a contact hole, the contact hole extends from the upper surface of the pre-metal dielectric layer to the body region, form a contact member filling the contact hole, and then form a front metal electrode and a back metal electrode.
[0015] Preferably, in step one, the deep trench is formed by photolithography and etching.
[0016] Preferably, the material of the first gate dielectric layer in step 1 is silicon dioxide.
[0017] Preferably, the material of the second gate dielectric layer in step 1 is silicon dioxide.
[0018] Preferably, the material of the isolation dielectric layer in step 1 is silicon dioxide or silicon nitride.
[0019] Preferably, in step 2, the gate polysilicon layer is etched to a thickness of 1100 to 1300 angstroms to form an opening pattern.
[0020] Preferably, in step 2, the second gate dielectric layer is removed by wet etching.
[0021] Preferably, the thermal oxidation in step three is 200 to 300 angstroms.
[0022] Preferably, the material of the pre-metal dielectric layer in step six is silicon dioxide.
[0023] Preferably, in step six, the contact hole is formed by photolithography and etching.
[0024] As described above, the method of reducing the input capacitance of a power MOSFET of the present invention has the following beneficial effects:
[0025] The present invention can reduce input capacitance by reducing the overlapping area of the source injection region and the gate near the groove and increasing the thickness of the oxide layer between the source injection region and the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 Shown is a schematic diagram of input capacitor composition of the prior art;
[0027] Figure 2 Shown is a schematic diagram of the process flow of the present invention;
[0028] Figure 3 It is a schematic diagram of the device structure after forming a gate polysilicon layer according to the present invention;
[0029] Figure 4 A schematic diagram showing an opening pattern formed by etching a gate polysilicon layer of a certain thickness according to the present invention;
[0030] Figure 5 It is a schematic diagram showing the removal of the exposed second gate dielectric layer according to the present invention;
[0031] Figure 6 It shows a schematic diagram of forming a thermal oxide layer, a body region, and a source region according to the present invention;
[0032] Figure 7 It is a schematic diagram of forming an ion implantation region according to the present invention;
[0033] Figure 8 It is a schematic diagram of forming a contact hole according to the present invention;
[0034] Fig. 9 It is a schematic diagram of forming a front metal electrode according to the present invention;
[0035] Fig.10 Shown are cross-sectional schematic diagrams of devices made by the prior art and the present invention;
[0036] Fig.11 It is a schematic diagram comparing the performance parameters of the device made by the prior art and the device made by the present invention. DETAILED DESCRIPTION
[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] See also Figure 2 The present invention provides a method for reducing the input capacitance of a power MOSFET, comprising:
[0039] Step 1: Provide a substrate 101, form an epitaxial layer 102 on the substrate 101, form deep trenches in the cell region and the gate lead-out region on the epitaxial layer, form a first gate dielectric layer 103 at the bottom of the deep trenches and a source polysilicon layer 104 on the first gate dielectric layer 103, form an isolation dielectric layer 105 on the first gate dielectric layer 103 and the source polysilicon layer 104, form a second gate dielectric layer 106 on the sidewalls of the remaining deep trenches and on the substrate 101, form a gate polysilicon layer 107 filling the remaining deep trenches, and form a Figure 3The structure shown can usually form a gate polysilicon layer 107 filling the deep trench by deposition and grinding, and the grinding method is chemical mechanical planarization grinding;
[0040] In some embodiments, in step one, a deep groove is formed by photolithography and etching, and the etching method is dry etching. After the etching is completed, the remaining photoresist can be removed by ashing process and wet cleaning method.
[0041] In some embodiments, the material of the first gate dielectric layer 103 in step 1 is silicon dioxide.
[0042] In some embodiments, the material of the second gate dielectric layer 106 in step 1 is silicon dioxide.
[0043] In some embodiments, the material of the isolation dielectric layer 105 in step 1 is silicon dioxide or silicon nitride.
[0044] Step 2: Etch the gate polysilicon layer 107 to a preset thickness to form an opening pattern, forming Figure 4 The structure shown in FIG. 1 is etched by dry etching or wet etching, and then the exposed second gate dielectric layer 106 is removed to form a Figure 5 The structure shown;
[0045] In some embodiments, in step 2, the gate polysilicon layer 107 is etched to a thickness of 1100 to 1300 angstroms to form an opening pattern, for example, 1200 angstroms.
[0046] In some embodiments, in step 2, the second gate dielectric layer 106 is removed by wet etching.
[0047] Step 3: Form a thermal oxide layer 108 by thermal oxidation. The thermal oxide layer 108 is located on the surface of the epitaxial layer 102 and the opening pattern. The corner of the upper surface of the gate polysilicon layer 107 is oxidized and consumed, so that the oxide layer between the gate and the source is increased, forming a Figure 6 The structure shown;
[0048] In some embodiments, the thermal oxidation in step three is 200 to 300 angstroms, such as 250 angstroms.
[0049] Step 4: forming a body region 109 and a source region 110 on the upper surface of the epitaxial layer 102 by ion implantation;
[0050] Step 5: Use the self-alignment process to increase the angled source implantation to form an ion implantation region 111 along the sidewall of the opening pattern. The ion implantation region 111 is located at the bottom corner of the opening pattern to form a Figure 7 The structure shown; here the trench at the gate polysilicon layer 107 is engraved deeply, reducing the overlapping area of the source injection region and the gate near the trench;
[0051] Step 6: Form a pre-metal dielectric layer 112 and form a contact hole. The contact hole extends from the upper surface of the pre-metal dielectric layer 112 to the body region 109 to form a Figure 8 The structure shown in FIG. 1 is used to form a contact 113 filling the contact hole, and then a front metal electrode 114 (such as Fig. 9 shown) and a back metal electrode (not shown).
[0052] In some embodiments, the material of the pre-metal dielectric layer 112 in step six is silicon dioxide.
[0053] In some embodiments, in step six, the contact hole is formed by photolithography and etching.
[0054] Cgs is inversely proportional to the gate oxide thickness (GOX thickness) and is proportional to the area of the overlap between the source region 110 and the gate. The input capacitance can be reduced by reducing the overlap area between the source injection region and the gate near the trench and increasing the oxide thickness between the source injection region and the gate.
[0055] See also Fig.10 , which shows a cross-sectional view of a device made by the prior art and the present invention, see Fig.11 As shown in the simulation diagram, the input capacitance Ciss of the shielded gate MOSFET structure prepared by the method of the present invention can be reduced by 28.46%, while other performance parameters remain unchanged, thereby improving the switching performance of the device.
[0056] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0057] In summary, the present invention can reduce the input capacitance by reducing the overlapping area of the source injection region and the gate near the trench and increasing the thickness of the oxide layer between the source injection region and the gate. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.
[0058] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for reducing the input capacitance of a power MOSFET, characterized in that: At least: Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a deep trench in the cell region and the gate lead-out region on the epitaxial layer, forming a first gate dielectric layer at the bottom of the deep trench and a source polysilicon layer located on the first gate dielectric layer, an isolation dielectric layer on the first gate-source dielectric layer and the source polysilicon layer, forming a second gate dielectric layer on the remaining sidewalls of the deep trench and the substrate, and forming a gate polysilicon layer filling the remaining deep trench; Step 2, etching the gate polysilicon layer to a preset thickness to form an opening pattern, and then removing the exposed second gate dielectric layer; Step 3, forming a thermal oxide layer by thermal oxidation, wherein the thermal oxide layer is located on the surface of the epitaxial layer and the opening pattern, and the corner of the upper surface of the gate polysilicon layer is consumed by oxidation, so that the oxide layer between the gate and the source is thickened; Step 4: forming a body region and a source region on the upper surface of the epitaxial layer by ion implantation; Step 5: using a self-alignment process to increase the angled source implantation to form an ion implantation region along the sidewall of the opening pattern; Step 6: Form a pre-metal dielectric layer, form a contact hole, the contact hole extends from the upper surface of the pre-metal dielectric layer to the body region, form a contact member filling the contact hole, and then form a front metal electrode and a back metal electrode.
2. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: In step one, the deep trench is formed by photolithography and etching.
3. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: The material of the first gate dielectric layer in step 1 is silicon dioxide.
4. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: The material of the second gate dielectric layer in step 1 is silicon dioxide.
5. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: The material of the isolation dielectric layer in step 1 is silicon dioxide or silicon nitride.
6. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: In step 2, the gate polysilicon layer is etched to a thickness of 1100 to 1300 angstroms to form an opening pattern.
7. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: In step 2, the second gate dielectric layer is removed by wet etching.
8. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: The thermal oxidation in step three is 200 to 300 angstroms.
9. The method for reducing the input capacitance of a power MOSFET according to claim 1, wherein: The material of the pre-metal dielectric layer in step six is silicon dioxide.
10. The method for reducing the input capacitance of a power MOSFET according to claim 1, characterized in that: In step six, the contact hole is formed by photolithography and etching.