Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, relating to the technical field of semiconductor manufacturing. The method includes: providing a substrate; etching the substrate to form trenches in the substrate; forming a first sub-field oxide structure in the trenches; forming a mask layer on the substrate; etching the mask layer to form openings, and the openings expose a part of the first sub-field oxide structure; forming a second sub-field oxide structure at the openings, and the second sub-field oxide structure is connected to the first sub-field oxide structure to form a field oxide structure; performing an ion implantation process to form a body region and a drift region in the substrate; forming a gate structure on the substrate, the gate structure straddles the body region and the drift region, and the gate structure covers a part of the field oxide structure. The first sub-field oxide structure having a certain depth in the substrate can enable the semiconductor device to obtain a high breakdown voltage, and the connected second sub-field oxide structure and the first sub-field oxide structure form a stepped shape to shorten the current path to reduce the on-resistance and improve the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor technology and its application fields, the manufacturing processes and structures of power semiconductor devices have been continuously improved, promoting the development of power devices towards high-performance directions. Among power devices, the Laterally Diffused Metal Oxide Semiconductor (LDMOS for short) has advantages such as high breakdown voltage, high input impedance, and easy integration, so it is widely used in the manufacturing of semiconductor integrated circuits.

[0003] The main indicators for improving the performance of LDMOS devices are the breakdown voltage BVDS and the on-resistance Rsp. Reducing the on-resistance is beneficial to improving the working efficiency of the device, while increasing the breakdown voltage makes a prominent contribution to increasing the output power and output impedance of the device. However, there is a contradiction between achieving a high breakdown voltage and achieving a low on-resistance. Summary of the Invention

[0004] Based on this, in view of the problems in the above background art, it is necessary to provide a semiconductor device and a method for manufacturing the same to reduce the on-resistance while meeting the voltage requirements.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a method for manufacturing a semiconductor device, including the following steps:

[0006] Provide a substrate;

[0007] Etch the substrate to form a trench in the substrate;

[0008] Form a first sub-field oxide structure in the trench;

[0009] Form a mask layer on the substrate;

[0010] Etch the mask layer to form an opening, and the opening exposes a part of the first sub-field oxide structure;

[0011] Form a second sub-field oxide structure at the opening, and the second sub-field oxide structure is connected to the first sub-field oxide structure to form a field oxide structure;

[0012] Perform an ion implantation process to form a body region and a drift region in the substrate;

[0013] Form a gate structure on the substrate, the gate structure straddles the body region and the drift region, and the gate structure covers a part of the field oxide structure.

[0014] In one embodiment, forming a first sub-field oxide structure in the trench includes:

[0015] Forming a shallow trench isolation structure in the trench, and using the shallow trench isolation structure as the first sub-field oxide structure.

[0016] In one embodiment, forming a second sub-field oxide structure at the opening includes:

[0017] Performing a local oxidation process at the opening to form a local oxidation structure, and using the local oxidation structure as the second sub-field oxide structure.

[0018] On the other hand, the present invention provides a semiconductor device, including:

[0019] A substrate, which includes spaced body regions and drift regions therein;

[0020] A field oxide structure, including a connected first sub-field oxide structure and a second sub-field oxide structure;

[0021] A gate structure, located on the top surface of the substrate, the gate structure straddling the body region and the drift region, and the gate structure covering a part of the field oxide structure.

[0022] In one embodiment, the first sub-field oxide structure includes a shallow trench isolation structure, and the second sub-field oxide structure includes a local oxidation structure.

[0023] In one embodiment, the first sub-field oxide structure and the second sub-field oxide structure form a stepped field oxide structure.

[0024] In one embodiment, the depth of the first sub-field oxide structure in the substrate is greater than the depth of the second sub-field oxide structure in the substrate.

[0025] In one embodiment, a part of the second sub-field oxide structure is located on the top surface of the substrate and another part is located inside the substrate, and the first sub-field oxide structure is located inside the substrate.

[0026] In one embodiment, the substrate includes a source electrode and a drain electrode, and the distance between the second sub-field oxide structure and the drain electrode is greater than the distance between the first sub-field oxide structure and the drain electrode.

[0027] In one embodiment, the gate structure completely covers the second sub-field oxide structure, and the gate structure covers a part of the first sub-field oxide structure; or, the gate structure partially covers the second sub-field oxide structure.

[0028] In one embodiment, the second sub-field oxygen structure is located above the drift region, the drift region includes a well region, the ion doping concentration of the well region is greater than that of the drift region, and the first sub-field oxygen structure is partially or entirely located within the well region.

[0029] According to the semiconductor device and its manufacturing method provided by the present invention, a first sub-field oxygen structure and a second sub-field oxygen structure are respectively formed. The first sub-field oxygen structure and the second sub-field oxygen structure are connected as a field oxygen structure. The first sub-field oxygen structure has a certain depth in the substrate, enabling the semiconductor device to obtain a high breakdown voltage. The connected first sub-field oxygen structure and second sub-field oxygen structure form a stepped shape, which can shorten the current path to reduce the on-resistance. By reducing the on-resistance while ensuring the breakdown voltage, the performance of the semiconductor device is improved. Description of the Drawings

[0030] To better describe and illustrate the embodiments and / or examples of the applications disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the currently described embodiments and / or examples, and the currently understood best mode of these applications.

[0031] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment;

[0032] Figure 2 It is a flowchart of a manufacturing method of a semiconductor device provided in an embodiment;

[0033] Figure 3A It is a schematic cross-sectional structure diagram of the substrate provided in step S201 of the manufacturing method of the semiconductor device provided in an embodiment;

[0034] Figure 3B It is a schematic cross-sectional structure diagram of the obtained structure after forming a trench in the substrate in step S202 of the manufacturing method of the semiconductor device provided in an embodiment;

[0035] Figure 3C It is a schematic cross-sectional structure diagram of the obtained structure after forming the first sub-field oxygen structure in step S203 of the manufacturing method of the semiconductor device provided in an embodiment;

[0036] Figure 3D It is a schematic cross-sectional structure diagram of the obtained structure after forming an opening in the mask layer in step S205 of the manufacturing method of the semiconductor device provided in an embodiment;

[0037] Figure 3ESchematic cross-sectional structure diagram of the obtained structure after forming the second sub-field oxygen structure in step S206 of the method for manufacturing a semiconductor device provided in an embodiment;

[0038] Figure 3F Schematic cross-sectional structure diagram of the obtained structure after forming the body region and the drift region in step S207 of the method for manufacturing a semiconductor device provided in an embodiment;

[0039] Figure 3G Schematic cross-sectional structure diagram of the obtained structure after forming the gate structure in step S208 of the method for manufacturing a semiconductor device provided in an embodiment.

[0040] Description of reference numerals:

[0041] 100, substrate; 101, first type trench; 102, second type trench; 110, pad oxide layer; 120, first mask layer; 130, shallow trench isolation structure; 140, field oxide structure; 141, first sub-field oxide structure; 142, second sub-field oxide structure; 150, second mask layer; 151, opening; 160, body region; 170, drift region; 180, well region; 190, gate structure. Detailed description of the embodiments

[0042] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0044] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of this application.

[0045] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of this application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0047] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present application should not be limited to the specific shapes of regions shown herein, but rather include shape deviations due to, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present application.

[0048] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present application. Although only the components related to the present application are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] In order to enable an LDMOS device to obtain a high breakdown voltage BVDS, an LDMOS device usually forms a drift region for withstanding the strong potential difference from the drain end to the source end. In addition, a field oxide structure is also provided as a breakdown voltage withstand region from the drain end to the gate. Without this field oxide structure, when there is a high voltage at the drain end, thermal breakdown from the drain end to the gate is likely to occur, damaging the device and unable to meet the requirements of the high operating voltage of the device. Shallow Trench Isolation (STI) can be used as the above-mentioned field oxide structure to increase the breakdown voltage. High-performance LDMOS needs to have both a high breakdown voltage BVDS and a low on-resistance Rsp. However, when using STI as the field oxide structure, it is difficult to further reduce the on-resistance while meeting the breakdown voltage requirement. If other processes are used and STI is abandoned, it will be difficult to increase the breakdown voltage due to insufficient oxide layer depth.

[0050] In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, as Figure 2 shown, including the following steps:

[0051] Step S201: Provide a substrate;

[0052] Step S202: Etch the substrate to form a trench in the substrate;

[0053] Step S203: Form a first sub-field oxide structure in the trench;

[0054] Step S204: Form a mask layer on the substrate;

[0055] Step S205: Etch the mask layer to form an opening that exposes a part of the first sub-field oxide structure;

[0056] Step S206: Form a second sub-field oxygen structure at the opening, and connect the first sub-field oxygen structure and the second sub-field oxygen structure to form a field oxygen structure;

[0057] Step S207: Perform an ion implantation process to form a body region and a drift region in the substrate;

[0058] Step S208: Form a gate structure on the substrate, the gate structure straddles the body region and the drift region, and the gate structure covers a part of the field oxygen structure.

[0059] First, perform step S201. Refer to Figure 3A as shown, provide a substrate 100.

[0060] In one embodiment, the substrate 100 is but not limited to a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a gallium arsenide substrate, or a combination of multiple of the above substrates. The substrate type of the substrate 100 can be P-type or N-type. In this embodiment, the substrate 100 uses a P-type substrate. In addition, an epitaxial layer may be formed on the top surface of the substrate 100, and the present application does not limit this.

[0061] Then, perform step S202. Refer to Figure 3B as shown, etch the substrate 100 to form a trench in the substrate 100.

[0062] In one embodiment, the trenches formed in the substrate 100 include a first type of trench 101 for forming shallow trench isolation (STI) and a second type of trench 102 for forming a first sub-field oxygen structure. Specifically, a pad oxide layer 110 and a first mask layer 120 are sequentially formed on the substrate 100. Among them, the pad oxide layer 110 includes, but is not limited to, silicon oxide, and the method for forming the pad oxide layer 110 can be completed by using process technologies familiar to those skilled in the art such as thermal oxidation. The first mask layer 120 includes, but is not limited to, silicon nitride, and the method for forming the first mask layer 120 can be completed by using process technologies such as chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), rapid thermal chemical vapor deposition (RTCVD), etc. Next, a photolithography process is performed to form a patterned first mask layer 120, and then the pad oxide layer 110 and the substrate 100 are etched using the patterned first mask layer 120 as a mask to form a plurality of trenches in the substrate 100. The method for etching the substrate 100 can use an anisotropic dry etching process, and the dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, etc. The depth range of the trenches formed in the substrate 100 includes 2500 Å to 4000 Å, such as 2500 Å, 3000 Å, 4000 Å. The plurality of trenches formed in the substrate 100 include a first type of trench 101 for forming shallow trench isolation and a second type of trench 102 for forming a first sub-field oxygen structure 141. The first type of trench 101 for forming shallow trench isolation defines an active region, and the second type of trench 102 for forming a first sub-field oxygen structure 141 is located within the active region.

[0063] Next, step S203 is performed. Referring to Figure 3C as shown, a first sub-field oxygen structure 141 is formed in the trench. Exemplarily, forming a first sub-field oxygen structure 141 in the trench includes: forming a shallow trench isolation structure in the trench, and using the shallow trench isolation structure as the first sub-field oxygen structure 141.

[0064] In one embodiment, a process technology such as high density plasma chemical vapor deposition (HDP) is used to form an oxide. The oxide fills the first type of trench 101 to form a shallow trench isolation structure 130, and the oxide fills the second type of trench 102 to form a first sub-field oxygen structure 141. In this way, the shallow trench isolation structure 130 and the first sub-field oxygen structure 141 can be formed synchronously. Or rather, the process steps for forming the first sub-field oxygen structure 141 are incorporated into the steps for forming the shallow trench isolation structure 130 to simplify the process flow. The formed shallow trench isolation structure 130 is used to define an active area (Active Area, abbreviated as AA). The active area is the area where the devices are located. Source electrodes, drain electrodes, and gate electrodes can be further formed in the active area. Different active areas are isolated from each other by the shallow trench isolation structure 130.

[0065] In one embodiment, after the groove is filled with the oxide, it further includes a step of planarizing the oxide. Specifically, chemical mechanical polishing (CMP) is performed to polish the surface of the oxide to be flush with the notch of the trench. Since the masking rates of the oxide and the first mask layer 120 are different, and the masking rate of the oxide is greater than the polishing rate of the silicon nitride, the surface of the oxide can be polished to be flush with the notch of the trench through the CMP process. Then, the first mask layer 120 is removed. Specifically, wet cleaning with a hot phosphoric acid solution can be used to remove the silicon nitride.

[0066] Then step S204 is executed to form a second mask layer 150 on the substrate 100.

[0067] In one embodiment, the second mask layer 150 includes but is not limited to silicon nitride. The method for forming the second mask layer 150 can adopt chemical vapor deposition (CVD), such as one of low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0068] Then step S205 is executed. Refer to Figure 3D As shown, the second mask layer 150 is etched to form an opening 151, and the opening 151 exposes a part of the first sub-field oxygen structure 141.

[0069] In one embodiment, a patterned photoresist layer (not shown) is first formed on the second mask layer 150, and then a lithography process is performed to transfer the pattern of the photoresist layer to the second mask layer 150 to form an opening 151. The opening 151 exposes a part of the first sub-field oxygen structure 141 so that the structure formed in the opening 151 can be connected to the first sub-field oxygen structure 141 subsequently.

[0070] Then step S206 is executed. Refer toFigure 3E As shown, a second sub-field oxygen structure 142 is formed at the opening 151, and the second sub-field oxygen structure 142 is connected to the first sub-field oxygen structure 141 to form a field oxygen structure 140. Exemplarily, forming the second sub-field oxygen structure 142 at the opening 151 includes: performing a local oxidation process at the opening 151 to form a local oxidation structure, and using the local oxidation structure as the second sub-field oxygen structure 142.

[0071] In one embodiment, through the Local Oxidation of Silicon (LOCOS) process, a field oxide can be selectively generated in a specific region. Specifically, using the pad oxide layer 110 as a protective layer on the silicon surface of the substrate 100 to protect it from the stress generated by the nitride, a local oxidation structure is generated as the second sub-field oxygen structure 142 at the position of the opening 151 formed in the second mask layer 150, that is, the region without the silicon nitride coverage. The thickness range of the second sub-field oxygen structure 142 includes 1200 Å to 2000 Å, such as 1200 Å, 1500 Å, 2000 Å. Due to the thermal oxidation consuming a part of the silicon, a part of the generated field oxide is recessed into the silicon substrate, so that a part of the second sub-field oxygen structure 142 is located inside the substrate 100 and another part is located on the top surface of the substrate 100, as Figure 3E shown. Since a part of the first sub-field oxygen structure 141 is exposed at the opening 151, the second sub-field oxygen structure 142 formed in this step is connected to the first sub-field oxygen structure 141 to form a whole, that is, a stepped field oxygen structure 140. In addition, a laterally extending part, called the bird's beak region, will be formed under the second mask layer 150 for the second sub-field oxygen structure 142. The second sub-field oxygen structure 142 can increase the connection area with the first sub-field oxygen structure 141 through the laterally extending bird's beak region, improving the overall performance of the field oxygen structure 140.

[0072] In one embodiment, after forming the second sub-field oxygen structure 142, it further includes the step of removing the second mask layer 150. Specifically, a wet cleaning can be performed using a hot phosphoric acid solution to remove the silicon nitride. In addition, since there is a certain damage to the pad oxide layer 110 in the above process, it further includes the step of removing the pad oxide layer 110. Specifically, a wet cleaning can be performed using a BOE solution (Buffered Oxide Etch) to remove the silicon oxide.

[0073] Then step S207 is executed. Referring to Figure 3F shown, an ion implantation process is performed to form a body region 160 and a drift region 170 in the substrate 100.

[0074] In one embodiment, before performing the ion implantation process, it further includes the step of forming a sacrificial oxide layer (not shown) on the surface of the substrate 100. Then, the first ion implantation is performed. The ions of the first ion implantation include P-type ions to form a body region 160 (P-body) on the top of the substrate 100. The body region 160 is located in the active region defined by the shallow trench isolation structure 130 and surrounds a part of the shallow trench isolation structure 130. Then, the second ion implantation is performed. The ions of the second ion implantation include N-type ions to form a drift region 170 (drift) on the top of the substrate 100. The field oxide structure 140 is located above the drift region 170, and the drift region 170 is spaced apart from the body region 160. Then, the third ion implantation is performed. The ions of the third ion implantation include N-type ions to form a well region 180 (N-well) in the drift region 170, so that the ion doping concentration of the well region 180 is greater than that of the drift region 170. Optionally, after forming the well region 180, a part or all of the first sub-field oxide structure 141 is located within the well region 180.

[0075] Then, step S208 is performed. Referring to Figure 3G As shown, a gate structure 190 is formed on the substrate 100. The gate structure 190 straddles the body region 160 and the drift region 170, and the gate structure 190 covers a part of the field oxide structure 140.

[0076] In one embodiment, a gate oxide layer and a gate material layer are sequentially formed on the substrate 100. Among them, the gate oxide layer includes but is not limited to silicon oxide, and the gate material layer includes but is not limited to polysilicon. Then, the gate oxide layer and the gate material layer are etched to form the gate structure 190. Further, the gate structure 190 may further include gate sidewalls formed at both ends of the stacked structure of the gate oxide layer and the gate material layer.

[0077] In one embodiment, the gate structure 190 straddles the body region 160 and the drift region 170. Further, the gate structure 190 also covers a part of the well region 180. Therefore, the gate structure 190 straddles the body region 160, the drift region 170, and the well region 180. Optionally, the gate structure 190 completely covers the second sub-field oxide structure 142 and covers a part of the first sub-field oxide structure 141, or the gate structure 190 partially covers the second sub-field oxide structure 142. In addition, referring to Figure 3G As shown, the gate oxide layer is only formed between the substrate 100 and the gate material layer, and the second sub-field oxide structure 142 is directly in contact with the gate material layer. Therefore, a part of the second sub-field oxide structure 142 is located within the gate structure 190, and another part of the second sub-field oxide structure 142 is located within the substrate 100.

[0078] In one embodiment, after forming the gate structure 190, it further includes the steps of forming source and drain. Specifically, taking the NLDMOS device as an example, N-type ion implantation is performed to form an N-type ion heavily doped region on the top of the body region 160 and the well region 180, and P-type ion implantation is performed to form a P-type ion heavily doped region on the top of the body region 160. Further, it also includes the step of forming salicide on the top of the source, drain, and gate structure 190 and the step of forming contact plugs (CT) to lead out the source, drain, and gate, so as to form Figure 1 the structure shown, which will not be elaborated here.

[0079] So far, the related steps of the manufacturing method of the semiconductor device according to the embodiment of the present invention have been introduced. It can be understood that the manufacturing method of the semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of this manufacturing method.

[0080] The present invention also provides a semiconductor device. Referring to Figure 1 the figure shown, it includes:

[0081] A substrate 100, which includes spaced body regions 160 and drift regions 170 therein;

[0082] A field oxide structure 140, which includes a connected first sub-field oxide structure 141 and a second sub-field oxide structure 142;

[0083] A gate structure 190, located on the top surface of the substrate 100, the gate structure 190 straddles the body region 160 and the drift region 170, and the gate structure 190 covers a part of the field oxide structure 140.

[0084] In one embodiment, the substrate 100 includes, but is not limited to, a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a gallium arsenide substrate, or a combination of the above multiple substrates. The substrate type of the substrate 100 can be P-type or N-type. In this embodiment, the substrate 100 uses a P-type substrate. In addition, an epitaxial layer may be formed on the top surface of the substrate 100, and the present application does not limit this.

[0085] In one embodiment, a shallow trench isolation structure 130 is included in the substrate 100. The shallow trench isolation structure 130 is used to define the active area (AA). The active area is the area where the devices are located. Source, drain, and gate electrodes can be further formed in the active area. Different active areas are isolated from each other by the shallow trench isolation structure 130. Further, spaced body regions 160 and drift regions 170 are included in the active area of the substrate 100. The doping ions in the body region 160 include P-type ions, and the doping ions in the drift region 170 include N-type ions. Among them, a well region 180 is further formed in the drift region 170, and the ion doping concentration in the well region 180 is greater than that in the drift region 170. Further, the active area of the substrate 100 includes a source electrode and a drain electrode. The source electrode is located on the top of the body region 160, and the ion doping concentration of the source electrode is greater than that of the body region 160. The source electrode includes an N-type ion heavily doped region and a P-type ion heavily doped region. The drain electrode is located on the top of the well region 180, and the ion doping concentration of the drain electrode is greater than that of the well region 180. The drain electrode includes an N-type ion heavily doped region.

[0086] In one embodiment, the field oxide structure 140 includes a connected first sub-field oxide structure 141 and second sub-field oxide structure 142. Among them, the first sub-field oxide structure 141 includes a shallow trench isolation structure, and the second sub-field oxide structure 142 includes a local oxidation structure. The first sub-field oxide structure 141 is formed synchronously with the shallow trench isolation structure 130. Therefore, the shape and size (e.g., depth, width) of the first sub-field oxide structure 141 are the same as those of the shallow trench isolation structure 130. The depth range of the first sub-field oxide structure 141 in the substrate 100 includes 2500 Å to 4000 Å, such as 2500 Å, 3000 Å, 4000 Å. The first sub-field oxide structure 141 is located in the substrate 100. Specifically, the first sub-field oxide structure 141 is partially or entirely located in the well region 180. A part of the second sub-field oxide structure 142 is located in the substrate 100 and another part is located on the top surface of the substrate 100. Specifically, the second sub-field oxide structure 142 is located above the drift region 170. The thickness range of the second sub-field oxide structure 142 includes 1200 Å to 2000 Å, such as 1200 Å, 1500 Å, 2000 Å.

[0087] In one embodiment, the materials of the first sub-field oxygen structure 141 and the second sub-field oxygen structure 142 are the same, such as silicon oxide. The first sub-field oxygen structure 141 and the second sub-field oxygen structure 142 are connected to form an integral structure, namely the field oxygen structure 140. The depth of the first sub-field oxygen structure 141 in the substrate 100 is greater than the depth of the second sub-field oxygen structure 142 in the substrate 100, and the second sub-field oxygen structure 142 and the first sub-field oxygen structure 141 form a stepped field oxygen structure 140. Since the first sub-field oxygen structure 141 has a certain depth in the substrate 100, the first sub-field oxygen structure 141, as a part of the field oxygen structure 140, can enable the LDMOS device to obtain a high breakdown voltage. In addition, the farther the field oxygen structure 140 is from the drain end, the lower the electric potential. Therefore, the second sub-field oxygen structure 142 can be adopted in the area of the field oxygen structure 140 far from the drain end. The depth of the second sub-field oxygen structure 142 in the substrate 100 is less than the depth of the first sub-field oxygen structure 141 in the substrate 100, thereby shortening the current path, increasing the over-current area, and reducing the conduction resistance Rsp loss. In this way, while meeting the breakdown voltage requirement, the conduction resistance is reduced, and at the same time, the electric field distribution under the field oxygen structure 140 is more uniform, and multiple peak electric fields are not likely to appear.

[0088] In one embodiment, the gate structure 190 includes a gate oxide layer and a gate material layer stacked in sequence in a direction away from the substrate 100. Among them, the gate oxide layer includes, but is not limited to, silicon oxide, and the gate material layer includes, but is not limited to, polysilicon. The gate structure 190 may further include gate sidewalls formed at both ends of the stacked structure of the gate oxide layer and the gate material layer. The gate structure 190 straddles the body region 160 and the drift region 170. Further, the gate structure 190 also covers a part of the well region 180. Therefore, the gate structure 190 straddles the body region 160, the drift region 170, and the well region 180. The gate structure 190 covers a part of the field oxygen structure 140. Optionally, the gate structure 190 completely covers the second sub-field oxygen structure 142 and covers a part of the first sub-field oxygen structure 141, or the gate structure 190 partially covers the second sub-field oxygen structure 142. In addition, referring to Figure 3G As shown, the gate oxide layer is only formed between the substrate 100 and the gate material layer, and the second sub-field oxygen structure 142 is directly connected to the gate material layer. Therefore, a part of the second sub-field oxygen structure 142 is located inside the gate structure 190, and another part of the second sub-field oxygen structure 142 is located inside the substrate 100.

[0089] According to the semiconductor device and its manufacturing method provided by the present invention, a first sub-field oxygen structure and a second sub-field oxygen structure are respectively formed. The first sub-field oxygen structure and the second sub-field oxygen structure are connected to serve as a field oxygen structure. The first sub-field oxygen structure has a certain depth in the substrate, enabling the semiconductor device to obtain a high breakdown voltage. The connected first sub-field oxygen structure and the second sub-field oxygen structure form a stepped shape, which can shorten the current path to reduce the on-resistance. By reducing the on-resistance while ensuring the breakdown voltage, the performance of the semiconductor device is improved.

[0090] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to this application.

[0091] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0092] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity in description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0093] The above-described embodiments only represent several implementation manners of this application. Their descriptions are relatively specific and detailed, but they should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, It includes the following steps: Provide a substrate; Etch the substrate to form trenches in the substrate; Form a first sub-field oxide structure in the trenches; Form a mask layer on the substrate; Etch the mask layer to form an opening that exposes a part of the first sub-field oxide structure; Form a second sub-field oxide structure at the opening, and the second sub-field oxide structure is connected to the first sub-field oxide structure to form a field oxide structure; Perform an ion implantation process to form a body region and a drift region in the substrate. The drift region includes a well region. The second sub-field oxide structure is located above the drift region, and the first sub-field oxide structure is partially or entirely located within the well region; Form a gate structure on the substrate. The gate structure straddles the body region and the drift region, and the gate structure covers a part of the field oxide structure; Form a source electrode and a drain electrode. The source electrode is located on top of the body region, and the drain electrode is located on top of the well region. The depth of the first sub-field oxide structure in the substrate is greater than the depth of the second sub-field oxide structure in the substrate, and the distance between the second sub-field oxide structure and the drain electrode is greater than the distance between the first sub-field oxide structure and the drain electrode.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, Forming a first sub-field oxide structure in the trenches includes: Form a shallow trench isolation structure in the trenches, and use the shallow trench isolation structure as the first sub-field oxide structure.

3. The method for manufacturing a semiconductor device according to claim 1, wherein Forming a second sub-field oxide structure at the opening includes: Perform a local oxidation process at the opening to form a local oxidation structure, and use the local oxidation structure as the second sub-field oxide structure.

4. A semiconductor device, characterized in that, It includes: A substrate that includes spaced body regions and drift regions. The drift region includes a well region. The source electrode is located on top of the body region, and the drain electrode is located on top of the well region; A field oxide structure that includes a connected first sub-field oxide structure and a second sub-field oxide structure. The second sub-field oxide structure is located above the drift region, and the first sub-field oxide structure is partially or entirely located within the well region. The depth of the first sub-field oxide structure in the substrate is greater than the depth of the second sub-field oxide structure in the substrate, and the distance between the second sub-field oxide structure and the drain electrode is greater than the distance between the first sub-field oxide structure and the drain electrode; A gate structure located on the top surface of the substrate. The gate structure straddles the body region and the drift region, and the gate structure covers a part of the field oxide structure.

5. The semiconductor device according to claim 4, wherein The first sub-field oxide structure includes a shallow trench isolation structure, and the second sub-field oxide structure includes a local oxidation structure.

6. The semiconductor device according to claim 4, wherein, The first sub-field oxide structure and the second sub-field oxide structure constitute a stepped field oxide structure.

7. The semiconductor device according to claim 4, wherein A part of the second sub-field oxide structure is located on the top surface of the substrate and another part is located within the substrate, and the first sub-field oxide structure is located within the substrate.

8. The semiconductor device according to claim 4, wherein: The gate structure completely covers the second sub-field oxide structure, and the gate structure covers a part of the first sub-field oxide structure; or, The gate structure partially covers the second sub-field oxide structure.

9. The semiconductor device according to claim 4, wherein, The ion doping concentration of the well region is greater than the ion doping concentration of the drift region.

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