Nitride enhanced field effect transistor based on P buried layer

Abstract

The invention relates to a nitride enhanced field effect transistor based on a P buried layer. The nitride enhanced field effect transistor comprises a substrate layer, an AlN nucleating layer, a GaN buffer layer, a GaN channel layer, an AlN barrier layer and an InN cap layer which are stacked in sequence, wherein a groove is formed in the GaN buffer layer, a P-GaN buried layer is prepared at the bottom of the groove, the thickness of the P-GaN buried layer is smaller than or equal to the depth of the groove, and the P-GaN buried layer is used for locally exhausting two-dimensional electron gas in the GaN channel layer; and a source metal layer, a drain metal layer and a gate metal layer are arranged on the cap layer at intervals. According to the device, the P-GaN buried layer used for exhausting the two-dimensional electron gas in the GaN channel layer is buried in the GaN buffer layer, so that the distance between the grid electrode and the channel in the nitride enhanced field effect transistor is shortened, the electric field intensity from the grid electrode to the channel is enhanced, the grid control capability of the device is improved, and the device performance is better.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices, and in particular relates to a nitride enhanced field effect transistor based on a P buried layer. Background Art

[0002] In the continuous evolution of semiconductor technology, the AlGaN / GaN material system has emerged as a field with great potential and research value. Modern power systems have an urgent need for high-efficiency, high-power density power conversion devices. Traditional silicon-based power devices are gradually approaching the limits of their material performance in the face of growing power processing requirements. The AlGaN / GaN heterojunction shows outstanding advantages due to its unique physical properties. At this heterojunction interface, a two-dimensional electron gas (2DEG) with high electron mobility and high concentration can be naturally formed. High electron mobility means that electrons can move quickly in the material, greatly reducing resistance losses; high-concentration two-dimensional electron gas provides sufficient carriers for the conduction of large currents. This makes the high electron mobility transistor (HEMT) based on AlGaN / GaN have excellent performance in high-voltage and high-power application scenarios. And due to its wide bandgap characteristics and good electron transport performance, AlGaN / GaN HEMT devices can work stably in the millimeter wave frequency band to achieve high-power and high-efficiency signal amplification and transmission. Compared with traditional silicon-based or gallium arsenide-based RF devices, the application of AlGaN / GaN RF devices in base station power amplifiers can significantly improve signal coverage and communication quality, while reducing base station power consumption and construction costs.

[0003] The conventional technical means at present is to deplete the two-dimensional electron gas in the channel layer by growing a P-GaN cap layer on the AlGaN barrier layer to achieve the transition of the device from the off state to the on state. However, this structural design increases the distance between the gate and the channel, causing the electric field strength from the gate to the channel to weaken, which greatly reduces the gate control ability of the device and greatly reduces the performance of the device. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a nitride enhanced field effect transistor based on a P buried layer. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] The present invention provides a nitride enhanced field effect transistor based on a P buried layer, comprising: a substrate layer, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, an AlN barrier layer and an InN cap layer stacked in sequence; wherein a groove is provided in the GaN buffer layer, a P-GaN buried layer is prepared at the bottom of the groove, the thickness of the P-GaN buried layer is equal to the depth of the groove, and the P-GaN buried layer is used for locally depleting the two-dimensional electron gas in the GaN channel layer; a source metal layer, a drain metal layer and a gate metal layer are arranged on the InN cap layer at intervals, and the gate metal layer is located between the source metal layer and the drain metal layer.

[0006] In some embodiments, the thickness of the GaN buffer layer ranges from 1 μm to 2 μm, and the depth of the groove ranges from 60 nm to 200 nm.

[0007] In some embodiments, the doping element of the P-GaN buried layer is Mg, and the doping concentration range is 1×10 17 cm -3 ~5×10 20 cm -3 .

[0008] In some embodiments, the thickness of the GaN channel layer ranges from 300 nm to 800 nm.

[0009] In some embodiments, the thickness of the AlN barrier layer ranges from 3 nm to 11 nm.

[0010] In some embodiments, the thickness of the InN cap layer ranges from 1 nm to 5 nm.

[0011] In some embodiments, the thickness of the AlN nucleation layer ranges from 20 nm to 100 nm.

[0012] In some embodiments, the material of the source metal layer and the drain metal layer includes a stacked metal of Ti, Al, Ni, and Au, and the material of the gate metal layer includes a stacked metal of Ni and Au.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] In view of the problem that the existing preparation methods increase the distance between the gate and the channel of the field effect transistor, resulting in the weakening of the electric field strength from the gate to the channel, which greatly reduces the gate control ability of the device and greatly reduces the performance of the device, the embodiment of the present invention provides a nitride enhanced field effect transistor based on a P buried layer, in which a P-GaN buried layer for depleting the two-dimensional electron gas in the GaN channel layer is buried in the GaN buffer layer. Compared with the P-GaN cap layer, this structural setting can shorten the distance between the gate and the channel in the nitride enhanced field effect transistor, which is more conducive to enhancing the electric field strength from the gate to the channel and improving the gate control ability of the device. AlN is used to replace AlGaN as a barrier layer and a GaN channel layer to form an AlN / GaN heterojunction. The stronger polarization effect of AlN can produce a higher density of two-dimensional electron gas. In addition, an InN cap layer is used above the barrier layer to achieve a lower contact resistance by utilizing the smaller work function difference between InN and metal, which has better device performance and has great application prospects in the fields of power electronics, communications, aerospace, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic structural diagram of a nitride enhanced field effect transistor based on a P buried layer proposed by the present invention;

[0016] Figure 2 It is a schematic diagram of the preparation process of a nitride enhanced field effect transistor based on a P buried layer provided in an embodiment of the present invention.

[0017] Reference numerals:

[0018] 1: substrate layer; 2: AlN nucleation layer; 3: GaN buffer layer; 4: P-GaN buried layer; 5: GaN channel layer; 6: AlN barrier layer; 7: InN cap layer; 8: source metal layer; 9: drain metal layer; 10: gate metal layer. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0020] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0021] Now, in conjunction with the accompanying drawings, a nitride enhanced field effect transistor based on a P buried layer proposed by the present invention is described in detail.

[0022] Figure 1 Schematic diagram of the structure of the nitride enhanced field effect transistor based on the P buried layer proposed by the present invention. It should be noted that this is only a schematic diagram of the structure and does not limit the thickness of each layer and the material color of the device. Figure 1 As shown, the device includes: a substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 5, an AlN barrier layer 6 and an InN cap layer 7 stacked in sequence; wherein a groove is opened in the GaN buffer layer 3, and the groove is filled with a P-GaN buried layer 4, the thickness of the P-GaN buried layer 4 is equal to the depth of the groove, and the P-GaN buried layer 4 is used to locally deplete the two-dimensional electron gas in the GaN channel layer 5; a source metal layer 8, a drain metal layer 9 and a gate metal layer 10 are arranged on the InN cap layer 7 at intervals, and the gate metal layer 10 is located between the source metal layer 8 and the drain metal layer 9.

[0023] Specifically, the material of the substrate layer 1 is a sapphire substrate, and the thickness thereof ranges from 100 μm to 1 mm. Also, the thickness of the AlN nucleation layer 2 ranges from 20 nm to 100 nm.

[0024] Here, the thickness of the GaN buffer layer 3 ranges from 1 μm to 2 μm, the depth of the groove ranges from 60 nm to 200 nm, the corresponding thickness of the P-GaN buried layer 4 ranges from 60 nm to 200 nm, and the doping element of the P-GaN buried layer 4 is Mg, and the doping concentration ranges from 1×10 17 cm -3 ~5×10 20 cm -3 .

[0025] Here, the AlN barrier layer 6 and the GaN channel layer 5 form an AlN / GaN heterojunction, wherein the thickness of the AlN barrier layer 6 ranges from 3nm to 11nm. Compared with the AlGaN / GaN heterojunction, a higher polarization can be achieved, a higher density of two-dimensional electron gas can be generated, and by setting a P-GaN buried layer 4 inside the GaN buffer layer 3 to deplete the two-dimensional electron gas corresponding to the buried layer position in the GaN channel layer 5, the distance between the gate and the channel is shortened, which is more conducive to enhancing the electric field strength from the gate to the channel and improving the gate control capability of the device.

[0026] Please continue to refer to Figure 1 The thickness of the GaN channel layer 5 ranges from 300 nm to 800 nm.

[0027] Here, the InN cap layer 7 is used to reduce the contact resistance, and the thickness of the InN cap layer 7 ranges from 1 nm to 5 nm. Since it is not easy to make a good ohmic contact with AlN, the use of the InN cap layer 7 with a smaller difference in work function with the metal can achieve a lower contact resistance.

[0028] Here, the material of the source metal layer 8 and the drain metal layer 9 includes a stacked metal of Ti, Al, Ni, and Au, wherein the thickness of the Ti metal is about 15 nm, the thickness of the Al metal is about 85 nm, the thickness of the Ni metal is about 30 nm, and the thickness of the Au metal is about 40 nm. Also, the material of the gate metal layer 10 includes a stacked metal of Ni and Au, wherein the thickness of the Ni metal is about 30 nm, and the thickness of the Au metal is about 100 nm.

[0029] Corresponding to the nitride enhanced field effect transistor based on the P buried layer proposed in the embodiment of the present invention, the embodiment of the present invention also provides a method for preparing the nitride enhanced field effect transistor based on the P buried layer. Figure 2 Schematic diagram of the preparation process of a nitride enhanced field effect transistor based on a P buried layer provided by an embodiment of the present invention. It should be noted that: Figure 2 The figure includes 9 small figures, and the direction of the arrows represents the preparation order of the device. In addition, for the sake of simplicity and to facilitate clear identification of the newly added parts, the components that have appeared in the previous small figures in each small figure are not numbered, and only the newly added components in the current small figure are numbered.

[0030] Specifically, the preparation method comprises:

[0031] Step 1: First, clean the sapphire substrate layer 1 to remove impurities and contaminants on the surface. Immerse the substrate in an acetone solution, then perform ultrasonic cleaning, then wash away the acetone with anhydrous ethanol and blow dry to remove organic impurities, and then treat with an acidic or alkaline solution to remove inorganic impurities. The cleaned substrate is heat treated in a high temperature (1000℃~1200℃) hydrogen (H□) atmosphere, and the hydrogen flow rate can be set to 1~5L / min. This step is mainly to remove the oxide layer on the surface of the substrate, making the surface smoother and more activated, and providing a good foundation for subsequent epitaxial growth. Finally, the substrate is nitrided at a nitridation temperature of 1000~1050℃, and a mixed gas of H2 and NH3 is introduced during the process;

[0032] Step 2: Using MOCVD process, prepare AlN nucleation layer 2 on the pre-treated substrate layer 1, such as Figure 2As shown in (1), specifically, the temperature in the reaction chamber is set to 1000°C, and at a pressure of 100 Torr, 60 sccm of trimethylaluminum (TMAl) and 1500 sccm of ammonia (NH2) are used as raw materials, and 2000 sccm of hydrogen (H2) is used as a carrier gas to perform nucleation layer deposition. This nucleation layer provides nucleation centers with the same orientation as the substrate, which can convert the subsequent initial 3D growth mode of GaN into a 2D layered growth mode;

[0033] Step 3: On the AlN nucleation layer 2, a non-intentionally doped GaN buffer layer 3 is prepared by using a MOCVD process, an MBE process or a HVPE process, such as Figure 2 As shown in (2) in the figure. Taking the MOCVD process as an example, the temperature in the reaction chamber is set to 1050°C, and trimethyl gallium (TMGa) with a flow rate of 150sccm and NH3 with a flow rate of 5000sccm, and 8000sccm of hydrogen are introduced as carrier gas. Under the condition of maintaining the pressure at 100Torr, a GaN buffer layer is grown to alleviate the lattice mismatch and reduce the stress.

[0034] Step 4: Use plasma reactive ion etching technology to etch a groove of a certain depth in the center of the GaN buffer layer 3. First, spin-coat a layer of positive photoresist on the upper surface of the buffer layer, and use a mask with a specific groove pattern for photolithography. Use ultraviolet exposure to transfer the mask pattern to the photoresist. Put the exposed sample into a developer for development to form a groove pattern corresponding to the mask on the photoresist. Use inductively coupled plasma etching technology, with chlorine (Cl2) and boron trichloride (BCl2) as etching gases, with a chlorine flow rate of 30sccm~50sccm, a boron trichloride flow rate of 10sccm~20sccm, and an etching power of 300W~500W to form grooves on the buffer layer, such as Figure 2 As shown in (3);

[0035] Step 5: Prepare a P-GaN buried layer 4 at the bottom of the groove, wherein the thickness of the P-GaN buried layer 4 is less than or equal to the depth of the groove. Figure 2 As shown in (4) in the figure. Taking the MOCVD process as an example, the reaction chamber temperature is maintained at 1050°C and the pressure is 120Torr. Trimethylgallium (TMG) with a flow rate of 30sccm and ammonia (NH2) with a flow rate of 1500sccm are introduced as growth sources. At the same time, bismuth magnesium (Cp2Mg) is introduced as a doping source with a flow rate of about 3sccm. During the growth process, the gas flow rate, temperature, pressure and other parameters are precisely controlled to ensure that P-GaN grows uniformly in the groove and has good crystal quality and electrical properties.

[0036] Step 6: Prepare a GaN channel layer 5 on the GaN buffer layer 3 by using MOCVD process, MBE process or HVPE process, such as Figure 2 As shown in (5) in FIG. 1 . Taking the MOCVD process as an example, the temperature of the reaction chamber is maintained at 1050°C, the pressure is maintained at 100 Torr, a nitrogen source with a flow rate of 2500 sccm, a gallium source with a flow rate of 70 sccm, and 5000 sccm of hydrogen as a carrier gas are introduced to grow a 400nm GaN channel layer on the buffer layer;

[0037] Step 7: Prepare an AlN barrier layer 6 on the GaN channel layer 5 by using a MOCVD process, an MBE process or a HVPE process. Figure 2 As shown in (6) in the figure. Taking the MOCVD process as an example, the temperature of the reaction chamber is maintained at 1100°C, and under the condition of maintaining the pressure at 150 Torr, TMAl with a flow rate of 30 sccm and NH3 with a flow rate of 750 sccm are introduced, and the hydrogen flow rate is 1500 sccm as a carrier gas to grow the AlN barrier layer to form a heterojunction with the GaN channel layer, and form a high-concentration, high-mobility two-dimensional electron gas (2DEG) on the surface of the heterojunction;

[0038] Step 8: Prepare an InN cap layer 7 on the AlN barrier layer 6 by using a MOCVD process, an MBE process or a HVPE process. Figure 2 As shown in (7) in the figure. Taking the MOCVD process as an example, the temperature of the reaction chamber is maintained at 550°C, and under the condition of maintaining the pressure at 80 Torr, TMIn with a flow rate of 20 sccm and NH3 with a flow rate of 500 sccm are introduced, and the hydrogen flow rate is 1000 sccm as a carrier gas to grow an InN cap layer;

[0039] Step 9: Using electron beam evaporation process, a source metal layer 8 and a drain metal layer 9 are respectively prepared on both sides of the upper surface of the InN cap layer 7, and then rapid thermal annealing is performed in a nitrogen-filled environment to form source and drain contact electrodes of the device, wherein the annealing temperature is 900°C. Figure 2 As shown in (8);

[0040] Step 10: Using electron beam evaporation process, a gate metal layer 10 is prepared at the center of the upper surface of the InN cap layer 7, and then a gate contact electrode is formed by rapid thermal annealing in an oxygen-filled environment, wherein the annealing temperature is 600° C., and a nitride-enhanced field effect transistor based on a P buried layer is obtained, such as Figure 2 As shown in (9) in .

[0041] In view of the problem that the existing preparation methods increase the distance between the gate and the channel of the field effect transistor, resulting in the weakening of the electric field strength from the gate to the channel, which greatly reduces the gate control ability of the device and greatly reduces the performance of the device, the embodiment of the present invention provides a nitride enhanced field effect transistor based on a P buried layer, in which a P-GaN buried layer is locally buried at the corresponding gate position in the GaN buffer layer for depleting part of the two-dimensional electron gas in the GaN channel layer. Compared with the enhanced implementation method of the P-GaN cap layer, this setting can shorten the distance between the gate and the channel in the transistor, which is more conducive to enhancing the electric field strength from the gate to the channel and improving the gate control ability of the device. AlN is used to replace AlGaN as a barrier layer and a GaN channel layer to form an AlN / GaN heterojunction. The stronger polarization of AlN can produce a higher density of two-dimensional electron gas. In addition, an InN cap layer is used above the barrier layer to achieve a lower contact resistance by utilizing the smaller work function difference between InN and metal, which has better device performance and has great application prospects in the fields of power electronics, communications, aerospace, etc.

[0042] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A nitride enhanced field effect transistor based on a P buried layer, characterized in that: include: A substrate layer (1), an AlN nucleation layer (2), a GaN buffer layer (3), a GaN channel layer (5), an AlN barrier layer (6) and an InN cap layer (7) stacked in sequence; A groove is provided in the GaN buffer layer (3), a P-GaN buried layer (4) is prepared at the bottom of the groove, the thickness of the P-GaN buried layer (4) is equal to the depth of the groove, and the P-GaN buried layer (4) is used to locally deplete the two-dimensional electron gas in the GaN channel layer (5); A source metal layer (8), a drain metal layer (9) and a gate metal layer (10) are arranged on the InN cap layer (7) at intervals, and the gate metal layer (10) is located between the source metal layer (8) and the drain metal layer (9).

2. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The thickness of the GaN buffer layer (3) ranges from 1 μm to 2 μm, and the depth of the groove ranges from 60 nm to 200 nm.

3. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The doping element of the P-GaN buried layer (4) is Mg, and the doping concentration range is 1×10 17 cm -3 ~5×10 20 cm -3 .

4. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The thickness of the GaN channel layer (5) ranges from 300 nm to 800 nm.

5. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The thickness of the AlN barrier layer (6) ranges from 3 nm to 11 nm.

6. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The thickness of the InN cap layer (7) ranges from 1 nm to 5 nm.

7. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The thickness of the AlN nucleation layer (2) ranges from 20 nm to 100 nm.

8. The nitride enhanced field effect transistor based on the P buried layer according to claim 1, characterized in that: The materials of the source metal layer (8) and the drain metal layer (9) include a stacked metal of Ti, Al, Ni and Au, and the material of the gate metal layer (10) includes a stacked metal of Ni and Au.

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