High electron mobility transistor and preparation method thereof

Abstract

The embodiment of the invention relates to a high-electron-mobility transistor and a preparation method thereof, and the high-electron-mobility transistor comprises a substrate; the heterojunction structure is located on the substrate and comprises a channel layer and a barrier layer which are sequentially stacked in the direction away from the substrate, and a two-dimensional electron gas channel is formed in the area, close to the barrier layer, of at least part of the channel layer; the source electrode and the drain electrode are distributed on the heterojunction structure at intervals; a gate layer on the heterojunction structure and between the source electrode and the drain electrode; the RESURF structure layer is located on the heterojunction structure and comprises a first structure part adjacent to the gate layer in the direction parallel to the plane where the substrate is located and a second structure part extending from the first structure part to the direction away from the gate layer; the thickness of the part, located between the first structure part and the channel layer, of the barrier layer is smaller than that of the part, located between the second structure part and the channel layer; therefore, the RESURF structure plays a better role in the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and a method for preparing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a field effect transistor based on the high mobility characteristics of the two-dimensional electron gas (2DEG) in the heterojunction. It has high electron mobility under low temperature and low electric field, and can achieve high-speed and low-noise operation.

[0003] The RESURF (Reduced Surface Field) structure in existing HEMT devices is usually formed by etching the gate material layer (taking GaN RESURF HEMT devices as an example, the gate material layer refers to the material layer used to form the p-GaN gate). The material and position of the RESURF structure are restricted by the gate material layer and are difficult to change, making it difficult to flexibly adjust the device electric field, which ultimately limits the role of the RESURF structure in the device. Summary of the invention

[0004] In view of this, embodiments of the present application provide a high electron mobility transistor and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a high electron mobility transistor, including: substrate; a heterojunction structure located on the substrate, the heterojunction structure comprising a channel layer and a barrier layer stacked in sequence in a direction away from the substrate, a two-dimensional electron gas channel being formed in at least a portion of the channel layer in a region close to the barrier layer; A source electrode and a drain electrode are spaced and distributed on the heterojunction structure; A gate layer, located on the heterojunction structure and between the source electrode and the drain electrode; A low surface field RESURF structural layer is located on the heterojunction structure and includes a first structural portion adjacent to the gate layer in a direction parallel to the plane of the substrate and a second structural portion extending from the first structural portion in a direction away from the gate layer, wherein the thickness of the barrier layer located between the first structural portion and the channel layer is less than the thickness of the barrier layer located between the second structural portion and the channel layer.

[0006] In combination with the first aspect of the present application, in an optional embodiment, the barrier layer has a groove extending from the surface of the barrier layer away from the substrate to the interior, the first structural portion covers the inner wall of the groove, and the second structural portion is located on the surface of the barrier layer away from the substrate.

[0007] In combination with the first aspect of the present application, in an optional implementation, the RESURF structure layer is formed by an atomic layer deposition process and / or a molecular beam epitaxy process, and the thickness of the RESURF structure layer is determined by the deposition thickness in the corresponding process.

[0008] In combination with the first aspect of the present application, in an optional embodiment, the RESURF structure layer includes two first structure parts and corresponding two second structure parts, wherein one first structure part and the second structure part are located between the gate layer and the drain electrode, and the other first structure part and the second structure part are located between the gate layer and the source electrode; the gate layer is located exactly in the middle of the source electrode and the drain electrode.

[0009] In combination with the first aspect of the present application, in an optional implementation manner, the RESURF structure layer and the gate layer are made of different materials.

[0010] In combination with the first aspect of the present application, in an optional embodiment, the gate layer is a P-type material layer; the first structural portion of the RESURF structure layer is an N-type material layer; in a direction perpendicular to the plane of the substrate, the projection of the RESURF structure layer does not overlap with the projection of the gate layer.

[0011] In combination with the first aspect of the present application, in an optional implementation, the RESURF structure layer also includes a third portion covering the gate layer; the gate layer is a P-type material layer; and the third portion is a P-type material layer.

[0012] In combination with the first aspect of the present application, in an optional implementation, in a direction perpendicular to the plane where the substrate is located, a projection area of ​​the first structure portion accounts for 5% to 50% of a total projection area of ​​the first structure portion and the second structure portion.

[0013] In a second aspect, an embodiment of the present application provides a method for preparing a high electron mobility transistor, the method comprising: Providing a semiconductor material layer, the semiconductor material layer comprising a substrate and a channel layer, a barrier layer and a gate material layer sequentially stacked on the substrate; wherein the channel layer and the barrier layer form a heterojunction structure, and at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel; Performing patterning on the gate material layer to form a gate layer in a predetermined gate formation region on the heterojunction structure; Adjusting the thickness of the barrier layer in the region of the heterojunction structure adjacent to the predetermined gate formation region so that the barrier layer includes a first barrier region and a second barrier region, wherein the first barrier region is located between the gate layer and the second barrier region, and the thickness of the first barrier region is less than the thickness of the second barrier region; forming a RESURF material layer on the gate layer and the heterojunction structure; Performing patterning on the RESURF material layer to form a RESURF structure layer, wherein the RESURF structure layer at least includes a first structure portion covering the first barrier region and a second structure portion covering the second barrier region; A source electrode and a drain electrode are formed in a source electrode preset formation region and a drain electrode preset formation region on the heterojunction structure, respectively.

[0014] In conjunction with the second aspect of the present application, in an optional implementation manner, adjusting the thickness of the barrier layer in a region of the heterojunction structure that is adjacent to the gate preset formation region includes: An etching process is performed on the barrier layer to form a groove in the first barrier region of the barrier layer, so that the thickness of the first barrier region is equal to the thickness of the portion of the barrier layer located below the bottom wall of the groove and is smaller than the thickness of the second barrier region.

[0015] The high electron mobility transistor and the preparation method thereof provided in the embodiments of the present application are configured such that the RESURF structure layer is configured to include different structure portions, and the first structure portion adjacent to the gate layer is closer to the channel layer, and the thickness of the barrier layer between the two is thinner, thereby reducing the density of the two-dimensional electron gas, effectively improving the withstand voltage, and achieving a better electric field balance effect; in this way, on the basis of the original function of reducing the scattering of the two-dimensional electron gas and improving the mobility, the RESURF structure plays a better role in the device.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 Schematic diagram of the cross-sectional structure of a high electron mobility transistor in one embodiment of the present application; Figures 2 to 8 for Figure 1 A schematic diagram of the cross-sectional structure of a high electron mobility transistor during the preparation process in the illustrated embodiment; Fig. 9 is a schematic cross-sectional structure diagram of a high electron mobility transistor in another embodiment of the present application; Fig.10 is a schematic cross-sectional structure diagram of a high electron mobility transistor in another embodiment of the present application; Fig.11 A schematic diagram of a process for preparing a high electron mobility transistor provided in an embodiment of the present application; Fig.12 A schematic diagram of a cross-sectional structure of a high electron mobility transistor in the related art; Figure 13 to Figure 14 for Fig.12 A schematic diagram of the cross-sectional structure of a high electron mobility transistor during the preparation process in the related art is shown.

[0018] Description of reference numerals: 100, substrate; 110, nucleation layer; 120, buffer layer; 130, heterojunction structure; 131, channel layer; 132, barrier layer; 133, two-dimensional electron gas channel; 1320, groove; 140, gate layer; 140', gate material layer; 150, RESURF structure layer; 150', RESURF material layer; 151, first structure part; 152, second structure part; 161, source ohmic contact layer; 162, drain ohmic contact layer; 171, source electrode; 172, drain electrode; 173, gate electrode; 180, dielectric layer. DETAILED DESCRIPTION

[0019] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0020] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0021] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0022] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0023] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0024] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0026] The present application embodiment provides a high electron mobility transistor, please refer to Figure 1 , Fig. 9 and Fig.10 The high electron mobility transistor comprises: a substrate 100; a heterojunction structure 130 located on the substrate 100, the heterojunction structure 130 comprising a channel layer 131 and a barrier layer 132 stacked in sequence in a direction away from the substrate 100, a two-dimensional electron gas channel 133 being formed in a region of at least part of the channel layer 131 close to the barrier layer 132; a source electrode 171 and a drain electrode 172, which are spaced apart and distributed on the heterojunction structure 130; a gate layer 140, which is located on the heterojunction structure 130 and located at the source The RESURF structure layer 150 is located between the electrode 171 and the drain electrode 172; the RESURF structure layer 150 is located on the heterojunction structure 130 and includes a first structure portion 151 adjacent to the gate layer 140 in a direction parallel to the plane of the substrate 100 and a second structure portion 152 extending from the first structure portion 151 in a direction away from the gate layer 140, and the thickness of the barrier layer 132 located between the first structure portion 151 and the channel layer 131 is less than the thickness of the portion located between the second structure portion 152 and the channel layer 131.

[0027] It can be understood that the embodiment of the present application sets the RESURF structure layer 150 to include different structural parts, and the first structure part 151 adjacent to the gate layer 140 is closer to the channel layer 131, and the thickness of the barrier layer 132 between the two is thinner, so that the density of the two-dimensional electron gas is smaller, the withstand voltage is effectively improved, and the electric field balance effect is better; in this way, on the basis of the original ability to reduce the scattering of the two-dimensional electron gas and improve the mobility, the RESURF structure plays a better role in the device.

[0028] Figures 2 to 8 for Figure 1 The cross-sectional structure diagram of the high electron mobility transistor in the manufacturing process in the embodiment shown in FIG. Figures 2 to 8 A high electron mobility transistor and its beneficial effects in one embodiment of the present application are further described in detail.

[0029] First, please refer to Figure 2 A semiconductor material layer is provided, the semiconductor material layer comprising a substrate 100 and a nucleation layer 110 , a buffer layer 120 , a channel layer 131 , a barrier layer 132 and a gate material layer 140 ′ sequentially stacked on the substrate 100 .

[0030] The material of the substrate 100 may be any suitable material known to those skilled in the art, such as a silicon (Si) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

[0031] The substrate 100 may include an upper surface for forming a HEMT device and a lower surface opposite to the upper surface. Ignoring the flatness of the upper and lower surfaces, the plane where the upper and lower surfaces of the substrate 100 are located, or strictly speaking, the center plane of the upper and lower surfaces, is defined as the plane where the substrate 100 is located; the direction parallel to the plane where the substrate 100 is located is the direction along the plane of the substrate 100. The direction perpendicular to the plane where the substrate 100 is located can also be called the thickness direction of the substrate 100, which is the stacking direction of various material layers deposited on the substrate 100 later, or the height direction of the device.

[0032] The substrate 100 may specifically be a growth substrate, and the heterojunction structure 130 may be an epitaxial layer formed on the growth substrate by using an epitaxial growth process.

[0033] In order to make the channel layer 131 have better crystal quality, a nucleation layer 110 and a buffer layer 120 may be formed between the substrate 100 and the heterojunction structure 130 (specifically, the substrate 100 and the channel layer 131); wherein the nucleation layer 110 is located between the substrate 100 and the buffer layer 120. In addition, the substrate 100 may also include other epitaxial layers, which are not specifically limited in the present application.

[0034] The material of the channel layer 131 may be an N-group alloy material, including but not limited to GaN, AlGaN, InGaN, InAlGaN, InAlScN, AlScN, InScN, etc. Further, the channel layer 131 may be an undoped material layer (e.g., an undoped GaN layer), so that at least the portion of the channel layer 131 below the two-dimensional electron gas presents a high resistance.

[0035] The material of the barrier layer 132 includes any material that can form a two-dimensional electron gas channel with the channel layer 131. Specifically, the material of the barrier layer 132 can also be an N-group alloy material, such as a gallium nitride-based alloy, specifically, for example, one or more of AlGaN, AlScN, InAlGaN and the like. Further, the material of the barrier layer 132 can be an undoped material (e.g., an undoped AlGaN layer); or, the barrier layer 132 can also be an N-doped material layer (e.g., an N-type doped AlGaN layer), so as to facilitate inducing a higher density of two-dimensional electron gas.

[0036] As an optional specific implementation, the material of the channel layer 131 may include gallium nitride; the material of the barrier layer 132 includes a gallium nitride-based alloy, specifically aluminum gallium nitride.

[0037] A two-dimensional electron gas channel 133 is formed in at least a portion of the channel layer 131 in a region close to the barrier layer 132. Specifically, the band gap width of the barrier layer 132 is greater than the band gap width of the channel layer 131, so that electrons in the wide-gap barrier layer 132 and electrons on the surface of the barrier layer 132 overflow and move to the interface of the channel layer 131 close to the barrier layer 132 and are confined in a potential well formed at the interface, thereby forming a two-dimensional electron gas (2DEG).

[0038] The gate material layer 140' may be a P-type gate material layer. Figure 1 As shown, after the gate material layer 140' is etched into the gate layer 140, the two-dimensional electron gas channel 133 below the gate layer 140 is depleted and serves as the channel region of the HEMT device. Further, the material of the gate material layer 140' may include a P-type oxide or a P-type nitride. In a specific example, the material of the gate material layer 140' may include one or more of nickel oxide, copper oxide, tungsten oxide, and vanadium oxide; or, the material of the gate material layer 140' may include p-type doped GaN, etc.

[0039] The process of forming the gate material layer 140' may include a deposition process. Figure 1 The gate layer 140 is shown as not being in direct contact with the channel layer 131 (for example, being located on the barrier layer 132), but the present application does not exclude the gate layer 140 being in direct contact with the channel layer 131. Those skilled in the art can adopt various modifications to arrange the gate material layer 140' without departing from the improved concept of the present application, and finally form the gate layer 140 required by the design.

[0040] Next, please refer to Figure 3 , step etching is performed to define the active area of ​​the device. Specifically, for example, a patterned photoresist layer is formed on the gate material layer 140'; step etching is performed using the patterned photoresist layer as a mask to define the active area of ​​the device; and the patterned photoresist layer is removed.

[0041] Next, please refer to Figure 4 , the gate material layer 140' is patterned to form a gate layer 140 in the gate preset formation region on the heterojunction structure 130. Specifically, for example, another patterned photoresist layer is formed on the gate material layer 140', the patterned photoresist layer covers the gate preset formation region and exposes the region outside the gate preset formation region; the patterned photoresist layer is used as a mask for etching to transfer the pattern on the patterned photoresist layer to the gate material layer 140' to form the gate layer 140; and the patterned photoresist layer is removed.

[0042] It should be noted that if a HEMT device without a RESURF structure is prepared, the process up to this step is substantially the same as described above; however, for the preparation of a HEMT device with a RESURF structure, the process up to this step is substantially the same as described above. Figure 4 The corresponding steps are not the same.

[0043] Please refer to Figure 12 to Figure 14 ;in, Fig.12 A schematic diagram of a cross-sectional structure of a high electron mobility transistor in the related art; Figure 13 to Figure 14 for Fig.12 The cross-sectional structure diagram of the high electron mobility transistor in the related art during the preparation process is shown. Figure 3 The corresponding steps and the previous steps in the related art are the same as those in the embodiment of the present application; Figure 3 After the corresponding steps, please refer to Fig.13 The related technology firstly uses a photolithography-etching process to thin the gate material layer 140' except for the gate preset formation area to the thickness of the RESURF structure layer 150; then, please refer to Fig.14 , and then a photolithography-etching process is performed to remove the gate material layer 140' except for the gate layer 140 and the RESURF structure layer 150. The above-mentioned photolithography-etching process is substantially the same as the step etching and the process of patterning the gate material layer 140' described above, and will not be described in detail here. Next, the dielectric layer 180 is deposited, and the source electrode 171, the drain electrode 172, the gate electrode 173 and other structures that penetrate the dielectric layer 180 and are in conductive contact with the corresponding area are formed, and finally the following is formed: Fig.12 The structure shown.

[0044] In the related art, the RESURF structure layer 150 is formed by etching the gate material layer 140'; specifically, by etching the gate material layer 140', a gate layer 140 located at a high step and a RESURF structure layer 150 located at a low step are formed. Considering that the RESURF structure layer 150 and the gate layer 140 are made of the same material, they also play a role in reducing the density of the two-dimensional electron gas. Therefore, it is usually necessary to make the RESURF structure layer 150 thin enough to reduce the impact on the density of the two-dimensional electron gas. However, due to the uncontrollability of the etching process, the thickness uniformity of the RESURF structure layer 150 will be affected by the thickness of the previous layer and the condition of the etching equipment. The step thickness between the RESURF structure layer 150 and the gate layer 140 has great instability. The film layer of the RESURF structure layer 150 finally formed has the risk of poor thickness uniformity, which cannot bring the performance of the RESURF HEMT device into full play and poses a huge challenge to the consistency of the device. In addition, the RESURF structure layer 150 and the gate layer 140 are both part of the gate material layer 140', so it is difficult to achieve separate adjustments to the material and position of the RESURF structure layer 150, and thus it is difficult to achieve flexible adjustment of the device electric field.

[0045] For the preparation steps of the high electron mobility transistor in the embodiment of the present application, please continue to refer to Figure 5 , the thickness of the barrier layer 132 in the region of the heterojunction structure 130 adjacent to the gate preset formation region is adjusted so that the barrier layer 132 includes a first barrier region (such as Figure 5 The second barrier region (shown as the dotted ellipse box) Figure 5 As shown in the rectangular dotted box in the middle, the first barrier region is located between the gate layer 140 and the second barrier region, and the thickness of the first barrier region is less than the thickness of the second barrier region.

[0046] As an optional specific implementation, the thickness of the barrier layer 132 in the region adjacent to the gate preset formation region in the heterojunction structure 130 can be adjusted by the following steps: performing an etching process on the barrier layer 132 to form a groove 1320 in the first barrier region of the barrier layer 132, so that the thickness of the first barrier region is equal to the thickness of the portion of the barrier layer 132 located below the bottom wall of the groove 1320, and is thus less than the thickness of the second barrier region. It can be understood that this specific implementation is to adjust the thickness of the barrier layer 132 by a photolithography-etching process, and specifically by etching the groove 1320 next to the gate layer 140. However, the present application is not limited thereto, and any process that can realize the first barrier region and the second barrier region can be applied here, for example, the thickness of the second barrier region can also be increased by deposition.

[0047] In some embodiments, in the high electron mobility transistor finally formed, the thickness of the second barrier region of the barrier layer 132 is equal to the thickness of the barrier layer 132 located between the source electrode 171 and the channel layer 131 and equal to the thickness of the barrier layer 132 located between the drain electrode 172 and the channel layer 131. Thus, the thickness of the first barrier region is also less than the thickness of the barrier layer 132 located between the source electrode 171 and the channel layer 131 and / or less than the thickness of the barrier layer 132 located between the drain electrode 172 and the channel layer 131.

[0048] In some embodiments, in the high electron mobility transistor finally formed, the thickness of the second barrier region of the barrier layer 132 is equal to the thickness of the barrier layer 132 located between the gate electrode 173 and the channel layer 131. Thus, the thickness of the first barrier region is also less than the thickness of the barrier layer 132 located between the gate electrode 173 and the channel layer 131.

[0049] In some embodiments, the first barrier region and the second barrier region may both be located between the gate layer 140 and the drain electrode 172 ; the groove 1320 is adjacent to the gate layer 140 on a side of the gate layer 140 facing the drain electrode 172 .

[0050] Next, please refer to Figure 6 A RESURF material layer 150 ′ is formed on the gate layer 140 and the heterojunction structure 130 .

[0051] The RESURF material layer 150' is formed by a deposition process. Specifically, optionally, the RESURF material layer 150' is formed by an atomic layer deposition (ALD) process and / or a molecular beam epitaxy (MBE) process, so that the thickness of the RESURF structure layer 150 is determined by the deposition thickness in the corresponding process. In this way, the film thickness of the formed RESURF material layer 150' (RESURF structure layer 150) has a high consistency (the precision of the ALD process can be controlled at the nanometer level, and the precision of the MBE process can be controlled at the atomic level), so that the electric field distribution under the gate layer 140 is more uniform, the interface state density is smaller, and the quality is more reliable; the dynamic resistance characteristics of the device are improved, and ultimately the device performance and reliability are improved.

[0052] In addition, since the RESURF material layer 150' and the gate material layer 140' are formed in different processes, correspondingly, different materials can be used for the RESURF structure layer 150 and the gate layer 140. The position of the RESURF structure layer 150 can be adjusted according to design requirements without being restricted by the gate layer 140, thereby achieving flexible adjustment of the device electric field.

[0053] As an optional specific implementation, the materials of the RESURF structure layer 150 and the gate layer 140 are different. For example, the material of the gate layer 140 is selected from deep energy level materials, such as tungsten oxide and / or vanadium oxide, which are materials with large work functions, so that the gate layer 140 can deplete the two-dimensional electron gas below more thoroughly. The material of the RESURF structure layer 150 can be selected from conventional P-GaN, P-type oxide materials, N-type materials, or high dielectric constant, high bandgap width materials, etc.

[0054] In addition to the ALD process and the MBE process, the embodiments of the present application may also adopt a CVD process, a PVD process, or one or more composite processes including the ALD process, the MBE process, the CVD process, and the PVD process.

[0055] Next, please refer to Figure 7 The RESURF material layer 150 ′ is patterned to form a RESURF structure layer 150 . The RESURF structure layer 150 at least includes a first structure portion 151 covering the first barrier region and a second structure portion 152 covering the second barrier region.

[0056] The patterning of the RESURF material layer 150 ′ is achieved, for example, by a photolithography-etching process, which will not be described in detail herein.

[0057] In a specific embodiment including the groove 1320 , the first structure portion 151 covers the inner wall of the groove 1320 , and the second structure portion 152 is located on the surface of the barrier layer 132 away from the substrate 100 .

[0058] The first structure portion 151 is adjacent to the gate layer 140 ; ​​further, the first structure portion 151 is adjacent to the gate layer 140 at a side of the gate layer 140 facing the drain electrode 172 .

[0059] In practical applications, in a direction perpendicular to the plane where the substrate 100 is located, the projection area of ​​the first structure portion 151 accounts for 5% to 50% of the total projection area of ​​the first structure portion 151 and the second structure portion 152. If the projection area accounts for less than 5%, it is difficult to adjust the thickness of the barrier layer 132 (i.e., the first barrier region) in the region adjacent to the gate preset formation region in the heterojunction structure 130; if the projection area accounts for more than 50%, it will cause too much impact on the density of the two-dimensional electron gas, which is not conducive to device performance.

[0060] Next, please refer to Figure 8 and Figure 1 A source electrode 171 and a drain electrode 172 are formed in the source electrode formation region and the drain electrode formation region on the heterojunction structure 130 , respectively.

[0061] Specifically, a dielectric layer 180 may be first formed on the heterojunction structure 130, the gate layer 140, and the RESURF structure layer 150; the material of the dielectric layer 180 may include one or more of SiO, SiON, SiN, and AlN. This embodiment is not limited to this. Then, an opening is formed in the dielectric layer 180 to expose the preset source formation region and the preset drain formation region. Next, a source ohmic contact layer 161 and a drain ohmic contact layer 162 are respectively formed in the source and drain openings, thereby reducing the contact resistance between the metal material and the semiconductor material. Finally, a metal material is filled in the source and drain openings to form a source electrode 171 and a drain electrode 172, respectively. An opening is formed in the dielectric layer 180 to expose the preset gate electrode formation region, and a metal material is filled in the opening to achieve the preparation of the gate electrode 173.

[0062] Understandably, Figures 2 to 8 and the corresponding description above, only by Figure 1 The embodiment shown is taken as an example to illustrate a feasible method for preparing the high electron mobility transistor provided in the embodiment of the present application; it is obvious that those skilled in the art can also prepare the high electron mobility transistor provided in the embodiment of the present application by other methods. In addition, it is obvious that the preparation of the high electron mobility transistor provided in other embodiments of the present application can also be achieved by simple process adjustment, for example, Fig. 9 and Fig.10 The embodiment shown.

[0063] Please refer to Fig. 9 In another embodiment, the RESURF structure layer 150 includes two first structure parts (151 on the left side of the figure and 151 on the right side of the figure) and two corresponding second structure parts (152 on the left side of the figure and 152 on the right side of the figure), wherein one first structure part 151 and the second structure part 152 are located between the gate layer 140 and the drain electrode 172, and the other first structure part 151 and the second structure part 152 are located between the gate layer 140 and the source electrode 171; the gate layer 140 is located in the middle of the source electrode 171 and the drain electrode 172. In this way, a RESURF structure of a bidirectional HEMT device can be realized to improve the device performance. It can be understood that although the comparison Fig. 9 The source electrode 171 and the drain electrode 172 are described, but in the bidirectional HEMT device, the functions of the source electrode 171 and the drain electrode 172 may be interchanged.

[0064] The sizes and materials of the two first structural parts may be the same or different; correspondingly, the sizes and materials of the two second structural parts may be the same or different.

[0065] Please refer to Figure 1 or Fig. 9In some embodiments, the RESURF structure layer 150 further includes a third portion covering the gate layer 140; the gate layer 140 is a P-type material layer; and the third portion is a P-type material layer. Thus, the gate layer 140 is covered by the third portion of the RESURF structure layer 150, the thickness of the gate layer 140 is increased, and both are P-type material layers (the specific materials may be the same or different), thus helping to deplete the two-dimensional electron gas in the lower region and enhance the gate control capability of the device.

[0066] Please refer to Fig.10 In some embodiments, the gate layer 140 is a P-type material layer; the first structure portion 151 of the RESURF structure layer 150 is an N-type material layer; in the direction perpendicular to the plane where the substrate 100 is located, the projection of the RESURF structure layer 150 does not overlap with the projection of the gate layer 140. In this way, the reverse adjustment of the two-dimensional electron gas density in the area below the first structure portion 151 can be achieved. Specifically, since the thickness of the barrier layer 132 between the first structure portion 151 and the channel layer 131 is thinner, the density of the two-dimensional electron gas is smaller, and the use of the N-type material layer can increase the two-dimensional electron gas density, further achieving the reverse fine adjustment of the two-dimensional electron gas density, balancing the relationship between the withstand voltage and the influence of the two-dimensional electron gas density, and achieving flexible adjustment according to design requirements.

[0067] Optionally, the material of the first structure portion 151 is, for example, N-type gallium oxide.

[0068] Optionally, the material of the second structure portion 152 may also be an N-type material layer; further, the entire RESURF structure layer 150 may be an N-type material layer; of course, the present application does not exclude the situation where the RESURF structure layer 150 is composed of sub-parts of different materials.

[0069] On this basis, the present application also provides a method for preparing a high electron mobility transistor, please refer to Fig.11 , the method comprising: Step S01, providing a semiconductor material layer, the semiconductor material layer comprising a substrate and a channel layer, a barrier layer and a gate material layer sequentially stacked on the substrate; wherein the channel layer and the barrier layer form a heterojunction structure, and at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel; Step S02, patterning the gate material layer to form a gate layer in a predetermined gate formation region on the heterojunction structure; Step S03, adjusting the thickness of the barrier layer in the region of the heterojunction structure adjacent to the predetermined gate formation region, so that the barrier layer includes a first barrier region and a second barrier region, the first barrier region is located between the gate layer and the second barrier region, and the thickness of the first barrier region is less than the thickness of the second barrier region; Step S04, forming a RESURF material layer on the gate layer and the heterojunction structure; Step S05, patterning the RESURF material layer to form a RESURF structure layer, wherein the RESURF structure layer at least includes a first structure portion covering the first barrier region and a second structure portion covering the second barrier region; Step S06, forming a source electrode and a drain electrode in the source electrode predetermined formation region and the drain electrode predetermined formation region on the heterojunction structure respectively.

[0070] It can be understood that the preparation method provided in the embodiment of the present application is a method for preparing the high electron mobility transistor in any of the aforementioned embodiments. Therefore, the beneficial effects of the high electron mobility transistor in any of the aforementioned embodiments are also applicable to the preparation method.

[0071] As an optional specific implementation, the thickness of the barrier layer in the area adjacent to the preset gate formation area in the heterojunction structure is adjusted, including: performing an etching process on the barrier layer to form a groove in the first barrier region of the barrier layer, so that the thickness of the first barrier region is equal to the thickness of the portion of the barrier layer located below the bottom wall of the groove, and is further less than the thickness of the second barrier region.

[0072] It is understandable that, since the preparation steps of the high electron mobility transistor have been described above, they will not be described in detail here. The technical features in the technical solutions described in the embodiments can be combined arbitrarily if there is no conflict.

[0073] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A high electron mobility transistor, characterized in that: include: substrate; a heterojunction structure located on the substrate, the heterojunction structure comprising a channel layer and a barrier layer stacked in sequence in a direction away from the substrate, a two-dimensional electron gas channel being formed in at least a portion of the channel layer in a region close to the barrier layer; A source electrode and a drain electrode are spaced and distributed on the heterojunction structure; A gate layer, located on the heterojunction structure and between the source electrode and the drain electrode; A low surface field RESURF structural layer is located on the heterojunction structure and includes a first structural portion adjacent to the gate layer in a direction parallel to the plane of the substrate and a second structural portion extending from the first structural portion in a direction away from the gate layer, wherein the thickness of the barrier layer located between the first structural portion and the channel layer is less than the thickness of the barrier layer located between the second structural portion and the channel layer.

2. The high electron mobility transistor according to claim 1, characterized in that: The barrier layer has a groove extending from the surface of the barrier layer away from the substrate to the inside, the first structure portion covers the inner wall of the groove, and the second structure portion is located on the surface of the barrier layer away from the substrate.

3. The high electron mobility transistor according to claim 1, characterized in that: The RESURF structure layer is formed by an atomic layer deposition process and / or a molecular beam epitaxy process, and the thickness of the RESURF structure layer is determined by the deposition thickness in the corresponding process.

4. The high electron mobility transistor according to claim 1, characterized in that: The RESURF structure layer includes two first structure parts and two corresponding second structure parts, wherein one first structure part and the second structure part are located between the gate layer and the drain electrode, and the other first structure part and the second structure part are located between the gate layer and the source electrode; the gate layer is located in the middle of the source electrode and the drain electrode.

5. The high electron mobility transistor according to claim 1, characterized in that: The RESURF structure layer and the gate layer are made of different materials.

6. The high electron mobility transistor according to claim 5, characterized in that: The gate layer is a P-type material layer; the first structure portion of the RESURF structure layer is an N-type material layer; in a direction perpendicular to the plane where the substrate is located, a projection of the RESURF structure layer does not overlap with a projection of the gate layer.

7. The high electron mobility transistor according to claim 1, characterized in that: The RESURF structure layer also includes a third portion covering the gate layer; the gate layer is a P-type material layer; and the third portion is a P-type material layer.

8. The high electron mobility transistor according to any one of claims 1 to 7, characterized in that: In a direction perpendicular to the plane where the substrate is located, a projection area of ​​the first structure portion accounts for 5% to 50% of a total projection area of ​​the first structure portion and the second structure portion.

9. A method for preparing a high electron mobility transistor, characterized in that: The method comprises: Providing a semiconductor material layer, the semiconductor material layer comprising a substrate and a channel layer, a barrier layer and a gate material layer sequentially stacked on the substrate; wherein the channel layer and the barrier layer form a heterojunction structure, and at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel; Performing patterning on the gate material layer to form a gate layer in a predetermined gate formation region on the heterojunction structure; Adjusting the thickness of the barrier layer in the region of the heterojunction structure adjacent to the predetermined gate formation region so that the barrier layer includes a first barrier region and a second barrier region, wherein the first barrier region is located between the gate layer and the second barrier region, and the thickness of the first barrier region is less than the thickness of the second barrier region; forming a RESURF material layer on the gate layer and the heterojunction structure; Performing patterning on the RESURF material layer to form a RESURF structure layer, wherein the RESURF structure layer at least includes a first structure portion covering the first barrier region and a second structure portion covering the second barrier region; A source electrode and a drain electrode are formed in a source electrode preset formation region and a drain electrode preset formation region on the heterojunction structure, respectively.

10. The method for preparing a high electron mobility transistor according to claim 9, characterized in that: Adjusting the thickness of the barrier layer in a region of the heterojunction structure that is adjacent to a predetermined gate formation region includes: An etching process is performed on the barrier layer to form a groove in the first barrier region of the barrier layer, so that the thickness of the first barrier region is equal to the thickness of the portion of the barrier layer located below the bottom wall of the groove and is smaller than the thickness of the second barrier region.

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