A VDMOS device

Abstract

The application provides a VDMOS device, comprising a cell, the cell comprising: a substrate and a drain arranged on the back side of the substrate; an epitaxial layer arranged on the substrate; two sources arranged at intervals in the epitaxial layer, the sources being grounded; a channel region formed below the sources, the channel region being grounded; a gate dielectric layer formed on the epitaxial layer, covering the part between the two sources and partially overlapping the two sources respectively; a combined gate formed on the gate dielectric layer, covering the part between the two sources and partially overlapping the two sources respectively, the combined gate comprising a first gate arranged from top to bottom, a combined gate isolation layer and a floating gate; the first gate, the combined gate isolation layer and the floating gate form a first capacitor, and the floating gate, the gate dielectric layer and the channel region form a second capacitor; the gate voltage is divided by the first capacitor and the second capacitor so that the potential of the floating gate is lower than the gate voltage. The embodiments of the application solve the technical problem of low short-circuit resistance of the conventional SiC substrate VDMOS.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a VDMOS device. Background Technology

[0002] Silicon carbide (SiC) is a third-generation wide-bandgap semiconductor with a bandgap of 3.2 eV, which is much larger than the 1.1 eV of traditional silicon. Its critical breakdown field strength is an order of magnitude higher than that of silicon, giving it the advantage of high temperature and high pressure resistance. At the same time, its fast saturation drift speed makes it suitable for manufacturing high-temperature and high-pressure power semiconductor devices with fast response, such as VDMOS (Vertical Double-diffused MOSFET) and JFET (Junction Field-Effect Transistor).

[0003] A vertically double-diffused MOSFET (VDMOS) is a vertical semiconductor device that combines the advantages of both bipolar transistors and ordinary MOS devices. The gate and source of a VDMOS are located on the device surface, while the drain is located on the back side. Its operating principle involves the gate controlling the channel's on / off state, allowing current to flow from the drain through an inverted channel on the device surface to the source. The conduction channel is located on the device surface. VDMOS is an ideal power device for both switching and linear applications, primarily used in electronic switches, adapters, power drives, and industrial control.

[0004] Figure 1 This is a schematic diagram of the SiC VDMOS structure in existing patent application CN116598356A. When a voltage is applied to Poly1-7, the capacitance effect of the metal oxide semiconductor is utilized, and positive charges are attracted near the surface of Pwell 1-3 to form an inversion channel on the surface, realizing the conduction from drain 1-10 to source 1-9. The current first flows vertically from drain 1-10 to the interface between the surface of substrate 1-6 and the epitaxial layer 1-5 above the substrate, and then flows into source 1-9 through the inversion channel 1-1 on the SiC surface.

[0005] In the field of power electronics, SiC MOSFETs are gradually replacing silicon-based IGBTs due to their superior characteristics such as high voltage withstand, low on-resistance, and low switching losses. Because SiC materials can operate at higher electric fields, the gate oxide layer 1-0 of SiC MOSFETs will face harsher operating environments. Non-clamped inductive switching tests and short-circuit tests are important experiments for characterizing the reliability of power devices.

[0006] Due to human error and machine malfunction, power devices may sometimes operate under short-circuit faults. Normally, once a short circuit is detected, the external protection circuit will trigger the protection mechanism to immediately shut down the circuit.

[0007] However, within the response time of the protection circuit, power devices are required to withstand a short circuit for a certain period of time; this is called short-circuit withstand capability. Although a short circuit lasts only on the order of microseconds, a very high density of current flows through the power device instantaneously, generating a large amount of heat and ultimately causing thermal failure. There are many factors that can cause short circuits, such as device failure in a half-bridge circuit, false gate turn-on signals, and aging of the insulation. Most domestic and international research focuses on exploring the short-circuit withstand capability of devices from the perspective of failure phenomena and external circuit protection; therefore, improving the short-circuit withstand capability of the devices themselves is also of great significance.

[0008] SiC has a wider bandgap, so the drift region concentration of SiC power devices can be higher than that of silicon-based power devices. SiC chips are also smaller and have higher current handling capabilities. Experimental tests show that the short-circuit withstand capability of Si IGBTs (one type of power device) can reach over 10 microseconds. In contrast, the short-circuit withstand capability of SiC MOSFETs (another type of power device) is significantly lower than that of Si IGBTs due to lower gate oxide reliability and thermal failure caused by excessive current density leading to overheating.

[0009] Most mainstream device manufacturers on the market have provided short-circuit withstand times for Si IGBTs, with most IGBT devices achieving a short-circuit withstand time of 10 microseconds under certain stress. However, for SiC MOSFETs, only Infineon has offered a short-circuit withstand time commitment of 3 microseconds.

[0010] Therefore, the low short-circuit withstand capability of traditional VDMOS on existing SiC substrates is a technical problem that urgently needs to be solved by those skilled in the art.

[0011] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0012] This application provides a VDMOS device to solve the technical problem of low short-circuit withstand capability of traditional SiC substrate VDMOS.

[0013] This application provides a VDMOS device, including a cell, wherein the cell includes:

[0014] A substrate and a drain electrode disposed on the back side of the substrate;

[0015] An epitaxial layer is located on the substrate;

[0016] Two sources are disposed at a distance within the epitaxial layer, and the sources are grounded.

[0017] A channel region is formed below the source electrode, and the channel region is grounded;

[0018] A gate dielectric layer is formed on top of the epitaxial layer, covering the portion between the two sources and overlapping the portions of the two sources respectively;

[0019] A combined gate is formed on a gate dielectric layer, covering the portion between the two sources and overlapping the portions of the two sources respectively. The combined gate includes a first gate, a combined gate isolation layer, and a floating gate arranged from top to bottom.

[0020] The combined gate isolation layer isolates the first gate and the floating gate, such that the first gate, the combined gate isolation layer and the floating gate form a first capacitor, and the floating gate, the gate dielectric layer and the channel region form a second capacitor; the external gate voltage is divided by the first capacitor and the second capacitor, so that the potential of the floating gate is lower than the gate voltage, and the potential of the floating gate controls the opening and closing of the channel region.

[0021] The embodiments of this application, by adopting the above technical solutions, have the following technical effects:

[0022] The gate voltage does not directly control the channel region, but rather controls the floating gate and thus the channel region through electric field coupling. This can improve the protection of the gate (i.e., the combined gate) and enhance the short-circuit withstand capability under short-circuit conditions.

[0023] The floating gate is controlled by electric field coupling as follows:

[0024] A first gate, a combined gate isolation layer, and a floating gate form a first capacitor; a floating gate, a gate dielectric layer, and a channel region form a second capacitor. The first and second capacitors form a structure of two capacitors connected in series. The characteristic of a series capacitor structure is that the electric field within the same dielectric is the same, so the electric field between the floating gate and the channel region is controlled by electric field coupling.

[0025] The protection formed for the gate (i.e., the combined gate) is also for this reason, because the electric field on the gate dielectric layer is coupled there, and there is a floating gate as a transition layer in between.

[0026] In a combined gate configuration, the voltage between the floating gate and the channel region truly determines the current. Changes in the electric field of the channel region affect the potential of the floating gate. With a high drain voltage, the channel's turn-on capability decreases, thus reducing the on-state current (i.e., reducing the short-circuit current). Since short-circuit power dissipation equals short-circuit current multiplied by short-circuit voltage, this reduction in short-circuit power dissipation lengthens the time it takes for the device to reach its failure temperature, increasing the short-circuit time.

[0027] When the VDMOS device in this embodiment is working normally:

[0028] The device has a low on-resistance, resulting in a large current, typically ranging from one hundred to several hundred amperes.

[0029] The VDMOS device in this embodiment of the application is in a short-circuit state:

[0030] The on-resistance of the device is relatively large, resulting in a small current, only a few amperes. Typical devices can only withstand a large current generated by a short circuit of less than 2 μs. However, the VDMOS device in the embodiments of this application has a combined gate, which results in a smaller short-circuit current, allowing the VDMOS device to withstand larger currents for a longer period of time, i.e., a longer short-circuit withstand capability. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0032] Figure 1 A schematic diagram of the SiC VDMOS structure in existing patent application CN116598356A;

[0033] Figure 2 This is a schematic diagram of a VDMOS device according to an embodiment of this application;

[0034] Figure 3 This is a simulation diagram of the VDMOS device according to an embodiment of this application;

[0035] Figure 4 The graphs show the drain output voltage Vd and drain current Id of the VDMOS device of this application and the SiC VDMOS of CN116598356A in the short-circuit state.

[0036] Figure label:

[0037] In the background technology:

[0038] Gate oxide layer 1-0, channel 1-1, N+ region 1-2, P-well 1-3, P+ region 1-4, epitaxial layer 1-5

[0039] Substrate 1-6, Poly 1-7, Source 1-9, Drain 1-10;

[0040] In this application:

[0041] First gate 1, combined gate isolation layer 3, floating gate 2, gate dielectric layer 4.

[0042] 11. Channel contact region, 12. Epitaxial layer, 13. Substrate, 14. Channel region, 15. Source electrode, 16. Source metal. Detailed Implementation

[0043] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0044] Example 1

[0045] like Figure 2 As shown, the VDMOS device in this embodiment includes cells, wherein the cells include:

[0046] Substrate 13 and drain electrode disposed on the back side of substrate 13;

[0047] Epitaxial layer 12 is located on the substrate 13;

[0048] Two sources 15 are disposed at a distance within the epitaxial layer 12, and the sources 15 are grounded.

[0049] The channel region 14 is formed below the source electrode 15, and the channel region is grounded;

[0050] Gate dielectric layer 4 is formed on the epitaxial layer 12, covering the portion between the two sources and overlapping the portions of the two sources respectively;

[0051] A combined gate is formed on the gate dielectric layer 4, covering the portion between the two sources and overlapping the portions of the two sources respectively. The combined gate includes a first gate 1, a combined gate isolation layer 3, and a floating gate 2 arranged from top to bottom.

[0052] In this configuration, the combined gate isolation layer isolates the first gate 1 and the floating gate 2. The first gate is connected to an external gate voltage, allowing the external gate voltage to directly control the first gate 1. The floating gate 2 is not connected to an external voltage, allowing the potential of the first gate 1 to couple to the floating gate 2. The potential of the floating gate 2 controls the opening and closing of the channel region 14. Specifically, the combined gate isolation layer 3 isolates the first gate 1 and the floating gate 2, forming a first capacitor with the first gate 1, the combined gate isolation layer 3, and the floating gate 2. The floating gate 2, the gate dielectric layer 4, and the channel region 14 form a second capacitor. The external gate voltage is divided by the first and second capacitors, causing the potential of the floating gate 2 to be lower than the gate voltage, and the potential of the floating gate 2 controls the opening and closing of the channel region 14.

[0053] In the VDMOS device of this embodiment, the source 15 is grounded, the drain voltage (typically a high voltage of several hundred volts) is connected to the drain, and the first gate 1 is connected to the gate voltage (typically a low voltage of a few volts), meaning the gate voltage directly controls the first gate 1. Since the floating gate 2 is not connected to an external voltage, the potential of the floating gate 2 is coupled to the floating gate 2 through the potential of the first gate 1.

[0054] The potential of the floating gate 2 obtained in this way is derived by dividing the potential at the bottom of the floating gate 2 by the voltage of the first gate 1. This technical feature is the voltage divider technique.

[0055] When two or more capacitors are connected in series with the same current flowing through them, the voltage U across each capacitor is determined by Q = CU. In other words, the voltage U across each capacitor is inversely proportional to its capacitance C: U = Q / C. The total voltage is the sum of the voltages across all the capacitors, where Q represents the amount of charge carried by the capacitor.

[0056] Correspondingly, in the VDMOS device of this application, the first gate 1, the combined gate isolation layer 3, and the floating gate 2 form a first capacitor; the floating gate 2, the gate dielectric layer 4, and the channel region 14 form a second capacitor. The channel region 14 is grounded, making its potential zero. The first gate 1 is connected to an external gate voltage. These two capacitors are connected in series. The potential of the floating gate 2 is determined by the gate voltage being divided by the first and second capacitors. That is, the potential of the floating gate 2 is lower than the gate voltage.

[0057] In this way, the gate voltage does not directly control the channel region 14, but controls the floating gate 2 and thus the channel region 14 through electric field coupling. This can improve the protection of the gate (i.e., the combined gate) and also enhance the short-circuit withstand capability under short-circuit conditions.

[0058] The floating gate 2 is controlled by electric field coupling as follows:

[0059] The first gate 1, the combined gate isolation layer 3, and the floating gate 2 form a first capacitor; the floating gate 2, the gate dielectric layer 4, and the channel region 14 form a second capacitor. The first capacitor and the second capacitor form a structure of two capacitors connected in series. The characteristic of the capacitor series structure is that the electric field within the same dielectric is the same, so the electric field between the floating gate 2 and the channel region 14 is controlled by electric field coupling.

[0060] The protection formed on the gate (i.e., the combined gate) is also for this reason. The electric field on the gate dielectric layer 4 is coupled there, and there is a floating gate 2 in the middle as a transition layer.

[0061] In the combined gate configuration, the voltage between the floating gate 2 and the channel region 14 truly determines the current. Changes in the electric field of the channel region 14 will also change the potential of the floating gate 2. Under high drain voltage, the turn-on capability of the channel in the channel region 14 will decrease, thus reducing the on-state current (i.e., reducing the short-circuit current). Short-circuit power dissipation = short-circuit current * short-circuit voltage. Therefore, the reduction in short-circuit power dissipation lengthens the time it takes for the device to reach its failure temperature, increasing the short-circuit time.

[0062] When the VDMOS device in this embodiment is working normally:

[0063] The device has a low on-resistance, resulting in a large current, typically ranging from one hundred to several hundred amperes.

[0064] The VDMOS device in this embodiment of the application is in a short-circuit state:

[0065] The on-resistance of the device is relatively large, resulting in a small current, only a few amperes. Typical devices can only withstand a large current generated by a short circuit of less than 2 μs. However, the VDMOS device in the embodiments of this application has a combined gate, which results in a smaller short-circuit current, allowing the VDMOS device to withstand larger currents for a longer period of time, i.e., a longer short-circuit withstand capability.

[0066] like Figure 2 As shown, the side edge of the combined gate is flush with the side edge of the gate dielectric layer 4.

[0067] Alternatively, the side edge of the gate dielectric layer 4 may protrude beyond the side edge of the combined gate.

[0068] In practice, the thickness of the floating grid 2 is greater than or equal to 0.05 μm and less than or equal to 1 μm.

[0069] During implementation, such as Figure 2 As shown, the floating gate 2 is a floating gate made of polycrystalline silicon material.

[0070] Alternatively, the floating gate 2 can be a floating gate made of a conductive material such as a metal; the floating gate 2 can also be a floating gate made of a conductive material such as an alloy.

[0071] During implementation, such as Figure 2 As shown, the thickness of the combined gate isolation layer 3 is greater than or equal to 10 nm and less than or equal to 1 μm. The combined gate isolation layer 3 is a combined gate isolation layer made of a high dielectric constant material.

[0072] During implementation, such as Figure 2 As shown, the substrate is a SiC substrate.

[0073] Alternatively, the substrate can be a diamond substrate; the substrate can also be a GaN substrate.

[0074] During implementation, such as Figure 2 As shown, the width of the overlap between the combined gate and the channel region 14 is greater than or equal to 0.1 μm and less than or equal to 1 μm.

[0075] This ensures that the combined grid controls the channel region 14.

[0076] In practice, the thickness of the gate dielectric layer 4 is more than twice the thickness of the gate isolation layer 3.

[0077] During implementation, such as Figure 2 As shown, the VDMOS device also includes:

[0078] Two channel contact areas 11 are respectively connected to the opposite sides of the two channel areas 14;

[0079] A grounded source metal 16 is formed on the epitaxial layer and connects the source 15 and the channel contact region 11.

[0080] In practice, the channel region 14 covers the bottom surface of the channel contact region 11, the bottom surface of the source electrode 15, and the side surface.

[0081] Figure 3 This is a simulation diagram of a VDMOS device according to an embodiment of this application. The VDMOS device in this embodiment uses a 100A gate dielectric layer 4 (Tox2) and a 400A combined gate isolation layer 3 (Tox1).

[0082] The simulation comparison of the VDMOS device of this application and the SiC VDMOS of CN116598356A under the short-circuit state is shown in the table below:

[0083]

[0084] In the table, Vth is the threshold voltage, Rsp is the on-resistance, BV is the breakdown voltage, and Idsat is the on-current under short-circuit conditions.

[0085] The third row of the table contains the short-circuit state parameters of the VDMOS device of this application, which uses a gate dielectric layer 4 (Tox2) with a thickness of 100A and a combined gate isolation layer 3 (Tox1) with a thickness of 400A.

[0086] The second row of the table contains the short-circuit state parameters of the SiC VDMOS of CN116598356A.

[0087] As can be seen from the table above, the on-resistance Rsp of the VDMOS device in this application is close to that of the SiC VDMOS device in CN116598356A, while the short-circuit current (short-circuit Idsat) is reduced by more than half. Therefore, the short-circuit withstand capability of the VDMOS device in this application is more than double that of the SiC VDMOS device in CN116598356A.

[0088] Figure 4 The graphs show the drain output voltage Vd and drain current Id of the VDMOS device of this application and the SiC VDMOS of CN116598356A in the short-circuit state.

[0089] Figure 4 In the diagram, the horizontal axis represents the drain output voltage in volts, and the vertical axis represents the drain current in amperes. This application includes four VDMOS devices. The combined gate isolation layer 3 (Tox1) of the four VDMOS devices has thicknesses of 300 Å (angstroms), 400 Å, 500 Å, and 600 Å, respectively, and the gate dielectric layer 4 (Tox2) of the four VDMOS devices has a thickness of 100 Å.

[0090] like Figure 4 The figure shows the drain current Id and drain output voltage Vd under simulation at 400 degrees Celsius and a gate voltage Vg of 18V.

[0091] By setting the temperature to 400 degrees Celsius to simulate the damage to the device, it can be seen that the single poly (the existing SiC VDMOS of CN116598356A) has a current of 1462 amps when the drain output voltage Vd is 800 volts.

[0092] The combined gate isolation layer 3 (Tox1 is 400A) of the VDMOS device in this application is the best simulation structure. It can be seen that the drain current Id is 637 Amperes at 800 volts, which means that it is greatly reduced in the saturation region. As a result, the heat generation power of the device is also greatly reduced.

[0093] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0095] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0097] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0098] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A VDMOS device, characterized by, The cell comprises: a substrate (13) and a drain arranged on the back side of the substrate (13); an epitaxial layer (12) arranged on the substrate (13); two sources (15) arranged in the epitaxial layer (12) at intervals, the sources (15) being grounded; a channel region (14) formed below the sources (15), the channel region being grounded; a gate dielectric layer (4) formed on the epitaxial layer (12), covering the part between the two sources and partially overlapping the two sources respectively; a combined gate formed on the gate dielectric layer (4), covering the part between the two sources and partially overlapping the two sources respectively, the combined gate comprising a first gate (1), a combined gate isolation layer (3) and a floating gate (2) arranged from top to bottom; wherein the combined gate isolation layer (3) isolates the first gate (1) and the floating gate (2), so that the first gate (1), the combined gate isolation layer (3) and the floating gate (2) form a first capacitor, and the floating gate (2), the gate dielectric layer (4) and the channel region (14) form a second capacitor; an external gate voltage is divided by the first capacitor and the second capacitor so that the potential of the floating gate (2) is lower than the gate voltage, and the potential of the floating gate (2) controls the opening and closing of the channel region (14).

2. The VDMOS device of claim 1, wherein, The side edges of the combined gate and the side edges of the gate dielectric layer (4) are flush; or the side edges of the gate dielectric layer (4) protrude from the side edges of the combined gate. The thickness of the floating gate (2) ranges from greater than or equal to 0.05 μm to less than or equal to 1 μm.

3. The VDMOS device of claim 1, wherein, The floating gate (2) is a floating gate of polysilicon material; or the floating gate (2) is a floating gate of metal material; or the floating gate (2) is a floating gate of alloy material.

4. The VDMOS device of claim 1, wherein, The thickness of the combined gate isolation layer (3) ranges from greater than or equal to 10 nm to less than or equal to 1 μm, and the combined gate isolation layer (3) is a combined gate isolation layer of high dielectric constant material.

5. The VDMOS device of claim 1, wherein, The substrate is a SIC substrate; or the substrate is a substrate of diamond material; or the substrate is a substrate of GaN material.

6. The VDMOS device of claim 1, wherein, The width of the overlap between the combined gate and the channel region (14) ranges from greater than or equal to 0.1 μm to less than or equal to 1 μm.

7. The VDMOS device of claim 1, wherein, The thickness of the gate dielectric layer (4) is more than twice the thickness of the gate isolation layer (3).

8. The VDMOS device of claim 7, requiring a short circuit tolerance greater than 5 us, characterized in that, Further comprising:

9. The VDMOS device according to any one of claims 1 to 8, characterized in that, two channel contact regions (11) connected to the sides opposite to the two channel regions (14) respectively; a grounded source metal (16) formed on the epitaxial layer and connected to the sources (15) and the channel contact regions (11). The channel region (14) covers the bottom surface of the channel contact region (11), the bottom surface and the side surface of the source (15).

10. The VDMOS device of claim 9, wherein, ​

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