SiC MOSFET device integrated with double self-bias MOS

Abstract

The invention relates to a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device integrated with double self-biased MOS (Metal Oxide Semiconductor), and belongs to the technical field of The device is in a symmetrical state in structure and comprises a main MOS (Metal Oxide Semiconductor), a self-biased PMOS (P-channel Metal Oxide Semiconductor) and a self-biased NMOS (N-channel Metal Oxide Semiconductor), and the self-biased PMOS and the self-biased NMOS are integrated on two sides of the main MOS. According to the invention, by integrating the self-biased PMOS, the self-biased PMOS is turned off during forward conduction, and the P-well region is floated, so that the on resistance of the device is reduced; and under the blocking condition, the self-biased PMOS is switched on, the P-well region is clamped, and compared with a complete floating device, a gate oxide layer of the device is effectively protected. A follow current function of a third quadrant is realized by integrating the self-biased NMOS, and under the condition, the P-well is in a floating state, and the body diode cannot be conducted, so that a bipolar degradation effect is completely avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a SiC MOSFET device integrating dual self-bias MOS. Background Art

[0002] Since the beginning of the 21st century, with the vigorous development of emerging fields such as new energy, electric vehicles, and smart grids, society has a surge in demand for high-performance power electronic components, especially those that can withstand high voltage under extreme conditions, radiation resistance, and support high-frequency, low-power operation. Silicon carbide (SiC) materials, with their unique physical properties - including wide band gap, high critical breakdown electric field strength, and high electron mobility, have demonstrated excellent capabilities, taking into account the characteristics of "high withstand voltage", "low on-resistance", and "high-frequency response".

[0003] In recent years, trench SiC MOSFET has attracted extensive attention in the industry because of its compact unit design and effective weakening of the junction field effect transistor (JFET) effect. In particular, trench SiC MOSFET with excellent gate oxide stability has been successfully developed and put into practical application. However, this type of MOSFET still faces key challenges, namely the high forward voltage drop (usually about 2 to 3V) and bidirectional performance degradation caused by the parasitic body diode, which not only increases energy loss, but may also affect the overall reliability of the device.

[0004] To overcome the above difficulties, researchers often use external anti-parallel Schottky barrier diodes (SBDs) to alleviate them, but this solution leads to the expansion of the module volume and the generation of additional capacitance. Therefore, integrating a freewheeling diode in the chip has become a mainstream research direction, such as built-in SBDs, heterojunction diodes, or channel diodes. However, these solutions have their own shortcomings. For example, the reverse leakage current of built-in SBDs is too large in high temperature environments, and built-in heterojunction diodes are difficult to popularize and apply due to complex interface state problems.

[0005] At present, in traditional designs, the P-type shield layer is mostly directly connected to the source, which will increase the on-resistance of the JFET region when it is turned on. The ideal state is to keep the P-type shield layer suspended in the on mode and reliably grounded in the off state, so that the device performance can be fully utilized. If this idea is realized, it will greatly improve the technical indicators of SiC MOSFET, making SiC MOSFET have higher efficiency and lower energy consumption. Summary of the invention

[0006] In view of this, the object of the present invention is to provide a SiC MOSFET device with integrated dual self-biased MOS, wherein self-biased PMOS and NMOS are simultaneously integrated on one side of the source trench of the dual trench SiC MOSFET device, wherein the self-biased PMOS is used to realize the floating of the P-type shielding layer in the on state and the clamping in the off state; and the self-biased NMOS is used to realize reverse conduction in the third quadrant, and the P-type shielding layer is in a floating state, so that the body diode is not turned on, and the freewheeling function is realized only by relying on the self-biased NMOS, so as to completely eliminate the bipolar degeneration effect.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A SiC MOSFET device with integrated dual self-bias MOS comprises an N+ substrate region, an N-drift region located on the surface of the N+ substrate region, a main MOS located on the surface of the N-drift region, a first dual self-bias MOS and a second dual self-bias MOS located on the surface of the N-drift region and distributed on both sides of the main MOS, a source metal contact region located on the top of the device, and a drain metal contact region located at the bottom of the device.

[0009] The first dual self-bias MOS and the second dual self-bias MOS have the same structure and are symmetrically distributed. The dual self-bias MOS includes a self-bias PMOS and a self-bias NMOS.

[0010] Furthermore, the main MOS includes a first polysilicon region, a first N+ source region and a first insulating dielectric layer. The first polysilicon region is located above the N-drift region and is completely wrapped by the first insulating dielectric layer; the first N+ source region is distributed on both sides of the first polysilicon region and is separated from the first polysilicon region by the first insulating dielectric layer.

[0011] Furthermore, the first dual self-bias MOS and the second dual self-bias MOS both include a P-well region, a P+ region, a second polysilicon region, a second insulating dielectric layer, a P-base region, a second N+ source region, and a P+ drain region. The P-well region is located on the surface of the N-drift region; the P+ region is located on the upper right of the P-well region; the second polysilicon region is located above the P-well and P+ regions, and is separated from the second N+ source region, the P-base region, the N-drift region, the P-well region, and the P+ region by the second insulating dielectric layer; the P-base region is located on the surface of the N-drift region, and its left side is adjacent to the first insulating dielectric layer, and its upper side is adjacent to the first N+ source region; the second N+ source region is located on the upper right of the P-base region; the P+ drain region is located on the upper surface of the P-base region, and is adjacent to the first N+ source region.

[0012] The P-well region serves as the source of the self-biased PMOS; the second N+ source region serves as the source of the self-biased NMOS; the P+ drain region serves as the drain of the self-biased PMOS; and the second polysilicon region serves as the gate of the self-biased PMOS and the self-biased NMOS.

[0013] The P+ drain region, the second N+ source region, and the second polysilicon region are all in contact with the source metal contact region, so that the P+ drain region and the second N+ source region are respectively connected to the second polysilicon region at the same potential, thereby short-circuiting the drain and gate of the self-biased PMOS, and short-circuiting the source and gate of the self-biased NMOS. In addition, the drain of the self-biased NMOS is connected to the drain of the main MOS, and both are connected to the drain metal contact region.

[0014] Furthermore, in the lateral direction of the device, the P-well region protrudes a portion from the second insulating dielectric layer, and the protruding portion is used to enhance the conduction capability of the self-biased PMOS.

[0015] The beneficial effects of the present invention are as follows: the present invention proposes a SiC MOSFET device with integrated dual self-bias MOS, the device structure is symmetrical, has two traditional forward conducting channels, and integrates two self-bias NMOS for reverse conduction and two self-bias PMOS for controlling floating and clamping. Through the integrated dual self-bias MOS, the present invention achieves the following beneficial effects:

[0016] 1) By short-circuiting the drain and gate of the self-biased PMOS, when the potential of the self-biased PMOS drain rises, the potential of the P-well region will continue to rise until the self-biased PMOS is turned on. Thus, when the device is in the forward conduction state, the drain voltage is not large enough, the potential of the P-well region is not large enough, the self-biased PMOS is turned off, and the P-type shielding layer (i.e., the P-well region) is in a floating state; in the blocking state, the drain voltage continues to rise, the potential of the P-well region continues to rise, the self-biased PMOS is turned on, and the P-well region is in a clamped state, which can better protect the gate oxide layer than the floating P-well.

[0017] 2) By short-circuiting the source and gate of the self-biased NMOS, the source potential of the self-biased NMOS rises in the third quadrant, and the self-biased NMOS is turned on. In addition, in the third quadrant, the self-biased PMOS is in the off state, and the body diode cannot be turned on. The reverse freewheeling function can only be achieved by relying on the self-biased NMOS, so the bipolar degeneration effect can be completely eliminated.

[0018] Compared with the traditional double-trench SiC MOSFET device, the SiC MOSFET device with integrated dual self-bias MOS proposed by the present invention has a lower specific on-resistance, completely shields the bipolar degradation effect, and has no effect on the breakdown voltage; compared with a completely floating device, the present invention can better protect the gate oxide layer of the device, so that the dynamic characteristics of the device are improved.

[0019] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 A schematic diagram of the structure of a SiC MOSFET device with integrated dual self-bias MOS provided in an embodiment of the present invention;

[0022] Figure 2 for Figure 1 An equivalent circuit diagram of the device;

[0023] Figure 3 The diagram is a comparison of the conduction characteristic curves of the traditional double trench device, the new device, the new device (floating) and the new device (grounded);

[0024] Figure 4 This is a comparison of the total current density of the traditional double trench device, the new device, the new device (floating) and the new device (grounded) when they are turned on;

[0025] Figure 5 Schematic diagram of the potential change of P-well when the traditional double trench device and the new device, the new device (floating) and the new device (grounded) are turned on;

[0026] Figure 6 The PMOS integrated in the new device follows V ds The increase of , thus opening and closing the state diagram;

[0027] Figure 7 Comparison of breakdown characteristic curves of the traditional double trench device, the new device, the new device (floating) and the new device (grounded);

[0028] Figure 8 The traditional dual trench device and the new device, the new device (floating) and the new device (grounded) are compared at Vds = 800V blocking condition, the comparison diagram of the gate oxide layer electric field strength of the device;

[0029] Fig. 9 Schematic diagram of the potential change of P-well in the blocking state of the traditional double trench device and the new device, the new device (floating) and the new device (grounded);

[0030] Fig.10 The PMOS integrated in the new device follows V ds The increase of , thus opening and closing the state diagram;

[0031] Fig.11 This is a comparison of the total current density and hole current density curves of the traditional double trench device and the new device when the third quadrant is turned on;

[0032] Fig.12 This is a comparison of the total current density of the traditional dual-trench device and the new device when the third quadrant is turned on. Fig.12 a is a new type of device, Fig.12 b is a traditional device;

[0033] Fig.13 This is a comparison of the hole density of the traditional double trench device and the new device when the third quadrant is turned on. Fig.13 a is a new type of device, Fig.13 b is a traditional device;

[0034] Fig.14 The NMOS integrated inside the new device in the third quadrant follows V sd The increase of , thus opening and closing the state diagram;

[0035] Fig.15 It is a comparison diagram of gate charge characteristic curves of traditional double trench device, new device, new device (floating) and new device (grounded);

[0036] Fig.16 This is a comparison chart of the capacitance characteristic curves of the traditional dual trench device, the new device, the new device (floating) and the new device (grounded).

[0037] Figure numerals: 1-drain metal contact region, 2-N+ substrate region, 3-N-drift region, 4-right P-well region, 5-right P+ region, 6-insulating dielectric layer region of right source auxiliary gate, 7-right P-base region, 8-polysilicon region of right source auxiliary gate, 9-source metal contact region, 10-N+ source region of right self-biased NMOS, 11-P+ drain region of right self-biased PMOS, 12-N+ source region of right main MOS, 13-polysilicon region of main gate, 14-insulating dielectric layer region of main gate. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0039] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0040] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0041] like Figure 1 As shown, a SiC MOSFET device with integrated dual self-bias MOS provided by an embodiment of the present invention is divided into four parts according to the structural characteristics, namely, the dual self-bias MOS structures on the left and right sides, the main MOS structure and the basic structure. In addition, the structure of the device is symmetrical, with two traditional forward conduction channels, integrating two self-bias NMOS for reverse conduction and two self-bias PMOS for controlling floating and clamping.

[0042] The device includes: a drain metal contact region 1, an N+ substrate region 2, an N-drift region 3, a right P-well region 4, a right P+ region 5, an insulating dielectric layer region 6 of a right source auxiliary gate, a right P-base region 7, a polysilicon region 8 of a right source auxiliary gate, a source metal contact region 9, an N+ source region 10 of a right self-biased NMOS, a P+ drain region 11 of a right self-biased PMOS, an N+ source region 12 of a right main MOS, a polysilicon region 13 of a main gate, and an insulating dielectric layer region 14 of a main gate. Since the SiC MOSFET device is a symmetrical structure, the left side structure of the device is symmetrical to the right side, and will not be repeated here.

[0043] The basic structure includes a drain metal contact region 1, an N+ substrate region 2, an N-drift region 3, and a source metal contact region 9. The drain metal contact region 1 is located on the lower surface of the N+ substrate region 2; the N+ substrate layer 2 is located on the lower surface of the N-drift region 3 and the upper surface of the drain metal contact region 1, and its thickness is 3 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 2×10 19 cm -3 The N-drift region 3 is located on the upper surface of the N+ substrate region 2, wherein the thickness of the N-drift region 3 between the upper surface of the N+ substrate region 2 and the lower surface of the P-well region 4 is 10 μm, and the SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 7×10 15 cm -3 The source metal contact region 9 is located on the upper surface of the polysilicon region 8 of the right source auxiliary gate, the N+ source region 10 of the right self-biased NMOS, the P+ drain region 11 of the right self-biased PMOS, the N+ source region 12 of the right main MOS and the insulating dielectric layer region 14 of the main gate.

[0044] The dual self-biased MOS structure includes: a right P-well region 4, a right P+ region 5, an insulating dielectric layer region 6 of a right source auxiliary gate, a right P-base region 7, a polysilicon region 8 of a right source auxiliary gate, an N+ source region 10 of a right self-biased NMOS, and a P+ drain region 11 of a right self-biased PMOS.

[0045] The right P-well region 4 is located on the right side of the N-drift region 3 and on the lower surface of the insulating dielectric layer region 6 of the right source auxiliary gate. The portion of the right P-well region 4 that extends beyond the insulating dielectric layer region 6 of the right source auxiliary gate is mainly used to enhance the conduction capability of the self-biased PMOS. The width of the portion of the right P-well region 4 that extends beyond the insulating dielectric layer region 6 is the same as the extension width of the conventional double trench SiC MOSFET of 0.15 μm. The right P-well region 4 has a thickness of 0.7 μm and a total width of 0.85 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 18 cm -3The right P+ region 5 is located at the upper right of the right P-well region 4 and is adjacent to the lower surface of the insulating dielectric layer region 6 of the right source auxiliary gate. It has a thickness of 0.3 μm and a width of 0.3 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 The right P-base region 7 is located on the upper surface of the N-drift region 3 and between the insulating dielectric layer region 6 of the right source auxiliary gate and the insulating dielectric layer region 14 of the main gate. The upper surface of the right P-base region 7 is in contact with the lower surfaces of the N+ source region 10 of the right self-biased NMOS, the P+ drain region 11 of the right self-biased PMOS and the N+ source region 12 of the right main MOS. The thickness of the right P-base region 7 is 0.3 μm and the width is 0.7 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 2×10 17 cm -3 The polysilicon region 8 of the right source auxiliary gate is isolated from the N+ source region 10 of the right self-biased NMOS, the right P-base region 7, the right P-well region 4 and the right P+ region 5 through the insulating dielectric layer region 6 of the right source auxiliary gate. The upper surface of the polysilicon region 8 of the right source auxiliary gate contacts the lower surface of the source metal contact region 9. The polysilicon region 8 of the right source auxiliary gate has a thickness of 1.55μm and a width of 0.68μm, and is made of pure polysilicon. Among them, the thickness of the left side of the insulating dielectric layer region 6 of the right source auxiliary gate is 0.02μm, and the thickness of the lower side is 0.05μm, and the material is SiO2. The N+ source region 10 of the right self-biased NMOS is located at the upper right of the right P-base region 7 and the lower surface of the source metal contact region 9. The right side is the insulating dielectric layer region 6 of the right source auxiliary gate. The thickness of the N+ source region 10 of the right self-biased NMOS is 0.2μm and the width is 0.15μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 19 cm -3 The P+ drain region 11 of the right self-biased PMOS is located on the upper surface of the right P-base region 7 and the lower surface of the source metal contact region 9. The left side is the N+ source region 12 of the right main MOS. The thickness of the P+ drain region 11 of the right self-biased PMOS is 0.2μm and the width is 0.25μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 .

[0046] The main MOS structure includes: an N+ source region 12 of the right main MOS, a polysilicon region 13 of the main gate, and an insulating dielectric layer region 14 of the main gate. The N+ source region 12 of the right main MOS is located on the upper surface of the right P-base region 7 and the lower surface of the source metal contact region 9. The left side is the insulating dielectric layer region 14 of the main gate, and the right side is the P+ drain region 11 of the right self-biased PMOS. The thickness of the N+ source region 12 of the right main MOS is 0.2μm, the width is 0.3μm, and the SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 19 cm -3 The polysilicon region 13 of the main gate is wrapped by the insulating dielectric layer region 14 of the main gate. The polysilicon region 13 of the main gate has a thickness of 1.75 μm and a width of 0.6 μm, and the material is pure polysilicon. The insulating dielectric layer region 14 of the main gate has a thickness of 0.05 μm and the material is SiO2.

[0047] like Figure 2 As shown in FIG. , it is an equivalent circuit diagram of the device described in this embodiment. Figure 2 It can be seen that the new device proposed in this embodiment actually integrates dual self-biased MOS in the metal on both sides of the traditional dual trench device, and the dual self-biased MOS on each side includes self-biased PMOS and self-biased NMOS. Among them, the drain and gate of the self-biased PMOS are short-circuited, and the source is the potential of P-well, which realizes the automatic switching of the device floating and clamping. The source and gate of the self-biased NMOS are short-circuited, and the drain is the drain of the main MOS, which realizes the freewheeling function in the third quadrant and completely eliminates the bipolar degradation effect.

[0048] Figure 3 The figure shows the comparison of the conduction characteristic curves of the traditional double trench device, the new device, the new device (floating) and the new device (grounded). Figure 3 It can be seen that the conduction characteristics of the new device (floating) are the best, followed by the new device. Both the traditional double-trench device and the new device (grounded) ground the P-well, the JFET is larger, and the conduction characteristics are poor. This proves that the new device optimizes the conduction performance of the traditional double-trench device. Among them, the new device (floating) is based on the new device proposed in this embodiment, and the voltage applied to the polysilicon region of the source auxiliary gate on the left and right sides of the device is removed; the new device (grounded) is based on the new device proposed in this embodiment, and the P+ regions on the left and right sides of the device are connected to the source metal contact region 9.

[0049] Figure 4 The figure shows the total current density comparison between the conventional double trench device, the new device, the new device (floating) and the new device (grounded) when the device is turned on. Figure 4It can be seen that the current conduction path of the new device (floating) is the widest, the current conduction path of the traditional double trench device and the new device (grounded) is the narrowest, and the current conduction path of the new device is in the middle, which also confirms Figure 3 The conduction curve results.

[0050] Figure 5 The figure shows the potential change of P-well when the traditional dual-trench device and the new device, the new device (floating) and the new device (grounded) are turned on. It can be seen that the P-well potential of the traditional dual-trench device and the new device (grounded) has been maintained at around -1.4V, while the potential of the new device (floating) shows a continuous upward trend, and finally increases slowly at around 11V. This is because the increase in P-well potential causes PNP to penetrate, and the P-well holes flow into the source, and the potential increase slows down. The new device achieves floating and clamping in the form of self-biased PMOS. It can be found that the clamping voltage is lower and can more effectively protect the gate oxide layer. At V ds <V on =13.86V, the self-biased PMOS is turned off and the P-well is in a floating state. ds >V on =13.86V, the self-biased PMOS is turned on and the P-well is in a clamped state.

[0051] Figure 6 The figure shows the integrated PMOS of the new device under conduction. ds The increase of , thus indicating the opening and closing state. Figure 6 It can be seen that when V gs =15V, V ds =5V, the self-biased PMOS is turned off, when V gs =15V, V ds =15V, the self-biased PMOS turns on.

[0052] Figure 7 The figure shows the breakdown characteristic curve comparison between the traditional double trench device, the new device, the new device (floating) and the new device (grounded). Figure 7 It can be seen that the breakdown voltage of the new device (floating) is the largest, the new device (grounded) is the smallest, the traditional double trench device is close to the new device, but overall the breakdown voltages of the four devices are not much different.

[0053] Figure 8 The figure shows the conventional dual trench device, the new device, the new device (floating), and the new device (grounded) at V ds=800V blocking condition, the gate oxide layer electric field strength of the device is compared. It can be seen that the gate oxide layer electric field strength of the new device (floating) is 3.13MV / cm at this time, which exceeds its safe electric field strength and is not conducive to the long-term use of the device. The remaining three devices are all less than 3MV / cm, and all achieve protection of the gate oxide layer. This shows that the new device reduces the potential of P-well by self-biasing PMOS clamping, which better protects the gate oxide layer of the device than completely floating.

[0054] Fig. 9 The figure shows the potential change of P-well in the case of blocking of the traditional double trench device, the new device, the new device (floating) and the new device (grounded). Fig. 9 It can be seen that the P-well potential of the traditional dual-trench device and the new device (grounded) has been maintained at around -1.4V. The potential of the new device (floating) shows a continuous upward trend, eventually reaching around 20V, which is not conducive to protecting the gate oxide layer of the device. The final potential of the new device is clamped at around 1.2V, which is more conducive to protecting the gate oxide layer of the device and ensuring the long-term reliability of the device.

[0055] Fig.10 The figure shows the integrated PMOS of the new device under blocking condition. ds As V gs =0V, V ds =5V, the self-biased PMOS is turned off, when V gs =0V, V ds =15V, the self-biased PMOS is turned on to achieve the clamping function.

[0056] Fig.11 The figure shows the comparison of total current density and hole current density curves of the traditional double trench device and the new device when the third quadrant is turned on. Fig.11 It can be seen that the new device completely relies on electronic conduction to achieve continuous current, even if V sd It reaches 4V, which exceeds the conduction voltage of the SiC diode, and the hole current of the device is almost 0, indicating that the new device provided in this embodiment completely eliminates the bipolar degradation effect. This is because in the third quadrant, the self-biased PMOS is in the off state, the P-well is floating, and it is impossible to continue the current. The traditional dual-trench device relies on the body diode for conduction, and its conduction mode is bipolar mode, which will cause the bipolar degradation effect, which is not conducive to the long-term reliability of the device.

[0057] Fig.12 The figure shows the total current density comparison of the third quadrant conduction of the traditional dual trench device and the new device. It can be seen that the total current channel of the new device is only the self-biased NMOS channel (such as Fig.12 a), while the traditional double trench device relies on the body diode for conduction, and its total current density permeates the entire device (as shown in Fig.12 b).

[0058] Fig.13 The figure shows the comparison of hole density between the traditional double trench device and the new device when the third quadrant is turned on. It can be seen that the hole current density of the new device is almost zero (such as Fig.13 a), while the hole current density of the conventional double trench device permeates the entire device (as shown in Fig.13 b).

[0059] Fig.14 The figure shows the NMOS integrated in the new device in the third quadrant. sd As can be seen, when V gs =-5V, V ds =0.5V, the self-biased M=NMOS is turned off, when V gs =-5V, V ds =2V, the self-biased NMOS is turned on to achieve reverse freewheeling. The turn-on voltage of the self-biased NMOS is much smaller than the conduction voltage of the SiC diode, which can completely eliminate the bipolar degeneration effect.

[0060] Fig.15 The figure shows the comparison of gate charge characteristic curves of the traditional double trench device, the new device, the new device (floating) and the new device (grounded). Fig.15 It can be seen that the Q of the new device (floating) gd and Q g The remaining three devices are similar, with little difference.

[0061] Fig.16 The figure shows the comparison of the capacitance characteristic curves of the traditional double trench device, the new device, the new device (floating) and the new device (grounded). Fig.16 It can be seen that the C rss Maximum, new device (grounded) and traditional double trench device C rss The new device is in the middle, which means the switching speed of the new device is also between floating and grounded. oss The smallest, the remaining three devices are not much different. The C iss The smallest one, and the remaining three devices are not much different.

[0062] In summary, the present invention provides a SiC MOSFET device with integrated dual self-biased MOS. The device realizes that when forward conduction occurs, the self-biased PMOS is turned off and the P-well region is floated, thereby reducing the on-resistance of the device. In the blocking state, the self-biased PMOS is turned on and the P-well region is clamped, which effectively protects the gate oxide layer of the device compared to a completely floating device. The freewheeling function of the third quadrant is realized by the integrated self-biased NMOS, and under this condition, the P-well is in a floating state, the body diode cannot be turned on, and the bipolar degradation effect is completely avoided. Compared with the traditional dual-trench SiC MOSFET, the SiC MOSFET device proposed by the present invention has an I ds =200A, the on-resistance decreased by 2%, I ds = Reverse conduction voltage drop V at -100A cut-in Compared with the P-well fully floating device, the gate oxide electric field at 800V in the blocking state is reduced by 28.4%, and the gate-drain charge Q gd Down 20.81%, Q g The gate charge dropped by 3.1% and the transfer capacitance C at 200V rss A decrease of 74.08%.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A SiC MOSFET device with integrated dual self-bias MOS, characterized in that: The device comprises an N+ substrate region, an N-drift region located on the surface of the N+ substrate region, a main MOS located on the surface of the N-drift region, and a first double self-bias MOS and a second double self-bias MOS located on the surface of the N-drift region and distributed on both sides of the main MOS; The first dual self-bias MOS and the second dual self-bias MOS have the same structure and are symmetrically distributed; the first dual self-bias MOS and the second dual self-bias MOS both include a self-bias PMOS and a self-bias NMOS; the self-bias PMOS is used to control floating and clamping; the self-bias NMOS is used for reverse conduction.

2. The SiC MOSFET device according to claim 1, characterized in that: The main MOS includes a first polysilicon region, a first N+ source region and a first insulating dielectric layer; the first polysilicon region is located above the N-drift region and is completely wrapped by the first insulating dielectric layer; the first N+ source region is distributed on both sides of the first polysilicon region and is separated from the first polysilicon region by the first insulating dielectric layer.

3. The SiC MOSFET device according to claim 1, characterized in that: The first dual self-bias MOS and the second dual self-bias MOS both include a P-well region, a P+ region, a second polysilicon region, a second insulating dielectric layer, a P-base region, a second N+ source region and a P+ drain region; the P-well region is located on the surface of the N-drift region; the P+ region is located on the upper right of the P-well region; the second polysilicon region is located above the P-well and P+ regions, and is separated from the second N+ source region, the P-base region, the N-drift region, the P-well region and the P+ region by the second insulating dielectric layer; the P-base region is located on the surface of the N-drift region and is adjacent to the main MOS; the second N+ source region is located on the upper right of the P-base region; the P+ drain region is located on the surface of the P-base region and is adjacent to the main MOS; The P-well region serves as the source of the self-biased PMOS; The second N+ source region serves as the source of the self-biased NMOS; The P+ drain region serves as the drain of the self-biased PMOS; the second polysilicon region serves as the gates of the self-biased PMOS and the self-biased NMOS; and the drain of the self-biased NMOS is connected to the drain of the main MOS.

4. The SiC MOSFET device according to claim 3, characterized in that: In the lateral direction of the device, the P-well region protrudes a portion from the second insulating dielectric layer, and the protruding portion is used to enhance the conduction capability of the self-biased PMOS.

5. The SiC MOSFET device according to claim 3, characterized in that: The drain and gate of the self-biased PMOS are short-circuited; the source and gate of the self-biased NMOS are short-circuited.

6. The SiC MOSFET device according to claim 1, characterized in that: The device also includes a source metal contact region, wherein the source metal contact region is located at the top of the device; The source metal contact region is respectively connected to the source of the main MOS, the drain and gate of the self-biased PMOS, and the source and gate of the self-biased NMOS.

7. The SiC MOSFET device according to claim 1, characterized in that: The device also includes a drain metal contact region, wherein the drain metal contact region is located at the bottom of the device; The drain metal contact region is connected to the drain of the main MOS and the drain of the self-biased NMOS respectively.

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