Semiconductor device with multi-step gate and multi-step field plate and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor substrate, a surface passivation layer over the semiconductor substrate, and a first interlayer dielectric over the surface passivation layer. A gate electrode includes a gate channel portion extending through the surface passivation layer to contact an upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom range higher than the first horizontal bottom range. A conductive field plate includes a first field plate having a third horizontal bottom range recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom range higher than the first horizontal bottom range of the first gate field plate.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to semiconductor devices having gate electrodes and field plates and methods for fabricating such devices. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic components and systems. High power, high frequency transistors are used in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly suitable for these RF power applications and power electronics applications due to its excellent electronic and thermal properties. Specifically, the high electron velocity and high breakdown field strength of GaN make devices made from this material ideal for RF power amplifiers and high power switching applications.

[0003] Some GaN transistors include a field plate, which is an electrically grounded region of metallization that extends above the gate electrode of the transistor. The field plate is used to modify the electric field distribution, especially at the drain-side gate edge. This can cause an increase in breakdown voltage and a reduction in high-field trapping effects. Accurate alignment of the gate channel with the field plate is critical to achieving the necessary device performance for a variety of RF and power applications. In addition, the gate resistance, R G It is an important factor in determining the maximum signal gain by affecting the input power. However, conventional methods of reducing gate resistance may result in gate-drain capacitance C GD Increase and gate-source capacitance C GS This may result in a reduction in gain or a decrease in cutoff frequency. Therefore, in order to meet the device performance requirements for a given application, there is a need for GaN devices and methods of manufacturing such devices that ensure accurate alignment of the gate channel with the field plate and relatively low gate resistance. Summary of the invention

[0004] According to a first aspect of the present invention, there is provided a semiconductor device, comprising:

[0005] a semiconductor substrate having an upper surface and a channel;

[0006] a source electrode and a drain electrode, the source electrode and the drain electrode being above the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode;

[0007] a surface passivation layer, the surface passivation layer being above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode;

[0008] a first interlayer dielectric (ILD0) above an upper surface of the surface passivation layer;

[0009] a gate electrode above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent;

[0010] a conductive field plate above the upper surface of the semiconductor substrate and between the gate electrode and the drain electrode, wherein the conductive field plate comprises a first field plate having a third horizontal bottom extent recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent higher than the first horizontal bottom extent of the first gate field plate; and

[0011] A field plate dielectric spacer is on the upper surface of the surface passivation layer between the third horizontal bottom extent of the first field plate and the fourth horizontal bottom extent of the second field plate.

[0012] In one or more embodiments, the surface passivation layer includes a lower surface passivation sublayer formed on the upper surface of the semiconductor substrate, an intermediate surface passivation sublayer formed on the lower surface passivation sublayer, and an upper surface passivation sublayer formed on the intermediate surface passivation sublayer and defining the upper surface of the surface passivation layer.

[0013] In one or more embodiments, the lower surface passivation sublayer is formed of silicon nitride;

[0014] The intermediate surface passivation sublayer is formed of silicon dioxide; and

[0015] The upper surface passivation sublayer is formed of a material selected from aluminum oxide, aluminum nitride and hafnium oxide.

[0016] In one or more embodiments, the third horizontal bottom extent of the first field plate contacts an upper surface of the intermediate-surface passivation sublayer.

[0017] In one or more embodiments, the third horizontal bottom extent of the first field plate contacts an upper surface of the lower surface passivation sublayer.

[0018] In one or more embodiments, the ILD0 includes a lower ILD0 sublayer on the upper surface of the surface passivation layer, and a middle ILD0 sublayer on the upper surface of the lower ILD0 sublayer;

[0019] The fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sublayer; and

[0020] The second horizontal bottom extent of the second gate field plate overlies an upper surface of the middle ILD0 sub-layer.

[0021] In one or more embodiments, the field plate dielectric spacer has an outer surface extending from the upper surface of the surface passivation layer to an upper surface of the lower ILD0 sub-layer.

[0022] In one or more embodiments, the conductive field plate further includes a third field plate having a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.

[0023] In one or more embodiments, the ILD0 further includes an upper ILD0 sublayer on the upper surface of the middle ILD0 sublayer; and

[0024] The third field plate overlies and contacts an upper surface of the upper ILD0 sub-layer.

[0025] In one or more embodiments, the lower ILD0 sublayer is formed of a material selected from silicon nitride;

[0026] The middle ILD0 sublayer is formed of a material selected from silicon dioxide; and

[0027] The upper ILDO sublayer is formed of a material selected from silicon nitride.

[0028] In one or more embodiments, the first gate field plate and the second gate field plate protrude upward and outward from the gate channel portion; and

[0029] The second field plate and the third field plate protrude upward and outward from the first field plate.

[0030] In one or more embodiments, the first gate field plate and the second gate field plate are located on the drain side of the gate electrode;

[0031] The gate electrode further comprises another first gate field plate and another second gate field plate located on a source side of the gate electrode;

[0032] The second field plate and the third field plate are located on a gate side of the conductive field plate; and

[0033] The conductive field plate additionally comprises another second field plate and another third field plate on the drain side of the conductive field plate.

[0034] In one or more embodiments, the first field plate and the second field plate are formed of a field plate metal; and

[0035] The semiconductor device additionally includes a source metallization extending from the field plate metal across the gate electrode to a source contact.

[0036] In one or more embodiments, the field plate metal includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, aluminum, molybdenum, nickel, polysilicon, platinum, copper and tantalum; and

[0037] The source metallization includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, titanium-aluminum-gold, aluminum, molybdenum, nickel, polysilicon, germanium, platinum, copper and tantalum.

[0038] According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0039] providing a semiconductor substrate having an upper surface and a channel;

[0040] forming a surface passivation layer over the upper surface of the semiconductor substrate;

[0041] forming a first interlayer dielectric (ILD0) over an upper surface of the surface passivation layer;

[0042] forming a source electrode and a drain electrode over the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode;

[0043] forming a gate electrode over the upper surface of the semiconductor substrate and between the source electrode and the drain electrode, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; and

[0044] A conductive field plate is formed above the upper surface of the semiconductor substrate and between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate having a third horizontal bottom extent recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent higher than the first horizontal bottom extent of the first gate field plate.

[0045] In one or more embodiments, forming the surface passivation layer includes forming a lower surface passivation sublayer on the upper surface of the semiconductor substrate, forming an intermediate surface passivation sublayer on the lower surface passivation sublayer, and forming an upper surface passivation sublayer on the intermediate surface passivation sublayer, wherein the upper surface of the upper surface passivation sublayer defines the upper surface of the surface passivation layer.

[0046] In one or more embodiments, the method further comprises:

[0047] Simultaneously forming a gate electrode opening and a field plate opening through the ILD0;

[0048] forming a field plate dielectric spacer in the field plate opening, wherein the field plate dielectric spacer contacts a sidewall of the ILD0 and the upper surface of the surface passivation layer; and

[0049] removing the upper surface passivation sublayer between the field plate dielectric spacers to expose a portion of the upper surface of the intermediate surface passivation sublayer, and

[0050] Wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the intermediate surface passivation sublayer between the field plate dielectric spacers.

[0051] In one or more embodiments, the method further comprises:

[0052] Simultaneously forming a gate electrode opening and a field plate opening through the ILD0;

[0053] forming a field plate dielectric spacer in the field plate opening, wherein the field plate dielectric spacer contacts a sidewall of the ILD0 and the upper surface of the surface passivation layer; and

[0054] removing the upper surface passivation sublayer and the intermediate surface passivation sublayer between the field plate dielectric spacers to expose a portion of the upper surface of the lower surface passivation sublayer, and

[0055] Wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the lower surface passivation sublayer between the field plate dielectric spacers.

[0056] In one or more embodiments, the method further comprises:

[0057] Simultaneously forming a gate electrode opening and a field plate opening through the ILD0;

[0058] forming a gate dielectric spacer in the gate electrode opening, wherein the gate dielectric spacer contacts a sidewall of the ILD0 and the upper surface of the surface passivation layer;

[0059] removing the surface passivation layer between the gate dielectric spacers to expose a portion of the upper surface of the semiconductor substrate; and

[0060] removing the gate dielectric spacer so that the gate electrode opening has a first horizontal bottom extent exposing the portion of the upper surface of the semiconductor substrate, a second horizontal bottom extent defined by the upper surface of the surface passivation layer, and a third horizontal bottom extent at or below the upper surface of the ILD0, and

[0061] The forming of the gate electrode includes depositing a gate metal in the gate electrode opening to form the gate channel portion contacting the upper surface of the semiconductor substrate at the first horizontal bottom range of the gate electrode opening, the first gate field plate contacting the upper surface of the surface passivation layer at the second horizontal bottom range of the gate electrode opening, and the second gate field plate contacting the third horizontal bottom range of the gate electrode opening.

[0062] In one or more embodiments, forming the conductive field plate includes:

[0063] The conductive field plate is formed to additionally include a third field plate having a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.

[0064] In one or more embodiments, forming the ILD0 includes:

[0065] forming a lower ILDO sublayer on the upper surface of the surface passivation layer;

[0066] forming a middle ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer; and forming an upper ILD0 sub-layer on an upper surface of the middle ILD0 sub-layer,

[0067] wherein the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sublayer,

[0068] The fifth horizontal bottom extent of the third field plate overlies and contacts the upper surface of the upper ILD0 sublayer, and

[0069] The second horizontal bottom extent of the second gate field plate overlies an upper surface of the middle ILD0 sub-layer.

[0070] In one or more embodiments, forming the conductive field plate includes forming the first field plate and the second field plate from a field plate metal; and

[0071] The method additionally includes forming a source metallization extending from the field plate metal across the gate electrode to a source contact.

[0072] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] A more complete understanding of the subject matter may be derived by referring to the detailed description and claims considered in conjunction with the following drawings, wherein like reference numerals refer to like elements throughout the various figures.

[0074] Figure 1 is a cross-sectional side view of an exemplary heterojunction field effect transistor (HFET) according to an embodiment;

[0075] Figure 2 is used to describe the manufacturing Figure 1 and 3 20 to 20 of various embodiments of the method of the heterojunction field effect transistor (HFET) device; and

[0076] Figure 3 , 4 , 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 are cross-sectional side views of embodiments of HFET devices during a series of fabrication steps according to example embodiments. DETAILED DESCRIPTION

[0077] Embodiments disclosed herein include field effect transistors (FETs), and in particular heterojunction field effect transistors (HFETs) including high electron mobility transistors (HEMTs). The transistor embodiments each include a gate electrode and a field plate structure. According to one or more embodiments, both the gate electrode and the field plate structure have a stepped configuration that produces a gate electrode having at least one gate field plate (GFP) and a field plate structure having a plurality of source connection field plates (SFP). The field plate structure may cause a gate-drain capacitance C GD In one or more embodiments, the field plate structure may be recessed relative to at least one of the GFPs, which may further reduce C GD. In addition, in the case of multiple SFPs, the field plate structure is configured to ensure dielectric reliability and high breakdown voltage. The manufacturing method disclosed herein allows at least one of the GFPs and at least one of the SFPs to be fully self-aligned with the gate channel. By self-aligning these device features, device-to-device performance variations (e.g., variations in capacitance, gain, cutoff frequency, output power, and capture) that may otherwise occur due to feature misalignment can be avoided. In addition, in at least one embodiment, the gate structure is designed to have a relatively low gate resistance R G , without causing the gate-drain capacitance C GD or gate-source capacitance C GS significant increase.

[0078] Figure 1 is a cross-sectional side view of an exemplary GaN heterojunction field effect transistor (HFET) device 100 according to an embodiment. Figure 1 The upper image in FIG. 1 shows an overall view of the GaN HFET device 100. In addition, to enhance understanding, an enlarged view of a portion 101 of the GaN HFET device 100 is shown below the overall view of the device 100. The portion 101 corresponds to an embodiment of a transistor structure, which is described below in conjunction with Figures 2 to 20 The fabrication of this transistor structure is described in detail.

[0079] GaN HFET device 100 includes semiconductor substrate 110, one or more isolation regions 120, and active region 125. The active region is defined as the portion of device 100 located between isolation regions 120. As will be described in detail below, various transistor structures are formed on and above upper surface 112 of semiconductor substrate 110, and variable conductive channel 107 below upper surface 112 of semiconductor substrate 110 enables current flow through device 100.

[0080] In an embodiment, the semiconductor substrate 110 may include a main substrate 102, a buffer layer 104 disposed over an upper surface 103 of the main substrate 102, a channel layer 106 disposed over the buffer layer 104, and a barrier layer 108 disposed over the channel layer 106. In some embodiments, a cap layer 109 is disposed over the channel layer 106, and the cap layer 109 defines an upper surface 112 of the substrate 110. In other embodiments, the cap layer 109 may not be included, and the barrier layer 108 may define the upper surface 112 of the substrate 110. In the drawings, the upper layers of the substrate 110 are colored to enhance distinguishability from the underlying depicted layers overlying the upper surface 112 of the substrate 110.

[0081] The main substrate 102 may include silicon carbide (SiC), or may include other materials, such as sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), diamond, polycrystalline SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP), or other substantially insulating or high resistivity materials. A nucleation layer (e.g., AlN, not shown) may be formed on the upper surface 103 of the main substrate 102 between the buffer layer 104 and the main substrate 102. Embodiments of the buffer layer 104, the channel layer 106, the barrier layer 108, and the cap layer 109 may include materials selected from Si, AlN, GaN, indium phosphide (InP), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium gallium nitride (InGaN), and / or other suitable materials. The layers 104, 106, 108, and 109 may be epitaxially grown on the main substrate 102. Some of the layers 104, 106, 108, and 109 may be intentionally doped with iron (Fe), chromium (Cr), carbon (C), magnesium (Mg), germanium (Ge), or other suitable dopant species.

[0082] In some embodiments, the barrier layer 108 has a larger band gap and a larger spontaneous polarization than the channel layer 106, and when the barrier layer 108 is in direct contact with the channel layer 106, the channel 107 is generated in the form of a two-dimensional electron gas (2-DEG) within the channel layer 106 near the interface between the channel layer 106 and the barrier layer 108. In addition, the strain between the barrier layer 108 and the channel layer 106 can cause additional piezoelectric charge to be introduced into the 2-DEG and the channel 107. In some embodiments, an additional AlN interlayer barrier layer (not shown) can be formed between the channel layer 106 and the barrier layer 108. The AlN interlayer barrier layer can increase the channel charge, reduce electron alloy scattering to produce increased mobility, and improve electron confinement of the resulting 2-DEG.

[0083] Without departing from the scope of the present subject matter, it should be understood that the material selection and layer arrangement forming the semiconductor substrate 110 are exemplary. It should be understood that including the main substrate 102, the buffer layer 104, the channel layer 106, the barrier layer 108 and the cap layer 109 in the semiconductor substrate 110 is exemplary, and the functions and operations of the various layers can be combined and can vary depending on the materials used in any specific embodiment.

[0084] In other embodiments using N-polar materials, the channel layer 106 may be disposed over the barrier layer 108 to create a 2-DEG and a channel 107 directly below the cap layer 109 and the gate electrode 160. Still other embodiments may include a semiconductor layer formed of materials including GaAs, gallium oxide (Ga2O4), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), and aluminum indium arsenide (AlInAs) to form the semiconductor substrate 110.

[0085] The isolation regions 120 may be formed via an implantation process configured to damage the epitaxial layer and / or other semiconductor layers to produce high resistivity regions of the semiconductor substrate 110 (i.e., to render the semiconductor substrate 110 high resistivity or semi-insulating in those high resistivity regions), while leaving the crystal structure intact in the active regions 125. In other embodiments, the isolation regions 120 may be formed by removing one or more of the epitaxial layer and / or other semiconductor layers of the semiconductor substrate 110, rendering the remaining layers of the semiconductor substrate 110 semi-insulating, and leaving an active region "mesa" surrounded by high resistivity or semi-insulating isolation regions (not shown). In still other embodiments, the isolation regions 120 may be formed by removing one or more of the epitaxial layer and / or other semiconductor layers of the semiconductor substrate 110, followed by using ion implantation to damage and further enhance the semi-insulating properties of the remaining layers of the semiconductor substrate 110, and leaving an active region "mesa" (not shown) surrounded by the implanted high resistivity or semi-insulating isolation regions 120.

[0086] Within the active region 125, the HFET device 100 includes a source electrode 140 (also referred to herein as a "first current carrying electrode"), a source contact 141, a drain electrode 145 (also referred to herein as a "second current carrying electrode"), a drain contact 146, a gate electrode 160 (also referred to herein as a "control electrode"), a source-connected field plate (SFP) structure 190 (also referred to herein as a "field plate," "multi-step field plate," or "conductive field plate"), a source region 142, and a drain region 147. In an embodiment, the GaN HFET device 100 may be configured as a transistor finger, wherein the source electrode 140, the drain electrode 145, the gate electrode 160, and the SFP structure 190 may be configured as an elongated element forming a transistor "finger." To construct a high power device, multiple instances of the GaN HFET device 100 may be implemented in parallel with multiple drain electrodes 145 all coupled together and with multiple gate electrodes 160 all coupled together.

[0087] The source region 142 and the drain region 147 extend from the upper surface 112 of the substrate 110 to a depth below the upper surface 112. In some embodiments, ion implantation may be used to form the source region 142 and the drain region 147, and these regions 142, 147 are located at opposite ends of the channel 107 at the upper surface 112 of the semiconductor substrate 110. In some embodiments, ion implantation may be used to form intentionally doped source region 142 and drain region 147, and thus, the source region 142 and the drain region 147 may be regions of the semiconductor substrate 110 into which source and drain dopants have been implanted. In other embodiments, rather than including intentionally doped source region 142 and drain region 147, these regions of the substrate 110 may not be intentionally doped. In practice, after depositing the constituent layers of the Ohmic stack forming the source contact 141 and the drain contact 146, an annealing process may be performed to alloy the Ohmic stack, thereby creating Ohmic contacts with the source region 142 and the drain region 147 of the semiconductor substrate 110 (i.e., with the 2-DEG of the channel 107). In yet other embodiments, in addition to or instead of the source region 142 and the drain region 147 (not shown) and in the same location as the source region 142 and the drain region 147, a heavily doped (e.g., Si doping> 1e19 cm -3 ) may be formed above the semiconductor substrate 110 and in contact with the semiconductor substrate 110.

[0088] At the upper surface 112 of the substrate 110, the source contact 141 extends from its proximal end near the source side of the gate electrode 160 toward the source electrode 140. The source contact 141 overlies and contacts the cap layer 109 and the source region 142 along substantially the entire length of the source contact 141. In other embodiments, if the cap layer 109 is not included, the source contact 141 may contact the barrier layer 108. In yet other embodiments, the source contact 141 may be recessed into the semiconductor substrate 110. The source electrode 140 is disposed on or over a portion of the distal end of the source contact 141 and is electrically coupled to the SFP structure 190 through the source metallization 148.

[0089] Similarly, at the upper surface 112 of the substrate 110, the drain contact 146 extends from its proximal end near the drain side of the gate electrode 160 toward the drain electrode 145. The drain contact 146 overlies and contacts the cap layer 109 and the drain region 147 along substantially the entire length of the drain contact 146. In other embodiments, if the cap layer 109 is not included, the drain contact 146 may contact the barrier layer 108. In yet other embodiments, the drain contact 146 may be recessed into the semiconductor substrate 110. The drain electrode 145 is disposed on or over a portion of the distal end of the drain contact 146 and is electrically coupled to a drain manifold (not shown) through a drain metallization 149.

[0090] In one or more embodiments, the source contact 141 and the drain contact 146 are formed of a conductive layer (eg, Figure 8 The conductive layer 830 may include one or more layers of titanium (Ti), titanium tungsten (TiW), titanium aluminum (TiAl), titanium tungsten nitride (TiWN), or other materials suitable for forming ohmic contacts with the source region 142 and the drain region 147. The source electrode 140 and the drain electrode 145 formed by the source metallization 148 and the drain metallization 149 overlie and contact the source contact 141 and the drain contact 146. The source electrode 140 and the drain electrode 145 (and the metallizations 148, 149) may be formed by a stack of multiple conductive layers. In some embodiments, the multilayer stack used to form the source electrode 140 and the drain electrode 145 and the source metallization 148 and the drain metallization 149 may include, for example, one or more layers of Ti, TiW, TiAl, TiWN, gold (Au), titanium-aluminum-gold (TiAlAu), Al, molybdenum (Mo), nickel (Ni), polysilicon, Ge, platinum (Pt), copper (Cu), tantalum (Ta), combinations of these materials, or other suitable materials.

[0091] exist Figure 1 In the embodiment of the present invention, the source metallization 148 is shown as extending from the source contact 141 across the gate electrode 160 to the SFP structure 190. This extension of the source metallization 148 may be continuous over the length of the transistor finger (i.e., along the dimension into the page). In other embodiments, in order to reduce the capacitive coupling between the gate electrode 160 and the source metallization 148, the source metallization 148 may cross the gate electrode 160 to the SFP structure 190 only in discrete locations along the length of the transistor finger. In other words, the source metallization 148 may be implemented as one or more conductive "strips" that electrically couple the source contact 141 to the SFP structure 190 at one or more locations along the transistor finger, rather than a continuous structure along the entire length of the transistor finger. Therefore, most of the transistor fingers may lack source metallization across the gate electrode 160. In yet other embodiments, the source metallization 148 may be positioned outside the active region 125, beyond the ends of the transistor fingers (not shown), so as to electrically couple the source contact 141 to the SFP structure 190. In both other embodiments and still other embodiments, the same metal layer may be used to form the SFP structure 190 and the source metallization 148. However, alternatively, separate metal layers may be used for the metal to form the SFP structure 190 and the source metallization 148, but are not limited thereto.

[0092] In an embodiment, a multi-layer surface passivation layer 130 (including at least a first surface passivation sublayer 131, a second surface passivation sublayer 132, and a third surface passivation sublayer 133) and a multi-layer lowermost interlayer dielectric (ILD0) 134 (including at least a first ILD0 sublayer 135, a second ILD0 sublayer 136, and a third ILD0 sublayer 137) are formed above the upper surface 112 of the semiconductor substrate 110 in the active area 125. Adjacent sublayers of these sublayers 131 to 133, 135 to 137 are formed of different dielectric materials. Therefore, adjacent sublayers 131 to 133, 135 to 137 have different etching properties, which, as will be described in more detail later, enable the formation of recessed features (e.g., SFP structures 190 ( Figure 1 and 19 ) or alternatively SFP structure 190'( Fig. 20 ) of the recessed portion). For example, various materials that may form the surface passivation sublayers 131-133 and the ILD0 sublayers 135-137 include, but are not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4 or other stoichiometries), silicon oxynitride (SiON in various stoichiometries), aluminum oxide (Al2O3), aluminum nitride (AlN), and hafnium oxide (HfO2), although other substantially insulating materials may also be used. Figure 1 In the embodiment shown in , the surface passivation layer 130 includes three sub-layers 131 to 133. In other embodiments, the surface passivation layer may include more than three sub-layers.

[0093] The gate electrode 160 extends through all of the surface passivation sublayers 131 to 133 and the ILD0 sublayers 135 to 137. The gate electrode 160 is located above the upper surface 112 of the substrate 110, between the source contact 141 and the drain contact 146. During operation, the gate electrode 160 is used to adjust the conductivity of the channel 107 in response to a time-varying voltage applied to the gate electrode 160, thereby adjusting the current between the source contact 141 and the drain contact 146. The contact area between the gate electrode 160 and the upper surface 112 of the substrate 110 is referred to herein as a "gate channel".

[0094] As mentioned previously and as will be described in detail below, the gate electrode 160 has a stepped configuration. The stepped configuration of the gate electrode 160 includes a gate channel portion 162 and a plurality of gate field plates (GFPs) 164, 166. The gate channel portion 162 is located at the gate channel and has a level (relative to the gate electrode 160) that defines the lowermost portion (i.e., the portion that contacts or is closest to the upper substrate surface 112) of the gate electrode 160. Figure 1) bottom extent. The first GFP 164 (GFP1) is integrally formed with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extent of the gate channel portion 162. More specifically, GFP1 164 overlies and contacts a portion of the dielectric surface passivation layer (e.g., a portion of the surface passivation sublayer 133). The second GFP 166 (GFP2) is also integrally formed with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extent of both the gate channel portion 162 and GFP1 164. More specifically, GFP2 166 overlies and contacts a portion of the additional dielectric layer (e.g., a portion of layer 136). Figure 1 As shown in FIG. 1 , the horizontal bottom extents of GFP1 164 and GFP2 166 protrude upward and outward from the gate channel portion 162 on both sides of the gate channel portion 162 .

[0095] As used herein, when a horizontal bottom extent of a first feature (e.g., GFP2 164) is referred to as being “higher” than a horizontal bottom extent of a second feature (e.g., GFP1 162), this means that the first feature is farther from the upper surface 112 of the semiconductor substrate 110 than the second feature (i.e., there is a thicker dielectric between the first feature and the upper surface 112 of the substrate 110 than there is between the second feature and the upper surface 112 of the substrate 110). Similarly, as used herein, when a horizontal bottom extent of a first feature (e.g., GFP1 162) is referred to as being “lower” than a horizontal bottom extent of a second feature (e.g., GFP2 164), this means that the first feature is closer to the upper surface 112 of the semiconductor substrate 110 than the second feature (i.e., there is a thinner dielectric between the first feature and the upper surface 112 of the substrate 110 than there is between the second feature and the upper surface 112 of the substrate 110).

[0096] In at least one embodiment, the gate electrode 160 has a relatively large cross-sectional area, which can result in a relatively low gate resistance R G , without causing the gate-drain capacitance C GD or gate-source capacitance C GSA Schottky contact is formed in the gate trench. According to an embodiment, for low loss, a Schottky gate electrode 160, such as one or more Schottky materials such as nickel (Ni), palladium (Pd), platinum (Pt), iridium (Ir), or copper (Cu), may be combined with one or more low stress conductive materials such as gold (Au), aluminum (Al), Cu, polysilicon, or other suitable materials in a metal stack to form the gate electrode 160. In various embodiments, the gate electrode 160 may be characterized by a gate length where the gate electrode 160 contacts the substrate surface 112, and the gate length may be between about 0.05 microns and about 1 micron. In other embodiments, the gate length may be between about 0.01 microns and about 5 microns, but other suitable dimensions may be used.

[0097] Numerous other gate electrode embodiments may be implemented without departing from the scope of the present subject matter. Figure 1 The exemplary embodiments of the present invention depict gate electrode 160 as disposed over semiconductor substrate 110. In other embodiments (not shown), gate electrode 160 may be recessed through cap layer 109 and partially extend into barrier layer 108, thereby increasing the electrical coupling of gate electrode 160 with channel 107 through barrier layer 108. In still other embodiments (not shown), cap layer 109 may be omitted, and gate electrode 160 may directly contact barrier layer 108. In still other embodiments, gate electrode 160 may be disposed over a gate insulator (not shown), which may be formed between gate electrode 160 and semiconductor substrate 110 to form a metal-insulator semiconductor field effect transistor (MISFET) device.

[0098] SFP structure 190 (and Fig. 20 The SFP structure 190 is an alternative SFP structure 190′ extending through the ILD0 sublayers 135 to 137, but only partially through the surface passivation layer 130 (i.e., the SFP structures 190, 190′ are recessed below the upper surface of the surface passivation layer 130). The SFP structure 190 is located above the upper surface 112 of the substrate 110, between the gate structure 160 and the drain contact 146. The SFP structure 190 is used to modify the electric field distribution, particularly the electric field distribution at the drain-side edge of the gate electrode 160, thereby potentially causing an increase in the breakdown voltage of the device 100 and a reduction in the high-field trapping effect.

[0099] As previously mentioned and as will be described in detail below, the SFP structure 190 (and the alternative SFP structure 190') also has a stepped configuration. The stepped configuration of the SFP structure 190 includes a plurality of source connection field plates (SFPs) 192, 196, 198, 199, wherein the horizontal bottom extent of SFP1 192 is at a first level, and the horizontal bottom extents of SFP2 196, SFP3 198, and SFP4 199 are at increasingly higher levels (i.e., SFP2 196, SFP3 198, and SFP4 199 protrude upward and outward from SFP1 192 on one or both sides of SFP1 192). In general, the SFP structure 190 may cause a gate-drain capacitance C to be increased compared to conventional devices lacking field plates. GD The plurality of SFPs include a first SFP 192 (SFP1) that includes a horizontal bottom extent separated from the upper surface 112 of the substrate 110 by a relatively thin underlying dielectric material (e.g., portions of the dielectric layers 131 and 132 for the SFP structure 190, or only portions of the dielectric layer 131 for the SFP structure 190'). In one or more embodiments, the bottom extent of SFP1 192 (or alternatively SFP1 192') is at a lower level than the bottom extent of GFP1 164 and GFP2 166 (i.e., SFP1 192 and SFP1 192' have a thinner underlying dielectric material than GFP1 164 and GFP2 166), which may allow C GD Reduced. Lower gate-drain capacitance C GD This in turn may result in an increase in the gain of the device 100. In addition, a plurality of additional SFPs (e.g., SFP2 196, SFP3 198, SFP4 199, etc.) are provided, each having an increasingly thicker underlying dielectric material (i.e., an increasingly higher horizontal bottom range) to weaken the electric field at the edge of SFP1 192 (or alternatively SFP1 192') in order to ensure dielectric reliability and improve breakdown.

[0100] In various embodiments, one or more conductive layers may be used to form the SFP structure 190 (and alternative SFP structure 190'). For example, the SFP structure 190 may be a structure formed of titanium (Ti), Au, Al, molybdenum (Mo), Ni, Si, Ge, Pt, Cu, Ta, combinations of these materials, or other suitable materials. In other embodiments, one or more conductive layers used to form the SFP structure 190 may include titanium tungsten (TiW), titanium aluminum (TiAl), or titanium tungsten nitride (TiWN).

[0101] As will be discussed in more detail below, embodiments of the method of manufacturing device 100 ensure that at least SFP1 192 is fully self-aligned with gate channel portion 162. By self-aligning these device features, device-to-device performance variations (e.g., variations in capacitance, gain, cutoff frequency, output power, and capture) that might otherwise occur due to feature misalignment can be avoided. According to embodiments, self-aligned gate channel portion 162 and SFP1 192 (or SFP1 192') are partially achieved by simultaneously forming a gate opening and a field plate opening (e.g., Figure 4 This is possible by virtue of the openings 460, 490) as will be described in detail later.

[0102] According to various embodiments, one or more additional dielectric layers 150, 170, 180 are disposed over the surface passivation sublayers 131-133 and the ILD0 sublayers 135-137, the gate electrode 160, and the SFP structure 190. For example, the additional dielectric layers 150, 170, 180 may be formed of one or more suitable materials, including silicon dioxide (SiO2), organosilicate glass, porous silicon dioxide, silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), and hafnium oxide (HfO2), although other substantially insulating materials may also be used.

[0103] As used herein, the term "low-k dielectric material" refers to a dielectric material having a dielectric constant lower than about 5.0, and the term "high-k dielectric material" refers to a dielectric material having a dielectric constant higher than about 5.0. In embodiments, the additional dielectric layers 150, 170, 180 may be formed of a low-k dielectric material. In some embodiments, the relatively low dielectric constant of the dielectric layer 150 may reduce parasitic capacitance between the gate electrode 160 and the source metallization 148 and the SFP structure 190, and may also reduce parasitic capacitance between the drain electrode 145 and the field plate structure 190.

[0104] The dielectric constants of the surface passivation sublayers 131-133 and the ILD0 sublayers 135-137 may exceed the dielectric constants of the additional dielectric layers 150, 170, 180. Additionally, the dielectric constants of the sublayers 131-133, 135 may exceed the dielectric constants of the upper ILD0 sublayers 136,137.

[0105] Figure 2 is used to describe the manufacturing Figure 1 and Fig.19 Embodiments of a method for manufacturing a GaN HFET device 100 and a GaN HFET device (eg, Fig. 20 100 ') is a process flow chart of an alternative embodiment of the method. To enhance understanding, Figure 2 Should be combined Figures 3 to 20Check, Figures 3 to 20 is a cross-sectional side view of a portion of a GaN HFET device 100, 100' during a series of fabrication steps. It should be understood that Fig.19 and 20 The depicted portions 100, 100' of the embodiment of the GaN HFET device shown in FIG. Figure 1 101 of the device 100 shown in FIG. Figures 3 to 20 Only portions of GaN HFET devices are depicted, but those GaN HFET devices will also include other adjacent device structures, such as Figure 1 Those device structures to the left and right of portion 101 are shown in the upper image in FIG. 1 (e.g., other GaN HFET devices would include a main substrate 102, source and drain regions 142 and 147, source and drain electrodes 140 and 145, source and drain contacts 141 and 146, isolation region 120, etc.).

[0106] First reference Figure 1 and 2 In block 202, fabrication of GaN HFET device 100 begins by providing semiconductor substrate 110. As previously mentioned, in at least one embodiment, providing semiconductor substrate 110 may include providing host substrate 102 and forming a plurality of semiconductor layers on or over host substrate 102. For example, host substrate 102 may include SiC, or may include other materials such as sapphire, Si, GaN, AlN, diamond, polycrystalline SiC, silicon-on-insulator, GaAs, InP, or other substantially insulating or high resistivity materials. Forming overlying semiconductor layers may include forming a nucleation layer (not shown) on or over upper surface 103 of host substrate 102, forming a buffer layer 104 on or over nucleation layer, forming a channel layer 106 on or over buffer layer 104, forming a barrier layer 108 on or over channel layer 106, and optionally forming a cap layer 109 on or over barrier layer 108. Embodiments of the buffer layer 104, the channel layer 106, the barrier layer 108, and the cap layer 109 may include materials selected from Si, AlN, GaN, InP, AlGaN, InAlN, InGaN, or other suitable materials. The semiconductor layers 104, 106, 108, and 109 may be epitaxially grown using one of metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination of these techniques, but alternatively, other suitable techniques may be used. Some of the layers 104, 106, 108, and 109 may be intentionally doped with Fe, Cr, C, Mg, Ge, or other suitable dopant species.

[0107] At this stage or later, source region 142 and drain region 147 may be formed through upper surface 112 of semiconductor substrate 110. Forming source region 142 and drain region 147 may include forming a sacrificial dielectric layer (e.g., selected from Si3N4, Al2O3, SiO2, AlN, and HfO2) on or above semiconductor substrate 110. An implantation mask may then be formed on the sacrificial dielectric layer, and dopant species (e.g., selected from one or more of Si, Ge, O, or other suitable n-type dopants) may be implanted into semiconductor substrate 110 through openings in the implantation mask to form source implant regions and drain implant regions within the semiconductor substrate. The implantation mask may then be removed (e.g., using one or more conventional wet chemical and plasma ashing techniques). The implanted regions may then be activated (e.g., by annealing semiconductor substrate 110) to form source region 142 and drain region 147. The sacrificial dielectric layer may then be removed (e.g., using wet or dry etching).

[0108] Reference Figure 2 and 3 , at block 204 and manufacturing stage 300 ( Figure 3 ), a multi-layer surface passivation layer 130 (including at least a lower surface passivation sublayer 131, an intermediate surface passivation sublayer 132, and an upper surface passivation sublayer 133) is formed on or above the upper surface 112 of the semiconductor substrate 110. In addition, a multi-layer lowermost interlayer dielectric (ILD0) 134 (including at least a first ILD0 sublayer 135, a second ILD0 sublayer 136, and a third ILD0 sublayer 137) is formed on or above the multi-layer surface passivation layer 130. According to an embodiment, adjacent pairs of sublayers are formed of different dielectric materials to achieve etching selectivity. In order to enhance the ability to distinguish the various sublayers 131, 132, 133, 135, 136, 137, the sublayers 132, 133, and 136 are filled with a stippled pattern in some figures. The patterning is not intended to imply that sub-layers 131 , 135 , 137 are formed of the same material or that sub-layers 132 , 133 , and 136 are formed of the same material, although in some embodiments, some of these layers may be formed of the same material.

[0109] According to an embodiment, adjacent pairs of sublayers are formed of different dielectric materials to achieve etching selectivity (e.g., adjacent sublayers may be etched using different etching chemistries to achieve self-alignment of gate channel 162 with SFP1 192, 192' and formation of a stepped configuration of gate electrode 160 and SFP structures 190, 190'). More specifically, sublayer 131 is formed of a different dielectric material than sublayer 132, sublayer 132 is formed of a different dielectric material than sublayer 133, sublayer 133 is formed of a different dielectric material than sublayer 135, sublayer 135 is formed of a different dielectric material than sublayer 136, and sublayer 136 is formed of a different dielectric material than sublayer 137.

[0110] Specifically, as described below in conjunction with various manufacturing stages, each underlying sublayer 131 to 133, 135, 136 may act as an etch stop layer when etching through each overlying sublayer 132, 133, 135 to 137 using any given etch chemistry. For example, an etch chemistry (or multiple chemistries) used to etch the upper surface passivation sublayer 133 as described later may have a high etch selectivity between the materials of the upper surface passivation sublayer 133 and the intermediate surface passivation sublayer 132, and an etch chemistry (or multiple chemistries) used to etch the intermediate surface passivation sublayer 132 may have a high etch selectivity between the materials of the intermediate surface passivation sublayer 132 and the lower surface passivation sublayer 131. As understood by those skilled in the art, etch selectivity is the ratio of etch rates between materials. In the present case, the etching selectivity of the etchant used to etch the upper surface passivation sublayer 133 can be defined as the ratio of the etching rate of the material of the upper surface passivation sublayer 133 ("etching rate 133") to the etching rate of the material of the intermediate surface passivation sublayer 132 ("etching rate 132") (i.e., the etching selectivity of the etchant used to etch the upper surface passivation sublayer 133 is equal to etching rate 133 / etching rate 132). In addition, an etchant having "low selectivity" to a certain material is configured to etch the material at a relatively high rate, while an etchant having "high selectivity" to a certain material is not configured to etch the material at a high rate (or not etch at all).

[0111] The three layers of the surface passivation layer 130 are first formed on the upper surface 112 of the semiconductor substrate 110. The lower surface passivation sublayer 131 is formed directly on the upper surface 112 of the semiconductor substrate 110 (e.g., on the cap layer 109 if the cap layer 109 is included, or on the barrier layer 108 if the cap layer 109 is not included). According to various embodiments, the lower surface passivation sublayer 131 may have a thickness in the range of about 50 angstroms to about 1000 angstroms, but the layer 131 may also be thinner or thicker.

[0112] According to some embodiments, the lower surface passivation sublayer 131 may be formed of silicon nitride (Si3N4, including silicon-rich or silicon-poor compositions thereof), but alternatively, layer 131 may be formed of another dielectric material. The lower surface passivation sublayer 131 may be formed using low pressure chemical vapor deposition (LPCVD), but alternatively, layer 131 may be formed using a different deposition method (e.g., atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), metal organic CVD (MOCVD), molecular beam epitaxy (MBE), inductively coupled plasma (ICP) deposition, electron cyclotron resonance (ECR) deposition, plasma enhanced ALD (PEALD) or other suitable techniques). As will be described later in conjunction with manufacturing stage 900' ( Fig.11 ) as described above, the lower surface passivation sublayer 131 forms a field plate opening (eg, Fig.11 In essence, this allows the field plate structure 190' ( Fig.13 ) of the embodiment can be recessed below GFP1164 ( Fig.16 ).

[0113] The intermediate surface passivation sublayer 132 is formed directly on the lower surface passivation sublayer 131. According to various embodiments, the intermediate surface passivation sublayer 132 may have a thickness in the range of about 50 angstroms to about 1000 angstroms, but the layer 132 may also be thinner or thicker.

[0114] According to some embodiments, the intermediate surface passivation sublayer 132 may be formed of silicon dioxide (SiO2), but alternatively, the layer 132 may be formed of another dielectric material. The intermediate surface passivation sublayer 132 may be formed using LPCVD and / or using a different deposition method (e.g., sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques). As will be described later in conjunction with manufacturing stage 900 ( Fig.10 ) as described above, the intermediate surface passivation sublayer 132 is used to form a field plate opening (eg, Fig.10 In essence, this allows the field plate structure 190 ( Fig.12 ) can also be recessed below GFP1 164 ( Fig.16 ).

[0115] According to an embodiment, the upper surface passivation sublayer 133 is formed directly on the intermediate surface passivation sublayer 132. According to various embodiments, the upper surface passivation sublayer 133 can have a thickness in the range of about 50 angstroms to about 1000 angstroms, but layer 133 can also be thinner or thicker. Therefore, in one or more embodiments, the total thickness of the surface passivation layer 130 (including the thickness of sublayers 131 to 133) can be between about 150 angstroms and about 3000 angstroms, but other thicknesses can be used.

[0116] According to some embodiments, the upper surface passivation sublayer 133 may be formed of aluminum oxide (Al2O3) or aluminum nitride (AlN), but alternatively, layer 133 may be formed of another dielectric material (e.g., Si3N4 or HfO2). The upper surface passivation sublayer 133 may be formed using sputtering, ALD or PEALD and / or using different deposition methods (e.g., LPCVD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition or other suitable techniques). Forming the upper surface passivation sublayer 133 completes the formation of the surface passivation layer 130. According to various embodiments, the material of layers 131 to 133 is primarily a high-k dielectric material that is configured to provide high dielectric withstand voltage capability for low equivalent oxide thickness.

[0117] The three layers of ILD0 134 are then formed on the surface passivation layer 130. According to an embodiment, a lower ILD0 sublayer 135 is formed directly on the upper surface passivation sublayer 133. According to various embodiments, the lower ILD0 sublayer 135 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, although the layer 135 may also be thinner or thicker.

[0118] According to an embodiment, and as indicated above, the lower ILD0 sublayer 135 is etched at a rate that is lower than the upper surface passivation sublayer 133 when exposed to an etch chemistry that will subsequently be used to etch the lower ILD0 sublayer 135 (e.g., as later described in conjunction with blocks 206 and Figure 4 The lower ILDO sublayer 135 may be formed of a dielectric material having a very high etch rate (described in detail). For example, and in accordance with some embodiments, the lower ILDO sublayer 135 may be formed of silicon nitride (Si3N4, including silicon-rich or silicon-poor compositions thereof) or other suitable materials. The lower ILDO sublayer 135 may be formed using LPCVD and / or using different deposition methods (e.g., sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques).

[0119] According to an embodiment, middle ILD0 sublayer 136 is formed directly on lower ILD0 sublayer 135. According to various embodiments, middle ILD0 sublayer 136 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, although layer 136 may also be thinner or thicker.

[0120] According to an embodiment, and as indicated above, the middle ILD0 sublayer 136 is etched at a rate compared to the lower ILD0 sublayer 135 when exposed to an etch chemistry that will subsequently be used to etch the middle ILD0 sublayer 136 (e.g., as later described in conjunction with blocks 216 and Fig.10 The intermediate ILD0 sublayer 136 may be formed of a dielectric material having a very high etch rate (described above). For example, and in accordance with some embodiments, the intermediate ILD0 sublayer 136 may be formed of silicon dioxide (SiO2) or other suitable materials. The intermediate ILD0 sublayer 136 may be formed using LPCVD and / or using different deposition methods (e.g., sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques).

[0121] According to an embodiment, upper ILD0 sublayer 137 is formed directly on middle ILD0 sublayer 136. According to various embodiments, upper ILD0 sublayer 137 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, although layer 137 may also be thinner or thicker. Thus, in one or more embodiments, the total thickness of ILD0 134 (including the thickness of sublayers 135-137) may be between about 1500 angstroms and about 6000 angstroms, although other thicknesses may be used.

[0122] According to an embodiment, and as indicated above, the upper ILD0 sublayer 137 is etched at a rate compared to the middle ILD0 sublayer 136 when exposed to an etch chemistry that will subsequently be used to etch the upper ILD0 sublayer 137 (e.g., as later described in conjunction with blocks 220 and Fig.15 The upper ILD0 sublayer 137 may be formed of a dielectric material having a very high etch rate (described above). For example, and in accordance with some embodiments, the upper ILD0 sublayer 137 may be formed of silicon nitride (Si3N4, including silicon-rich or silicon-poor compositions thereof) or other suitable materials. The upper ILD0 sublayer 137 may be formed using LPCVD and / or using different deposition methods (e.g., sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques).

[0123] Reference Figure 1 , 2 and 4, at block 206 and manufacturing stage 400 ( Figure 4 ), for the source ohmic contact 141 and the drain ohmic contact 146 to be formed ( Figure 1 ) openings 440, 445, 460, 490, gate electrode 160 ( Figure 1 ) and SFP 190( Figure 1 , 19 )(or Fig. 20The SFP 190′) is formed through ILD0 134 (but not through the surface passivation layer 130) over the source and drain regions 142, 147 and over the final location of the gate electrode 160 and the SFP 190 using a sequential or simultaneous selective etching process performed with appropriate selectivity to terminate on the surface passivation layer 130.

[0124] For example, to form openings 440, 445, 460, 490, photoresist layer 410 may be deposited over the upper surface of ILD0 134 (i.e., on the upper surface of ILD0 sublayer 137), and photoresist openings 420 may be formed over (and including) locations where openings 440, 445, 460, 490 in ILD0 134 are to be formed. Figure 1 , 19 , 20 above the final locations of the source and drain regions 142, 147 and the gate electrode 160 and SFP 190, 190'). The various sub-layers 137, 136, 135 of ILD0 134 may then be etched sequentially or simultaneously with appropriate selectivity through the resist openings to terminate on the upper surface passivation sub-layer 133.

[0125] A plurality of dry and / or wet etching techniques may be used to etch the openings 440, 445, 460, 490 through the sub-layers 137, 136, 135. For example, according to various embodiments, the openings 440, 445, 460, 490 may be formed using reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, atomic layer etching (ALE), and wet chemical etching. Dry etching may be advantageous over wet etching because dry etching etches substantially anisotropically (i.e., produces substantially vertical sidewalls).

[0126] In one or more embodiments, a single etchant (e.g., a fluorine-based chemistry) may be used to etch through all of the sub-layers 137, 136, 135 while terminating on the surface passivation sub-layer 133 (e.g., the etchant has a low selectivity between Si3N4 and SiO2, but a high selectivity to Al2O3). In other embodiments, multiple etchants may be used to sequentially etch through all of the sub-layers 137, 136, 135. For example, an etchant used to etch the upper ILD0 sub-layer 137 (e.g., Si3N4) may selectively etch through the upper ILD0 sub-layer 137 and then terminate on the middle ILD0 sub-layer 136. Thus, the etchant should have a high selectivity to the material of the underlying middle ILD0 sub-layer 136 (i.e., the etchant should not be designed to etch the underlying middle ILD0 sub-layer 136 in bulk). After etching through the ILD0 sublayer 137, the etchant used to etch the middle ILD0 sublayer 136 (e.g., SiO2) can selectively etch through the middle ILD0 sublayer 136 and then stop on the lower ILD0 sublayer 135. Therefore, the etchant should have a high selectivity to the material of the underlying lower ILD0 sublayer 135 (i.e., the etchant should not be designed to etch a large amount of the underlying lower ILD0 sublayer 135). Finally, the etchant used to etch the lower ILD0 sublayer 135 (e.g., Si3N4) can selectively etch through the lower ILD0 sublayer 135 and then stop on the upper surface passivation sublayer 133. Therefore, the etchant should have a high selectivity to the material of the underlying upper surface passivation sublayer 133 (i.e., the etchant should not be designed to etch a large amount of the underlying upper surface passivation sublayer 133).

[0127] According to various embodiments, to etch through the upper ILD0 sublayer 137, a suitable dry etching technique may use, for example, but not limited to, fluorine-based chemistries (e.g., one or more of sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or other suitable chemistries). Alternatively, a suitable wet etching chemistry may be used.

[0128] In various embodiments, the middle ILD0 sublayer 136 (e.g., SiO2) can then be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a fluorine-based chemistry (e.g., the same as layer 137), a chlorine-based chemistry, or another suitable dry etch chemistry. Alternatively, a suitable wet etch chemistry can be used.

[0129] Finally, the lower ILD0 sublayer 135 (e.g., Si3N4) can then be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a fluorine-based chemistry (e.g., the same as layer 137) or other suitable dry etch chemistry. Alternatively, a suitable wet etch chemistry can be used. Once the etching process is completed, the patterned photoresist 410 is removed.

[0130] At this stage, if the various materials of the surface passivation layer 130 and ILD0 134 can be retained in the high temperature annealing, the ohmic source region 142 and the ohmic drain region 147 can be processed for self-alignment. Alternatively, in other embodiments, after the passivation layer is removed only in the area of ​​the ohmic source region 142 and the ohmic drain region 147 (e.g., in blocks 212 and Figure 7 In these other embodiments, the self-aligned ohmic doping may be provided by selective epitaxy rather than by ohmic source and drain implantation (ie, omitting source region 142 and drain region 147).

[0131] Reference Figure 1 , 2 and 5, at block 208 and manufacturing stage 500 ( Figure 5 ), followed by forming a conformal dielectric spacer layer 520. Conformal dielectric spacer layer 520 is deposited on the upper surface of the remaining portion of ILD0 134, over the portion of surface passivation layer 130 exposed by openings 440, 445, 460, and 490 (i.e., the portion of upper surface passivation sublayer 133 exposed by openings 440, 445, 460, and 490), and on the sidewalls of openings 440, 445, 460, and 490 (i.e., on the sidewalls of sublayers 135 to 137 that are etched through). According to various embodiments, conformal dielectric spacer layer 520 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, but layer 520 may also be thinner or thicker. According to some embodiments, conformal dielectric spacer layer 520 may be formed of silicon dioxide (SiO2) or other suitable materials. The conformal dielectric spacer layer 520 can be formed using atomic layer deposition (ALD), which is well suited for forming thin conformal layers, and / or using different deposition methods (e.g., LPCVD, sputtering, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques).

[0132] Reference Figure 1 , 2 and 6, at block 210 and manufacturing stage 600 ( Figure 6), an etching process is then performed to form dielectric spacers 640, 645, 660, 690 from portions of the conformal dielectric spacer layer 520. For ease of description, and due to the proximity of the dielectric spacers to other features to be formed, dielectric spacer 640 may be referred to as a source dielectric spacer, dielectric spacer 645 may be referred to as a drain dielectric spacer, dielectric spacer 660 may be referred to as a gate dielectric spacer, and dielectric spacer 690 may be referred to as a field plate dielectric spacer 690.

[0133] To form the dielectric spacers 640, 645, 660, 690, the conformal dielectric spacer layer 520 (eg, SiO2) is anisotropically etched until the upper surface of the surface passivation layer 130 is exposed. Figure 6 As shown in , this causes portions of the conformal dielectric spacer layer 520 to remain on portions of the upper surface of the surface passivation layer 130 , and also remain on the vertical sidewalls of the ILD0 134 .

[0134] For example, the conformal dielectric spacer layer 520 can be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a fluorine-based chemistry (e.g., HF or CF4+H2 plasma). The etchant should have high selectivity to the material of the upper surface passivation sublayer 133 (e.g., Al2O3), and also have high selectivity to the material of the upper ILD0 sublayer 137 (e.g., Si3N4) (i.e., the etchant should not be designed to etch a large amount of the upper surface passivation sublayer 133 or the upper ILD0 sublayer 137).

[0135] Once the etching process is completed, the dielectric spacers 640, 645, 660, 690 remain adjacent to the sidewalls of the openings 440, 445, 460, 490. For example, the gate dielectric spacer 660 is formed on the sidewalls of the ILD0 134 exposed in the gate opening 460, and the field plate dielectric spacer 690 is formed on the sidewalls of the ILD0 134 exposed in the field plate opening 490. Each of the dielectric spacers 640, 645, 660, 690 includes a portion of the conformal dielectric spacer layer 520 having a horizontal bottom extent on the upper surface passivation sublayer 133, a vertical sidewall on the sidewalls of the ILD0 134, and a convex curved outer surface 694 extending from the upper surface passivation sublayer 133 to the upper surface of the ILD0 134.

[0136] Reference Figure 1 , 2 and 7, at block 212 and manufacturing stage 700 ( Figure 7), a selective etching process is used to pattern and etch source contact openings 740 and drain contact openings 745 through the surface passivation layer 130 while terminating on the top surface 112 of the semiconductor substrate 110. More specifically, a photoresist layer 710 is applied over the exposed portions of the surface passivation layer 130, the remaining portions of the ILD0 134, and the dielectric spacers 640, 645, 660, 690, and the photoresist layer 710 is processed and patterned to form resist openings 720 over the source region 142 and the drain region 147. According to one or more embodiments, the patterned photoresist layer 710 covers the structures between the dielectric spacers 640, 645.

[0137] The portions of the surface passivation sublayers 133, 132, 131 sequentially exposed through the openings 720 are then sequentially etched through the openings 720 to remove the exposed portions of the sublayers 133, 132, 131. At this point, portions of the upper surface 112 of the semiconductor substrate 110 above the source region 142 and the drain region 147 are exposed in the source contact opening 740 and the drain contact opening 745. A plurality of dry and / or wet etching techniques may be sequentially used to etch openings through the upper surface passivation sublayer 133 and the lower surface passivation sublayer 131.

[0138] In various embodiments, the etchant used to etch the upper surface passivation sublayer 133 (e.g., Al2O3) can selectively etch through the upper passivation sublayer 133 and then terminate on the intermediate passivation sublayer 132. For example, in various embodiments, the upper passivation sublayer 133 can be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a chlorine-based chemistry (e.g., Cl2, CCl4, BCl3) or other suitable dry etching chemistry. Alternatively, thermal or plasma ALE can be employed using, for example, NbF5 and CCl4 or Sn(acac)2 and HF pyridine. Alternatively, suitable wet etching chemistries for etching the upper passivation sublayer 133 include piranha etching, KOH, NH4OH+, or another suitable wet etching chemistry.

[0139] The intermediate passivation sublayer 132 (e.g., SiO2) may be etched after the etching process for the upper passivation sublayer 133 has been completed. The intermediate passivation sublayer 132 may be etched using an etching process and / or etching chemistry different from the etching process and / or etching chemistry used to etch the upper passivation sublayer 133. For example, in various embodiments, a suitable dry etching technique may use, for example, but not limited to, RIE, ICP, or ECR in combination with a fluorine-based chemistry (e.g., SF6 or CF4) or other suitable dry etching chemistry. Alternatively, a suitable wet etching chemistry for etching the intermediate passivation sublayer 132 includes HF or buffered HF, or another suitable wet etching chemistry.

[0140] The lower passivation sublayer 131 (e.g., Si3N4) may be etched after or at the same time as or alternatively after the etching process for the middle passivation sublayer 132 has been performed. In various embodiments, the lower passivation sublayer 131 may be etched using an etching process and / or etching chemistry that is the same or different from the etching process and / or etching chemistry used to etch the middle passivation sublayer 132. For example, according to various embodiments, a suitable dry etching technique may use, for example, but not limited to, one or more of fluorine-based chemistries (e.g., SF6, CF4) or other suitable chemistries. Alternatively, a suitable wet etching chemistry may be used. The patterned photoresist 710 is retained for the next manufacturing stage.

[0141] Reference Figure 1 , 2 and 8, at block 214 and manufacturing stage 800 ( Figure 8 ), the conductive source contact 141 and the conductive drain contact 146 are formed by the ohmic contact metal 830 above the source region 142 and the drain region 147. According to one or more embodiments, the ohmic contact metal 830 for the conductive source contact 141 and the conductive drain contact 146 can be deposited using a lift-off process. More specifically, the patterned photoresist layer 710 is used as a mask to prevent the ohmic contact metal 830 from being deposited in regions other than above the source region 142 and the drain region 147.

[0142] An ohmic contact metal 830 in the form of a conductive layer or conductive layer stack is deposited over the exposed portions of the source and drain regions 142, 147, the exposed source and drain dielectric spacers 640, 645, and the upper surface of the patterned photoresist layer 710. According to one or more embodiments, the ohmic contact metal 830 may include one or more layers of titanium (Ti), titanium aluminum (TiAl), titanium tungsten (TiW), titanium tungsten nitride (TiWN), and / or other suitable materials. In some embodiments, if etch selectivity is required during subsequent processing steps, a thin layer of gold may be deposited on top of the conductive layer to provide a desired etching selectivity during those subsequent processing steps (e.g., before performing blocks 226 and 227). Fig.18 The photoresist layer 710 is then removed, thereby stripping the portion of the ohmic contact metal 830 that overlies the photoresist layer 710. The portion of the ohmic contact metal 830 that is deposited on the source region 142 and the drain region 147 and the source dielectric spacer 640 and the drain dielectric spacer 645 remains, thereby forming the source contact 141 and the drain contact 146.

[0143] In an alternative embodiment, rather than using a lift-off process to form source contact 141 and drain contact 146, a subtractive process may be used. More specifically, during manufacturing stage 700 ( Figure 7 ), ohmic contact metal 830 may be deposited directly over the surface of the device, and a photoresist mask (not shown) may be applied over the ohmic contact metal 830 and patterned to cover only those portions of the ohmic contact metal 830 that correspond to the source contact 141 and the drain contact 146. The portions of the ohmic contact metal 830 not covered by the patterned photoresist mask may then be removed, and the patterned photoresist mask removed.

[0144] Reference Figure 1 , 2 , 9 and 10, at block 216 and manufacturing stage 900 ( Fig. 9 , 10 ), a multi-level field plate opening 990 is formed. Fig. 9 To form the field plate opening 990, a photoresist layer 910 may be deposited over the source and drain contacts 141, 146, the upper surface of the ILD0 134, and the dielectric spacers 640, 645, 660, 690. A photoresist opening 920 may then be formed over the location where the field plate opening 990 is to be formed. In accordance with one or more embodiments, the width of the photoresist opening 920 encompasses two field plate dielectric spacers 690 and extends over portions of the ILD0 134 beyond those spacers 690.

[0145] Reference Fig.10 , the upper and middle sublayers 137 and 136 of the ILD0 134 and portions of the field plate dielectric spacer 690 may then be sequentially etched through the resist openings 920 while terminating on the lower ILD0 sublayer 135 and the upper passivation sublayer 133. A plurality of dry and / or wet etching techniques may be used to etch portions of the upper and middle sublayers 137 and 136 of the ILD0 134 and the field plate dielectric spacer 690 to form the field plate openings 990. For example, according to various embodiments, the field plate openings 990 may be formed using RIE, ICP etching, ECR etching, or other suitable techniques.

[0146] According to one or more embodiments, a first etching process is performed to etch at least a portion of the upper ILD0 sublayer 137, the middle ILD0 sublayer 136, and at least a portion of the field plate dielectric spacer 690. According to one or more embodiments, the etchant used to etch these features has a low selectivity to the material of the upper ILD0 sublayer 137 (e.g., Si3N4), to the material of the middle ILD0 sublayer 136 (e.g., SiO2), and to the dielectric spacer 690 (e.g., also SiO2). Therefore, the etchant is used to etch the material of the upper ILD0 sublayer 137, the middle ILD0 sublayer 136, and the dielectric spacer 690. According to an embodiment, this etching process is terminated before all of the dielectric spacers 690 have been removed and before all of the middle ILD0 sublayer 136 have been removed.

[0147] According to various embodiments, to etch through the upper ILD0 sublayer 137, at least a portion of the middle ILD0 sublayer 136, and a portion of the dielectric spacer 690, a suitable dry etching technique may be used, such as, but not limited to, one or more of SF6, CF4, or other suitable chemistries. In one or more embodiments, the process may include a timed etch designed to terminate before all of the middle ILD0 sublayer 136 is removed and before all of the field plate dielectric spacers 690 are removed.

[0148] After terminating the first etching process, a second anisotropic etching process is performed to etch any remaining portions of the middle ILD0 sublayer 136 (e.g., SiO2) (terminating on the lower ILD0 sublayer 136), while also etching additional portions of the dielectric spacers 690 (e.g., also SiO2) (terminating before removing all of the dielectric spacers 690). According to one or more embodiments, the middle ILD0 sublayer 136 and the remaining portions of the dielectric spacers 690 may be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a chemistry that etches the material of the middle ILD0 sublayer 136 and the dielectric spacers 690 (e.g., SiO2) and with high selectivity to the material of the lower ILD0 sublayer 136 (e.g., Si3N4) and the lower surface passivation sublayer 131. For example, in various embodiments, this etching process may use a fluorine-based chemistry, such as HF, C3F8, C2F6+H2, CF4+H2, or other suitable dry etching chemistry. After completing this etching process, each of the partially etched dielectric spacers 690 has a convexly curved outer surface 194 extending from the upper surface passivation sub-layer 133 to the upper surface of the lower ILD0 sub-layer 135 .

[0149] At this point, an additional etching process may be performed to remove portions of the upper surface passivation sublayer 133 (e.g., Al2O3) exposed between the field plate dielectric spacers 660 while terminating on the intermediate surface passivation sublayer 132 (e.g., SiO2). For example, the exposed portions of the upper surface passivation sublayer 133 may be etched using a suitable technique (e.g., RIE, ICP etching, ECR etching).

[0150] According to one or more embodiments, plasma etching may first be used with an etchant that has low selectivity to the material of the upper surface passivation sublayer 133 and to the material of the field plate dielectric spacer 690. According to various embodiments, a suitable dry etching technique may use one or more of, for example, but not limited to, BCl3 or C4F8 chemistry or another suitable dry etching chemistry. In some embodiments where extremely precise etching is required, thermal or plasma ALE may be employed using, for example, NbF5 and CCl4 or Sn(acac)2 and HF pyridine. Alternatively, a suitable wet etching chemistry for etching the exposed portion of the upper surface passivation sublayer 133 may be used in other embodiments. Ideally, the etchant may completely remove the exposed portion of the upper surface passivation sublayer 133 without completely removing the field plate dielectric spacer 690.

[0151] Once formed, the field plate opening 990 is defined by a first (lowermost) horizontal bottom extent 992, the sidewalls of the upper surface passivation sublayer 133, the convex curved surfaces 194 of the left and right field plate dielectric spacers 690, and the left and right second (higher) horizontal bottom extents 996. The first horizontal bottom extent 992 is defined by the exposed surface of the middle surface passivation sublayer 132, and the bottom extent 992 is separated from the upper surface 112 of the semiconductor substrate 110 by a first thickness of dielectric material (e.g., the thickness of the middle surface passivation sublayer 132 and the lower surface passivation sublayer 131). Again, the convex curved surface 194 of the field plate dielectric spacer 690 extends from the surface passivation layer 130 to the upper surface of the lower ILD0 sublayer 135. Finally, a second horizontal bottom extent 996 is defined by the upper surface of the lower ILD0 sublayer 135 and is separated from the upper surface 112 by thicker dielectric material (e.g., the thickness of the surface passivation layer 130 and the lower ILD0 sublayer 135). In other words, each of the bottom extents 992, 996 of the field plate opening 990 has increasingly thicker underlying dielectric material (i.e., the horizontal bottom extents 992, 996 become increasingly farther from the upper surface 112 of the semiconductor substrate 110). It may be noted here that the field plate opening 990 formed in the manufacturing stage 900 has a lowermost horizontal bottom extent 992 that is recessed into the surface passivation layer 130 by substantially the thickness of the upper surface passivation sublayer 133.

[0152] According to an alternative embodiment, to fabricate the second embodiment of the device 100', an additional etching process may be performed to form the field plate opening 990' even further recessed into the surface passivation layer 130. More specifically, referring now to Fig.11 , and then performing one or more additional dry and / or wet etching processes to etch the portion of the intermediate surface passivation sublayer 132 exposed between the field plate dielectric spacers 690 while terminating on the lower surface passivation sublayer 131. Figure 7 The description of the manufacturing stage 700 of Detailed Description discusses in detail the details associated with the method of etching through the intermediate surface passivation sublayer 132, and those details are intended to be incorporated herein. Basically, the etchant used to etch the intermediate passivation sublayer 132 (e.g., SiO2) can selectively etch through the intermediate passivation sublayer 132 and then stop on the lower passivation sublayer 131 (i.e., sublayer 131 acts as an etch stop layer). For example, the intermediate passivation sublayer 132 can be dry etched using a suitable technique (e.g., RIE, ICP, ECR, or ALE) in combination with a fluorine-based chemistry (e.g., C3F6+H2 or CF4+H2) or another suitable dry etch chemistry that favors SiO2 and has high selectivity to Si3N4. In some embodiments, where the upper surface passivation sublayer 133, the intermediate ILD0 sublayer 136, and the spacer 690 are formed of the same material (e.g., SiO2), the etching of the upper surface passivation sublayer 133 can be integrated before the second etching step so that etching the intermediate ILD0 sublayer 136, the dielectric spacer 690, and the remaining portion of the intermediate surface passivation sublayer 132 can be combined into a single dry etching step using a suitable selective chemistry.

[0153] Once formed, the field plate opening 990' is defined by the first (lowest) horizontal bottom extent 992', the sidewalls of the upper surface passivation sublayer 133 and the intermediate surface passivation sublayer 132, the convex curved surfaces 194 of the left and right field plate dielectric spacers 690, and the left and right second (higher) horizontal bottom extents 996. The first horizontal bottom extent 992' is defined by the exposed surface of the lower surface passivation sublayer 131, and the bottom extent 992' is separated from the upper surface 112 of the semiconductor substrate 110 by a first thickness of dielectric material (e.g., the thickness of the lower surface passivation sublayer 131). The convex curved surface 194 of the field plate dielectric spacer 690 extends from the surface passivation layer 130 to the upper surface of the lower ILD0 sublayer 135. Finally, a second horizontal bottom extent 996 is defined by the upper surface of the lower ILD0 sublayer 135 and is separated from the upper surface 112 by thicker dielectric material (e.g., the thickness of the surface passivation layer 130 and the lower ILD0 sublayer 135). In other words, each of the bottom extents 992', 996 of the field plate opening 990' has an increasingly thicker underlying dielectric material (i.e., the horizontal bottom extents 992', 996 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). It may be noted here that the field plate opening 990' formed in the manufacturing stage 900' has a lowermost horizontal bottom extent 992' that is even further recessed into the surface passivation layer 130 than the field plate opening 990. More specifically, the field plate opening 990' is recessed into the surface passivation layer 130 by substantially the thickness of the upper surface passivation sublayer 133 and the intermediate surface passivation sublayer 132.

[0154] After performing only fabrication stage 900 or performing both fabrication stages 900 and 900', patterned photoresist layer 910 may be retained for use in the next fabrication stage (ie, Fig.12 or stage 1000 of 13).

[0155] Reference Figure 1 , 2 and 10, at block 218 and manufacturing stage 1000 ( Fig.12 ), for the first embodiment of the device 100, the multi-step field plate 190 is then formed by the field plate metal 1030 within the field plate opening 990. According to one or more embodiments, a lift-off process can be used to deposit the field plate metal 1030. More specifically, the patterned photoresist layer 910 is used as a mask to prevent the field plate metal 1030 from being deposited in areas other than the location of the field plate 190 to be formed during the lift-off process.

[0156] A field plate metal 1030 in the form of a conductive layer or stack of conductive layers may then be deposited within the field plate opening 990 and on the upper surface of the remaining portion of the patterned photoresist layer 910. According to one or more embodiments, the field plate metal 1030 may include one or more layers of Ti, TiW, TiAl, TiWN, Au, Al, Mo, Ni, polysilicon, Pt, Ta, combinations of these materials, or other suitable materials. The lowermost conductive layer may serve as an adhesion layer. In some embodiments, if etch selectivity is desired during subsequent processing steps, a thin layer of gold may be deposited on top of the conductive layer to provide a desired adhesion layer during those subsequent processing steps (e.g., before performing blocks 226 and 230). Fig.18 The photoresist layer 910 is then removed, thereby stripping the portion of the field plate metal 1030 that overlies the photoresist layer 910. The portion of the field plate metal 1030 that is deposited within the field plate opening remains, thereby forming a conductive field plate 190.

[0157] In an alternative embodiment, a lift-off process is used to form the conductive field plate 190, and a subtractive process may be used. More specifically, in the manufacturing stage 900 ( Fig.10 ), a field plate metal 1030 can be deposited directly over the surface of the device, and a photoresist mask (not shown) can be applied over the field plate metal 1030 and patterned to cover only those portions of the field plate metal 1030 that correspond to the field plates 190. Portions of the field plate metal 1030 not covered by the patterned photoresist mask can then be removed, and the patterned photoresist mask can then be removed.

[0158] As previously discussed, the SFP structure 190 has a stepped configuration including a first SFP 192 (SFP1) and a second SFP 196 (SFP2). The second SFP 196 may be arranged generally symmetrically (or asymmetrically) on both sides of the first SFP 192. In other words, one of the second SFPs 196 is located on the gate side of the SFP structure 190, and the other of the second SFPs 196 is located on the drain side of the SFP structure 190. In other words, the second SFP 196 protrudes upward and outward from the SFP1 192 on both sides (i.e., the gate side and the drain side) of the SFP1 192.

[0159] For SFP structure 190( Fig.12 ), the first SFP 192 has a bottom range (e.g., Fig.10The bottom range 992 of the second SFP 196 is separated from the upper surface 112 of the semiconductor substrate 110 by a first thickness of dielectric material (e.g., the thickness of the lower surface passivation sublayer 131 and the intermediate surface passivation sublayer 132). In essence, the SFP1 192 is recessed below the upper surface of the surface passivation layer 130 by the thickness of the upper surface passivation sublayer 133. The second SFP 196 has a bottom range (e.g., Fig.10 The bottom range 996 of the SFP 192 is separated from the upper surface 112 by thicker dielectric material (e.g., the thickness of the surface passivation layer 130 and the lower ILD0 sublayer 135). In other words, each of the bottom ranges of the SFP 192, 196 has increasingly thicker underlying dielectric material (i.e., the horizontal bottom ranges 992, 996 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). As previously mentioned, the second SFP 196 is provided to weaken the electric field at the edge of the first SFP 192 in order to ensure dielectric reliability and high breakdown voltage.

[0160] Reference Figure 1 , 2 and 13, at block 218 and manufacturing stage 1000 ( Fig.12 ), for the second embodiment of the device 100', the multi-step field plate 190' is manufactured at stage 1000' ( Fig.13 ) is formed in the field plate opening 990' by the field plate metal 1030. Fig.12 The description of the manufacturing stage 1000 of the present invention discusses in detail the details associated with the composition of the field plate metal 1030 and the method of depositing the field plate metal 1030, and those details are intended to be incorporated herein. In short, using a stripping process, the field plate metal 1030 for the field plate 190' can be deposited on the surface of the patterned photoresist layer 910 and through the opening 920 in the photoresist layer 910, and then the photoresist layer 910 can be removed. Alternatively, rather than using a stripping process to form the field plate 190', a subtractive process can be used. In either case, the field plate metal 1030 may include one or more layers of Ti, TiW, TiAl, TiWN, Au, Al, Mo, Ni, polysilicon, Pt, Ta, a combination of these materials, or other suitable materials. The portion of the field plate metal 1030 deposited within the field plate opening 990' is retained, thereby forming a conductive field plate 190'.

[0161] Again, in this second embodiment, the SFP structure 190' has a stepped configuration including a first SFP 192' (SFP1) and a second SFP 196 (SFP2). The second SFP 196 is generally symmetrically arranged on both sides of the SFP1 192'. The SFP1 192' has a bottom range (e.g., Fig.11The bottom range 992' of the semiconductor substrate 110 is separated from the upper surface 112 of the semiconductor substrate 110 by a first thickness of dielectric material (e.g., the thickness of the lower surface passivation sublayer 131). In essence, the SFP1 192' is recessed below the upper surface of the surface passivation layer 130 by a greater depth than the SFP1 192 (described in conjunction with the first embodiment of the device 100). Fig.12 ) or even greater depth. In the device 100', the second SFP 196 has a bottom range (e.g., Fig.11 The bottom range 996 of the SFP 192', 196 is separated from the upper surface 112 by thicker dielectric material (e.g., the thickness of the surface passivation layer 130 and the lower ILD0 sublayer 135). In other words, each of the bottom ranges of the SFP 192', 196 has increasingly thicker underlying dielectric material (i.e., the horizontal bottom ranges 992', 996 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). As previously mentioned, the second SFP 196 is provided to weaken the electric field at the edge of the SFP1 192', so as to ensure dielectric reliability and high breakdown voltage.

[0162] It should be noted here that the following manufacturing stages 1100, 1200, 1300 and 1400 are identical for the first and second embodiments of the apparatus 100, 100'. For the sake of brevity, these manufacturing stages will only be shown for the first embodiment of the apparatus 100. The finished versions of both the first and second embodiments of the apparatus 100, 100' will be shown in Fig.19 and 20 Shown in.

[0163] Reference Figure 1 , 2 , 14 and 15, at block 220 and manufacturing stage 1100 ( Fig.14 , 15 ), a multi-level gate electrode opening 1160 is formed. First, refer to Fig.14 To form the gate electrode opening 1160, a photoresist layer 1110 may be deposited over the source and drain contacts 141, 146, the upper surface of the ILD0 134, and the dielectric spacers 660, and a photoresist opening 1120 may be formed over the location where the gate electrode opening 1160 is to be formed. According to one or more embodiments, the width of the photoresist opening 1120 encompasses the two gate dielectric spacers 660 and extends over portions of the ILD0 134 beyond those spacers 660.

[0164] Reference Fig.15To form the gate electrode opening 1160, various features and layers are removed through the resist opening 1120. More specifically, several etching processes may be performed to remove the gate dielectric spacers 660 and portions of the surface passivation layer 130 exposed between the gate dielectric spacers 660. A portion of the upper sublayer 137 of the ILD0 134 exposed through the resist opening 1120 may also be removed in the process.

[0165] According to one or more embodiments, one or more first etching processes are performed to remove portions of the upper surface passivation sublayer 133 (e.g., Al2O3) exposed between the gate dielectric spacers 660. A plurality of dry and / or wet etching techniques may be used to etch these features. For example, according to various embodiments, RIE, ICP etching, ECR etching, and wet chemical etching may be used to etch these features.

[0166] According to one or more embodiments, plasma etching may first be used in combination with an etchant that selectively removes the material of the upper surface passivation sublayer 133 with selectivity to the material of the dielectric spacer 660 and to the material of the exposed portion of the ILD0 sublayer 137. Some loss of these materials may be tolerated. According to various embodiments, suitable dry etching techniques may use, for example, but not limited to, one or more of fluorine-based chemistries (e.g., C4F8 or CF4), chlorine-based chemistries (e.g., BCl3), or another suitable dry etching chemistry. Ideally, the etchant may completely remove the exposed portion of the upper surface passivation sublayer 133. Alternatively, a suitable wet etching chemistry may be used. Alternatively, some embodiments may employ ALE or plasma ALE. After exposing the intermediate passivation sublayer 132 (e.g., SiO2) between the gate dielectric spacers 660, the exposed portions of the intermediate passivation sublayer 132 can be removed during the same process used to remove the remaining portions of the gate dielectric spacers 660 (e.g., also SiO2) using a suitable dry or wet etching chemistry (e.g., HF plasma etching for SiO2 or HF-based wet etching).

[0167] These etching processes cause complete removal of the gate dielectric spacer 660 and the portions of the upper surface passivation sublayer 133 and the intermediate surface passivation sublayer 132 exposed between the gate dielectric spacer 660, so that a portion of the lower surface passivation sublayer 131 is exposed between the remaining portions of the upper surface passivation sublayer 133 and the intermediate surface passivation sublayer 132 that were protected by the gate dielectric spacer 660 in the previous etching step.

[0168] Then, an additional etching process may be performed to etch the exposed portion of the lower surface passivation sublayer 131 (e.g., Si3N4), while terminating on the upper surface 112 of the substrate 110. The additional etching process may also be configured to remove all or part of the exposed portion of the upper ILD0 sublayer 137 (e.g., Si3N4), but should be configured to terminate on the middle ILD0 sublayer 136. Some portions of the upper ILD0 sublayer 137 may be retained. In order to etch the exposed portion of the lower surface passivation sublayer 131 and the exposed portion of the upper ILD0 sublayer 137, RIE, ICP etching, ECR etching and / or wet chemical etching may be used. Suitable dry etching techniques may use, for example, but not limited to, one or more of SF6+O2, CF4+O2, NF3+N2+O2+H2 or other suitable chemicals. Suitable wet etching chemicals include, for example, but not limited to, HF, buffered HF or other suitable wet etchants.

[0169] Once formed, the gate electrode opening 1160 has a first (lowest) horizontal bottom extent 1162, left and right second (middle) horizontal bottom extents 1164, and left and right third (higher) horizontal bottom extents 1166. The first horizontal bottom extent 1162 is defined by an exposed portion of the upper surface 112 of the semiconductor substrate 110. The second horizontal bottom extent 1164 is defined by the surface of the upper surface passivation sublayer 133 and is separated from the upper surface 112 by a first thickness of dielectric material (e.g., the thickness of the surface passivation layer 130). Finally, the third horizontal bottom extent 1166 is defined by the surface of the middle ILD0 sublayer 136 and is separated from the upper surface 112 by a thicker dielectric material (e.g., the thickness of the surface passivation layer 130, the lower ILD0 sublayer 135, the middle ILD0 sublayer 136, and the possible remaining portion of the upper ILD0 sublayer 137). In other words, each of the bottom extents 1164, 1166 of the gate electrode opening 1160 has an increasingly thicker underlying dielectric material (i.e., the horizontal bottom extents 1164, 1166 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). The patterned photoresist layer 1110 may be retained for use in the next manufacturing stage (i.e., Fig.16 stage 1200).

[0170] Reference Figure 1 , 2 and 16, at block 222 and manufacturing stage 1200 ( Fig.16), and then forming a multi-step gate electrode 160. According to one or more embodiments, a stripping resist process may be used to form the gate electrode 160. A previously deposited and patterned photoresist layer 1110 may be utilized for this process. A gate metal layer 1210 is deposited over the photoresist layer 1110 and into the gate electrode opening 1160. In one or more embodiments, the various layers of the gate metal layer 1210 may be deposited by evaporation, sputtering, PVD, ALD, or other suitable deposition techniques.

[0171] The conductive layer of the gate metal layer 1210 may include Au, Ag, Al, Cu, Ti, Ni, Pt, and / or other substantially conductive materials. In essence, a Schottky contact is formed in the gate channel (i.e., the portion of the gate electrode 160 closest to the upper surface 112 of the semiconductor substrate 110). The thickness of the conductive layer of the gate metal layer 1210 may be between about 1000 angstroms and about 20,000 angstroms, but other thickness values ​​may be used. According to one or more embodiments, the thickness of the gate metal layer 1210 is greater than the cumulative thickness of the surface passivation layer 130 and the ILD0 134.

[0172] Once the gate metal layer 1210 is deposited, a stripping process is then performed to remove the photoresist layer 1110 and the portion of the gate metal layer 1210 deposited on the photoresist layer 1110 while leaving the portion of the gate metal layer 1210 deposited into the gate electrode opening 1160 intact.

[0173] In an alternative embodiment, rather than using a lift-off process to form gate electrode 160, a subtractive process may be used. More specifically, during manufacturing stage 1100 ( Fig.15 ), a gate metal layer 1210 may be deposited directly over the surface of the device, and a photoresist mask (not shown) may be applied over the gate metal layer 1210 and patterned to cover only those portions of the gate metal layer 1210 that correspond to the gate electrode 160. Portions of the gate metal layer 1210 not covered by the patterned photoresist mask may then be removed, and the patterned photoresist mask removed.

[0174] As previously discussed, the gate electrode 160 has a stepped configuration including the gate channel portion 162 and the first GFP 164 and the second GFP 166 that are generally symmetrically (or asymmetrically) arranged on both sides of the gate channel portion 162. In other words, one of the first GFPs 164 is located on the drain side of the gate electrode 160, and the other of the first GFPs 164 is located on the source side of the gate electrode 160. Similarly, one of the second GFPs 166 is located on the drain side of the gate electrode 160, and the other of the second GFPs 166 is located on the source side of the gate electrode 160. In other words, the first GFP 164 and the second GFP 166 protrude upward and outward from the gate channel portion 162 on both sides (i.e., the source side and the drain side) of the gate electrode 160.

[0175] The gate channel portion 162 is located at the gate channel and has a horizontal bottom extent that defines the lowermost portion of the gate electrode 160 (i.e., the portion that contacts or is closest to the upper substrate surface 112). The first GFP 164 (GFP1) is formed integrally with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extent of the gate channel portion 162. More specifically, GFP1 164 overlies and contacts the upper surface of the surface passivation sublayer 133. The second GFP 166 (GFP2) is also formed integrally with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extents of both the gate channel portion 162 and GFP1 164. More specifically, GFP2 166 overlies and contacts the upper surface of the intermediate ILD0 sublayer 136. As can be seen in FIG. Fig.16 As can be seen in FIG. 1 , the gate electrode 160 has a relatively large cross-sectional area, which can result in a relatively low gate resistance R G , without causing the gate-drain capacitance C GD or gate-source capacitance C GS significant increase.

[0176] It may be noted here that in one or more embodiments, the bottom extent of SFP1 192 (or SFP1 192') is recessed relative to the bottom extent of GFP1 164 (i.e., SFP1 192 (and SFP1 192') has a thinner underlying dielectric than the dielectric below GFP1 164). In addition, the bottom extent of SFP1 192 (or SFP 192') and SFP2 196 may be recessed relative to the bottom extent of GFP2 166 (i.e., both SFP1 192 and SFP2 196 have a thinner underlying dielectric than the dielectric below GFP2 166). This may cause C GD The lower gate-drain capacitance C GDThis can also lead to an increase in the gain of the device 100 (or device 100 ′).

[0177] Reference Figure 1 , 2 and 17, at block 224 and manufacturing stage 1300 ( Fig.17 ), a second interlayer dielectric (ILD1) 150 is deposited over ILD0 134, gate electrode 160, and field plate 190 (or 190'). In various embodiments, the dielectric material for ILD1 150 may be the same as or different from the dielectric material for ILD0 134. Preferably, the dielectric material for ILD1 150 is a low-k dielectric material different from the material of ILD0 top sublayer 137 in order to provide etching selectivity. For example, the material for ILD1 150 may be selected from SiO2, organic silicate glass, porous SiO2, Si3N4, SiON, HfO2, Al2O3 or AlN and other suitable materials. ILD1 150 may be formed using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. In various embodiments, ILD1 150 may have a thickness in a range of about 0.2 microns to about 2.0 microns, although ILD1 150 may also be thinner or thicker.

[0178] Reference Figure 1 , 2 and 18, at block 226 and manufacturing stage 1400 ( Fig.18 ), a selective etching process is used to form an opening 1490 through ILD1 150 to expose the field plate 190 (or 190'). At the same time, an opening is also formed through ILD1 150 to expose the source ohmic contact 141 and the drain ohmic contact 146, but Fig.18 Those openings are not shown in FIG. 1 because they are located at Fig.18 14. For the location of the openings through ILD1 150 to the source ohmic contact 141 and the drain ohmic contact 146, see Figure 1 .

[0179] To form field plate opening 1490, photoresist layer 1410 is applied over ILD1 150, and photoresist layer 1410 is processed and patterned to form photoresist opening 1420 having a first side 1421 aligned along the width of field plate 190 (or 190'), and a second side 1422 aligned over a point along ILD0 134 to the right of the rightmost edge of field plate 190 (or 190'). In addition, source opening and drain opening (see Figure 1) is formed through the photoresist layer 1410 above the source contact 141 and the drain contact 146.

[0180] The portion of ILD1 150 exposed by opening 1420 is then etched through opening 1420 to remove the exposed portion of ILD1 150. The etching process continues until field plate 190 (or 190') is fully exposed and reaches portion 1434 of the upper surface of ILD0 134 (i.e., the etching process terminates on the upper surface of ILD0 134). This process creates an unfilled field plate opening 1490 above field plate 190. The bottom extent of field plate opening 1490 is defined by the upper surface of field plate 190 (or 190') and exposed portion 1434 of ILD0 134.

[0181] A variety of dry and / or wet etching techniques may be used to etch the opening through the ILD1 150. For example, according to various embodiments, the ILD1 150 may be etched using RIE, ICP etching, ECR etching, and wet chemical etching.

[0182] Reference Figure 1 , 2 , 19 and 20, at block 228 and manufacturing stage 1500 ( Fig.19 ) and 1500'( Fig. 20 ), remove the photoresist 1410 ( Fig.18 ), and depositing metallization over ILD1150 (and into the source opening, drain opening, and field plate opening through ILD1150) to form source electrode 140 ( Figure 1 )、Drain electrode 145( Figure 1 )、Source metallization 148( Figure 1 ) and drain metallization 149 ( Figure 1 ). It should be noted here that Fig.19 Corresponding to the first embodiment of the device 100, the first embodiment of the device 100 comprises a first embodiment of the field plate 190, and Fig. 20 Corresponding to the second embodiment of the device 100 ′, the second embodiment of the device 100 ′ comprises a second embodiment of the field plate 190 ′.

[0183] In any embodiment of the device 100 or 100', the field plate opening 1490 ( Fig.18 ), source metallization 148 is deposited to contact field plate 190 ( Fig.19 ) or field plate 190'( Fig. 20 ) and extends over ILD1 150 to source contact 141 to provide a conductive field plate to source connection. In addition, source metallization 148 contacts a portion 1434 of the upper surface of ILD0 134 ( Fig.18), which forms a third source connection field plate SFP3 198 having a horizontal bottom extent extending beyond the right edge of the field plate 190 or 190'. According to one or more embodiments, SFP3 198 is separated from the upper surface 112 of the semiconductor substrate 110 by an even thicker dielectric (e.g., the cumulative thickness of the surface passivation layer 130 and the ILD0 134) than the dielectrics below the other field plates (SFP1 192, SFP2 196). In addition, SFP3 198 is higher than GFP2 166 (i.e., SFP3 198 has a thicker underlying dielectric than GFP2 166). Further, the source metallization 148 contacts the upper surface of the ILD1 150, which forms a fourth source connection field plate SFP4 199 having a horizontal bottom extent extending beyond the right edge of the field plate 190 or 190'. According to one or more embodiments, SFP4 199 is separated from the upper surface 112 of the semiconductor substrate 110 by an even thicker dielectric, such as the cumulative thickness of the surface passivation layer 130, ILD0 134, and ILD1 150. This taller SFP4 199 may be particularly beneficial for high voltage devices.

[0184] For example, for forming the source electrode 140 ( Figure 1 )、Drain electrode 145( Figure 1 ) and source metallization 148 and drain metallization 149 ( Figure 1 ) may be blanket deposited and etched, or may be deposited using a lift-off process. More specifically, a patterned multilayer conductive stack may be formed over ILD1 150. According to various embodiments, the conductive stack may include one or more metal layers and / or other suitable materials. In some embodiments, the first layer within the multilayer stack may include an adhesion layer (e.g., TiW or another suitable material), and additional layers may include gold (Au) and other suitable metals.

[0185] Reference again Figure 1 In block 230, the final passivation layers 170 and 180 ( Figure 1 ) to complete the device 100 or 100'. For example, the passivation layer 170 can be formed of Si3N4 or another suitable material, and the passivation layer 180 can be formed of polybenzoxazole (PBO) or another suitable material. The passivation layers 170, 180 can be deposited, for example, using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. Additional patterned conductive layers and dielectric layers can be formed over the passivation layers 170, 180, openings can be formed through each of the dielectric layers, and one or more intervening patterned conductive layers can be formed to enable electrical connectivity with other device elements.

[0186] An embodiment of a semiconductor device includes a semiconductor substrate having an upper surface and a channel, and a source electrode and a drain electrode above the upper surface of the semiconductor substrate. The source electrode and the drain electrode are electrically coupled to the channel, and the channel extends between the source electrode and the drain electrode. The device also includes a surface passivation layer above the upper surface of the semiconductor substrate, between the source electrode and the drain electrode, and a first interlayer dielectric (ILD0) above the upper surface of the surface passivation layer. A gate electrode is included above the upper surface of the semiconductor substrate, between the source electrode and the drain electrode. The gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom range overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom range higher than the first horizontal bottom range. A conductive field plate is included above the upper surface of the semiconductor substrate, between the gate electrode and the drain electrode. The conductive field plate includes a first field plate having a third horizontal bottom extent recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent higher than the first horizontal bottom extent of the first gate field plate.

[0187] According to another embodiment, the surface passivation layer includes a lower surface passivation sublayer formed on the upper surface of the semiconductor substrate, an intermediate surface passivation sublayer formed on the lower surface passivation sublayer, and an upper surface passivation sublayer formed on the intermediate surface passivation sublayer and defining an upper surface of the surface passivation layer. The third horizontal bottom range of the first field plate is recessed below the upper surface of the surface passivation layer.

[0188] According to another further embodiment, the first gate field plate and the second gate field plate protrude upward and outward from the gate channel portion, and the second field plate protrudes upward and outward from the first field plate.

[0189] According to yet another further embodiment, the first gate field plate and the second gate field plate are located on the drain side of the gate electrode, and the gate electrode additionally comprises another first gate field plate and another second gate field plate located on the source side of the gate electrode. Additionally, the second field plate is located on the gate side of the conductive field plate, and the conductive field plate additionally comprises another second field plate on the drain side of the conductive field plate.

[0190] An embodiment of a method for manufacturing a semiconductor device includes: providing a semiconductor substrate having an upper surface and a channel; forming a surface passivation layer above the upper surface of the semiconductor substrate; forming a first interlayer dielectric (ILD0) above the upper surface of the surface passivation layer; and forming a source electrode and a drain electrode above the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel, and the channel extends between the source electrode and the drain electrode. The method further includes forming a gate electrode between the source electrode and the drain electrode above the upper surface of the semiconductor substrate. The gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent. The method further includes forming a conductive field plate between the gate electrode and the drain electrode above the upper surface of the semiconductor substrate. The conductive field plate includes a first field plate having a third horizontal bottom extent recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent higher than the first horizontal bottom extent of the first gate field plate.

[0191] According to another embodiment, forming the surface passivation layer includes forming a lower surface passivation sublayer on the upper surface of the semiconductor substrate, forming an intermediate surface passivation sublayer on the lower surface passivation sublayer, and forming an upper surface passivation sublayer on the intermediate surface passivation sublayer, wherein the upper surface of the upper surface passivation sublayer defines the upper surface of the surface passivation layer.

[0192] According to another further embodiment, the method further comprises simultaneously forming a gate electrode opening and a field plate opening through the ILD0, and forming a field plate dielectric spacer on a sidewall of the ILD0 in the field plate opening. The method further comprises removing the upper surface passivation sublayer between the field plate dielectric spacers to expose a portion of an upper surface of the intermediate surface passivation sublayer. Forming the conductive field plate comprises forming the first field plate on the portion of the upper surface of the intermediate surface passivation sublayer between the field plate dielectric spacers.

[0193] According to yet another further embodiment, the method further comprises simultaneously forming a gate electrode opening and a field plate opening through the ILD0, and forming a field plate dielectric spacer on a sidewall of the ILD0 in the field plate opening. The method further comprises removing the upper surface passivation sublayer and the intermediate surface passivation sublayer between the field plate dielectric spacers to expose a portion of an upper surface of the lower surface passivation sublayer. Forming the conductive field plate comprises forming the first field plate on the portion of the upper surface of the lower surface passivation sublayer between the field plate dielectric spacers.

[0194] The foregoing detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or example is not necessarily to be construed as being preferred or superior to other embodiments. In addition, it is not intended to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology, or specific embodiments.

[0195] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for implementing the described one or more embodiments to those skilled in the art. It should be understood that various changes may be made to the function and arrangement of elements without departing from the scope defined by the claims, which scope is included in known equivalents and foreseeable equivalents at the time of filing this patent application.

[0196] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference purposes only, and therefore these terms are not intended to be limiting, and unless the context clearly indicates, the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order.

[0197] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically joined. Likewise, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically joined. Thus, while the schematic diagrams shown in the drawings depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate having an upper surface and a channel; a source electrode and a drain electrode, the source electrode and the drain electrode being above the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode; a surface passivation layer, the surface passivation layer being above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode; a first interlayer dielectric (ILD0) above an upper surface of the surface passivation layer; a gate electrode above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; a conductive field plate above the upper surface of the semiconductor substrate and between the gate electrode and the drain electrode, wherein the conductive field plate comprises a first field plate having a third horizontal bottom extent recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent higher than the first horizontal bottom extent of the first gate field plate; as well as A field plate dielectric spacer is on the upper surface of the surface passivation layer between the third horizontal bottom extent of the first field plate and the fourth horizontal bottom extent of the second field plate.

2. The semiconductor device according to claim 1, wherein: The surface passivation layer includes a lower surface passivation sublayer formed on the upper surface of the semiconductor substrate, an intermediate surface passivation sublayer formed on the lower surface passivation sublayer, and an upper surface passivation sublayer formed on the intermediate surface passivation sublayer and defining the upper surface of the surface passivation layer.

3. The semiconductor device according to claim 2, wherein: The lower surface passivation sublayer is formed of silicon nitride; The intermediate surface passivation sublayer is formed of silicon dioxide; and The upper surface passivation sublayer is formed of a material selected from aluminum oxide, aluminum nitride and hafnium oxide.

4. The semiconductor device according to claim 2, wherein: The third horizontal bottom extent of the first field plate contacts an upper surface of the intermediate surface passivation sublayer.

5. The semiconductor device according to claim 2, wherein: The third horizontal bottom extent of the first field plate contacts an upper surface of the lower surface passivation sublayer.

6. The semiconductor device according to claim 1, wherein: The ILD0 includes a lower ILD0 sublayer on the upper surface of the surface passivation layer, and a middle ILD0 sublayer on the upper surface of the lower ILD0 sublayer; The fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sublayer; and The second horizontal bottom extent of the second gate field plate overlies an upper surface of the middle ILD0 sub-layer.

7. The semiconductor device according to claim 6, wherein: The field plate dielectric spacer has an outer surface extending from the upper surface of the surface passivation layer to an upper surface of the lower ILD0 sub-layer.

8. The semiconductor device according to claim 1, wherein: The conductive field plates additionally include a third field plate having a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.

9. The semiconductor device according to claim 1, wherein: The first field plate and the second field plate are formed of a field plate metal; and The semiconductor device additionally includes a source metallization extending from the field plate metal across the gate electrode to a source contact.

10. A method for manufacturing a semiconductor device, characterized in that: The method comprises: providing a semiconductor substrate having an upper surface and a channel; forming a surface passivation layer over the upper surface of the semiconductor substrate; forming a first interlayer dielectric (ILD0) over an upper surface of the surface passivation layer; forming a source electrode and a drain electrode over the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode; forming a gate electrode over the upper surface of the semiconductor substrate and between the source electrode and the drain electrode, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; and A conductive field plate is formed above the upper surface of the semiconductor substrate and between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate having a third horizontal bottom extent recessed below the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent higher than the first horizontal bottom extent of the first gate field plate.

Images