Capacitive coupling gated junction field effect transistor

Abstract

The invention provides a capacitive coupling grid-control junction field effect transistor. The capacitive coupling grid-control junction field effect transistor comprises a substrate, an epitaxial layer and a drain electrode, the groove is formed downwards from the upper surface of the epitaxial layer; the groove-type gate of the first doping type is formed on the inner wall and the bottom of the groove; the first source electrode is used for being connected with a source voltage and is formed on the bottom of the gate, and the gate and the first source electrode are connected so that the two have the same potential; the groove type dielectric layer is formed on the first source electrode; the inner wall and the bottom of the dielectric layer are filled with the gate electrode; the source regions of the first doping type are at least arranged on one side of the gate at intervals; the source region and the first source electrode are respectively connected with source voltage; the channel region of the second doping type is formed between the source region and the gate; wherein the structures below the source region, the channel region and the gate are used as gate surrounding structures of the second doping type, and the gate and the gate surrounding structures form PN junctions. According to the invention, the technical problem of large switching loss is solved, and the conduction capability of the body diode is also improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a capacitively coupled gate-controlled junction field effect transistor. Background Art

[0002] Silicon carbide devices have the advantages of high voltage resistance, low on-resistance, faster switching speed, higher operating temperature, heat dissipation and good radiation resistance, and have been widely used in power electronic circuits. Silicon carbide devices include MOSFET and JFET. As a three-port device similar to MOSFET, the working principle of JFET device is to use gate voltage to control the reverse bias of PN, so as to achieve the purpose of controlling the opening and closing of the channel. It has the advantages of low noise, small size, and high-frequency response. JFET devices made of silicon carbide materials can also be used in high-power application scenarios, such as new energy vehicles, high-voltage power transmission, etc.

[0003] Silicon carbide capacitive-coupled gate-controlled JFET solves the problem that JFET devices cannot be used in power applications (the controlled gate voltage is too small), and also solves the gate oxide reliability problem of SiC MOSFET, becoming a key focus of power device research and development.

[0004] Now the vertical trench type capacitive coupled gate controlled junction field effect transistor of patent CN117613098B is as follows Figure 1 As shown, substrate 1-1, epitaxial layer 1-2, second doping type ohmic contact region 1-3, source region 1-4, channel 1-5, gate 1-6, dielectric layer 1-7, coupling capacitor upper electrode 1-8, source 1-9, drain 1-10.

[0005] A power device is actually a switch, so in the application process, switching loss is something that cannot be ignored. The original vertical trench capacitive-coupled gate-controlled junction field-effect transistor did not take this issue into consideration. Setting the gate will result in a larger Miller platform capacitance and increased switching loss of the device.

[0006] The device needs to achieve a higher withstand voltage at the same epitaxial concentration to improve the reliability of the device, and the original device BV (breakdown voltage) needs to be improved from other design aspects.

[0007] Therefore, the switching loss of the conventional capacitively coupled gate-controlled junction field effect transistor is relatively large, which is a technical problem that needs to be urgently solved by those skilled in the art.

[0008] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0009] The embodiment of the present application provides a capacitively coupled gate-controlled junction field effect transistor to solve the technical problem of large switching loss in traditional capacitively coupled gate-controlled junction field effect transistors.

[0010] The present application provides a capacitively coupled gate-controlled junction field effect transistor, comprising:

[0011] A substrate, an epitaxial layer of a second doping type, and a drain, wherein the epitaxial layer is located on the substrate, and the drain is located on the back side of the substrate;

[0012] A groove is formed downward from the upper surface of the epitaxial layer;

[0013] A trench-type gate of a first doping type is formed on the inner wall and bottom of the trench;

[0014] A first source electrode for connecting a source voltage, formed on the bottom of the gate, the gate and the first source electrode are connected so that they have the same potential;

[0015] A trench-type dielectric layer formed on the first source electrode;

[0016] A gate electrode filled on the inner wall and bottom of the dielectric layer;

[0017] A source region of a first doping type is arranged at least at one side of the gate; the source region and the first source electrode are respectively connected to a source voltage;

[0018] A channel region of a second doping type formed between the source region and the gate;

[0019] The source region, the channel region, and the structure under the gate serve as a gate surrounding structure of the second doping type, and the gate and the gate surrounding structure form a PN junction.

[0020] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0021] The gate-drain capacitance Cgd (i.e., Miller platform capacitance) of the capacitively coupled gate-controlled junction field effect transistor of the prior art is relatively large. The capacitively coupled gate-controlled junction field effect transistor of the present application converts part of the Miller capacitance into gate-source capacitance Cgs and drain-source capacitance Cds. Wherein, the gate-source capacitance Cgs is the parasitic capacitance between the gate and the source, and the drain-source capacitance Cds is the parasitic capacitance between the drain and the source. Compared with the prior art, the gate-drain capacitance Cgd of the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is relatively small, that is, the gate-drain capacitance Cgd that needs to be overcome in the process of turning on and off in the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is relatively small, with faster turn-on and turn-off speeds, and also with smaller switching losses, and the introduction of the built-in first source electrode also improves the conduction capability of the body diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0023] Figure 1 It is a schematic diagram of a vertical trench capacitively coupled gate-controlled junction field effect transistor of patent CN117613098B;

[0024] Figure 2-1 A schematic diagram of a capacitively coupled gate-controlled junction field effect transistor being turned on in an embodiment of the present application;

[0025] Figure 2-2 A schematic diagram of turning off a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0026] Figure 3 A schematic diagram of completing step 2 of the method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0027] Figure 4 A schematic diagram of completing step 5 of the method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0028] Figure 5 A schematic diagram of completing step 7 of the method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0029] Figure 6 A schematic diagram of completing step 8 of the method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0030] Figure 7 A schematic diagram of completing step 9 of the method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0031] Figure 8 A schematic diagram of completing step 10 of the method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0032] Fig. 9 A simulation diagram of the on-state current density of the capacitively coupled gate-controlled junction field effect transistor during forward conduction according to an embodiment of the present application;

[0033] Fig.10 is a curve showing the change of the drain-source current Ids with the drain-source voltage Vds when the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is forward-conducted;

[0034] Fig.11 A simulation diagram of the electric field distribution under the breakdown voltage of the capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0035] Fig.12 is a curve showing the change of the drain-source current Ids with the drain-source voltage Vds at the breakdown voltage of the capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0036] Fig.13 A simulation diagram of a current path of a capacitor-coupled gate-controlled junction field effect transistor turning off a diode according to an embodiment of the present application;

[0037] Fig.14 1 is a curve showing the change of the source-current Ids of the capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application as a inverse of the source-drain voltage Vsd.

[0038] Reference numerals:

[0039] In the background technology:

[0040] Substrate 1-1, epitaxial layer 1-2, second doping type ohmic contact region 1-3, source region 1-4, channel 1-5,

[0041] Grid 1-6,

[0042] Dielectric layer 1-7, coupling capacitor upper electrode 1-8, source electrode 1-9, drain electrode 1-10;

[0043] This application:

[0044] Source region 1, first doping type source contact region 2, second doping type source contact region 3,

[0045] Channel region 4, gate 5, dielectric layer 6, gate electrode 7, current guiding layer 8, first source electrode 9,

[0046] Epitaxial layer 10, substrate 11, drain 12, second source electrode 13,

[0047] The current guiding layer foundation is 8-0, the source region foundation is 1-0, and the channel region foundation is 4-0. DETAILED DESCRIPTION

[0048] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0049] Embodiment 1

[0050] like Figure 2-1 and Figure 2-2 As shown, the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application includes:

[0051] A substrate 11, an epitaxial layer of a second doping type, and a drain 12, wherein the epitaxial layer is located on the substrate, and the drain is located on the back side of the substrate;

[0052] A groove is formed downward from the upper surface of the epitaxial layer;

[0053] A trench-type gate 5 of a first doping type, formed on the inner wall and bottom of the trench;

[0054] A first source electrode 9 for connecting a source voltage is formed on the bottom of the gate 5, and the gate 5 and the first source electrode 9 are connected so that they have the same potential;

[0055] A trench-type dielectric layer 6 is formed on the first source electrode 9;

[0056] A gate electrode 7 for connecting a gate voltage, filled on the inner wall and bottom of the dielectric layer;

[0057] A source region 1 of a first doping type is arranged at least at one side of the gate 5; the source region 1 and the first source electrode 9 are respectively connected to a source voltage;

[0058] A channel region 4 of a second doping type, formed between the source region 1 and the gate 5;

[0059] The source region 1 , the channel region 4 , and the structure under the gate 5 serve as a gate surrounding structure of the second doping type, and the gate 5 and the gate surrounding structure form a PN junction.

[0060] In implementation, the source region 1 and the structure below the source region 1 form a PN junction. Specifically, there are at least two implementation methods:

[0061] A first implementation manner: the epitaxial layer is formed from the source region 1 to the substrate 11 , and a PN junction is formed between the source region 1 and a portion of the epitaxial layer located below the source region 1 .

[0062] The second implementation method: The field effect transistor also includes:

[0063] A current guiding layer 8 of the second doping type is formed in the epitaxial layer below the source region 1 , the channel region 4 and the gate 5 ; correspondingly, the source region 1 and the current guiding layer 8 form a PN junction.

[0064] In implementation, there are two source regions 1 of the first doping type, and the two source regions 1 of the first doping type are respectively arranged at intervals on both sides of the gate 5;

[0065] There are two channel regions 4 , which are formed between two source regions 1 and the channel regions 4 , respectively.

[0066] The gate-drain capacitance Cgd (i.e., Miller platform capacitance) of the capacitively coupled gate-controlled junction field effect transistor of the prior art is relatively large. The capacitively coupled gate-controlled junction field effect transistor of the present application converts part of the Miller capacitance into gate-source capacitance Cgs and drain-source capacitance Cds. Wherein, the gate-source capacitance Cgs is the parasitic capacitance between the gate and the source, and the drain-source capacitance Cds is the parasitic capacitance between the drain and the source. Compared with the prior art, the gate-drain capacitance Cgd of the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is relatively small, that is, the gate-drain capacitance Cgd that needs to be overcome in the process of turning on and off in the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is relatively small, with faster turn-on and turn-off speeds, and also with smaller switching losses. The introduction of the built-in first source electrode also improves the conduction capability of the body diode.

[0067] In the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the source region 1 is connected to the source voltage, and the first source electrode 9 is also connected to the source voltage. Since the gate 5 and the first source electrode 9 are connected, the two have the same potential. In this way, the gate 5 is no longer in a floating state, but has the same potential as the first source electrode 9.

[0068] When the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off, the path of the diode current is as follows: Figure 2-2 As shown:

[0069] A diode current path ① formed by a PN junction formed by the source region 1 and the structure below the source region 1;

[0070] A diode current path ② formed by a PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5;

[0071] The bottom of the gate 5 and the structure outside the bottom of the gate 5 form a diode current path ③.

[0072] In diode current path ② and diode current path ③, since gate 5 and first source electrode 9 have the same potential, that is, both are connected to the source voltage; the structure outside the side wall of gate 5 and the structure outside the bottom of gate 5 are connected to the drain electrode, which is achieved through the epitaxial layer 10, substrate 11 and drain 12.

[0073] In the diode current path ①, the source region 1 is connected to the source voltage, and the structure below the source region 1 is connected to the drain electrode, which is achieved by connecting the epitaxial layer 10, the substrate 11 and the drain 12.

[0074] Therefore, there are more paths for the diode current, and not only the body diode (i.e., the PN junction formed by the source region 1 and the structure below the source region 1) can withstand the voltage, but also the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5, and the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5 can withstand the voltage. In this way, the requirement for the withstand voltage of the body diode is reduced.

[0075] In the field of semiconductor technology, under certain temperature conditions, the minority carrier concentration determined by intrinsic excitation is constant, so the drift current formed by the minority carriers is constant and basically has nothing to do with the magnitude of the negative pressure. This current is also called the diode current. That is, the total diode current in this application has nothing to do with the magnitude of the negative pressure. The total diode current is divided into more separate diode current paths.

[0076] When the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off,

[0077] The depletion region of the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5 is widened, reducing the electric field at the channel region 4 to achieve lateral depletion to withstand a larger potential difference;

[0078] The depletion region of the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5 is widened, reducing the electric field at the channel region 4 to achieve vertical depletion to withstand a larger potential difference.

[0079] That is, the depletion region of the PN junction at the lower corner of the gate 5 (the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5, and the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5) is wider. At the same time, the electric field falling on the epitaxial layer is more balanced, and the breakdown voltage of the device can also be effectively improved.

[0080] When the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off,

[0081] The depletion region of the PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5 is widened, reducing the electric field at the channel region 4 to achieve lateral depletion to withstand a larger potential difference;

[0082] The depletion region of the PN junction formed by the bottom of the gate 5 and the structure outside the bottom of the gate 5 is widened, reducing the electric field at the channel region 4 to achieve vertical depletion to withstand a larger potential difference.

[0083] In implementation, the source region 1, the channel region 4, and the gate 5 form a first JFET structure, the first JFET structure is controlled by the gate 5, and the opening and closing of the channel region 4 is controlled by the depletion region of the PN junction formed by the channel region 4 and the gate 5;

[0084] The PN junction formed by the channel region 4 and the gate 5, the dielectric layer 6 and the gate electrode 7 form a second JFET structure with capacitive coupling gate control. The second JFET structure is indirectly controlled by the gate electrode 7. The gate electrode 7 indirectly controls the depletion region of the PN junction formed by the channel region 4 and the gate 5 through the dielectric layer 6, thereby opening and closing the channel region 4.

[0085] In this way, when the capacitively coupled gate-controlled junction field effect transistor is turned on, Figure 2-1 As shown, the gate 5 in the first JFET structure and the depletion region of the PN junction formed by the gate electrode 7 in the second JFET structure together with the channel region 4 and the gate 5 shrink, so that the field effect transistor is quickly forward-conducted.

[0086] When the capacitively coupled gate-controlled junction field effect transistor is turned off, and the PN junction formed by the source region 1 and the channel region 4, and the PN junction formed by the channel region 4 and the gate 5 are reverse biased, the channel region is depleted, the device is turned off, and the PN junction lowers the potential at the bottom of the channel region 4, thereby reducing the leakage current.

[0087] In addition, the gate 5 is outside the dielectric layer 6, and the dielectric layer 6 wraps the gate 5. This solves the reliability problem caused by the gate oxide layer, and there will be no electrical characteristic drift like MOSFET, such as VTH drift; there will be no stress breakdown problem of the gate oxide layer under long-term stress, and the reliability is greatly improved.

[0088] That is, the first JFET structure is directly controlled by the gate 5 , and the control stability is relatively high. Compared with the background technology, in the present application, the first JFET structure is directly controlled by the gate 5 , and the second JFET structure is indirectly controlled by the gate electrode 7 .

[0089] In implementation, such as Figure 2-1 and Figure 2-2 As shown, the doping concentration of the current guiding layer 8 is greater than the doping concentration of the epitaxial layer 10;

[0090] The PN junction formed by the gate 5 and the structure surrounding the gate is specifically a PN junction formed by the current guiding layer 8 and the gate 5 .

[0091] The current guiding layer 8 makes the on-resistance small.

[0092] In implementation, such as Figure 2-1 and Figure 2-2 As shown, the upper surface of the first source electrode 9 is lower than the bottom of the channel region 4 , so that the bottom of the gate 5 is lower than the bottom of the channel region 4 .

[0093] In implementation, such as Figure 2-1 and Figure 2-2 As shown, the bottom surface of the source region 1 is lower than the bottom surface of the channel region 4 .

[0094] That is, the lower surface of the gate 5 and the lower surface of the source region 1 are both lower than the lower surface of the channel region 4. This facilitates pinch-off of the first JFET structure formed by the source region 1, the channel region 4, and the gate 5, thereby controlling the opening and closing of the channel region 4.

[0095] In implementation, such as Figure 2-1 and Figure 2-2 As shown, the field effect transistor also includes:

[0096] Two first doping type source contact regions 2, respectively connected to the two source regions 1;

[0097] Two second doping type source contact regions 3 are respectively connected to the two channel regions 4, and the second doping type source contact region 3 and the first doping type source contact region 2 on the same side are connected;

[0098] Two second source electrodes 13 are respectively located on two first doping type source contact regions 2 , and the second source electrode 13 on the same side connects the first doping type source contact region 2 and the second doping type source contact region 3 on the same side.

[0099] The first source electrode 9 is connected to the second source electrode 13 , so that the first source electrode 9 is connected to the source voltage.

[0100] Fig. 9 It is a simulation diagram of the on-state current density of the capacitively coupled gate-controlled junction field effect transistor during forward conduction according to an embodiment of the present application.

[0101] Fig.10 4 is a curve showing the change of the drain-source current Ids with the drain-source voltage Vds during forward conduction of the capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application. Fig.10 The horizontal axis is the drain-source voltage Vds, in V; the vertical axis is the drain-source current Ids, in A.

[0102] from Fig.10 It can be seen that when the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is forward-conducted, the drain-source current Ids changes linearly with the drain-source voltage Vds.

[0103] Fig.11 This is a simulation diagram of the electric field distribution under the breakdown voltage of the capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application.

[0104] Fig.12 4 is a curve showing the change of the drain-source current Ids with the drain-source voltage Vds at the breakdown voltage of the capacitively coupled gate controlled junction field effect transistor according to an embodiment of the present application. Fig.12 The horizontal axis is the drain-source voltage Vds, in V; the vertical axis is the drain-source current Ids, in A.

[0105] from Fig.11 It can be seen that the electric field position under the breakdown voltage is far away from the channel region 4 and is located at the corner of the gate 5. That is, through the PN junction formed by the source region 1 and the channel region 4, the PN junction formed by the channel region 4 and the gate 5, and the PN junction formed by the gate 5 and the current guiding layer 8, the PN junction reduces the potential at the bottom of the channel region 4 under reverse bias.

[0106] from Fig.12 It can be seen that in the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the drain-source current Ids suddenly increases when the drain-source voltage Vds reaches the breakdown voltage.

[0107] Fig.13 It is a simulation diagram of the body diode current path of the capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application.

[0108] Fig.14 1 is a curve showing the change of the source-current Ids of the capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application as a inverse of the source-drain voltage Vsd. Fig.14 The horizontal axis is the source-drain voltage Vsd, in V; the vertical axis is the source-drain current Isd, in A.

[0109] from Fig.13 It can be seen that the PN junction formed by the source region 1 and the structure under the source region 1 forms a diode current path ①;

[0110] A diode current path ② formed by a PN junction formed by the sidewall of the gate 5 and the structure outside the sidewall of the gate 5;

[0111] The bottom of the gate 5 and the structure outside the bottom of the gate 5 form a diode current path ③.

[0112] from Fig.14It can be seen that in the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the source-drain current Isd increases rapidly when the source-drain voltage Vsd increases from zero to the source voltage, and when the source-drain voltage Vsd approaches the source voltage. The reason is that the diode current path ①, the diode current path ②, and the diode current path ③ work together.

[0113] Specifically, the doping concentration of the source region 1 is in the range of greater than or equal to 10 17 cm 3 Less than or equal to 10 18 cm 3 ;

[0114] The doping concentration of the first doping type source contact region 2 is in the range of greater than or equal to 10 18 cm 3 .

[0115] The method for preparing a capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application comprises the following steps:

[0116] Step 1: After the epitaxy is prepared, N-type ion implantation is performed based on a hard mask to form a current guiding layer foundation 8-0;

[0117] Step 2: Perform P-type ion implantation based on a hard mask to form a source region base 1-0; Figure 3 As shown;

[0118] Step 3: Perform a second N-type ion implantation based on the hard mask to form a partial channel region foundation 4-0;

[0119] Step 4: Perform a third N-type ion implantation based on the hard mask to form an N-type second doping type source contact region 3;

[0120] Step 5: Perform P-type ion implantation based on the hard mask to form a P-type first doping type source contact region 2; Figure 4 As shown;

[0121] Step 6: Etching to form a groove 14;

[0122] Step 7: Based on the mask, ion implantation is performed to form a P-type heavily doped gate 5 at the bottom and sidewalls of the trench 14; impurity annealing is performed to activate the ion implantation; Figure 5 As shown;

[0123] Step 8: depositing a first source electrode 9, wherein the thickness of the first source electrode 9 is in the range of 300 nanometers to less than or equal to 500 nanometers; Figure 6 As shown;

[0124] Step 9: Deposit and form a dielectric layer 6, wherein the bottom thickness of the dielectric layer 6 ranges from 50 nanometers to 80 nanometers, and the sidewall thickness of the dielectric layer 6 ranges from 30 nanometers to 60 nanometers; Figure 7 As shown;

[0125] Step 10: forming a second source electrode 13 by deposition based on a mask; Figure 8 shown.

[0126] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0127] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0128] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0129] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0130] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0131] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A capacitively coupled gate controlled junction field effect transistor, characterized in that: include: A substrate (11), an epitaxial layer of a second doping type, and a drain (12), wherein the epitaxial layer is located on the substrate, and the drain is located on the back side of the substrate; A groove is formed downward from the upper surface of the epitaxial layer; A trench-type gate (5) of a first doping type, formed on the inner wall and bottom of the trench; A first source electrode (9) for connecting a source voltage, formed on the bottom of the gate (5), the gate (5) and the first source electrode (9) being connected so that they have the same potential; A trench-type dielectric layer (6) formed on the first source electrode (9); A gate electrode (7) filled on the inner wall and bottom of the dielectric layer; A source region (1) of a first doping type is arranged at least at one side of the gate (5); the source region (1) and the first source electrode (9) are respectively connected to a source voltage; A channel region (4) of a second doping type is formed between the source region (1) and the gate (5); The source region (1), the channel region (4) and the structure below the gate (5) serve as a gate periphery structure of the second doping type, and the gate (5) and the gate periphery structure form a PN junction.

2. The field effect transistor according to claim 1, characterized in that An epitaxial layer is provided between the source region (1) and the substrate (11), and a PN junction is formed between the source region (1) and a portion of the epitaxial layer located below the source region (1).

3. The field effect transistor according to claim 2, characterized in that: There are two source regions (1) of the first doping type, and the two source regions (1) of the first doping type are arranged at intervals on both sides of the gate (5); There are two channel regions (4), which are respectively formed between the two source regions (1) and the channel regions (4).

4. The field effect transistor according to claim 3, characterized in that: When the capacitively coupled gate-controlled junction field effect transistor is turned off: A diode current path formed by a gate (5) and a PN junction formed by a structure around the gate; A diode current path is formed by a PN junction formed by the source region (1) and the structure below the source region (1).

5. The field effect transistor according to claim 4, characterized in that: The source region (1), the channel region (4), and the gate (5) form a first JFET structure, the first JFET structure is controlled by the gate (5), and the opening and closing of the channel region (4) is controlled by the depletion region of the PN junction formed by the channel region (4) and the gate (5); The PN junction formed by the channel region (4) and the gate (5), the dielectric layer (6), and the gate electrode (7) form a second JFET structure with capacitive coupling gate control; the second JFET structure is indirectly controlled by the gate electrode (7), and the gate electrode (7) indirectly controls the depletion region of the PN junction formed by the channel region (4) and the gate (5) through the dielectric layer (6), thereby controlling the opening and closing of the channel region (4).

6. The field effect transistor according to claim 5, characterized in that: When the capacitively coupled gate-controlled junction field effect transistor is turned on, the gate (5) in the first JFET structure and the gate electrode (7) in the second JFET structure jointly shrink the depletion region of the PN junction formed by the channel region (4) and the gate (5), so that the field effect transistor is quickly forward-conducted; When the capacitively coupled gate-controlled junction field effect transistor is turned off, and the PN junction formed by the source region (1) and the channel region (4), and the PN junction formed by the channel region (4) and the gate (5) are reverse biased, the channel region is depleted, the device is turned off, and the PN junction reduces the potential at the bottom of the channel region (4), thereby reducing leakage current.

7. The field effect transistor according to any one of claims 2 to 6, characterized in that: Also includes: A current guiding layer (8) of a second doping type is formed in the epitaxial layer and is located below the source region (1), the channel region (4) and the gate (5), wherein the source region (1) and the current guiding layer (8) form a PN junction; wherein the doping concentration of the current guiding layer (8) is greater than the doping concentration of the epitaxial layer (10); The PN junction formed by the gate (5) and the structure surrounding the gate is specifically a PN junction formed by the current guiding layer (8) and the gate (5).

8. The field effect transistor according to claim 7, characterized in that: The upper surface of the first source electrode (9) is lower than the bottom of the channel region (4), so that the bottom of the gate (5) is lower than the bottom of the channel region (4); The lower surface of the source region (1) is lower than the bottom of the channel region (4).

9. The field effect transistor according to claim 7, characterized in that: The bottom surface of the source region (1) is lower than the bottom surface of the channel region (4).

10. The field effect transistor according to claim 7, characterized in that: Also includes: Two first doping type source contact regions (2), respectively connected to the two source regions (1); Two second doping type source contact regions (3) are respectively connected to the two channel regions (4), and the second doping type source contact region (3) and the first doping type source contact region (2) on the same side are connected; Two second source electrodes (13) are respectively located on two first doping type source contact regions (2), and the second source electrode (13) on the same side is connected to the first doping type source contact region (2) and the second doping type source contact region (3) on the same side.

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