Vertical capacitive coupling grid-control junction field effect transistor

Abstract

The invention provides a vertical capacitive coupling grid-control junction field effect transistor. The vertical capacitive coupling grid-control junction field effect transistor comprises a cell, wherein the cell is divided into VCGJFET regions and MOSFET regions which are alternately arranged in a second transverse direction; in the first transverse direction, the MOSFET region is provided with a first doping type MOSFET region drain region, a second doping type MOSFET region channel region and a first doping type MOSFET region source region which are sequentially and adjacently arranged. The VCGJFET region is provided with a top gate of a first doping type; in the second transverse direction, the top gates and the drain regions of the MOSFET region are alternately and adjacently connected; wherein the top gate, the drain region of the MOSFET region, the channel region of the MOSFET region and the source region of the MOSFET region are connected with one another. The technical problems that the carrier concentration in the top gate of a traditional vertical capacitive coupling gate-controlled junction field effect transistor is increased and no discharge path exists are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a vertical capacitively coupled gate-controlled junction field effect transistor. Background Art

[0002] like Figure 1 As shown, the top gate 8 of the vertical capacitively coupled gate-controlled junction field effect transistor (VCGJFET for short) of patent CN117637854B is floating. Substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel 1 1-5, channel 2 1-6, first doping type source region 1-7, top gate 1-8, dielectric layer 1-9, VCGJFET region gate electrode 1-10, source 1-12, drain 1-13. The vertical capacitively coupled gate-controlled junction field effect transistor in patent CN 117637854B has the following problems:

[0003] (1) When the gate-source bias voltage Vgs of the vertical capacitively coupled gate-controlled junction field effect transistor is 0V and a positive bias voltage is applied to the drain-source, the carrier concentration in the top gate 1-8 increases by 1 to 5 times when the device is in a high-temperature blocking state. However, these carriers have no discharge path, resulting in an increase in the potential difference of the top gate 1-8, which is equivalent to applying a positive bias voltage of less than 1V to the top gate 8, making it impossible for the device to be completely turned off.

[0004] (2) The carrier concentration in the top gate 1-8 increases and there is no discharge path, making the device unstable when turned off.

[0005] (3) When a vertical capacitively coupled gate-controlled junction field effect transistor is used as a freewheeling diode, the gate and source are short-circuited at high temperatures and the blocking voltage of the device is too low.

[0006] Therefore, the carrier concentration in the top gate of the traditional vertical capacitively coupled gate-controlled junction field effect transistor increases and there is no discharge path, making the device unstable when turned off, which is a technical problem that technical personnel in this field urgently need to solve.

[0007] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0008] The present application provides a vertical capacitively coupled gate-controlled junction field effect transistor to solve the technical problem that the carrier concentration in the top gate of a traditional vertical capacitively coupled gate-controlled junction field effect transistor increases and has no discharge path, making the device unstable when turned off.

[0009] The present application provides a vertical capacitively coupled gate-controlled junction field effect transistor including a cell, wherein the cell is divided into alternately arranged VCGJFET regions and MOSFET regions in a second lateral direction;

[0010] In a first lateral direction, the MOSFET region has a MOSFET region drain region of a first doping type, a MOSFET region channel region of a second doping type, and a MOSFET region source region of a first doping type that are arranged adjacent to each other in sequence;

[0011] The VCGJFET region has a top gate of a first doping type; in a second lateral direction, the top gate and the drain region of the MOSFET region are alternately adjacently connected;

[0012] Wherein, the top gate, the drain region of the MOSFET region, the channel region of the MOSFET region, and the source region of the MOSFET region are connected.

[0013] Due to the adoption of the above technical solution, this application has the following technical effects:

[0014] The vertical capacitively coupled gate-controlled junction field effect transistor of the present application sets a controllable discharge path for the carriers in the top gate 81 of the VCGJFET region 100 by setting the MOSFET region 200: top gate 81→MOSFET region drain region 82→MOSFET region channel region 6→MOSFET region source region 42, such as Figure 2-2 and Figure 4 and top gate 81→MOSFET region channel region 6→MOSFET region source region 42. When the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET region source region 42 via the MOSFET region drain region 82 and the MOSFET region channel region 6, and the carriers in the top gate 81 can also move to the MOSFET region source region 42 via the MOSFET region channel region 6, so as to realize stable turn-off of the VCGJFET region 100. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 It is a schematic diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of patent CN117637854B;

[0017] Figure 2-1 A three-dimensional schematic diagram of a first implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application;

[0018] Figure 2-2 for Figure 2-1 A top perspective view of a cell of a vertical capacitively coupled gate controlled junction field effect transistor;

[0019] Figure 2-3 for Figure 2-1 A schematic diagram of a first working state of a vertical capacitively coupled gate-controlled junction field effect transistor;

[0020] Figure 2-4 for Figure 2-1 A schematic diagram of a second working state of a vertical capacitively coupled gate-controlled junction field effect transistor;

[0021] Figure 2-5 for Figure 2-1 A schematic diagram of a third working state of a vertical capacitively coupled gate-controlled junction field effect transistor;

[0022] Figure 2-6 for Figure 2-1 A schematic diagram of a fourth working state of a vertical capacitively coupled gate-controlled junction field effect transistor;

[0023] Figure 3 for Figure 2-1 A-A' cross-sectional view of a vertical capacitively coupled gate-controlled junction field effect transistor;

[0024] Figure 4 for Figure 2-1 BB' cross-sectional view of a vertical capacitively coupled gate-controlled junction field effect transistor;

[0025] Figure 5 A cross-sectional view of the second implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application at position AA';

[0026] Figure 6 A cross-sectional view of the second implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application at the position BB';

[0027] Figure 7 A cross-sectional view of the third implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application at position AA';

[0028] Figure 8 A cross-sectional view of the third implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application at the position BB';

[0029] Fig. 9 A comparison diagram of the electron concentration at the top gate 81 position of the first implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application and the background art patent CN117637854B;

[0030] Fig.10 for Fig. 9 The electron concentration comparison diagram after the vertical axis is enlarged;

[0031] Fig.11 A comparison diagram of hole concentration at the top gate 81 position of the first implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application and the background art patent CN117637854B;

[0032] Fig.12 for Fig.11 A comparison diagram of hole concentration after the vertical axis is enlarged;

[0033] Fig.13 This is a potential comparison diagram at the top gate 81 position between the first implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application and the background art patent CN117637854B.

[0034] Reference numerals:

[0035] In the background technology:

[0036] Substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel 1-5,

[0037] Channel 2 1-6, first doping type source region 1-7, top gate 1-8, dielectric layer 1-9,

[0038] VCGJFET region gate electrode 1-10, source 1-12, drain 1-13;

[0039] In this application:

[0040] Substrate 1, epitaxial layer 2, bottom gate 3, drain 13, buffer layer 14,

[0041] Channel 1 51, channel 2 52, current spreading layer 53,

[0042] The first doping type source region 4, the first doping type region 8,

[0043] VCGJFET region 100,

[0044] The first doped source region 41 of the VCGJFET region, the second doped source region 7 of the VCGJFET region,

[0045] Top gate 81, top gate inner region 81-1, top gate outer region 81-2,

[0046] VCGJFET region dielectric layer 91, VCGJFET region gate electrode 10-1, VCGJFET region source electrode 12-1,

[0047] MOSFET area 200,

[0048] MOSFET region source region 42, MOSFET region channel region 6, MOSFET region drain region 82,

[0049] MOSFET region dielectric layer 92, MOSFET region gate electrode 10-2, MOSFET region source electrode 12-2. DETAILED DESCRIPTION

[0050] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0051] The following is a concentrated description of the doping types of various regions of the vertical capacitively coupled gate controlled junction field effect transistor:

[0052] A substrate 1 of a second doping type, an epitaxial layer 2 of a second doping type, a bottom gate 3 of a first doping type,

[0053] The first doping type source region 4, the first doping type region 8,

[0054] Drain 13,

[0055] Buffer layer 14,

[0056] A channel 1 51 of the second doping type, a channel 2 52 of the second doping type,

[0057] The current spreading layer 53 of the second doping type,

[0058] VCGJFET region 100,

[0059] The first doping type VCGJFET region first doping source region 41,

[0060] The second doping type VCGJFET region second doping source region 7,

[0061] A top gate 81 of the first doping type, a top gate inner region 81 - 1 of the first doping type heavily doped,

[0062] The top gate outer region 81 - 2 is lightly doped with the first doping type,

[0063] VCGJFET region dielectric layer 91, VCGJFET region gate electrode 10-1,

[0064] VCGJFET region source electrode 12-1,

[0065] MOSFET area 200,

[0066] A MOSFET region source region 42 of a first doping type, a MOSFET region channel region 6 of a second doping type,

[0067] The drain region 82 of the MOSFET region of the first doping type,

[0068] MOSFET region dielectric layer 92, MOSFET region gate electrode 10-2, MOSFET region source electrode 12-2.

[0069] As an optional manner, the first doping type is P-type doping, and the second doping type is N-type doping.

[0070] As an optional manner, the first doping type is N-type doping, and the second doping type is P-type doping.

[0071] Embodiment 1

[0072] like Figure 2-1 , Figure 2-2 , Figures 3 to 8 As shown, the vertical capacitively coupled gate-controlled junction field effect transistor of the present application includes a cell, and the cell is divided into alternately arranged VCGJFET regions 100 and MOSFET regions 200 in a second lateral direction;

[0073] The cell comprises:

[0074] A first doping type region 8, a portion located in the MOSFET region serving as a drain region 82 of the MOSFET region and a portion located in the VCGJFET region serving as a top gate 81 of the VCGJFET region 100;

[0075] A first doping type source region 4, a portion located in the MOSFET region serving as a MOSFET region source region 42 and a portion located in the VCGJFET region serving as a VCGJFET region first doping source region 41;

[0076] In a first lateral direction, the MOSFET region 200 has a MOSFET region drain region 82 of a first doping type, a MOSFET region channel region 6 of a second doping type, and a MOSFET region source region 42 of a first doping type that are arranged adjacent to each other in sequence;

[0077] The VCGJFET region 100 has a top gate 81 of a first doping type;

[0078] When the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET region source region 42 via the first doping type region 8 and the MOSFET region channel region 6;

[0079] The top gate 81, the MOSFET region drain region 82, the MOSFET region channel region 6, and the MOSFET region source region 42 are connected as a discharge path for the carriers of the top gate 81. That is, the top gate 81 is connected through the MOSFET region drain region 82, the MOSFET region channel region 6, and the MOSFET region source region 42.

[0080] Specifically, in the vertical capacitively coupled gate-controlled junction field effect transistor of the present application, the plane perpendicular to the thickness direction of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application is a lateral direction, the direction in which the drain region 82 of the first doping type MOSFET region, the channel region 6 of the second doping type MOSFET region, and the grounded source region 42 of the first doping type MOSFET region are arranged in sequence is a lateral first direction, and the direction perpendicular to the lateral first direction is a lateral second direction, such as Figure 2-1 and Figure 2-2 shown.

[0081] The present application discloses a vertical capacitively coupled gate-controlled junction field-effect transistor (VCGJFET for short).

[0082] The vertical capacitively coupled gate-controlled junction field effect transistor of the present application has a VCGJFET region 100, which is the main structure for realizing the functions of the vertical capacitively coupled gate-controlled junction field effect transistor. The turning off of the VCGJFET region 100 is consistent with the turning off of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application, and the turning on of the VCGJFET region 100 is consistent with the turning on of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application. In addition, a controllable switch, namely, a MOSFET region 200, is provided for the VCGJFET region 100, and the control of whether the carriers at the top gate 81 can flow out of the top gate 81 is realized by controlling the MOSFET region 200.

[0083] The specific configuration is that the MOSFET region 200 has a first doping type MOSFET region drain region 82 , a second doping type MOSFET region channel region 6 , and a grounded first doping type MOSFET region source region 42 that are adjacently arranged in sequence as the structure forming the MOSFET region 200 .

[0084] When the VCGJFET region 100 is in operation, the current carrier concentration in the top gate 81 of the VCGJFET region 100 will increase, resulting in an increase in the potential difference of the top gate 81 .

[0085] At this time, when the gate of the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET region source region 42 through the first doping type region 8 and the MOSFET region channel region 6, so that the carriers flow out from the top gate 81, so that the potential of the top gate 81 is reduced and does not remain at a high potential. That is, when the VCGJFET region 100 is turned off, the first doping type region 8, the MOSFET region channel region 6, and the MOSFET region source region 42 serve as a discharge path for the carriers at the top gate 81, reducing the potential of the top gate 81.

[0086] In this way, when the VCGJFET region 100 is turned off in the vertical capacitively coupled gate-controlled junction field effect transistor device of the present application, whether at room temperature or high temperature, the first doping type region 8, the MOSFET region channel region 6, and the MOSFET region source region 42 will serve as a discharge path for the carriers at the top gate 81, reducing the potential of the top gate 81, so that the VCGJFET region 100 can be stably turned off regardless of whether it is at room temperature or high temperature.

[0087] The vertical capacitively coupled gate-controlled junction field effect transistor of the present application sets a controllable discharge path for the carriers in the top gate 81 of the VCGJFET region 100 by setting the MOSFET region 200: the top gate 81 → the first doping type region 8 → the MOSFET region channel region 6 → the MOSFET region source region 42, as shown in FIG. Figure 2-2 and Figure 4 When the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET region source region 42 via the first doping type region 8 and the MOSFET region channel region 6 to achieve stable turn-off of the VCGJFET region 100.

[0088] In the embodiment of the present application, the top gate 81 and the MOSFET region drain region 82 are two parts of the first doping type region 8 of the same structure; the MOSFET region source region 42 and the VCGJFET region first doping source region 41 are two parts of the first doping type source region 4 of the same structure.

[0089] In this way, the first doping type region 8 as a whole can be manufactured using the same photoresist layer, and the first doping type source region 4 as a whole can be manufactured using the same photoresist layer, thereby meeting the performance requirements while saving process steps and costs.

[0090] In practice, the MOSFET region 200 is a normally-on structure and the threshold voltage Vth MOS is a negative value;

[0091] The VCGJFET region 100 is a normally-off structure and the threshold voltage Vth JFET is a positive value;

[0092] The gate electrode of the VCGJFET region (corresponding to the VCGJFET region gate electrode 10-1 in the figure) and the gate electrode of the MOSFET region 200 (corresponding to the MOSFET region gate electrode 10-2 in the figure) share a device gate electrode, the source electrode of the VCGJFET region 100 (corresponding to the VCGJFET region source electrode 12-1 in the figure) and the source electrode of the MOSFET region 200 share a device source electrode, and the device gate-source voltage of the vertical capacitively coupled gate-controlled junction field effect transistor device is represented by Vgs.

[0093] The vertical capacitive-coupled gate-controlled junction field effect transistor of the present application has four working states.

[0094] like Figure 2-3 As shown, the first working state is as follows:

[0095] When the MOSFET threshold voltage Vth MOS ≤Device gate-source voltage Vgs≤zero:

[0096] The MOSFET region 200 is in the subthreshold section, and the carriers in the top gate 81 move through the first doping type region 8, the MOSFET region channel region 6, to the MOSFET region source region 42, the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off. Figure 2-3 As shown, Vth MOS -100V, Vth JFET is 200V.

[0097] Specifically, the first working state has two situations:

[0098] The first case: When the MOSFET region threshold voltage Vth MOS ≤Device gate-source voltage Vgs≤zero, the vertical capacitively coupled gate-controlled junction field effect transistor of the present application operates at room temperature:

[0099] The MOSFET region 200 is in the subthreshold section, and the carriers in the top gate 81 move through the first doping type region 8, the MOSFET region channel region 6, and to the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0100] The second case: When the MOSFET region threshold voltage Vth MOSWhen the device gate-source voltage Vgs is less than or equal to zero and the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present application operates at high temperature (the carrier concentration at high temperature is much higher than that at room temperature):

[0101] The potential of the device gate electrode is zero, the MOSFET region 200 is in the subthreshold region, the carriers in the top gate 81 move through the first-doped type region 8, the MOSFET region channel region 6, and reach the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0102] In implementation, as Figure 2-4 shown, the second operating state is as follows:

[0103] When the gate-source voltage Vgs of the device is less than the MOSFET region threshold voltage Vth MOS :

[0104] The MOSFET region 200 is turned on, the carriers in the top gate 81 move through the first-doped type region 8, the MOSFET region channel region 6, and reach the MOSFET region source region 42, the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0105] Specifically, the second operating state has two cases:

[0106] The first case: When the gate-source voltage Vgs of the device is less than the MOSFET region threshold voltage Vth MOS : When the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present application operates at room temperature:

[0107] The MOSFET region 200 is turned on, the carriers in the top gate 81 move through the first-doped type region 8, the MOSFET region channel region 6, and reach the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0108] The second case: When the gate-source voltage Vgs of the device is less than the MOSFET region threshold voltage Vth MOS : When the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present application operates at high temperature (the carrier concentration at high temperature is much higher than that at room temperature):

[0109] The potential of the device gate electrode is zero, the MOSFET region 200 is turned on, the carriers in the top gate 81 move through the first doped type region 8 and the MOSFET region channel region 6 to the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0110] In implementation, as Figure 2-5 shown, the third working state is as follows:

[0111] When 0 < the gate-source voltage Vgs of the device < the threshold voltage Vth of the VCGJFET region JFET the MOSFET region 200 is turned off, and the VCGJFET region 100 is in the sub-threshold region;

[0112] As Figure 2-6 shown, the fourth working state is as follows:

[0113] When the gate-source voltage Vgs of the device ≥ the threshold voltage Vth of the VCGJFET region JFET the MOSFET region 200 is turned off, and the VCGJFET region (100) is turned on.

[0114] In implementation, as Figure 2-1 , Figure 2-2 shown, as Figures 3 to 8 shown, one cell includes one VCGJFET region 100 and two MOSFET regions 200, and the two MOSFET regions 200 are symmetrically arranged; the cell further includes:

[0115] Two block-shaped second doped type VCGJFET region second doped source regions 7; the VCGJFET region second doped source region 7 and the MOSFET region channel region 6 on the same side are connected.

[0116] In implementation, as Figure 2-1 , Figure 2-2 shown, as Figures 3 to 8 shown, the VCGJFET region second doped source region 7 and the MOSFET region channel region 6 are in the same layer, and the VCGJFET region second doped source region 7 and the MOSFET region channel region 6 on the same side are alternately adjacent and connected.

[0117] The VCGJFET region second doped source region 7 and the MOSFET region channel region 6 are in the same layer, effectively utilizing the layer space where the VCGJFET region second doped source region 7 is located, making the space utilization rate of the field effect transistor relatively high.

[0118] In implementation, as Figure 2-1, Figure 2-2 As shown, Figures 3 to 8 As shown, the cell also includes:

[0119] Two block-shaped first doped source regions 41 of the VCGJFET region of the first doping type; the first doped source regions 41 of the VCGJFET region and the source regions 42 of the MOSFET region located on the same side are alternately arranged adjacent to each other;

[0120] The VCGJFET region dielectric layer 91 is located above the first doping type region 8;

[0121] A VCGJFET region gate electrode 10 - 1 formed on the VCGJFET region dielectric layer 91;

[0122] A block-shaped MOSFET region dielectric layer 92 is located above the MOSFET region drain region 82, the MOSFET region channel region 6 and the MOSFET region source region 42;

[0123] The MOSFET region gate electrode 10 - 2 is located above the MOSFET region dielectric layer 92 ;

[0124] A bulk VCGJFET region source electrode 12 - 1 is formed on the VCGJFET region second doped source region 7 and the VCGJFET region first doped source region 41 ;

[0125] The MOSFET region source electrode 12 - 2 is formed on the MOSFET region source region 42 .

[0126] In implementation, such as Figure 2-1 , Figure 2-2 As shown, Figures 3 to 8 As shown, the cell also includes:

[0127] A substrate 1 of a second doping type and an epitaxial layer 2 of a second doping type, wherein the epitaxial layer 2 is located above the substrate 1;

[0128] Two bottom gates 3 of the first doping type are formed in the epitaxial layer and spaced apart in a first lateral direction; the first doping type region 8 is formed in the epitaxial layer and located above the two bottom gates 3;

[0129] A drain electrode 13 is arranged on the lower surface of the substrate 1;

[0130] The MOSFET region source region 42 , the MOSFET region channel region 6 , the MOSFET region drain region 82 , the MOSFET region dielectric layer 92 , and the MOSFET region gate electrode 10 - 2 form a MOSFET region.

[0131] In implementation, such as Figure 3 and Figure 4 As shown, Figure 7 and Figure 8 As shown, the top gate 81 is a combined top gate of the first doping type;

[0132] The top gate includes a top gate inner region 81-1 and a top gate outer region 81-2, wherein the top gate inner region 81-1 is formed from top to bottom in the epitaxial layer, the top gate outer region 81-2 surrounds the bottom and side surfaces of the top gate inner region 81-1, and there is a gap between the top gate outer region 81-2 and the bottom gate 3; wherein the doping concentration of the top gate outer region 81-2 is less than the doping concentration of the top gate inner region 81-1.

[0133] The top gate outer region 81-2 surrounds the bottom and side surfaces of the top gate inner region 81-1, and the doping concentration of the top gate outer region 81-2 is less than the doping concentration of the top gate inner region 81-1, so that the potential difference of the top gate from the outer surface of the top gate outer region 81-2 to the top surface of the top gate inner region 81-1 is relatively slow.

[0134] In the field of semiconductors, under uniform doping conditions, the potential expression at position x in a P-type doped region is The following relationship (1) is satisfied:

[0135]

[0136] Where e is the electron charge, N a is the doping concentration of the P-type doped region, εs is the semiconductor dielectric constant, x p is the position where the electric field E is zero.

[0137] According to the relationship (1), the carriers in the N-type doped top gate 81 are discharged through the normally-on MOSFET region 200 (formed by the P-type doped MOSFET region drain region 82, the N-type doped MOSFET region channel region 6, the MOSFET region source region 42, the MOSFET region dielectric layer 92, the MOSFET region gate electrode 10-2, and the MOSFET region source electrode 12-2) with a negative threshold voltage, thereby reducing the carrier concentration in the top gate 81, thereby preventing the top gate 81 from raising its potential at room temperature and high temperature.

[0138] According to equation (1), in the P-type doping region, the N a The smaller the value, the electric potential at the same position (i.e. the same x) That is, the position x in the P-type doped region is relative to the position x where the electric field E is zero. p The potential difference is small. Specifically in this application, the top gate 81 is a P-type doped region.

[0139] From this, we can see that in two P-type doping regions with different doping concentrations, when the positions where the electric field E is zero in the two P-type doping regions are the same, which P-type doping region has the highest N? a The smaller the value, the electric potential at the same position (i.e. the same x) That is, the position x in the P-type doped region is relative to the position x where the electric field E is zero. p The potential difference is small. In this way, the flow channel for carriers increases, widening the process window of the vertical capacitively coupled gate-controlled junction field effect transistor. The process window and current channel widening are achieved simultaneously.

[0140] In this application, the position x where the electric field E is zero p It is the surface of the top gate inner region 81-1. The top gate outer region 81-2 surrounds the bottom and side surfaces of the top gate inner region 81-1, and the doping concentration of the top gate outer region 81-2 is less than the doping concentration of the top gate inner region 81-1, so that the potential difference of the top gate from the outer surface of the top gate outer region 81-2 to the top surface of the top gate inner region 81-1 is relatively slow. The process window and the current channel widening are achieved simultaneously. By controlling the concentration of the channel, the magnitude of the on-current can be controlled.

[0141] Taking the VCGJFET region of the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application as a PMOS transistor as an example, the gate electrode 10-1 of the VCGJFET region is connected to a positive voltage (such as 15 volts) of the gate voltage, and the source electrode 12-1 of the VCGJFET region is grounded. When the drain 13 is connected to a positive voltage, an electric field is generated between the drain 13 and the source electrode 12-1 of the VCGJFET region, thereby generating a conduction current, and the direction of the current is as follows: Figure 3 Shown by the curved dashed line with an arrow.

[0142] When the bias voltage of the gate electrode 10-1 of the VCGJFET region is less than or equal to 0V, the potential of the top gate inner region 81-1 is less than or equal to 0.8V (i.e., consistent with the bias voltage), the top gate outer region 81-2 and the channel of the VCGJFET region (at Figure 3 The PN junction formed by the middle finger channel 1 51 and the channel 2 52 is reverse biased, the channel of the VCGJFET region is pinched off, and the VCGJFET region of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application is turned off.

[0143] In addition, through simulation, it can be found that the on-resistance Ron,sp of the vertical capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application under high temperature conditions is within 3 times of that at normal temperature, and is compatible with the application of existing SiC MOSFETs. That is, the application scenarios of the vertical capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application are compatible with the existing technology and have strong versatility.

[0144] In implementation, such as Figure 3 and Figure 4 As shown, Figure 7 and Figure 8 As shown, the cross section of the top gate outer region 81 - 2 is U-shaped, the inner bottom of the top gate outer region 81 - 2 is wrapped around the bottom surface of the top gate inner region 81 - 1 , and the inner wall of the top gate outer region 81 - 2 is wrapped around the side surface of the top gate inner region 81 - 1 .

[0145] In this way, the top gate outer region 81-2 wraps the bottom and side surfaces of the top gate inner region 81-1, so that the bottom and side surfaces of the top gate inner region 81-1 have the top gate outer region 81-2 with a slower potential change, making the overall process window of the top gate larger.

[0146] Specifically, the top gate inner region 81 - 1 is heavily doped.

[0147] The heavily doped top gate inner region 81 - 1 is used to disconnect the depletion region on the surface of the top gate, thereby meeting the requirement of blocking withstand voltage.

[0148] In practice, the doping concentration of the top gate outer region 81 - 2 is 1 to 2 orders of magnitude lower than the doping concentration of the top gate inner region 81 - 2 .

[0149] Specifically, Figure 2-1 , Figures 3 to 8 As shown, the cell also includes:

[0150] A buffer layer 14 is formed between the substrate 1 and the epitaxial layer 2 .

[0151] Specifically, the VCGJFET region gate electrode 10 - 1 , the VCGJFET region dielectric layer 91 , and the top gate 81 constitute a gate structure of the VCGJFET region.

[0152] As an optional manner, as shown in the figure, the top gate 81 of the first doping type, the portion between the top gate 81 and the bottom gate 3, and the bottom gate 3 form a JFET region 1;

[0153] The two bottom gates 3 and the portion between the bottom gates 3 form a second JFET region;

[0154] The top gate of JFET region one is indirectly controlled by the VCGJFET region dielectric layer 91 separated by the VCGJFET region gate electrode 10 - 1 , so that JFET region one and JFET region two are controlled by the VCGJFET region dielectric layer 91 separated by the VCGJFET region gate electrode 10 - 1 .

[0155] As an alternative, Figure 7 and Figure 8 As shown, the cell also includes:

[0156] A channel 1 51 of the second doping type is formed in a portion between the top gate 81 and the bottom gate 3, and the top gate 81 is located above the channel 1 51;

[0157] The JFET region 1 is specifically formed by the top gate 81 , the channel 1 51 , and the bottom gate 3 , and the JFET region 2 is specifically formed by the two bottom gates 3 and a portion of the epitaxial layer located between the bottom gates 3 .

[0158] As another option, the cell also includes:

[0159] A channel 1 51 of the second doping type is formed in a portion between the top gate 81 and the bottom gate 3, and the top gate 81 is located above the channel 1 51;

[0160] A second channel 52 of the second doping type is formed between the two bottom gates 3;

[0161] The JFET region 1 is specifically formed by a top gate 81 , a channel 1 51 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 and a channel 2 52 .

[0162] As another alternative, Figure 3 and Figure 4 As shown, Figure 5 and Figure 6 As shown, the cell also includes:

[0163] A channel 1 51 of the second doping type is formed in a portion between the top gate 81 and the bottom gate 3, and the top gate 81 is located above the channel 1 51;

[0164] A second channel 52 of the second doping type is formed between the two bottom gates 3;

[0165] A current spreading layer 53 of the second doping type is formed in the epitaxial layer 2 below the bottom gate 3 and the second channel 52;

[0166] The JFET region 1 is specifically formed by a top gate 81 , a channel 1 51 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 , a channel 2 52 , and a current spreading layer 53 .

[0167] The doping concentrations of the first channel 5, the second channel 52 and the current spreading layer 53 are greater than the doping concentration of the epitaxial layer, which is beneficial to reducing the on-resistance of the device and improving the device performance.

[0168] In the implementation, the doping concentration of the top gate outer region 81-2 is in the range of greater than or equal to 2×10 17 cm -3 Less than or equal to 5×10 18 cm -3The doping concentration of the top gate inner region 81-1 is in the range of greater than or equal to 2×10 18 cm -3 Less than or equal to 4×10 20 cm -3 .

[0169] In implementation, the thickness of the bottom of the top gate outer region 81 - 2 ranges from 0.02 μm to 0.2 μm, and the thickness of the sidewall of the top gate outer region 81 - 2 ranges from 0.02 μm to 0.2 μm.

[0170] The thickness of the top gate inner region 81 - 1 ranges from 0.02 μm to equal to 0.1 μm.

[0171] The doping concentration and thickness of the top gate inner region 81-1 meet the above value range requirements to prevent the depletion region on the surface of the top gate inner region 81-1 from being connected during blocking, resulting in low withstand voltage. That is, to achieve the depletion region on the surface of the top gate inner region 81-1 not being connected and meet the blocking withstand voltage requirements.

[0172] The doping concentration of the top gate outer region 81 - 2 , the bottom thickness and the sidewall thickness of the top gate outer region 81 - 2 meet the above value range requirements in order to widen the process window range of the top gate and prevent the process from failing to achieve device performance.

[0173] Fig. 9 This is a comparison diagram of electron concentration at the top gate 81 when the patent CN117637854B, which is the background technology of the first implementation method of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application, is turned off. Fig.10 for Fig. 9 The electron concentration comparison diagram after the vertical axis is enlarged.

[0174] Fig. 9 and Fig.10 The horizontal axis is the size of the top gate 81 and the drain region 82 of the MOSFET region, in μm; Fig. 9 and Fig.10 The horizontal axis and Figure 3 The straight dashed line with arrow in the middle corresponds to; Fig. 9 and Fig.10 The vertical axis is the electron concentration in cm -3 . T = 300K is the working ambient temperature, T = 450K is the working ambient temperature.

[0175] from Fig. 9 and Fig.10It can be seen that, vertically downward in the middle position of the upper surface of the top gate, when it is turned off after high-temperature operation (T=300K and T=450K), the carriers of the top gate 81 of the present application are discharged by moving through the drain region 82 of the MOSFET region and the channel region 6 of the MOSFET region to the source region 42 of the MOSFET region. The electron concentration of the present application is much smaller than the electron concentration of the background technology patent CN117637854B, which avoids the increase of the potential of the top gate 81 of the present application at high temperature.

[0176] Fig.11 This is a comparison diagram of hole concentrations at the top gate 81 when the patent CN117637854B, which is the background technology of the first implementation of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application, is turned off. Fig.12 for Fig.11 A comparison of hole concentrations after the vertical axis is enlarged.

[0177] Fig.11 and Fig.12 The horizontal axis is the size of the top gate 81 and the drain region 82 of the MOSFET region, in μm; Fig.11 and Fig.12 The horizontal axis and Figure 3 The straight dashed line with arrow in the middle corresponds to; Fig.11 and Fig.12 The vertical axis is the hole concentration, in cm -3 . T = 300K is the working ambient temperature, T = 450K is the working ambient temperature.

[0178] from Fig.11 and Fig.12 It can be seen that, vertically downward in the middle position of the upper surface of the top gate, when it is turned off after high-temperature operation (T=300K and T=450K), the carriers of the top gate 81 of the present application are discharged by moving through the drain region 82 of the MOSFET region and the channel region 6 of the MOSFET region to the source region 42 of the MOSFET region. The hole concentration of the present application is much smaller than the hole concentration of the background technology patent CN117637854B, which avoids the increase of the potential of the top gate 81 of the present application at high temperature.

[0179] Since the patent CN117637854B of the present application and the background art is P-channel hole conduction, the overall electron concentration is low and the overall hole concentration is high.

[0180] Fig.13 This is a potential comparison diagram at the top gate 81 position of patent CN117637854B, which is the background technology of the first implementation method of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application. Fig.13 The horizontal axis is the size of the top gate 81 and the drain region 82 of the MOSFET region, in μm; Fig.13 The horizontal axis and Figure 3 The straight dashed line with arrow in the middle corresponds to; Fig.13 The vertical axis is the electric potential, and the unit is V. T = 300K is the working ambient temperature, and T = 450K is the working ambient temperature.

[0181] from Fig.13 It can be seen that, vertically downward in the middle position of the upper surface of the top gate, the potential of the present application is much smaller than the potential of the background art patent CN117637854B.

[0182] Embodiment 2

[0183] The vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is different from the embodiment 1 only in that:

[0184] The top gate 81 and the MOSFET region drain region 82 are two independent structures, each having its own preparation steps;

[0185] The MOSFET region source region 42 and the VCGJFET region first doped source region 41 are two independent structures, each having its own preparation steps.

[0186] Correspondingly, when the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET region source region 42 via the MOSFET region drain region 82 and the MOSFET region channel region 6 , and the carriers in the top gate 81 also move to the MOSFET region source region 42 via the MOSFET region channel region 6 .

[0187] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0188] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0189] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0190] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0191] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0192] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A vertical capacitively coupled gate controlled junction field effect transistor, characterized in that: It comprises a cell, wherein the cell is divided into alternately arranged VCGJFET regions (100) and MOSFET regions (200) in a second lateral direction; In a first lateral direction, the MOSFET region (200) comprises a MOSFET region drain region (82) of a first doping type, a MOSFET region channel region (6) of a second doping type, and a MOSFET region source region (42) of a first doping type, which are arranged adjacent to each other in sequence; The VCGJFET region (100) has a top gate (81) of a first doping type; in a second lateral direction, the top gate (81) and the drain region (82) of the MOSFET region are alternately arranged adjacent to each other; Wherein, the top gate (81), the MOSFET region drain region (82), the MOSFET region channel region (6), and the MOSFET region source region (42) are connected.

2. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 1, characterized in that: The top gate (81) and the MOSFET region drain region (82) are two parts of the same first doping type region (8); wherein the first doping type region (8) located in the MOSFET region serves as the MOSFET region drain region (82) and the first doping type region (8) located in the VCGJFET region serves as the top gate (81) of the VCGJFET region (100); Correspondingly, when the VCGJFET region (100) is turned off, carriers in the top gate (81) move to the MOSFET region source region (42) via the first doping type region (8) and the MOSFET region channel region (6).

3. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The MOSFET region (200) is a normally open structure and has a threshold voltage Vth MOS is a negative value; The VCGJFET region (100) is a normally-off structure and has a threshold voltage Vth JFET is a positive value; The gate electrode of the VCGJFET region and the gate electrode of the MOSFET region (200) share a device gate electrode, the source electrode of the VCGJFET region (100) and the source electrode of the MOSFET region (200) share a device source electrode, and the device gate-source voltage of the vertical capacitively coupled gate-controlled junction field effect transistor is denoted by Vgs; The first working state of the vertical capacitively coupled gate controlled junction field effect transistor is as follows: When the MOSFET threshold voltage Vth MOS ≤Device gate-source voltage Vgs≤zero: The MOSFET region (200) is in a subthreshold section, carriers in the top gate (81) move through the first doping type region (8), the MOSFET region channel region (6), and to the MOSFET region source region (42), the potential of the top gate (81) decreases, and the VCGJFET region (100) is stably turned off.

4. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The second working state is as follows: When the gate-source voltage Vgs of the device < the threshold voltage Vth of the MOSFET region MOS : The MOSFET region (200) is turned on, and carriers in the top gate (81) move to the MOSFET region source region (42) via the first doping type region (8), the MOSFET region channel region (6), and the potential of the top gate (81) decreases, and the VCGJFET region (100) is stably turned off.

5. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The third working state is as follows: When 0 < gate-source voltage Vgs of the device < threshold voltage Vth of the VCGJFET region JFET the MOSFET region (200) is turned off and the VCGJFET region (100) is in the sub-threshold region; The fourth working state is as follows: When the gate-source voltage Vgs of the device ≥ the threshold voltage Vth of the VCGJFET region JFET When the MOSFET region (200) is turned off, the VCGJFET region (100) is turned on.

6. The vertical capacitively coupled gate controlled junction field effect transistor according to any one of claims 1 to 5, characterized in that: One of the cells comprises one of the VCGJFET regions (100) and two of the MOSFET regions (200), and the two MOSFET regions (200) are symmetrically arranged; the cell further comprises: Two block-shaped second doping type VCGJFET region second doping source regions (7); the VCGJFET region second doping source regions (7) and the MOSFET region channel region (6) located on the same side are connected.

7. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 6, characterized in that: The second doped source region (7) of the VCGJFET region and the channel region (6) of the MOSFET region are located in the same layer, and the second doped source region (7) of the VCGJFET region and the channel region (6) of the MOSFET region located on the same side are alternately adjacently connected.

8. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 7, characterized in that: The cell also includes: Two block-shaped first doping type VCGJFET region first doping source regions (41); the VCGJFET region first doping source regions (41) and the MOSFET region source regions (42) located on the same side are alternately arranged adjacent to each other; A VCGJFET region dielectric layer (91) located above the first doping type region (8); A VCGJFET region gate electrode (10-1) formed on the VCGJFET region dielectric layer (91); A block-shaped MOSFET region dielectric layer (92) is located above the MOSFET region drain region (82), the MOSFET region channel region (6) and the MOSFET region source region (42); A MOSFET region gate electrode (10-2) located above the MOSFET region dielectric layer (92); A block-shaped VCGJFET region source electrode (12-1) is formed on the VCGJFET region second doped source region (7) and the VCGJFET region first doped source region (41); A MOSFET region source electrode (12-2) formed on the MOSFET region source region (42); The MOSFET region source region (42) and the VCGJFET region first doped source region (41) are two parts of the same first doped type source region (4); The first doping type source region (4) located in the MOSFET region serves as a MOSFET region source region (42) and the first doping type source region (41) located in the VCGJFET region serves as a VCGJFET region first doping source region (41).

9. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 8, characterized in that: The cell also includes: A substrate (1) of a second doping type and an epitaxial layer (2) of a second doping type, wherein the epitaxial layer (2) is located above the substrate (1); Two bottom gates (3) of the first doping type are formed in the epitaxial layer and are spaced apart in a first lateral direction; the first doping type region (8) is formed in the epitaxial layer and is located above the two bottom gates (3); A drain electrode (13) is arranged on the lower surface of the substrate (1); The MOSFET region source region (42), the MOSFET region channel region (6), the MOSFET region drain region (82), the MOSFET region dielectric layer (92), and the MOSFET region gate electrode (10-2) form a MOSFET region.

10. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 9, characterized in that: The top gate (81) is a combined top gate of the first doping type; The top gate comprises a top gate inner region (81-1) and a top gate outer region (81-2), wherein the top gate inner region (81-1) is formed from top to bottom in the epitaxial layer, the top gate outer region (81-2) surrounds the bottom surface and the side surface of the top gate inner region (81-1), and there is a gap between the top gate outer region (81-2) and the bottom gate (3); wherein the doping concentration of the top gate outer region (81-2) is less than the doping concentration of the top gate inner region (81-1).

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