A vertical capacitively coupled gate-controlled junction field-effect transistor

Abstract

The application provides a vertical capacitive-coupled gate-controlled junction field effect transistor including a cell, the cell is divided into VCGJFET regions and MOSFET regions arranged alternately in a transverse second direction; in a transverse first direction, the MOSFET region has a MOSFET region drain region of a first doping type, a MOSFET region channel region of a second doping type and a MOSFET region source region of the first doping type arranged successively and adjacently; the VCGJFET region has a top gate of the first doping type; in the transverse second direction, the top gate and the MOSFET region drain region are arranged alternately and adjacently; wherein the top gate, the MOSFET region drain region, the MOSFET region channel region and the MOSFET region source region are connected. The application solves the technical problem that the carrier concentration in the top gate of the conventional vertical capacitive-coupled gate-controlled junction field effect transistor is increased and there is no discharge path.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a vertical capacitively coupled gate-controlled junction field-effect transistor. Background Technology

[0002] like Figure 1 As shown, the top gate 8 of the vertical capacitively coupled gate controlled junction field-effect transistor (VCGJFET) in patent CN117637854B is floating. The structure includes: substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second-doped source region 1-4, channel one 1-5, channel two 1-6, first-doped source region 1-7, top gate 1-8, dielectric layer 1-9, VCGJFET region gate electrode 1-10, source 1-12, and drain 1-13. The problem with the vertical capacitively coupled gate controlled junction field-effect transistor in patent CN 117637854B is:

[0003] (1) When the gate-source bias voltage Vgs of a vertical capacitively coupled gate-controlled junction field-effect transistor is 0V and a positive bias voltage is applied to the drain and source, the carrier concentration in the top gate 1-8 increases by 1 to 5 times when the device is in a high-temperature blocking state. However, these carriers have no discharge path, which causes the potential difference of the top gate 1-8 to rise, which is equivalent to applying a positive bias voltage of less than 1V to the top gate 8, making it impossible for the device to be completely turned off.

[0004] (2) The carrier concentration in the top gate 1-8 increases and there is no discharge path, making the device unstable when turned off.

[0005] (3) When a vertical capacitively coupled gate-controlled junction field-effect transistor is used as a freewheeling diode, the gate and source are shorted at high temperatures, and the blocking voltage of the device is too low.

[0006] Therefore, the increased carrier concentration and lack of discharge path in the top gate of traditional vertical capacitively coupled gate-controlled field-effect transistors make the device unstable during turn-off, which is a technical problem that urgently needs to be solved by those skilled in the art.

[0007] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0008] This application provides a vertical capacitively coupled gate-controlled junction field-effect transistor to solve the technical problem that the increased carrier concentration and lack of discharge path in the top gate of traditional vertical capacitively coupled gate-controlled junction field-effect transistors cause unstable turn-off of the device.

[0009] This application provides a vertical capacitively coupled gate-controlled junction field-effect transistor including a cell, wherein the cell is divided into alternately arranged VCGJFET region and MOSFET region in the second lateral direction;

[0010] In the first transverse direction, the MOSFET region has a MOSFET drain region of a first doping type, a MOSFET channel region of a second doping type, and a MOSFET source region of a first doping type arranged sequentially and adjacently.

[0011] The VCGJFET region has a top gate of a first doping type; in the second lateral direction, the top gate and the drain region of the MOSFET region are alternately connected adjacently.

[0012] The top gate, the drain region of the MOSFET region, the channel region of the MOSFET region, and the source region of the MOSFET region are connected.

[0013] This application, by adopting the above technical solution, has the following technical effects:

[0014] The vertical capacitively coupled gate-controlled field-effect transistor of this application, by setting the MOSFET region 200, provides a controllable discharge path for the carriers in the top gate 81 of the VCGJFET region 100: top gate 81 → MOSFET drain region 82 → MOSFET channel region 6 → MOSFET source region 42, as shown. Figure 2-2 and Figure 4 The curved dashed line with arrows indicates the region; and the path is: top gate 81 → MOSFET channel region 6 → MOSFET source region 42. When the VCGJFET region 100 is turned off, the carriers in the top gate 81 move through the MOSFET drain region 82 and the MOSFET channel region 6 to the MOSFET source region 42. The carriers in the top gate 81 can also move through the MOSFET channel region 6 to the MOSFET source region 42, thereby achieving a stable turn-off of the VCGJFET region 100. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 This is a schematic diagram of a vertical capacitively coupled gate-controlled field-effect transistor (VFET) according to patent CN117637854B.

[0017] Figure 2-1 This is a three-dimensional schematic diagram of the first implementation of the vertical capacitively coupled gate-controlled junction field-effect transistor of this application;

[0018] Figure 2-2 for Figure 2-1 A top perspective view of a cell of a vertical capacitively coupled gate-controlled field-effect transistor;

[0019] Figure 2-3 for Figure 2-1 A schematic diagram of the first operating state of a vertical capacitively coupled gate-controlled field-effect transistor;

[0020] Figure 2-4 for Figure 2-1 A schematic diagram of the second operating state of a vertical capacitively coupled gate-controlled field-effect transistor;

[0021] Figure 2-5 for Figure 2-1 A schematic diagram of the third operating state of a vertical capacitively coupled gate-controlled field-effect transistor;

[0022] Figure 2-6 for Figure 2-1 A schematic diagram of the fourth operating state of a vertical capacitively coupled gate-controlled field-effect transistor;

[0023] Figure 3 for Figure 2-1 A-A' cross-sectional view of a vertical capacitively coupled gate-controlled field-effect transistor;

[0024] Figure 4 for Figure 2-1 A B-B' cross-sectional view of a vertical capacitively coupled gate-controlled field-effect transistor;

[0025] Figure 5 This is a cross-sectional view at position A-A' of the second implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application;

[0026] Figure 6 This is a cross-sectional view at position B-B' of the second implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application;

[0027] Figure 7 This is a cross-sectional view at position A-A' of the third implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application;

[0028] Figure 8 This is a cross-sectional view at position B-B' of the third implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application;

[0029] Figure 9 The electron concentration comparison diagram at position 81 of the top gate of patent CN117637854B, which is the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application and the background technology.

[0030] Figure 10 for Figure 9 A magnified comparison of electron concentration along the vertical axis;

[0031] Figure 11 This is a comparison diagram of hole concentration at position 81 of the top gate in patent CN117637854B, which is the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application and the background technology.

[0032] Figure 12 for Figure 11 A comparison of hole concentration magnified along the vertical axis;

[0033] Figure 13 This is a comparison diagram of the potential at position 81 of the top gate in patent CN117637854B, which is the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application and the background technology.

[0034] Figure label:

[0035] In the background technology:

[0036] Substrate 1-1, Epitaxial layer 1-2, Bottom gate 1-3, Second doped source region 1-4, Channel 5

[0037] Channel 2 1-6, First Doped Source Region 1-7, Top Gate 1-8, Dielectric Layer 1-9

[0038] VCGJFET region gate electrode 1-10, source electrode 1-12, drain electrode 1-13;

[0039] In this application:

[0040] Substrate 1, Epitaxial layer 2, Bottom gate 3, Drain 13, Buffer layer 14

[0041] Channel 1 51, Channel 2 52, Current spreading layer 53

[0042] Source region 4 (first doped type), source region 8 (first doped type)

[0043] VCGJFET Zone 100,

[0044] The first doped source region of the VCGJFET region is 41, and the second doped source region of the VCGJFET region is 7.

[0045] Top grid 81, inner area of ​​top grid 81-1, outer area of ​​top grid 81-2,

[0046] VCGJFET region dielectric layer 91, VCGJFET region gate electrode 10-1, VCGJFET region source electrode 12-1.

[0047] MOSFET region 200,

[0048] MOSFET source region 42, MOSFET channel region 6, MOSFET drain region 82.

[0049] MOSFET region dielectric layer 92, MOSFET region gate electrode 10-2, MOSFET region source electrode 12-2. Detailed Implementation

[0050] To make the technical solutions and advantages of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0051] The following section will focus on explaining the doping types of each region in a vertical capacitively coupled gate-controlled field-effect transistor:

[0052] Substrate 1 with a second doping type, epitaxial layer 2 with a second doping type, and bottom gate 3 with a first doping type.

[0053] Source region 4 (first doped type), source region 8 (first doped type)

[0054] Drain 13,

[0055] Buffer layer 14,

[0056] Second-doped channel 51, second-doped channel 52

[0057] The second type of doped current spreading layer 53,

[0058] VCGJFET Zone 100,

[0059] The first doped source region of the VCGJFET of the first doping type is 41.

[0060] The second doped source region 7 of the VCGJFET region of the second doped type.

[0061] The top gate 81 of the first doped type, and the heavily doped inner region of the top gate 81-1 of the first doped type.

[0062] The lightly doped first-doped type of top gate outer region 81-2,

[0063] VCGJFET region dielectric layer 91, VCGJFET region gate electrode 10-1

[0064] VCGJFET source electrode 12-1,

[0065] MOSFET region 200,

[0066] The MOSFET source region 42 is of the first doping type, and the MOSFET channel region 6 is of the second doping type.

[0067] The drain region of the first doped type MOSFET is 82.

[0068] MOSFET region dielectric layer 92, MOSFET region gate electrode 10-2, MOSFET region source electrode 12-2.

[0069] As an alternative approach, the first doping type is P-type doping, and the second doping type is N-type doping.

[0070] As an alternative approach, the first doping type is N-type doping, and the second doping type is P-type doping.

[0071] Example 1

[0072] like Figure 2-1 , Figure 2-2 , Figures 3 to 8 As shown, the vertical capacitively coupled gate-controlled field-effect transistor of this application includes a cell, which is divided into alternating VCGJFET region 100 and MOSFET region 200 in the second lateral direction.

[0073] The cells include:

[0074] The first doped type region 8, the portion located in the MOSFET region serves as the MOSFET region drain region 82 and the portion located in the VCGJFET region serves as the top gate 81 of the VCGJFET region 100;

[0075] The first doped source region 4 has a portion located in the MOSFET region as the MOSFET region source region 42 and a portion located in the VCGJFET region as the VCGJFET region first doped source region 41.

[0076] In the first transverse direction, the MOSFET region 200 has a first doped type MOSFET drain region 82, a second doped type MOSFET channel region 6, and a first doped type MOSFET source region 42 arranged sequentially and adjacently.

[0077] The VCGJFET region 100 has a top gate 81 of a first doping type;

[0078] When the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET source region 42 via the first doped type region 8 and the MOSFET channel region 6.

[0079] The top gate 81, the MOSFET drain region 82, the MOSFET channel region 6, and the MOSFET source region 42 are connected to form a discharge path for the carriers of the top gate 81. This achieves the connection of the top gate 81 through the MOSFET drain region 82, the MOSFET channel region 6, and the MOSFET source region 42.

[0080] Specifically, in the vertical capacitively coupled gate-controlled junction field-effect transistor of this application, the surface perpendicular to the thickness direction of the transistor is the lateral direction. The direction in which the drain region 82 of the first doped MOSFET region, the channel region 6 of the second doped MOSFET region, and the source region 42 of the grounded first doped MOSFET region are arranged sequentially is the first lateral direction, and the direction perpendicular to the first lateral direction is the second lateral direction. Figure 2-1 and Figure 2-2 As shown.

[0081] The present application discloses a vertical capacitively coupled gate-controlled junction field-effect transistor (VCGJFET).

[0082] The vertical capacitively coupled gate-controlled field-effect transistor (VCGJFET) of this application has a VCGJFET region 100. The VCGJFET region 100 is the main structure that implements the function of the VCGJFET itself. The turn-off of the VCGJFET region 100 is consistent with the turn-off of the VCGJFET of this application, and the turn-on of the VCGJFET region 100 is consistent with the turn-on of the VCGJFET of this application. Furthermore, a controllable switch, namely a MOSFET region 200, is provided for the VCGJFET region 100. By controlling the MOSFET region 200, the flow of charge carriers at the top gate 81 can be controlled.

[0083] Specifically, the MOSFET region 200 is configured such that the MOSFET region 200 has a first-doped MOSFET region drain region 82, a second-doped MOSFET region channel region 6, and a grounded first-doped MOSFET region source region 42 arranged in sequence, as the structure for forming the MOSFET region 200.

[0084] When the VCGJFET region 100 is operating, the current concentration in the top gate 81 of the VCGJFET region 100 will increase, resulting in an increase in the potential difference of the top gate 81.

[0085] At this time, when the gate of VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the MOSFET source region 42 via the first doped region 8 and the MOSFET channel region 6, thereby causing the carriers to flow out of the top gate 81, which lowers the potential of the top gate 81 instead of keeping it at a high potential. In other words, when the VCGJFET region 100 is turned off, the first doped region 8, the MOSFET channel region 6, and the MOSFET source region 42 serve as the discharge path for the carriers at the top gate 81, thus lowering the potential of the top gate 81.

[0086] In this way, when the VCGJFET region 100 of the vertical capacitively coupled gate-controlled field-effect transistor device of this application is turned off at room temperature or high temperature, the first doped region 8, the MOSFET channel region 6, and the MOSFET source region 42 will all serve as discharge paths for carriers at the top gate 81, reducing the potential of the top gate 81, so that the VCGJFET region 100 can be stably turned off at both room temperature and high temperature.

[0087] The vertical capacitively coupled gate-controlled field-effect transistor of this application, by setting the MOSFET region 200, provides a controllable discharge path for the carriers in the top gate 81 of the VCGJFET region 100: top gate 81 → first doped type region 8 → MOSFET channel region 6 → MOSFET source region 42, as shown. Figure 2-2 and Figure 4 The curved dashed line with arrows indicates that when the VCGJFET region 100 is turned off, the carriers in the top gate 81 move through the first doped type region 8 and the MOSFET channel region 6 to the MOSFET source region 42 to achieve stable turn-off of the VCGJFET region 100.

[0088] In this embodiment, the top gate 81 and the MOSFET drain region 82 are two parts of the same structure of the first doped type region 8; the MOSFET source region 42 and the VCGJFET first doped source region 41 are two parts of the same structure of the first doped type source region 4.

[0089] In this way, the first doped region 8, as a whole, can be fabricated using the same photomask layer, and the first doped source region 4, as a whole, can also be fabricated using the same photomask layer. This achieves performance while saving on processes and costs.

[0090] In implementation, the MOSFET region 200 is a normally open structure with a threshold voltage Vth. MOS It is a negative value;

[0091] The VCGJFET region 100 is normally off and has a threshold voltage Vth. JFET It is a positive value;

[0092] The gate electrode of the VCGJFET region (corresponding to VCGJFET region gate electrode 10-1 in the figure) and the gate electrode of the MOSFET region 200 (corresponding to MOSFET region gate electrode 10-2 in the figure) share a single device gate electrode. The source electrode of the VCGJFET region 100 (corresponding to VCGJFET region source electrode 12-1 in the figure) and the source electrode of the MOSFET region 200 share a single device source electrode. The device gate-source voltage of the vertical capacitively coupled gate-controlled junction field-effect transistor device is represented by Vgs.

[0093] The vertical capacitively coupled gate-controlled field-effect transistor of this application has four operating states.

[0094] like Figure 2-3 As shown, the first working state is as follows:

[0095] When the MOSFET region threshold voltage Vth MOS When the device gate-source voltage Vgs ≤ zero:

[0096] When the MOSFET region 200 is in the subthreshold range, the charge carriers in the top gate 81 move through the first doped region 8, the MOSFET channel region 6, and the MOSFET source region 42, causing the potential of the top gate 81 to decrease and the VCGJFET region 100 to be stably turned off. Figure 2-3 As shown, as Vth MOS -100V, Vth JFET It is 200V.

[0097] Specifically, the first working state has two scenarios:

[0098] First scenario: When the MOSFET threshold voltage Vth... MOS When the device gate-source voltage Vgs ≤ zero, the vertical capacitively coupled gate-controlled junction field-effect transistor of this application operates at room temperature as follows:

[0099] When the MOSFET region 200 is in the subthreshold range, the charge carriers in the top gate 81 move through the first doped type region 8, the MOSFET channel region 6, and then flow out through the MOSFET source electrode 12-2. The potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0100] The second scenario: when the MOSFET region threshold voltage Vth MOSWhen the device gate-source voltage Vgs ≤ 0 and the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present application operates at high temperature (the carrier concentration at high temperature is much higher than that at room temperature):

[0101] The potential of the device gate electrode is zero, the MOSFET region 200 is in the subthreshold region, the carriers in the top gate 81 move through the first-doped type region 8, the MOSFET region channel region 6, and reach the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0102] In implementation, as Figure 2-4 shown, the second operating state is as follows:

[0103] When the gate-source voltage Vgs of the device < MOSFET region threshold voltage Vth MOS :

[0104] The MOSFET region 200 is turned on, the carriers in the top gate 81 move through the first-doped type region 8, the MOSFET region channel region 6, and reach the MOSFET region source region 42, the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0105] Specifically, the second operating state has two cases:

[0106] The first case: When the gate-source voltage Vgs of the device < MOSFET region threshold voltage Vth MOS : When the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present application operates at room temperature:

[0107] The MOSFET region 200 is turned on, the carriers in the top gate 81 move through the first-doped type region 8, the MOSFET region channel region 6, and reach the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0108] The second case: When the gate-source voltage Vgs of the device < MOSFET region threshold voltage Vth MOS : When the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present application operates at high temperature (the carrier concentration at high temperature is much higher than that at room temperature):

[0109] The potential of the device gate electrode is zero, the MOSFET region 200 is turned on, the carriers in the top gate 81 move through the first doped type region 8 and the MOSFET region channel region 6 to the MOSFET region source region 42 (and then flow out through the MOSFET region source electrode 12-2), the potential of the top gate 81 decreases, and the VCGJFET region 100 is stably turned off.

[0110] In implementation, as Figure 2-5 shown, the third working state is as follows:

[0111] When 0 < the gate-source voltage Vgs of the device < the threshold voltage Vth of the VCGJFET region JFET the MOSFET region 200 is turned off and the VCGJFET region 100 is in the sub-threshold segment;

[0112] As Figure 2-6 shown, the fourth working state is as follows:

[0113] When the gate-source voltage Vgs of the device ≥ the threshold voltage Vth of the VCGJFET region JFET the MOSFET region 200 is turned off and the VCGJFET region (100) is turned on.

[0114] In implementation, as Figure 2-1 , Figure 2-2 shown, as Figures 3 to 8 shown, one cell includes one VCGJFET region 100 and two MOSFET regions 200, and the two MOSFET regions 200 are symmetrically arranged; the cell further includes:

[0115] Two block-shaped second doped type VCGJFET region second doped source regions 7; the VCGJFET region second doped source region 7 and the MOSFET region channel region 6 on the same side are connected.

[0116] In implementation, as Figure 2-1 , Figure 2-2 shown, as Figures 3 to 8 shown, the VCGJFET region second doped source region 7 and the MOSFET region channel region 6 are located in the same layer, and the VCGJFET region second doped source region 7 and the MOSFET region channel region 6 on the same side are alternately and adjacently connected.

[0117] The VCGJFET region second doped source region 7 and the MOSFET region channel region 6 are located in the same layer, effectively utilizing the layer space where the VCGJFET region second doped source region 7 is located, making the space utilization rate of the field effect transistor relatively high.

[0118] In implementation, as Figure 2-1, Figure 2-2 As shown, Figures 3 to 8 As shown, the cell further includes:

[0119] Two block-shaped VCGJFET regions of the first doping type, first doped source regions 41; the VCGJFET region first doped source regions 41 and the MOSFET region source regions 42 located on the same side are alternately arranged adjacent to each other;

[0120] VCGJFET region dielectric layer 91 is located above the first doped type region 8;

[0121] VCGJFET region gate electrode 10-1 is formed on the VCGJFET region dielectric layer 91;

[0122] A block-shaped MOSFET region dielectric layer 92 is located above the MOSFET region drain region 82, the MOSFET region channel region 6, and the MOSFET region source region 42;

[0123] The MOSFET region gate electrode 10-2 is located above the MOSFET region dielectric layer 92;

[0124] A block-shaped source electrode 12-1 of the VCGJFET region is formed on the second doped source region 7 of the VCGJFET region and the first doped source region 41 of the VCGJFET region.

[0125] The MOSFET source electrode 12-2 is formed on the MOSFET source region 42.

[0126] During implementation, such as Figure 2-1 , Figure 2-2 As shown, Figures 3 to 8 As shown, the cell further includes:

[0127] A substrate 1 of a second doping type and an epitaxial layer 2 of a second doping type are located above the substrate 1;

[0128] Two bottom gates 3 of the first doping type are formed in the epitaxial layer and are spaced apart in the first lateral direction; the first doping type region 8 is formed in the epitaxial layer and is located above the two bottom gates 3;

[0129] Drain 13 is disposed on the lower surface of the substrate 1;

[0130] The MOSFET region is formed by the source region 42, the channel region 6, the drain region 82, the dielectric layer 92, and the gate electrode 10-2.

[0131] During implementation, such as Figure 3 and Figure 4 As shown, Figure 7 and Figure 8 As shown, the top gate 81 is a combined top gate of the first doping type;

[0132] The top gate includes an inner top gate region 81-1 and an outer top gate region 81-2. The inner top gate region 81-1 is formed from top to bottom within the epitaxial layer. The outer top gate region 81-2 surrounds the bottom and side surfaces of the inner top gate region 81-1, and there is a gap between the outer top gate region 81-2 and the bottom gate 3. The doping concentration of the outer top gate region 81-2 is less than that of the inner top gate region 81-1.

[0133] The top gate outer region 81-2 surrounds the bottom and side surfaces of the top gate inner region 81-1, and the doping concentration of the top gate outer region 81-2 is less than that of the top gate inner region 81-1, so that the potential difference of the top gate from the outer surface of the top gate outer region 81-2 to the top surface of the top gate inner region 81-1 is relatively gentle.

[0134] In the semiconductor field, under uniform doping conditions, the potential expression at position x in a p-type doped region is... The following relation (1) must be satisfied:

[0135]

[0136] Where e is the electron charge, N a ε is the doping concentration of the P-type doped region, εs is the semiconductor dielectric constant, and x is the doping concentration of the P-type doped region. p It is the location where the electric field E is zero.

[0137] According to equation (1), the carriers in the N-type doped top gate 81 are discharged through the normally open MOSFET region 200 (formed by the P-type doped MOSFET drain region 82, the N-type doped MOSFET channel region 6, the MOSFET source region 42, the MOSFET dielectric layer 92, the MOSFET gate electrode 10-2, and the MOSFET source electrode 12-2) with a negative threshold voltage, thereby reducing the carrier concentration in the top gate 81 and preventing the potential of the top gate 81 from rising at room temperature and high temperature.

[0138] According to equation (1), it can also be seen that in the P-type doped region, the N of the P-type doped region... a The smaller the value, the lower the potential at the same location (i.e., the same x). The smaller the value, the better. That is, the smaller the value of position x in the P-type doped region relative to the position where the electric field E is zero. p The potential difference is relatively small. Specifically in this application, the top gate 81 is a P-type doped region.

[0139] This shows that when two P-type doped regions with different doping concentrations have the same zero electric field E, then the N of which P-type doped region is at the same location... a The smaller the value, the lower the potential at the same location (i.e., the same x). The smaller the value, the better. That is, the smaller the value of position x in the P-type doped region relative to the position where the electric field E is zero. p The potential difference is relatively small. This increases the current-carrier flow path, widening the process window for vertical capacitively coupled gate-controlled field-effect transistors. The widening of the process window and the current path are achieved simultaneously.

[0140] In this application, the position x where the electric field E is zero p This refers to the surface of the inner top gate region 81-1. The outer top gate region 81-2 surrounds the bottom and sides of the inner top gate region 81-1, and the doping concentration of the outer top gate region 81-2 is lower than that of the inner top gate region 81-1, resulting in a gentler potential difference between the outer surface of the outer top gate region 81-2 and the top surface of the inner top gate region 81-1. The process window and current path widening are achieved simultaneously; by controlling the channel concentration, the magnitude of the conduction current can be controlled.

[0141] Taking the VCGJFET region of the vertical capacitively coupled gate-controlled field-effect transistor in this application embodiment as a PMOS transistor as an example, when the gate electrode 10-1 of the VCGJFET region is connected to a positive gate voltage (e.g., 15 volts), and the source electrode 12-1 of the VCGJFET region is grounded, and the drain electrode 13 is connected to a positive voltage, an electric field is generated between the drain electrode 13 and the source electrode 12-1 of the VCGJFET region, thus generating a conduction current. The direction of the current is as follows: Figure 3 The image shows a curved dashed line with an arrow in the center.

[0142] When the bias voltage of the gate electrode 10-1 in the VCGJFET region is less than or equal to 0V, the potential in the inner region 81-1 of the top gate is less than or equal to 0.8V (i.e., consistent with the bias voltage), and the channel between the outer region 81-2 of the top gate and the VCGJFET region (in...) Figure 3 When the PN junction formed by the middle channel 51 and the middle channel 52 is reverse biased, the channel of the VCGJFET region is pinched off, and the VCGJFET region of the vertical capacitively coupled gate-controlled field-effect transistor of this application is turned off.

[0143] Furthermore, simulations show that the on-resistance Ron,sp of the vertical capacitively coupled gate-controlled field-effect transistor in this embodiment is less than three times that at room temperature, making it compatible with existing SiC MOSFET applications. In other words, the application scenarios of the vertical capacitively coupled gate-controlled field-effect transistor in this embodiment have good compatibility with existing technologies and strong versatility.

[0144] During implementation, such as Figure 3 and Figure 4 As shown, Figure 7 and Figure 8 As shown, the cross-section of the outer region 81-2 of the top grid is U-shaped, the inner bottom of the outer region 81-2 of the top grid wraps around the bottom surface of the inner region 81-1 of the top grid, and the inner wall of the outer region 81-2 of the top grid wraps around the side of the inner region 81 of the top grid.

[0145] In this way, the outer region 81-2 of the top gate wraps around the bottom and sides of the inner region 81-1 of the top gate, so that the bottom and sides of the inner region 81-1 of the top gate have the outer region 81-2 of the top gate with a relatively slow potential change, and the overall process window of the top gate is larger.

[0146] Specifically, the inner region 81-1 of the top gate is heavily doped.

[0147] The heavily doped top gate inner region 81-1 is designed to prevent the depletion regions on the surface of the top gate from being connected, thereby achieving the required blocking voltage.

[0148] In practice, the doping concentration of the outer region 81-2 of the top gate is one to two orders of magnitude lower than that of the inner region 81-2 of the top gate.

[0149] Specifically, such as Figure 2-1 , Figures 3 to 8 As shown, the cell further includes:

[0150] A buffer layer 14 is formed between the substrate 1 and the epitaxial layer 2.

[0151] Specifically, the gate electrode 10-1, the dielectric layer 91, and the top gate 81 of the VCGJFET region constitute the gate structure of the VCGJFET region.

[0152] As an alternative approach, as shown in the figure, a top gate 81 of the first doped type, a portion located between the top gate 81 and the bottom gate 3, and the bottom gate 3 form a JFET region 1;

[0153] The two bottom gates 3, and the portion located between the bottom gates 3, form JFET region two;

[0154] The top gate of JFET region one is indirectly controlled by the VCGJFET region gate electrode 10-1 separated by the VCGJFET region dielectric layer 91, so that JFET region one and JFET region two are controlled by the VCGJFET region gate electrode 10-1 separated by the VCGJFET region dielectric layer 91.

[0155] As an optional approach, such as Figure 7 and Figure 8 As shown, the cell also includes:

[0156] A second doped type of channel 51 is formed in the portion between the top gate 81 and the bottom gate 3, with the top gate 81 located above the channel 51;

[0157] Specifically, JFET region one is formed by top gate 81, channel one 51, and bottom gate 3, while JFET region two is formed by two bottom gates 3 and the portion of the epitaxial layer located between the bottom gates 3.

[0158] As another alternative approach, cells also include:

[0159] A second doped type of channel 51 is formed in the portion between the top gate 81 and the bottom gate 3, with the top gate 81 located above the channel 51;

[0160] A second doped channel 52 is formed between the two bottom gates 3;

[0161] Specifically, JFET region one is formed by top gate 81, channel one 51, and bottom gate 3, while JFET region two is formed by two bottom gates 3 and channel two 52.

[0162] As another alternative, such as Figure 3 and Figure 4 As shown, Figure 5 and Figure 6 As shown, the cell also includes:

[0163] A second doped type of channel 51 is formed in the portion between the top gate 81 and the bottom gate 3, with the top gate 81 located above the channel 51;

[0164] A second doped channel 52 is formed between the two bottom gates 3;

[0165] The second doped current spreading layer 53 is formed in the epitaxial layer 2 at a position below the bottom gate 3 and the second channel 52;

[0166] Specifically, JFET region one is formed by top gate 81, channel one 51, and bottom gate 3, while JFET region two is formed by two bottom gates 3, channel two 52, and current spreading layer 53.

[0167] The doping concentrations of channel 1 5, channel 2 52, and current spreading layer 53 are greater than the doping concentration of the epitaxial layer, which helps to reduce the on-resistance of the device and improve the device performance.

[0168] In practice, the doping concentration of the outer region 81-2 of the top gate is greater than or equal to 2 × 10⁻⁶. 17 cm -3 Less than or equal to 5 × 10 18 cm -3The doping concentration of the inner region 81-1 of the top gate is greater than or equal to 2 × 10⁻⁶. 18 cm -3 Less than or equal to 4 × 10 20 cm -3 .

[0169] In practice, the thickness of the bottom of the outer region 81-2 of the top grid is greater than or equal to 0.02 μm and less than or equal to 0.2 μm, and the thickness of the sidewall of the outer region 81-2 of the top grid is greater than or equal to 0.02 μm and less than or equal to 0.2 μm.

[0170] The thickness of the inner region 81-1 of the top grid is 0.02μm less than or equal to 0.1μm.

[0171] The doping concentration and thickness of the top gate inner region 81-1 meet the above requirements to prevent the depletion region on the surface of the top gate inner region 81-1 from becoming interconnected during blocking, which would lead to a low breakdown voltage. In other words, this is to ensure that the depletion region on the surface of the top gate inner region 81-1 is not interconnected, thus meeting the required blocking breakdown voltage.

[0172] The doping concentration, bottom thickness, and sidewall thickness of the top gate outer region 81-2 must meet the above requirements in order to broaden the process window of the top gate and prevent the process from failing to achieve the device performance.

[0173] Figure 9 This is a comparison diagram of electron concentration at position 81 of the top gate when the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application is turned off, according to patent CN117637854B, which is the background technology of the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application. Figure 10 for Figure 9 A magnified comparison of electron concentrations along the vertical axis.

[0174] Figure 9 and Figure 10 The horizontal axis represents the dimensions of the top gate 81 and the MOSFET drain region 82, in μm. Figure 9 and Figure 10 The horizontal axis and Figure 3 The dashed line with the arrowhead corresponds to the line. Figure 9 and Figure 10 The vertical axis represents electron concentration, measured in cm⁻¹. -3 T = 300K is the ambient temperature for operation, and T = 450K is the ambient temperature for operation.

[0175] from Figure 9 and Figure 10As can be seen, the top gate is vertically downward at the middle position of the upper surface. When it is turned off after high temperature operation (T=300K and T=450K), the carriers of the top gate 81 of this application move to the source region 42 of the MOSFET region through the drain region 82 of the MOSFET region and the channel region 6 of the MOSFET region for discharge. The electron concentration of this application is much smaller than that of the prior art patent CN117637854B, thus avoiding the rise of the potential of the top gate 81 of this application at high temperature.

[0176] Figure 11 This is a comparison diagram of hole concentration at position 81 of the top gate when the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application is turned off, according to patent CN117637854B, which is the background technology of the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application. Figure 12 for Figure 11 A comparison chart of hole concentration magnified along the vertical axis.

[0177] Figure 11 and Figure 12 The horizontal axis represents the dimensions of the top gate 81 and the MOSFET drain region 82, in μm. Figure 11 and Figure 12 The horizontal axis and Figure 3 The dashed line with the arrowhead corresponds to the line. Figure 11 and Figure 12 The vertical axis represents hole concentration, measured in cm³. -3 T = 300K is the ambient temperature for operation, and T = 450K is the ambient temperature for operation.

[0178] from Figure 11 and Figure 12 As can be seen, the top gate is vertically downward at the middle position of the upper surface. When it is turned off after high temperature operation (T=300K and T=450K), the carriers of the top gate 81 of this application move to the source region 42 of the MOSFET region through the drain region 82 of the MOSFET region and the channel region 6 of the MOSFET region for discharge. The hole concentration of this application is much smaller than the hole concentration of the prior art patent CN117637854B, thus avoiding the rise of the potential of the top gate 81 of this application at high temperature.

[0179] Since the present application and the prior art patent CN117637854B are P-channel hole conductors, the overall electron concentration is low and the overall hole concentration is high.

[0180] Figure 13 The potential comparison diagram at the top gate 81 position of patent CN117637854B, which is the background technology of the first implementation of the vertical capacitively coupled gate-controlled field-effect transistor of this application. Figure 13 The horizontal axis represents the dimensions of the top gate 81 and the MOSFET drain region 82, in μm. Figure 13 The horizontal axis and Figure 3 The dashed line with the arrowhead corresponds to the line. Figure 13 The vertical axis represents electric potential, with units of V. T = 300K represents the ambient operating temperature, and T = 450K represents the ambient operating temperature.

[0181] from Figure 13 As can be seen from this, the potential of this application is much smaller than that of the prior art patent CN117637854B, which is located vertically downward at the middle position of the upper surface of the top grid.

[0182] Example 2

[0183] The vertical capacitively coupled gate-controlled junction field-effect transistor of this application differs from that of Embodiment 1 only in that:

[0184] The top gate 81 and the MOSFET drain region 82 are two independent structures, each with its own fabrication steps;

[0185] The MOSFET source region 42 and the first doped source region 41 of the VCGJFET region are two independent structures, each with its own fabrication steps.

[0186] Correspondingly, when the VCGJFET region 100 is turned off, the carriers in the top gate 81 move to the source region 42 of the MOSFET region via the drain region 82 of the MOSFET region and the channel region 6 of the MOSFET region. The carriers in the top gate 81 also move to the source region 42 of the MOSFET region via the channel region 6 of the MOSFET region.

[0187] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0188] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0189] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0190] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0191] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0192] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A vertical capacitively coupled gate-controlled junction field effect transistor, characterized by The cell is divided into VCGJFET region (100) and MOSFET region (200) alternately arranged in the second direction; In the first direction, the MOSFET region (200) has first-doped-type MOSFET region drain region (82), second-doped-type MOSFET region channel region (6) and first-doped-type MOSFET region source region (42) arranged in sequence; The VCGJFET region (100) has first-doped-type top gate (81); in the second direction, the top gate (81) and the MOSFET region drain region (82) are arranged alternately adjacent; The top gate (81), the MOSFET region drain region (82), the MOSFET region channel region (6) and the MOSFET region source region (42) are connected. The direction perpendicular to the thickness direction of the vertical capacitive-coupled gate-controlled junction field effect transistor is the lateral direction, the first-doped-type MOSFET region drain region (82), the second-doped-type MOSFET region channel region (6) and the first-doped-type MOSFET region source region (42) arranged in sequence is the first lateral direction, and the direction perpendicular to the first lateral direction is the second lateral direction.

2. The vertical capacitively coupled gated junction field effect transistor of claim 1, wherein, The top gate (81) and the MOSFET region drain region (82) are two parts of the same first-doped-type region (8); wherein the part of the first-doped-type region (8) in the MOSFET region is the MOSFET region drain region (82) and the part in the VCGJFET region is the top gate (81) of the VCGJFET region (100); Correspondingly, when the VCGJFET region (100) is turned off, the carriers in the top gate (81) move to the MOSFET region source region (42) through the first-doped-type region (8) and the MOSFET region channel region (6).

3. The vertical capacitively coupled gated junction field effect transistor of claim 2, wherein, The MOSFET region (200) is normally on structure and threshold voltage Vth MOS is negative; The VCGJFET region (100) is normally off structure and threshold voltage Vth JFET is positive; The gate electrode of the VCGJFET region and the gate electrode of the MOSFET region (200) share a device gate electrode, the source electrode of the VCGJFET region (100) and the source electrode of the MOSFET region (200) share a device source electrode, and the device gate-source voltage of the vertical capacitive-coupled gate-controlled junction field effect transistor is represented by Vgs; The first working state of the vertical capacitive-coupled gate-controlled junction field effect transistor is as follows: When the MOSFET region threshold voltage Vth MOS ≤ device gate-source voltage Vgs≤ zero: The MOSFET region (200) is in the sub-threshold section, the carriers in the top gate (81) move to the MOSFET region source region (42) through the first-doped-type region (8) and the MOSFET region channel region (6), the potential of the top gate (81) is reduced, and the VCGJFET region (100) is stably turned off.

4. The vertical capacitively coupled gated junction field effect transistor of claim 2, wherein, The second working state is as follows: When the device gate-source voltage Vgs < the MOSFET region threshold voltage Vth MOS : The MOSFET region (200) is turned on, the carriers in the top gate (81) move to the MOSFET region source region (42) through the first doping type region (8) and the MOSFET region channel region (6), the potential of the top gate (81) is reduced, and the VCGJFET region (100) is stably turned off.

5. The vertical capacitively coupled gated junction field effect transistor of claim 2, wherein, The third working state is as follows: When 0 < gate-source voltage Vgs of the device < threshold voltage Vth of the VCGJFET region JFET the MOSFET region (200) is off, and the VCGJFET region (100) is in subthreshold regime; The fourth working state is as follows: When the gate-source voltage Vgs of the device is greater than the threshold voltage Vth of the VCG JFET region JFET the MOSFET region (200) is off and the VCG JFET region (100) is on.

6. The vertical capacitively coupled gated junction field effect transistor of any one of claims 1 to 5, wherein, One of the cells includes one VCGJFET region (100) and two MOSFET regions (200), and the two MOSFET regions (200) are symmetrically arranged; the cell further includes: Two block-shaped second-doping-type VCGJFET region second-doping source regions (7); the VCGJFET region second-doping source regions (7) and the MOSFET region channel regions (6) located on the same side are connected.

7. The vertical capacitively coupled gated junction field effect transistor of claim 6, wherein, The VCGJFET region second-doping source regions (7) and the MOSFET region channel regions (6) are located on the same layer, and the VCGJFET region second-doping source regions (7) and the MOSFET region channel regions (6) located on the same side are alternately and adjacently arranged.

8. The vertical capacitively coupled gated junction field effect transistor of claim 7, wherein, The cell further includes: Two block-shaped first-doping-type VCGJFET region first-doping source regions (41); the VCGJFET region first-doping source regions (41) and the MOSFET region source regions (42) located on the same side are alternately and adjacently arranged; A VCGJFET region dielectric layer (91) is located above the first-doping-type region (8); A VCGJFET region gate electrode (10-1) is formed above the VCGJFET region dielectric layer (91); A block-shaped MOSFET region dielectric layer (92) is located above the MOSFET region drain region (82), the MOSFET region channel region (6), and the MOSFET region source region (42); A MOSFET region gate electrode (10-2) is located above the MOSFET region dielectric layer (92); A block-shaped VCGJFET region source electrode (12-1) is formed above the VCGJFET region second-doping source region (7) and the VCGJFET region first-doping source region (41); A MOSFET region source electrode (12-2) is formed above the MOSFET region source region (42); The MOSFET region source region (42) and the VCGJFET region first-doping source region (41) are two parts of the same first-doping-type source region (4); The first-doping-type source region (4) is located in the MOSFET region as a MOSFET region source region (42) and in the VCGJFET region as a VCGJFET region first-doping source region (41).

9. The vertical capacitively coupled gated junction field effect transistor of claim 8, wherein, The cell further includes: A second-doping-type substrate (1) and a second-doping-type epitaxial layer (2) are located above the substrate (1); Two first doped type bottom gates (3) are formed in the epitaxial layer and are spaced apart in the first lateral direction; the first doped type region (8) is formed in the epitaxial layer and is located above the two bottom gates (3); A drain (13) is arranged on the lower surface of the substrate (1); The MOSFET region source region (42), the MOSFET region channel region (6), the MOSFET region drain region (82), the MOSFET region dielectric layer (92), and the MOSFET region gate electrode (10-2) form a MOSFET region.

10. The vertical capacitively coupled gated junction field effect transistor of claim 9, wherein, The top gate (81) is a combined top gate of the first doped type; The top gate includes a top gate inner region (81-1) and a top gate outer region (81-2); the top gate inner region (81-1) is formed in the epitaxial layer from top to bottom; the top gate outer region (81-2) surrounds the bottom surface and the side surface of the top gate inner region (81-1); and the top gate outer region (81-2) is spaced apart from the bottom gate (3); wherein the doping concentration of the top gate outer region (81-2) is less than the doping concentration of the top gate inner region (81-1).

Images