Grid-control junction field effect transistor

Abstract

The invention provides a grid-controlled junction field effect transistor, which comprises a substrate and an epitaxial layer formed on the substrate, the channel region of the second doping type is formed downwards from the top surface of the epitaxial layer; the second doping type source electrode contact region is formed downwards from the top surface of the epitaxial layer and is connected to the outer edge of the channel region; the grid electrode of the first doping type is formed on the channel region in the vertical direction, and the outer edge of the grid electrode is located in the outer edge of the channel region in the transverse direction, so that a preset distance is kept between the grid electrode and the source electrode contact region of the second doping type in the transverse direction; and the well region is positioned below the second doping type source contact region. According to the invention, the technical problem that the input capacitance and grid leakage of a traditional grid-controlled junction field effect transistor are relatively large is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a gate-controlled junction field effect transistor. Background Art

[0002] Silicon carbide devices have the advantages of high voltage resistance, low on-resistance, faster switching speed, higher operating temperature, heat dissipation and good radiation resistance, and have been widely used in power electronic circuits. Silicon carbide devices include MOSFET and JFET. As a three-port device, the working principle of JFET device is to use gate voltage to control the reverse bias and forward bias of PN, so as to achieve the purpose of controlling the opening and closing of the channel. It has the advantages of low noise, small size, and high-frequency response. JFET devices made of silicon carbide materials can also be used in high-power application scenarios, such as new energy vehicles, high-voltage power transmission, etc.

[0003] The gate-controlled junction field-effect transistor with a silicon carbide step, referred to as JFET, is the full name of Junction Field-Effect Transistor. Existing gate-controlled junction field-effect transistors are Figure 1 As shown, well region 1, first doping type source contact region 2, second doping type source contact region 3, gate 4, channel region 5, dielectric layer 9. The gate-controlled junction field effect transistor is a power device. A power device is actually a switch, so in the application process, switching loss cannot be ignored. Figure 1 The traditional gate-controlled junction field effect transistor shown does not take this problem into consideration. When the device is turned on, there will be a large input capacitance and gate leakage, which will lead to increased switching loss and drive of the device.

[0004] Therefore, the input capacitance and gate leakage of conventional gate-controlled junction field effect transistors are relatively large, which is a technical problem that those skilled in the art urgently need to solve.

[0005] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0006] The present application provides a gate-controlled junction field effect transistor to solve the technical problems of large input capacitance and gate leakage of a traditional gate-controlled junction field effect transistor.

[0007] The present application provides a gate-controlled junction field effect transistor, comprising: A substrate, an epitaxial layer formed on the substrate; A channel region of a second doping type is formed downward from the top surface of the epitaxial layer; A second doping type source contact region is formed downward from the top surface of the epitaxial layer and connected to the outer edge of the channel region; A gate of the first doping type is formed on the channel region in the vertical direction, and an outer edge of the gate is located within an outer edge of the channel region in the lateral direction, so that the gate and the second doping type source contact region maintain a preset spacing in the lateral direction; The well region is located below the second doping type source contact region.

[0008] Due to the adoption of the above technical solution, this application has the following technical effects: The gate-controlled junction field effect transistor of the present application, because the gate is formed on the channel region in the vertical direction, and the outer edge of the gate is located within the outer edge of the channel region in the lateral direction, the gate and the second doping type source contact region maintain a preset spacing in the lateral direction, that is, the gate of the first doping type and the source contact region of the second doping type are completely non-contacting, and the two will not form a PN junction. In this way, during the opening and closing process of the gate-controlled junction field effect transistor of the present application, there is no PN junction between the gate of the first doping type and the source contact region of the second doping type, and correspondingly, no loss will be generated. In addition, the input capacitance of the gate-controlled junction field effect transistor of the present application is very small, and the gate-controlled junction field effect transistor has a faster switching speed; at the same time, the gate leakage is also very small. In addition, because the gate and the second doping type source contact region are separated, this can adjust the forward and reverse leakage between the gate and the source, and improve the reliability of the device operation and the driving loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of a gate-controlled junction field effect transistor of background technology; Figure 2 A schematic diagram of a gate-controlled junction field effect transistor of the present application; Figure 3 for Figure 2 The corresponding simulation diagram; Figure 4 for Figure 1 Schematic diagram of the depletion line of the gate-controlled junction field effect transistor when Vgs=0V; Figure 5 for Figure 2 Schematic diagram of the depletion line of a gate-controlled junction field effect transistor when Vgs=0V.

[0010] Reference numerals: Well region 1, first doping type source contact region 2, second doping type source contact region 3, Gate 4, channel region 5, source electrode 6, gate electrode 7, dielectric layer 9, current guiding layer 10, Epitaxial layer 11 , buffer layer 12 , substrate 13 , drain electrode 14 . DETAILED DESCRIPTION

[0011] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0012] The present application aims to solve the technical problem that large input capacitance and gate leakage result in large switching losses. Embodiment 1

[0013] like Figure 2 and Figure 3 As shown, the gate-controlled junction field effect transistor of the present application comprises: A substrate 13, and an epitaxial layer formed on the substrate 13; A channel region 5 of a second doping type is formed downward from the top surface of the epitaxial layer; A second doping type source contact region 3, formed downward from the top surface of the epitaxial layer and connected to the outer edge of the channel region 5; A gate 4 of the first doping type is formed on the channel region 5 in the vertical direction, and an outer edge of the gate 4 is located inside an outer edge of the channel region 5 in the lateral direction, that is, the gate 4 is smaller than the channel region 5, so that the gate 4 and the second doping type source contact region 3 maintain a preset spacing in the lateral direction; A well region 1, located below the second doping type source contact region 3; The well region 1 , the second doping type source contact region 3 , the gate 4 , and the channel region 5 form a JFET structure.

[0014] Background technology Figure 1 In the embodiment, the gate 4 of the first doping type and the source contact region 3 of the second doping type are connected to form a PN junction. Figure 1 During the opening process of the gate-controlled junction field effect transistor, the depletion region of the PN junction formed by the gate 4 and the source contact region 3 becomes narrower. This process causes loss.

[0015] exist Figure 1During the closing process of the gate-controlled junction field effect transistor, the direction of the external electric field of the PN junction formed by the gate 4 and the source contact region 3 begins to be the same as the direction of the built-in electric field, and the depletion region gradually widens. This process also causes loss.

[0016] In the gate-controlled junction field effect transistor of the present application, since the gate 4 is formed on the channel region 5 in the vertical direction, and the outer edge of the gate 4 is located within the outer edge of the channel region 5 in the lateral direction, that is, the gate 4 is smaller than the channel region 5, so that the gate 4 and the second doping type source contact region 3 maintain a preset spacing in the lateral direction, that is, the first doping type gate 4 and the second doping type source contact region 3 are completely non-contacting, and the two will not form a PN junction. In this way, during the opening and closing process of the gate-controlled junction field effect transistor of the present application, the first doping type gate 4 and the second doping type source contact region 3 have no PN junction. The first doping type gate 4 and the second doping type source contact region 3 have no PN junction, which has at least the following advantages: The first doping type gate 4 and the second doping type source contact area 3 have no PN junction, so that the input capacitance of the gate-controlled junction field effect transistor of the present application is very small; the small input capacitance makes the gate-controlled junction field effect transistor have a faster switching speed and smaller switching loss.

[0017] If the gate 4 of the first doping type and the source contact region 3 of the second doping type directly form a PN junction, the PN junction between the two will have the leakage of the PN junction between the two, thereby causing gate leakage. The gate 4 of the first doping type and the source contact region 3 of the second doping type of the gate-controlled junction field effect transistor of the present application do not form a PN junction, and will not cause gate leakage.

[0018] In addition, because the gate 4 is separated from the second doping type source contact region 3, the forward and reverse leakage between the gate and the source can be adjusted, thereby improving the reliability and driving loss of the device.

[0019] The current path of the gate-controlled junction field effect transistor of the present invention is used when it is turned on. Figure 2 The dashed line with an arrow in FIG.

[0020] The reasons why the input capacitance of the gate-controlled junction field effect transistor of the present application is very small are described in detail below: If the gate 4 is in contact with the second doping type source contact region 3, a PN junction will be formed between the gate 4 and the second doping type source contact region 3, and there will be a PN junction capacitance between the gate 4 and the second doping type source contact region 3. The input capacitance is originally mainly formed by the PN junction capacitance formed by the gate 4 and the second doping type source contact region 3.

[0021] In the present application, the first doping type gate 4 and the second doping type source contact region 3 are completely not in contact, and neither forms a PN junction nor has a corresponding capacitance. Therefore, the input capacitance of the gate-controlled junction field effect transistor of the present application is very small.

[0022] The gate-controlled junction field effect transistor of the present application also retains the advantages of reliability and electrical properties of the traditional gate-controlled junction field effect transistor.

[0023] Specifically, Figure 2 and Figure 3 As shown, the well region 1, the second doping type source contact region 3, the gate 4, and the channel region 5 form a JFET structure, which is controlled by a single gate (i.e., controlled by the gate 4), and the opening and closing of the channel is controlled by changes in the PN junction depletion region formed by the first doping type gate 4 and the second doping type channel region 5.

[0024] Specifically, as an optional manner, the first doping type is P type, and the second doping type is N type. In the drawings of the present application, the drawings are all made with the first doping type being P type, and the second doping type being N type.

[0025] Specifically, as another optional manner, the first doping type is N-type, and the second doping type is P-type.

[0026] In implementation, such as Figure 2 and Figure 3 As shown, the preset spacing between the gate 4 and the second doping type source contact region 3 in the lateral direction has a value range of greater than 0 μm and less than or equal to 0.3 μm.

[0027] The preset distance is maintained between the first doping type gate 4 and the second doping type source contact region 3, ensuring that the first doping type gate 4 and the second doping type source contact region 3 are completely not in contact with each other and thus no PN junction is formed.

[0028] The preset distance between the gate 4 and the second doping type source contact region 3 in the lateral direction should not be too large. If the preset distance between the gate 4 and the second doping type source contact region 3 in the lateral direction is too large, the on-resistance will increase.

[0029] In implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field effect transistor of the present application also includes: A gate electrode 7 is formed on the gate 4 in the vertical direction, and the outer edge of the gate electrode 7 is located inside the outer edge of the gate 4 in the lateral direction, that is, the gate electrode 7 is smaller than the gate 4; A source electrode 6 is formed on the second doping type source contact region 3, and the distance between the source electrode 6 and the gate 4 is greater than the distance between the second doping type source contact region 3 and the gate 4; The dielectric layer 9 is filled between the source electrode 6 , the gate electrode 7 and the gate 4 .

[0030] The dielectric layer 9 is filled between the source electrode 6, the gate electrode 7, and the gate 4, and the dielectric layer 9 is located on the second doping type source contact region 3 and the portion of the channel region 5 exposed from between the source electrode 6 and the gate 4. In this way, the dielectric layer 9 completely separates the second doping type source contact region 3 and the gate 4, and they are completely non-contacting.

[0031] In implementation, such as Figure 2 and Figure 3 As shown, the doping concentration of the gate 4 is in the range of greater than or equal to 1×10 18 cm -3 ; The doping concentration of the second doping type source contact region 3 is in the range of greater than or equal to 1×10 18 cm -3 .

[0032] The gate electrode 7 and the source electrode 6 are usually made of metal. The doping concentration of the gate 4 is relatively high, which can reduce the connection resistance between the gate electrodes 7 and the gate electrodes 7. The doping concentration of the second doping type source contact region 3 is relatively high, which can reduce the connection resistance between the second doping type source contact region 3 and the source electrode 6.

[0033] The doping concentration of the gate 4 is high, so the depletion between the gate 4 and the channel region 5 is relatively wide, so that the breakdown voltage BV is relatively high and the gate-source voltage Vgs is relatively low.

[0034] In implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field effect transistor also includes: A first doping type source contact region 2 is formed downward from the top surface of the epitaxial layer, and the first doping type source contact region 2 is connected to a side of the second doping type source contact region 3 away from the channel region 5; A drain electrode 14 is formed on the back side of the substrate 13 .

[0035] In implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field effect transistor of the present application also includes: A buffer layer 12 of a second doping type, formed between the substrate 13 and the epitaxial layer 11; A current guiding layer 10 of a second doping type is formed under the channel region 5 and the well region 1 .

[0036] Specifically, the doping concentration of the current guiding layer 10 is greater than the doping concentration of the epitaxial layer 11 .

[0037] In implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field effect transistor has a symmetrical structure, and the well region 1, the first doping type source contact region 2, the second doping type source contact region 3, the source electrode 6, and the dielectric layer 9 are each two.

[0038] In implementation, such as Figure 2 and Figure 3 As shown, the doping concentration of the well region 1 ranges from 1×10 17 cm -3 Less than or equal to 1×10 18 cm -3 ; The doping concentration of the first doping type source contact region 2 is in the range of greater than or equal to 1×10 18 cm -3 .

[0039] Figure 4 for Figure 1 Schematic diagram of the depletion line of a gate-controlled junction field effect transistor when Vgs=0V.

[0040] like Figure 4 As shown, the white curve is the depletion line. Figure 1 When the gate-controlled junction field effect transistor is turned on with Vgs=0V, there is a white depletion line at the PN junction of the gate 4 and the source contact area 3 (that is, the position where the gate 4 and the source contact area 3 contact each other), resulting in loss.

[0041] Figure 5 for Figure 2 Schematic diagram of the depletion line of a gate-controlled junction field effect transistor when Vgs=0V.

[0042] like Figure 5 As shown, the white curve is the depletion line. Figure 2 When the gate-controlled junction field effect transistor is turned on with Vgs=0V, the first doping type gate 4 and the second doping type source contact area 3 are completely not in contact with each other, and no PN junction is formed between them. Therefore, at the position where the first doping type gate 4 and the second doping type source contact area 3 are close to each other, the gate 4 and the second doping type source contact area 3 are not in contact, so there is no white depletion line.

[0043] contrast Figure 4In the figure, there is a white depletion line at the PN junction of the gate 4 and the source contact region 3 (ie, the position where the gate 4 and the source contact region 3 contact each other).

[0044] Background Art Figure 1 Gate-controlled junction field effect transistor and application thereof Figure 2 The performance comparison of gate-controlled junction field effect transistors is shown in the following table:

[0045] Among them, pgate in the table corresponds to the gate 4, Np corresponds to the second doping type source contact region 3, Pbottom corresponds to the well region 1, and corresponds to the oxide dielectric layer 9.

[0046] From the above table, we can see that: This application Figure 2 Background technology of gate-source capacitance Cgs ratio of gate-controlled junction field effect transistor Figure 1 The gate-source capacitance Cgs of the gate-controlled junction field effect transistor is much smaller; the reason is that in the present application, the gate 4 and the second doping type source contact region 3 are not in contact, and there is no corresponding capacitance.

[0047] This application Figure 2 Background technology of gate-source current Igs ratio of gate-controlled junction field effect transistor Figure 1 The gate-source current Igs of the gate-controlled junction field effect transistor is small.

[0048] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0049] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0050] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0051] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0052] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0053] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A gate-controlled junction field effect transistor, characterized in that: include: A substrate (13), and an epitaxial layer formed on the substrate (13); A channel region (5) of a second doping type, formed downward from the top surface of the epitaxial layer; A second doping type source contact region (3), formed downward from the top surface of the epitaxial layer and connected to the outer edge of the channel region (5); A gate electrode (4) of a first doping type is formed on the channel region (5) in a vertical direction, and an outer edge of the gate electrode (4) is located within an outer edge of the channel region (5) in a lateral direction, so that a preset spacing is maintained between the gate electrode (4) and the second doping type source contact region (3) in a lateral direction; The well region (1) is located below the second doping type source contact region (3).

2. The gate-controlled junction field effect transistor according to claim 1, characterized in that: The preset spacing between the gate (4) and the second doping type source contact region (3) in the lateral direction has a value range of greater than or equal to 0.1 μm and less than or equal to 0.3 μm.

3. The gate-controlled junction field effect transistor according to claim 1 or 2, characterized in that: Also includes: A gate electrode (7) is formed on the gate (4) in the vertical direction, and an outer edge of the gate electrode (7) is located inside an outer edge of the gate (4) in the lateral direction; A source electrode (6) is formed on the second doping type source contact region (3), and the distance between the source electrode (6) and the gate (4) is greater than the distance between the second doping type source contact region (3) and the gate (4); A dielectric layer (9) is filled between the source electrode (6), the gate electrode (7), and the gate (4).

4. The gate-controlled junction field effect transistor according to claim 1 or 2, characterized in that: The doping concentration of the gate (4) is in the range of greater than or equal to 1×10 18 cm -3 ; The doping concentration of the second doping type source contact region (3) is in the range of greater than or equal to 1×10 18 cm -3 .

5. The gate-controlled junction field effect transistor according to claim 3, characterized in that: Also includes: A first doping type source contact region (2) is formed downward from the top surface of the epitaxial layer, and the first doping type source contact region (2) is connected to a side of the second doping type source contact region (3) away from the channel region (5); A drain electrode (14) is formed on the back side of the substrate (13).

6. The gate-controlled junction field effect transistor according to claim 5, characterized in that: Also includes: A buffer layer (12) of a second doping type, formed between the substrate (13) and the epitaxial layer (11); A current guiding layer (10) of a second doping type is formed below the channel region (5) and the well region (1).

7. The gate-controlled junction field effect transistor according to claim 6, characterized in that: The gate-controlled junction field effect transistor has a symmetrical structure, wherein the well region (1), the first doping type source contact region (2), the second doping type source contact region (3), the source electrode (6), and the dielectric layer (9) are each two.

8. The gate-controlled junction field effect transistor according to claim 1, characterized in that: The doping concentration of the well region (1) is in the range of greater than or equal to 1×10 17 cm -3 Less than or equal to 1×10 18 cm -3 .

9. The gate-controlled junction field effect transistor according to claim 5, characterized in that: The doping concentration of the first doping type source contact region (2) is in the range of greater than or equal to 1×10 18 cm -3 .

10. The gate-controlled junction field effect transistor according to claim 1, characterized in that: The first doping type is P type, and the second doping type is N type.

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