Trench gate field effect transistor, power chip and manufacturing method thereof

Abstract

The embodiment of the invention provides a trench gate field effect transistor. The trench gate field effect transistor comprises an N + substrate, an N-type epitaxial layer, a first dielectric layer, a control gate, a p-type base region, a drain electrode and a source electrode, wherein the N-type epitaxial layer and the p-type base body region are sequentially arranged above the N + substrate, the drain electrode is arranged below the N + substrate, the first dielectric layer is located in the N-type epitaxial layer and the p-type base body region, a control gate is arranged in the first dielectric layer, and the p-type base body region is connected with the source electrode; the trench gate field effect transistor further comprises a buried oxide layer, and the buried oxide layer is located below the first dielectric layer and is in contact connection with the lower side of the first dielectric layer. The embodiment of the invention also provides a power chip and a manufacturing method thereof.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench gate field effect transistor, a power chip and a manufacturing method thereof. Background Art

[0002] Compared with planar field effect transistors, trench gate field effect transistors (Trench MOS) have the advantages of high device density and high drive current. A typical structure of trench gate field effect transistors is shielded-gate field effect transistors (Shielded-Gate Trench MOS). Shielded-gate field effect transistors are one of the most advanced power field effect transistor device technologies, with lower on-resistance, faster switching speed, etc. In system applications, they have lower conduction losses and lower switching losses, and the system has higher conversion and transmission efficiency.

[0003] In the related art, the bottom of the trench gate overlaps with the drain in a large area, resulting in a large parasitic output capacitance from the drain. The shielded gate field effect transistor has a shielding gate at the bottom of the trench, which reduces the drain-gate capacitance at the expense of increasing the drain-source capacitance. Its output capacitance does not decrease, limiting the further improvement of the performance of the trench gate transistor.

[0004] In addition, trench gate field effect transistors are usually discrete devices and require additional control chips in practical applications. Summary of the invention

[0005] The technical problem to be solved by the embodiments of the present application is to provide a trench gate field effect transistor, a power chip and a manufacturing method thereof to improve the electrical performance of the trench gate field effect transistor in view of the deficiencies of the prior art.

[0006] In order to solve the above technical problems, the first aspect of the embodiment of the present application provides a trench gate field effect transistor, including: an N+ substrate, an N-type epitaxial layer, a first dielectric layer, a control gate, a p-type body region, a drain, and a source;

[0007] The N-type epitaxial layer and the p-type matrix region are sequentially arranged above the N+ substrate, the drain is arranged below the N+ substrate, the first dielectric layer is located in the N-type epitaxial layer and the p-type matrix region, a control gate is arranged in the first dielectric layer, and the p-type matrix region is connected to the source;

[0008] Wherein, the trench gate field effect transistor further includes a buried oxide layer, and the buried oxide layer is located below the first dielectric layer and is in contact with and connected to the lower side of the first dielectric layer.

[0009] Optionally, the buried oxide layer is located in the N+ substrate and located on an upper portion of the N+ substrate.

[0010] Optionally, the first dielectric layer passes through the N-type epitaxial layer and continues downward through a portion of the N+ substrate to contact the buried oxide layer.

[0011] Optionally, the buried oxide layer is located in the N-type epitaxial layer.

[0012] Optionally, the N-type epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the thickness of the first epitaxial layer is less than the thickness of the second epitaxial layer, the first epitaxial layer is located on the N+ substrate, the second epitaxial layer is located on the first epitaxial layer, and the buried oxide layer is located in the first epitaxial layer.

[0013] Optionally, the projection of the first dielectric layer on the horizontal plane is located within the region of the projection of the buried oxide layer on the horizontal plane, and the area of ​​the projection of the buried oxide layer on the horizontal plane is larger than the area of ​​the projection of the first dielectric layer on the horizontal plane.

[0014] Optionally, the trench gate field effect transistor further includes a shielding gate, wherein the shielding gate is located in the first dielectric layer and below the control gate, and the shielding gate is connected to the source.

[0015] A second aspect of an embodiment of the present application provides a power chip, comprising the above-mentioned trench gate field effect transistor.

[0016] Optionally, it also includes a second dielectric layer, which extends downward from the upper surface of the N-type epitaxial layer and contacts the buried oxide layer. The buried oxide layer and the second dielectric layer form an electrical isolation region. A control circuit is formed in the electrical isolation region. The control circuit is connected to the control gate of the trench gate field effect transistor to control the trench gate field effect transistor to turn on or off. The electrical isolation region is used to isolate the trench gate field effect transistor from interfering with the control circuit.

[0017] Optionally, a shielding gate is provided in the first dielectric layer of the trench gate field effect transistor, the shielding gate is located below the control gate, a connecting portion is provided in the second dielectric layer, the connecting portion is connected to the shielding gate, and the connecting portion is used to connect the shielding gate to the source; or,

[0018] The buried oxide layer in contact with the second dielectric layer extends to the edge of the power chip in a direction away from the trench gate field effect transistor.

[0019] A third aspect of an embodiment of the present application provides a method for manufacturing a power chip, comprising:

[0020] Providing an N+ substrate;

[0021] forming a plurality of buried oxide layers in the N+ substrate;

[0022] An N-type epitaxial layer is formed on an N+ substrate, and a first deep trench is dug in the N-type epitaxial layer, wherein the first deep trench extends downward to a corresponding buried oxide layer;

[0023] forming a first dielectric layer and a control gate in the first deep trench, wherein the first dielectric layer surrounds the control gate and the first dielectric layer contacts the buried oxide layer;

[0024] A p-type base region, a source region and a drain are formed, wherein the p-type base and the source region are connected to the source respectively, and the drain is located at the bottom of the N+ substrate.

[0025] Optionally, also include:

[0026] Digging a second deep trench in the N-type epitaxial layer, the second deep trench extending downward to the corresponding buried oxide layer, wherein the second deep trench is different from the first deep trench;

[0027] forming a second dielectric layer in the second deep trench, wherein the second dielectric layer contacts the corresponding buried oxide layer, and the second dielectric layer and the corresponding buried oxide layer form an electrical isolation region;

[0028] A control circuit is formed in the electrically isolated region.

[0029] A fourth aspect of an embodiment of the present application provides a method for manufacturing a power chip, comprising:

[0030] Providing an N+ substrate, and forming a first epitaxial layer on the N+ substrate;

[0031] forming a plurality of buried oxide layers in the first epitaxial layer;

[0032] forming a second epitaxial layer on the first epitaxial layer, digging a first deep trench in the second epitaxial layer and the first epitaxial layer, wherein the first deep trench extends downward to the corresponding buried oxide layer;

[0033] forming a first dielectric layer and a control gate in the first deep trench, wherein the first dielectric layer surrounds the control gate and the first dielectric layer contacts the buried oxide layer;

[0034] A p-type base region, a source region and a drain are formed, wherein the p-type base and the source region are connected to the source respectively, and the drain is located at the bottom of the N+ substrate.

[0035] Optionally, also include:

[0036] Digging a second deep trench in the second epitaxial layer and the first epitaxial layer, the second deep trench extending downward to the corresponding buried oxide layer, wherein the second deep trench is different from the first deep trench;

[0037] forming a second dielectric layer in the second deep trench, wherein the second dielectric layer contacts the corresponding buried oxide layer, and the second dielectric layer and the corresponding buried oxide layer form an electrical isolation region;

[0038] A control circuit is formed in the electrically isolated region.

[0039] The trench gate field effect transistor of the embodiment of the present application is provided with a buried oxide layer, which is in contact with the first dielectric layer, and a control gate is provided in the first dielectric layer. Since the buried oxide layer in contact with the first dielectric layer is provided, the thickness of the insulating layer is increased, and the distance between the two plates of the capacitor is increased, so that the output capacitance is reduced from the drain side, and the parasitic capacitance is reduced, which is beneficial to the improvement of the electrical performance of the trench gate field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1a is an application circuit diagram of the power chip of the first embodiment of the present application;

[0042] Figure 1b is an application circuit diagram of a power chip according to another embodiment of the present application;

[0043] Figure 2a This is a schematic diagram of the structure of the power chip of the first embodiment of the present application;

[0044] Figure 2b is a schematic diagram of the structure of a power chip according to another embodiment of the present application;

[0045] Figure 3 This is a simulation comparison diagram of the output capacitance of the power chip of the first embodiment of the present application viewed from the drain electrode and the related art;

[0046] Figure 4a is a manufacturing flow chart of the power chip of the first embodiment of the present application;

[0047] Figure 4b yes Figure 4a Detailed flowchart of step S140;

[0048] Figure 5a-Figure 5i is a schematic diagram of a method for manufacturing a power chip structure according to a first embodiment of the present application;

[0049] Figure 5j yes Figure 5i The cross-sectional top view along the AA line;

[0050] Figure 6 is a schematic diagram of the structure of a power chip according to a second embodiment of the present application;

[0051] Figure 7a This is a simulation diagram of the electric field outside the first dielectric layer of a power chip in the related art;

[0052] Figure 7b This is a simulation diagram of the electric field outside the first dielectric layer of the power chip in the second embodiment of the present application;

[0053] Figure 8 is a manufacturing flow chart of a power chip according to the second embodiment of the present application;

[0054] Figure 9a-9i It is a schematic diagram of a method for manufacturing a power chip structure according to a second embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] The terms "including" and "having" and any variations thereof that appear in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In addition, the terms "first", "second" and "third" are used to distinguish different objects, not to describe a specific order. The connections of this application include direct connections and indirect connections. Indirect connection means that other electronic components, pins, etc. may exist between the two connected components.

[0057] First embodiment

[0058] The present application embodiment provides a power chip, which is made on the same semiconductor substrate. Figure 1a The power chip includes a trench gate field effect transistor M1 and a control circuit 180. In this embodiment, the trench gate field effect transistor is described by taking the shielded gate field effect transistor M1 as an example. The control circuit 180 is connected to the shielded gate field effect transistor M1 to control the shielded gate field effect transistor M1 to turn on or off. In this embodiment, the trench gate field effect transistor M1 is a VDMOS (Vertical Double Diffused MOSFET). Figure 1aIn the embodiment, the power chip is connected as a high-side switch, which is a switch connected between the positive electrode of the power source 310 and the load 320. However, the present application is not limited thereto. In other embodiments of the present application, see Figure 1b , the power chip is connected as a low-side switch, which is a switch connected between the load 320 and the negative electrode of the power source 310.

[0059] See also Figure 2a The shielded gate field effect transistor includes an N+ substrate 110, an N-type epitaxial layer 130, a shielding gate 144, a control gate 147, a p-type base region 150, a source region 162, a p-type contact region 161, a first dielectric layer, a drain 170, and a source (not shown in the figure). The drain 170 is located below the N+ substrate 110, the N-type epitaxial layer 130 is located above the N+ substrate 110, the first dielectric layer extends from the N-type epitaxial layer 130 to the N+ substrate 110, a shielding gate 144 and a control gate 147 are arranged in the first dielectric layer, the control gate 147 is located above the shielding gate 144, the p-type base region 150 is located above the epitaxial layer, and a p-type contact region 161 and a source region 162 are formed on the p-type base region 150, wherein the shielding gate 144 is electrically connected to the source, and the source region 162 and the p-type contact region 161 are electrically connected to the source.

[0060] In this embodiment, a buried oxide layer 120 is also formed in the N+ substrate 110. The buried oxide layer 120 is an insulating layer. The buried oxide layer 120 is, for example, SiO2. The buried oxide layer 120 is located below the shielding gate 144. The buried oxide layer 120 contacts the first dielectric layer. Here, the first dielectric layer contacts the upper surface of the buried oxide layer 120 or the first dielectric layer extends into part of the buried oxide layer 120. The projection of the first dielectric layer on the horizontal plane is located in the area of ​​the projection of the buried oxide layer 120 on the horizontal plane. The area of ​​the projection of the buried oxide layer 120 on the horizontal plane is greater than the area of ​​the projection of the first dielectric layer on the horizontal plane. In this embodiment, by adding the buried oxide layer 120, the buried oxide layer 120 contacts the first dielectric layer, thereby increasing the thickness of the insulating layer and increasing the distance between the two plates of the capacitor. According to the capacitance formula C=εS / (4πkd), the output capacitance (mainly the drain-source capacitance in this embodiment) is reduced from the drain 170 side, which is beneficial to the improvement of the electrical performance of the shielded gate field effect transistor.

[0061] The inventor of the present application also simulated the output capacitance without and with the buried oxide layer 120, see Figure 3 ,from Figure 3 It can be clearly seen that, from the perspective of the drain 170 , the output capacitance (solid line) with the buried oxide layer 120 is reduced relative to the output capacitance (dashed line) without the buried oxide layer 120 .

[0062] Please continue to see Figure 2aIn this embodiment, the power chip further includes a second dielectric layer, the second dielectric layer contacts the buried oxide layer 120 below, the second dielectric layer and the buried oxide layer 120 form an electrical isolation region, the region within the electrical isolation region is electrically isolated from the region outside the electrical isolation region, in the figure, the region within the electrical isolation region is the region above the buried oxide layer 120 and the region to the right of the second dielectric layer, the region outside the electrical isolation region is the region below the buried oxide layer 120 or the region to the left of the second dielectric layer, the region outside the electrical isolation region forms a shielded gate field effect transistor, and at the same time, a control circuit 180 is formed within the electrical isolation region, the control circuit 180 is connected to the control gate 147 of the shielded gate field effect transistor, and is used to control the shielded gate field effect transistor to control its on or off. In this embodiment, the first dielectric layer and the second dielectric layer are both insulating layers, and the first dielectric layer and the second dielectric layer are, for example, SiO2 (silicon dioxide). In this embodiment, the shielded gate field effect transistor is used as a power switch, which can carry a large current, withstand a large voltage, and has a large power. The control circuit 180 is a signal detection and processing module, which carries a small current and has a low power. The control circuit 180 includes NMOS, PMOS, triodes, etc. The control circuit 180 includes, for example, a gate driver, a level shifter, etc. The specific circuit of the control circuit 180 is a conventional technology in the field and is not described here. In this embodiment, the control circuit 180 and the shielded gate field effect transistor are physically isolated in three dimensions by the buried oxide layer 120 and the second dielectric layer, rather than by PN junction isolation, so the reliability is high, and the large signal of the shielded gate field effect transistor has little interference with the control circuit 180, and isolation in this way does not increase the process steps and does not increase the cost.

[0063] In this embodiment, a connecting portion 145 is further formed in the second dielectric layer. The connecting portion 145 is, for example, polysilicon, and the shield gate 144 is connected to the source via the connecting portion 145. By adding the connecting portion 145 in the second dielectric layer, the complexity of the connection of the shield gate 144 is reduced. In addition, in other embodiments of the present application, see Figure 2b , trench gate field effect transistors are not limited to Figure 2a The shielded gate field effect transistor in the embodiment can also be other trench gate field effect transistors. In this case, the shielding gate may not be included. In this case, the first deep trench 141 only has a control gate, and the corresponding connecting portion 145 may not be formed in the second dielectric layer. In this case, from the perspective of the drain 170, the parasitic output capacitance between it and the trench gate is the drain-gate capacitance, and the parasitic drain-gate capacitance is reduced.

[0064] The present application also provides a method for manufacturing a power chip. Figure 2a-Figure 5i ,include:

[0065] S110: providing an N+ substrate 110;

[0066] S120: forming a plurality of buried oxide layers 120 in the N+ substrate 110;

[0067] See also Figure 5b , oxygen ions are implanted on the upper part of the N+ substrate 110, and then heated at a high temperature, the oxygen ions react with the N+ substrate 110 to form a plurality of buried oxide layers 120 in the N+ substrate 110, the buried oxide layers 120 are electrically insulating layers, and the buried oxide layers 120 are spaced apart from each other. In this embodiment, the buried oxide layers 120 are formed on the upper part of the N+ substrate 110.

[0068] S130: forming an N-type epitaxial layer 130 on the N+ substrate 110, and digging a first deep trench 141 and a second deep trench 142 in the N-type epitaxial layer 130, wherein the first deep trench 141 and the second deep trench 142 both extend downward to the corresponding buried oxide layer 120;

[0069] See also Figure 5c In this embodiment, the electron concentration in the N-type epitaxial layer 130 is less than the electron concentration in the N+ substrate 110. The first deep trench 141 and the second deep trench 142 extend downward from the upper surface of the N-type epitaxial layer 130 and penetrate the N-type epitaxial layer 130. The first deep trench 141 and the second deep trench 142 also enter the N-type substrate. The first deep trench 141 and the second deep trench 142 contact the upper surface of the buried oxide layer 120 or enter a portion of the buried oxide layer 120. In this embodiment, the number of first deep trenches 141 is multiple, the number of second deep trenches 142 is one or more (one in the figure, and can be set to multiple according to isolation requirements), and there is one buried oxide layer 120 connected to the second deep trench 142. The buried oxide layer 120 extends to the edge of the N+ substrate 110. The buried oxide layer 120 is referred to as the second buried oxide layer 120 here, and the other buried oxide layers 120 are referred to as the first buried oxide layer 120. The second buried oxide layer 120 electrically isolates the area above it from the area below it, that is, the second buried oxide layer 120 performs vertical electrical isolation, and the second deep trench 142 electrically isolates the left area from the right area in the figure, that is, the second deep trench 142 performs horizontal electrical isolation, so that the second deep trench 142 and the second buried oxide layer 120 are combined to form an electrically isolated area.

[0070] S140 : forming a first dielectric layer, a shield gate 144 and a control gate 147 in the first deep trench 141 , and forming a second dielectric layer and a connecting portion 145 in the second deep trench 142 .

[0071] See also Figure 5d-Figure 5hIn this embodiment, the first dielectric layer includes a field oxide layer 143, a spacer oxide layer 146, a gate oxide layer 148 and a gate protection layer 149, and the second dielectric layer includes a field oxide layer 143 and a spacer oxide layer 146. In addition, in other embodiments of the present application, the shield gate 144 may not be formed in the first deep trench 141, and the connecting portion 145 may not be formed in the second deep trench 142. In this case, the first deep trench 141 and the second deep trench 142 are only filled with the field oxide layer 143 and the gate protection layer 149.

[0072] In this embodiment, step S140 specifically includes:

[0073] S141: forming a field oxide layer 143 in the first deep trench 141 and the second deep trench 142;

[0074] See also Figure 5d , forming a field oxide layer 143 on the surface of the first deep trench 141 and the second deep trench 142 by oxidation and / or deposition in the first deep trench 141 and the second deep trench 142 , the field oxide layer 143 is, for example, SiO 2 ;

[0075] S142: forming a shielding grid 144 in the first deep trench 141 and forming a connecting portion 145 in the second deep trench 142;

[0076] See also Figure 5e A conductive material such as polysilicon is deposited in the first deep trench 141 and the second deep trench 142, and then etched to form a shielding gate 144 and a connecting portion 145, wherein the connecting portion 145 has a height in the longitudinal direction greater than the height of the shielding gate 144 in the longitudinal direction.

[0077] S143: forming a spacer oxide layer 146 and a gate oxide layer 148 in the first deep trench 141 and the second deep trench 142;

[0078] See also Figure 5f , firstly etch away the field oxide layer 143 above the shield gate 144, and then form a spacer oxide layer 146 and a gate oxide layer 148 in the first deep trench 141 and the second deep trench 142. The spacer oxide layer 146 and the gate oxide layer 148 are insulating layers, and the spacer oxide layer 146 and the gate oxide layer 148 are, for example, SiO2. In addition, in other embodiments of the present application, the spacer oxide layer 146 may be formed first, and then etched, and then the gate oxide layer 148 may be formed.

[0079] S144: forming a control gate 147 on the spacer oxide layer 146 of the first deep trench 141;

[0080] See also Figure 5g , a conductive material is deposited in the first deep trench 141 , the conductive material being, for example, polysilicon, metal, etc., and then etched to form a control gate 147 .

[0081] S145 : forming a gate protection layer 149 on the control gate 147 .

[0082] See also Figure 5h , the gate protection layer 149 is, for example, SiO2 or other insulating materials. In this embodiment, the first dielectric layer is in contact with the upper surface of the first buried oxide layer 120, or the first dielectric layer is inserted into a portion of the first buried oxide layer 120. Since the first buried oxide layer 120 is added, the electrical distance between the shielding gate 144 and the N+ substrate 110 is increased. Moreover, based on the fact that the second dielectric layer and the second buried oxide layer 120 are formed without adding process steps, the second dielectric layer is in contact with the upper surface of the second buried oxide layer 120, or the second dielectric layer is inserted into a portion of the second buried oxide layer 120. The second dielectric layer and the second buried oxide layer 120 form a spatial electrical isolation region. Since the second dielectric layer and the buried oxide layer 120 are both insulating layers, the components in the electrical isolation region are less disturbed by the components outside the electrical isolation region.

[0083] S150 : forming a p-type body region 150 , a source region 162 , a p-type contact region 161 , a control circuit 180 and a drain 170 .

[0084] See also Figure 5i , a p-type base region 150, a source region 162, and a p-type contact region 161 are formed outside the electrical isolation region, wherein the p-type base region 150 is connected to the source based on the p-type contact region 161, and the source region 162 is also connected to the source, and a drain 170 is formed under the N+ substrate 110, thereby forming a shielded gate field effect transistor, and the shielded gate field effect transistor is a VDMOS. Moreover, a control circuit 180 is formed in the electrical isolation region, and the control circuit 180 includes an NMOS, a PMOS, a triode, etc. The control circuit 180 is connected to the control gate of the shielded gate field effect transistor to control the shielded gate field effect transistor to turn on or turn off. In this embodiment, how the control circuit 180 is formed is a conventional technology in the art, and will not be repeated here.

[0085] Also, see Figure 5j , Figure 5j yes Figure 5i The cross-sectional view along line AA clearly shows how the shielding grid 144 is electrically connected to the connecting portion 145 .

[0086] Second embodiment

[0087] See also Figure 6 , Figure 6It is a partial cross-sectional film layer diagram of the power chip of the second embodiment of the present application. This embodiment is similar to the first embodiment, so the parts not described in this embodiment can refer to the first embodiment. The main difference between this embodiment and the first embodiment is that the buried oxide layer 120 is located in the N-type epitaxial layer 130.

[0088] See also Figure 6 In this embodiment, the power chip includes a shielded gate field effect transistor and a control circuit 180. The shielded gate field effect transistor includes an N+ substrate 110, an N-type epitaxial layer, a shielding gate 144, a control gate 147, a p-type body region 150, a source region 162, a p-type contact region 161, a first dielectric layer, a drain 170, and a source (not shown in the figure). In this embodiment, the N-type epitaxial layer includes a first epitaxial layer 181 and a second epitaxial layer 182. The thickness of the first epitaxial layer 181 is smaller than that of the second epitaxial layer 182. The first epitaxial layer 181 is located on the N+ substrate 110, and the second epitaxial layer 182 is located on the first epitaxial layer 181. The second epitaxial layer 182 and the first epitaxial layer 181 are made of the same material.

[0089] In this embodiment, a buried oxide layer 120 is also formed in the first epitaxial layer 181. The buried oxide layer 120 is an insulating layer. The buried oxide layer 120 is, for example, SiO2. The buried oxide layer 120 is located below the shielding gate 144. The buried oxide layer 120 contacts the first dielectric layer. Moreover, the projection of the first dielectric layer on the horizontal plane is located within the region of the projection of the buried oxide layer 120 on the horizontal plane. The area of ​​the projection of the buried oxide layer 120 on the horizontal plane is greater than the area of ​​the projection of the first dielectric layer on the horizontal plane. In this embodiment, by adding the buried oxide layer 120, the buried oxide layer 120 contacts the first dielectric layer, thereby increasing the thickness of the insulating layer and increasing the distance between the two plates of the capacitor. According to the capacitance formula C=εS / (4πkd), the parasitic capacitance (mainly the source-drain capacitance) of the output from the drain 170 is reduced, which is beneficial to the improvement of the electrical performance of the shielded gate field effect transistor. Moreover, since a buried oxide layer 120 is added below the first dielectric layer, the buried oxide layer 120 is located in the N-type epitaxial layer 130 instead of in the N+ substrate 110, and the first dielectric layer is in contact with the buried oxide layer 120, thereby changing the electric field distribution between the shielding gate 144 and the N+ substrate 110, weakening the peak electric field on the first dielectric layer, weakening the stress on the first dielectric layer, slowing down the degradation of the performance of the first dielectric layer, and improving the robustness and life of the shielded gate field effect transistor.

[0090] The inventors of the present application also simulated the electric field distribution when the buried oxide layer 120 is not added to the first epitaxial layer 181 and when the buried oxide layer 120 is added to the first epitaxial layer 181. When the shielded gate field effect transistor is turned off, the same blocking voltage is applied to its drain and source. Figure 7a 1 is an electric field distribution diagram without adding the buried oxide layer 120 in the first epitaxial layer 181. Figure 7b The electric field distribution diagram of the embodiment in which the buried oxide layer 120 is added to the first epitaxial layer 181 (the redder the color, the stronger the electric field, and the bluer the color, the weaker the electric field) is shown. It can be clearly seen from the diagram that the external electric field on the lower side of the first dielectric layer in the embodiment is relatively uniform, and the peak intensity of the electric field is weakened, and the stress on the first dielectric layer is reduced, which is beneficial to improving the life and reliability.

[0091] Since the N epitaxial layer is relatively thick and the depth of oxygen ion implantation into the N-type epitaxial layer is limited, the buried oxide layer 120 cannot be directly disposed below the first dielectric layer. To solve this problem, in the present embodiment, a first epitaxial layer 181 is first formed on the N+ substrate 110, and then oxygen ions are implanted and reacted at high temperature to form a buried oxide layer 120 in the first epitaxial layer 181, and then a second epitaxial layer 182 is formed on the first epitaxial layer 181. By such treatment, the buried oxide layer 120 can be formed at the lower portion of the N-type epitaxial layer 130, and then the buried oxide layer 120 can be brought into contact with the first dielectric layer.

[0092] In this embodiment, the formation of the second dielectric layer and the connecting portion 145 is the same as that of the first embodiment, and will not be described in detail herein.

[0093] The present application also provides a method for manufacturing a power chip. Figure 6-Figure 9i ,include:

[0094] S210: providing an N+ substrate 110, and forming a first epitaxial layer 181 on the N+ substrate 110;

[0095] S220: forming a plurality of buried oxide layers 120 in the first epitaxial layer 181;

[0096] See also Figure 9b , oxygen ions are implanted into the first epitaxial layer 181 and then heated at a high temperature. The oxygen ions react with the first epitaxial layer 181 to form a plurality of buried oxide layers 120 in the first epitaxial layer 181 . The buried oxide layers 120 are electrically insulating layers, and the buried oxide layers 120 are spaced apart from each other.

[0097] S230: forming a second epitaxial layer 182 on the first epitaxial layer 181, and digging a first deep trench 141 and a second deep trench 142 in the second epitaxial layer 182 and the first epitaxial layer 181, wherein the first deep trench 141 and the second deep trench 142 both extend downward to the corresponding buried oxide layer 120;

[0098] See also Fig.9cThe thickness of the first epitaxial layer 181 is less than that of the second epitaxial layer 182, and the concentration of electrons in the first epitaxial layer 181 and the second epitaxial layer 182 is less than the concentration of electrons in the N+ substrate 110. The first deep trench 141 and the second deep trench 142 extend downward from the upper surface of the second epitaxial layer 182 and penetrate the second epitaxial layer 182, and the first deep trench 141 and the second deep trench 142 also enter the first epitaxial layer 181, and the first deep trench 141 and the second deep trench 142 are in contact with the surface of the buried oxide layer 120 or enter part of the buried oxide layer 120. In this embodiment, the number of first deep trenches 141 is multiple, the number of second deep trenches 142 is one or more (one in the figure, and can be set to multiple according to isolation requirements), and there is one buried oxide layer 120 connected to the second deep trench 142. The buried oxide layer 120 extends to the edge of the first epitaxial layer 181. The buried oxide layer 120 is referred to as the second buried oxide layer 120 here, and the other buried oxide layers 120 are referred to as the first buried oxide layer 120. The second buried oxide layer 120 electrically isolates the area above it from the area below it, that is, the second buried oxide layer 120 performs vertical electrical isolation, and the second deep trench 142 electrically isolates the left area from the right area in the figure, that is, the second deep trench 142 performs horizontal electrical isolation, so that the second deep trench 142 and the second buried oxide layer 120 are combined to form a three-dimensional electrical isolation area.

[0099] S240 : forming a first dielectric layer, a shield gate 144 and a control gate 147 in the first deep trench 141 , and forming a second dielectric layer and a connecting portion 145 in the second deep trench 142 .

[0100] See also Figure 9d-9h In this embodiment, the first dielectric layer includes a field oxide layer 143, a spacer oxide layer 146, a gate oxide layer 148 and a gate protection layer 149, and the second dielectric layer includes a field oxide layer 143 and a spacer oxide layer 146. In addition, in other embodiments of the present application, the connecting portion 145 may not be formed in the second deep trench 142, and in this case, only the field oxide layer 143 and the spacer oxide layer 146 are filled in the second deep trench 142. For the specific steps of step S240, please refer to the description of step S140 in the first embodiment, which will not be repeated here.

[0101] S250: forming a p-type body region 150, a source region 162, a p-type contact region 161, a control circuit 180 and a drain 170;

[0102] See also Figure 9i, a p-type base region 150, a source region 162, and a p-type contact region 161 are formed outside the electrical isolation region, wherein the p-type base region 150 is connected to the source based on the p-type contact region 161, and the source region 162 is also connected to the source, and a drain 170 is formed under the N+ substrate 110, thereby forming a shielded gate field effect transistor, and the shielded gate field effect transistor is a VDMOS. Moreover, a control circuit 180 is formed in the electrical isolation region, and the control circuit 180 includes an NMOS, a PMOS, a triode, etc. The control circuit 180 is connected to the control gate 147 of the shielded gate field effect transistor to control the shielded gate field effect transistor to turn on or turn off. In this embodiment, how the control circuit 180 is formed is a conventional technology in the art, and will not be repeated here.

[0103] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0104] It should be understood that the "plurality" mentioned in this article refers to two or more. Those skilled in the art will easily think of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are indicated by the following claims.

[0105] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A trench gate field effect transistor, characterized in that: include: N+ substrate, N-type epitaxial layer, first dielectric layer, control gate, p-type body region, drain, source; The N-type epitaxial layer and the p-type matrix region are sequentially arranged above the N+ substrate, the drain is arranged below the N+ substrate, the first dielectric layer is located in the N-type epitaxial layer and the p-type matrix region, a control gate is arranged in the first dielectric layer, and the p-type matrix region is connected to the source; Wherein, the trench gate field effect transistor further includes a buried oxide layer, and the buried oxide layer is located below the first dielectric layer and is in contact with and connected to the lower side of the first dielectric layer.

2. The trench gate field effect transistor according to claim 1, characterized in that: The buried oxide layer is located in the N+ substrate and on the upper part of the N+ substrate.

3. The trench gate field effect transistor according to claim 2, characterized in that: The first dielectric layer passes through the N-type epitaxial layer and continues downward through a portion of the N+ substrate to contact the buried oxide layer.

4. The trench gate field effect transistor according to claim 1, characterized in that: The buried oxide layer is located in the N-type epitaxial layer.

5. The trench gate field effect transistor according to claim 4, characterized in that: The N-type epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the thickness of the first epitaxial layer is smaller than the thickness of the second epitaxial layer, the first epitaxial layer is located on the N+ substrate, the second epitaxial layer is located on the first epitaxial layer, and the buried oxide layer is located in the first epitaxial layer.

6. The trench gate field effect transistor according to any one of claims 1 to 4, characterized in that: The projection of the first dielectric layer on the horizontal plane is located within the region of the projection of the buried oxide layer on the horizontal plane, and the projection area of ​​the buried oxide layer on the horizontal plane is larger than the projection area of ​​the first dielectric layer on the horizontal plane.

7. The trench gate field effect transistor according to any one of claims 1 to 4, characterized in that: The trench gate field effect transistor further includes a shielding gate, which is located in the first dielectric layer and below the control gate, and is connected to the source.

8. A power chip, characterized in that: Comprising a trench gate field effect transistor as described in any one of claims 1-7.

9. The power chip according to claim 8, characterized in that: It also includes a second dielectric layer, which extends downward from the upper surface of the N-type epitaxial layer and contacts the buried oxide layer. The buried oxide layer and the second dielectric layer form an electrical isolation region. A control circuit is formed in the electrical isolation region. The control circuit is connected to the control gate of the trench gate field effect transistor to control the trench gate field effect transistor to turn on or off. The electrical isolation region is used to isolate the trench gate field effect transistor from interfering with the control circuit.

10. The power chip according to claim 9, characterized in that: A shielding gate is provided in the first dielectric layer of the trench gate field effect transistor, the shielding gate is located below the control gate, a connecting portion is provided in the second dielectric layer, the connecting portion is connected to the shielding gate, and the connecting portion is used to connect the shielding gate to the source; or, The buried oxide layer in contact with the second dielectric layer extends to the edge of the power chip in a direction away from the trench gate field effect transistor.

11. A method for manufacturing a power chip, characterized in that: include: Providing an N+ substrate; forming a plurality of buried oxide layers in the N+ substrate; An N-type epitaxial layer is formed on an N+ substrate, and a first deep trench is dug in the N-type epitaxial layer, wherein the first deep trench extends downward to a corresponding buried oxide layer; forming a first dielectric layer and a control gate in the first deep trench, wherein the first dielectric layer surrounds the control gate and the first dielectric layer contacts the buried oxide layer; A p-type base region, a source region and a drain are formed, wherein the p-type base and the source region are connected to the source respectively, and the drain is located at the bottom of the N+ substrate.

12. The method for manufacturing a power chip according to claim 11, characterized in that: Also includes: Digging a second deep trench in the N-type epitaxial layer, the second deep trench extending downward to the corresponding buried oxide layer, wherein the second deep trench is different from the first deep trench; forming a second dielectric layer in the second deep trench, wherein the second dielectric layer contacts the corresponding buried oxide layer, and the second dielectric layer and the corresponding buried oxide layer form an electrical isolation region; A control circuit is formed in the electrically isolated region.

13. A method for manufacturing a power chip, characterized in that: include: Providing an N+ substrate, and forming a first epitaxial layer on the N+ substrate; forming a plurality of buried oxide layers in the first epitaxial layer; forming a second epitaxial layer on the first epitaxial layer, digging a first deep trench in the second epitaxial layer and the first epitaxial layer, wherein the first deep trench extends downward to the corresponding buried oxide layer; forming a first dielectric layer and a control gate in the first deep trench, wherein the first dielectric layer surrounds the control gate and the first dielectric layer contacts the buried oxide layer; A p-type base region, a source region and a drain are formed, wherein the p-type base and the source region are connected to the source respectively, and the drain is located at the bottom of the N+ substrate.

14. The method for manufacturing a power chip according to claim 13, characterized in that: Also includes: Digging a second deep trench in the second epitaxial layer and the first epitaxial layer, the second deep trench extending downward to the corresponding buried oxide layer, wherein the second deep trench is different from the first deep trench; forming a second dielectric layer in the second deep trench, wherein the second dielectric layer contacts the corresponding buried oxide layer, and the second dielectric layer and the corresponding buried oxide layer form an electrical isolation region; A control circuit is formed in the electrically isolated region.

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