Separation gate SiC MOSFET device and preparation method thereof

Abstract

The invention discloses a separation gate SiC MOSFET device and a preparation method thereof, and relates to the technical field of semiconductors, and the separation gate SiC MOSFET device comprises a plurality of cellular structures which are arranged in an array; the cellular structure comprises a body region arranged in the epitaxial layer, an N + source region is arranged in the middle region of the body region, and a P + region is arranged in the middle region of the N + source region; wherein a part of the upper surface of the body region, a part of the upper surface of the N + source region and the upper surface of the P + region are exposed; n + regions are arranged between adjacent cellular structures, and stepped P regions are arranged on the upper surfaces of the N + regions; or, an N + region is arranged between the diagonal cellular structures, and a stepped P region is arranged on the upper surface of the N + region. According to the invention, the performance of the SiC MOSFET device can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a split-gate SiC MOSFET device and a preparation method thereof. Background Art

[0002] As a typical representative of the third-generation semiconductor materials, SiC material has many advantages such as wide bandgap, high thermal conductivity, high critical electric field, and high electron mobility. The devices made from it are one of the most promising devices at present. They have the characteristics of low impedance, high voltage, high temperature, high frequency, high efficiency, and radiation resistance. Therefore, they are widely used in automotive electronics, photovoltaic inverters, energy storage, aerospace and other fields.

[0003] SiC devices mainly include three series: SiC SBD, SiC MOSFET and SiC IGBT. At present, the market is mainly dominated by the development of SiC SBD and SiC MOSFET. In SiC MOSFET field effect transistors, breakdown usually occurs on the edge curved section, that is, the PN junction corner curve, the area covered with gate oxide layer. When the MOSFET is in operation, the electric field strength here is the largest. In the existing design of some split-gate devices, the original gate as a whole is divided into two parts, left and right, to reduce the overlapping area of ​​the gate and drain, and reduce the charge capacitance at the gate oxide without reducing the on-resistance, thereby improving the dynamic and short-circuit performance; although the split-gate design reduces the gate capacitance and gate charge, the split-gate SiC MOSFET exposes the edge of the gate (Poly-Si), which causes the gate oxide layer to generate a high electric field under the blocking characteristics.

[0004] Therefore, there is an urgent need to provide a split-gate SiC MOSFET device to improve the defects existing in the prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a split-gate SiC MOSFET device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a split-gate SiC MOSFET device, comprising:

[0007] A plurality of array-arranged cellular structures; the cellular structure comprises a body region arranged in an epitaxial layer, an N+ source region is arranged in the middle region of the body region, and a P+ region is arranged in the middle region of the N+ source region; wherein a portion of the upper surface of the body region, a portion of the upper surface of the N+ source region, and an upper surface of the P+ region are exposed;

[0008] An N+ region is provided between adjacent cell structures, and a stepped P region is provided on the upper surface of the N+ region;

[0009] And / or, an N+ region is disposed between the diagonal cell structures, and a stepped P region is disposed on an upper surface of the N+ region.

[0010] In a second aspect, the present invention further provides a method for preparing a split-gate SiC MOSFET device, which is used to prepare the split-gate SiC MOSFET device provided above, comprising:

[0011] providing an epitaxial layer;

[0012] By means of ion implantation, a plurality of array-arranged body regions are formed in the epitaxial layer;

[0013] By means of ion implantation, an N+ source region is formed in the middle region of the body region;

[0014] By ion implantation, a P+ region is formed in the middle of the N+ source region;

[0015] By means of ion implantation, an N+ region is formed between adjacent body regions; by means of ion implantation, a stepped P region is formed in the N+ region;

[0016] And / or, by ion implantation, an N+ region is formed between the diagonal body regions; by ion implantation, a stepped P region is formed in the N+ region.

[0017] Beneficial effects of the present invention:

[0018] The present invention provides a split-gate SiC MOSFET device and a preparation method thereof, comprising an epitaxial layer, wherein an array-arranged cellular structure is arranged in the epitaxial layer, wherein the cellular structure comprises a body region, wherein an N+ source region is arranged in the middle region of the body region, wherein a P+ region is arranged in the middle region of the N+ source region, wherein the P+ region runs through the entire N+ source region in a direction perpendicular to the epitaxial layer; wherein the entire upper surface of the P+ region is exposed, the upper surface of the side region of the N+ source region is exposed, and the upper surface of the side region of the body region is exposed; further, an N+ region is arranged between adjacent cellular structures, and the upper surface of the N+ region A stepped P region is provided, the N+ region and the stepped P region are both provided in the epitaxial layer, and the upper surface of the stepped P region is exposed; and / or, an N+ region is provided between the diagonal cell structures, a stepped P region is provided on the upper surface of the N+ region, the N+ region and the stepped P region are both provided in the epitaxial layer, and the upper surface of the stepped P region is exposed; in this way, a stepped P region is provided between adjacent body regions, i.e., in the JFET region, and when the device withstands voltage, the stepped P region and the body region are pinched off more quickly, thereby reducing the electric field strength that the gate oxide layer needs to withstand, and enhancing the reliability of the device.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of a split-gate SiC MOSFET device provided in an embodiment of the present invention;

[0021] Figure 2 is another schematic diagram of a split-gate SiC MOSFET device provided by an embodiment of the present invention;

[0022] Figure 3 is a top view of a split-gate SiC MOSFET device provided by an embodiment of the present invention;

[0023] Figure 4 is another top view of a split-gate SiC MOSFET device provided by an embodiment of the present invention;

[0024] Figure 5 is another top view of a split-gate SiC MOSFET device provided by an embodiment of the present invention;

[0025] Figure 6 The present invention provides a flow chart of a method for preparing a split-gate SiC MOSFET device. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0027] In the prior art, split-gate SiC MOSFET devices have the following defects, specifically:

[0028] 1. The Miller charge Qgd of SiC MOSFET device is too large;

[0029] The gate charge of SiC MOSFET devices includes Qgs (gate-source charge) and Qgd (gate-drain charge), where Qgd is also called Miller charge.

[0030] If Qgd is too large, the device will require a longer charging time, slowing down its switching speed and increasing the switching loss of the device. In addition, excessive accumulation of gate charge will also damage the reliability of the device, resulting in failures such as HTRB and HTGB.

[0031] At the same time, if Qgd is too large, it may also cause parasitic conduction in SiC MOSFET devices, and the device will be temporarily partially turned on, resulting in damage. Therefore, it is necessary to take certain measures to reduce the PTO parasitic conduction factor to avoid the occurrence of the above parasitic conduction. The calculation formula of the parasitic conduction factor (PTO) is:

[0032]

[0033] 2. The gate oxide reliability of SiC MOSFET devices is poor;

[0034] SiC MOSFET devices have attracted much attention in the field of power conversion due to their high voltage, high frequency, high temperature and high power density. For SiC MOSFET devices, gate oxide reliability is an important part of evaluating device reliability. The bandgap width of SiC material is greater than that of Si, so the device is smaller and the electric field strength that the gate oxide withstands is also higher.

[0035] In summary, if you want to improve the performance of SiC MOSFET devices, on the one hand, you need to reduce the charge Qgd, and on the other hand, you need to protect the gate oxide.

[0036] In view of this, the present invention proposes a split-gate SiC MOSFET device, which reduces the charge Qgd and the capacitance Ciss, and on this basis, adds a protective gate oxide layer structure.

[0037] See also Figure 1 , Figure 1 1 is a schematic diagram of a split-gate SiC MOSFET device provided by an embodiment of the present invention. A split-gate SiC MOSFET device provided by the present invention comprises: a plurality of cell structures 10 arranged in an array; the cell structure 10 comprises a body region 30 arranged in an epitaxial layer 20, an N+ source region 40 is arranged in the middle region of the body region 30, and a P+ region 50 is arranged in the middle region of the N+ source region 40; wherein a portion of the upper surface of the body region 30, a portion of the upper surface of the N+ source region 40 and an upper surface of the P+ region 50 are exposed;

[0038] An N+ region 60 is disposed between adjacent cell structures 10 , and a stepped P region 70 is disposed on the upper surface of the N+ region 60 ;

[0039] And / or, an N+ region 60 is disposed between the diagonal cell structures 10 , and a stepped P region 70 is disposed on an upper surface of the N+ region 60 .

[0040] For more details, please see Figure 1The split-gate SiC MOSFET device provided in this embodiment has fast switching characteristics and can be used for high-frequency applications, including a substrate and an epitaxial layer 20 stacked in sequence, an array-arranged cellular structure 10 is arranged in the epitaxial layer 20, the cellular structure 10 includes a body region 30, an N+ source region 40 is arranged in the middle region of the body region 30, a P+ region 50 is arranged in the middle region of the N+ source region 40, and the P+ region 50 runs through the entire N+ source region 40 along a direction D2 perpendicular to the epitaxial layer; wherein the entire upper surface of the P+ region 50 is exposed, the upper surface of a portion of the N+ source region 40 is exposed, and the upper surface of a portion of the body region 30 is exposed; further, an N+ region 6 is arranged between adjacent cellular structures 10 0, a stepped P region 70 is arranged on the upper surface of the N+ region 60, both the N+ region 60 and the stepped P region 70 are arranged in the epitaxial layer 20, and the upper surface of the stepped P region 70 is exposed; and / or, an N+ region 60 is arranged between the diagonal cell structures 10, a stepped P region 70 is arranged on the upper surface of the N+ region 60, both the N+ region 60 and the stepped P region 70 are arranged in the epitaxial layer 20, and the upper surface of the stepped P region 70 is exposed; in this way, a stepped P region 70 is arranged between adjacent body regions 30, that is, in the JFET region, and when the device withstands voltage, the stepped P region 70 and the body region 30 are pinched off more quickly, thereby reducing the electric field strength that the gate oxide layer needs to withstand and enhancing the device reliability.

[0041] In addition, when the device is reverse biased, the PN junction is reverse biased, and as the withstand voltage increases, the depletion region gradually expands, protecting the gate oxide layer and enhancing the reliability of the device, such as Figure 2 shown.

[0042] In addition, in the present embodiment, an N+ region 60 is provided between adjacent cellular structures 10 and / or between diagonal cellular structures 10. When the SiC MOSFET device is turned on, the device resistance is mainly the channel resistance, the JFET region resistance, and the drift region resistance. N+ injection is performed in the JFET region to increase the carrier concentration, thereby reducing the JFET region resistance.

[0043] It should be noted that Figure 1 The illustrated embodiment only schematically shows the positional relationship of the various film layers included in the SiC MOSFET device, and does not represent its actual size; Figure 2 The illustrated embodiment only schematically shows a schematic diagram of the depletion region of the SiC MOSFET device; in addition, the SiC MOSFET device also includes a drain located on the lower surface of the substrate, a gate dielectric located on the upper surface and side of the gate 90, and a source covering the uppermost layer.

[0044] In an optional embodiment of the present invention, please continue to refer to Figure 1, further comprising: a gate dielectric layer 80, which is disposed on the upper surface of the epitaxial layer 20, covers the upper surface of the exposed body region 30, contacts a portion of the upper surface of the exposed N+ source region 40, and contacts a portion of the upper surface of the stepped P region 70;

[0045] The gate 90 is disposed on the upper surface of the gate dielectric layer 80 , and along a direction D2 perpendicular to the epitaxial layer, the orthographic projection of the gate 90 overlaps with the orthographic projection of the gate dielectric layer 80 .

[0046] For more details, please see Figure 1 The split-gate SiC MOSFET device provided in this embodiment further includes a gate dielectric layer 80 disposed on the upper surface of the epitaxial layer 20, the gate dielectric layer 80 covers the upper surface of the exposed body region 30, covers a portion of the upper surface of the exposed N+ source region 40, and also covers a portion of the upper surface of the exposed stepped P region 70, and the gate 90 covers the upper surface of the gate dielectric layer 80. In this embodiment, the gate 90 is set as a split-gate structure, and the gate 90 is not completely covered in the area between the adjacent body regions 30, but only covers a portion of the upper surface of the stepped P region 70, which can effectively reduce the contact area between the gate 90 and the drain, and can achieve the effect of reducing the capacitance charge.

[0047] Considering the existing full-surface gate structure, the middle area below the gate oxide layer is often the weakest place and is prone to burn spots. The present embodiment is configured as a separated gate structure, which can effectively avoid the occurrence of burn spots.

[0048] In addition, due to the two-dimensional curvature effect, the electric field strength at the gate top corner is the highest. Due to the stress concentration at the corner, degradation is likely to occur during actual application, affecting the long-term reliability of the device. The stepped P region 70 in this embodiment covers the corner stress concentration area, and the electric field shielding effect of the stepped P region 70 can prevent gate oxide breakdown due to the electric field concentration at this location.

[0049] It should be noted that, in the existing planar SiC MOSFET device, the gate completely extends from the upper surface of one body region to the upper surface of another body region. During the process of turning on and off the device, the overlapping area between the gate and the drain is large, which makes the values ​​of the Miller charge Qgd and the transfer capacitance Ciss too large, which is not conducive to the application of high-speed switching. The split gate structure provided by the present invention can effectively reduce the capacitive charge of the gate 90 part of the device and optimize the dynamic performance of the device.

[0050] In addition, in the existing planar SiC MOSFET devices, the JFET region is uniformly N-type doped, and the electric field strength at the center of the gate oxide layer is too high, resulting in gate reliability failure. This phenomenon is more significant under the split gate design. The present invention provides a stepped P region 70 under the split gate to reduce the high electric field stress of the gate oxide layer.

[0051] In an optional embodiment of the present invention, along a direction D2 perpendicular to the epitaxial layer, the orthographic projection of the gate 90 is a ring structure, and the orthographic projections of adjacent gates 90 overlap with the orthographic projection of the same stepped P region 70 .

[0052] Specifically, by setting the gate 90 to a ring structure, the contact area between the gate 90 and the drain can be reduced, so that the capacitance charge of the device is reduced, and the dynamic performance of the SiC MOSFET device is optimized.

[0053] In an optional embodiment of the present invention, please continue to refer to Figure 4 , the stepped P region 70 includes a first P region 71 and a second P region 72, the first P region 71 is located on the upper surface of the N+ region 60, the second P region 72 is located on both sides of the first P region 71 along a direction D1 parallel to the epitaxial layer, and along a direction D2 perpendicular to the epitaxial layer, the orthographic projection of the first P region 71 overlaps with the orthographic projection of the N+ region 60, and the orthographic projection of the second P region 72 does not overlap with the orthographic projection of the N+ region 60;

[0054] Along a direction D2 perpendicular to the epitaxial layer, a height of the first P region 71 is greater than a height of the second P region 72 .

[0055] For more details, please see Figure 2 The stepped P region 70 provided in this embodiment includes a first P region 71 and a second P region 72. Along a direction D2 perpendicular to the epitaxial layer, the orthographic projection of the gate 90 overlaps with the orthographic projection of the second P region 72 located on one side of the first P region 71, and the orthographic projections of adjacent gates 90 overlap with the orthographic projections of the second P regions 72 located on both sides of the first P region 71 of the same stepped P region 70; in this way, the P region is set to be stepped, while protecting the gate dielectric layer 80, the resistance of the JFET region is reduced as much as possible.

[0056] It should be noted that if Figure 2 As shown, in this embodiment, ion implantation is performed on both sides of the first P region 71 to form the second P region 72, thereby forming a stepped P region 70, which can cover the top corners of the gate oxide layer where the electric field strength is concentrated.

[0057] In an optional embodiment of the present invention, the doping concentration of the first P region 71 is less than the doping concentration of the second P region 72 .

[0058] Specifically, in this embodiment, since there is an N+ region 60 in the JFET region to reduce the resistance of the JFET region, a concentrated injection is performed above the N+ region 60, that is, at the first P region 71 to protect the gate oxide layer from the influence of the N+ injection region, and the injection concentration in the second P region 72 can be lower than that in the first P region 71.

[0059] In an optional embodiment of the present invention, the doping concentration of the first P region 71 is 1E16-1E20 cm 2 The doping concentration of the second P region 72 is 1E16-1E18 cm 2 .

[0060] In an optional embodiment of the present invention, see Figure 3 , Figure 3 It is a top view of the split-gate SiC MOSFET device provided by an embodiment of the present invention. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the stepped P region 70 presents a grid shape and is arranged between adjacent cellular structures 10 and between diagonal cellular structures 10.

[0061] For more details, please see Figure 3 The stepped P region 70 provided in this embodiment is in a grid shape and is arranged between adjacent cellular structures 10 and between diagonal cellular structures 10. The stepped P region 70 can be set at the position with the highest electric field strength.

[0062] In an optional embodiment of the present invention, see Figure 4 , Figure 4 It is another top view of the split-gate SiC MOSFET device provided by an embodiment of the present invention. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the stepped P region 70 presents an intermittent strip shape and is arranged between adjacent cellular structures 10 .

[0063] For more details, please see Figure 4 The stepped P region 70 provided in this embodiment is in the shape of discontinuous strips, arranged between adjacent cellular structures 10, and is not disposed between diagonal cellular structures 10. The stepped P region 70 can be disposed at a position that withstands the highest electric field strength.

[0064] In an optional embodiment of the present invention, see Figure 5 , Figure 5 It is another top view of the split-gate SiC MOSFET device provided by an embodiment of the present invention. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the stepped P region 70 is in a dot shape and is disposed between the diagonal cell structures 10 .

[0065] For more details, please see Figure 5 The stepped P region 70 provided in this embodiment is in a dot shape and is only arranged between diagonal cellular structures 10, and is not arranged between adjacent cellular structures 10. The stepped P region 70 can be arranged at the position with the highest electric field strength.

[0066] Based on the same inventive concept, see Figure 6 , Figure 61 is a flow chart of a method for preparing a split-gate SiC MOSFET device provided in an embodiment of the present invention. The present invention also provides a method for preparing a split-gate SiC MOSFET device, which is used to prepare the split-gate SiC MOSFET device provided in the above embodiment of the present invention. The embodiment of the SiC MOSFET device is referred to above and will not be described in detail here. The preparation method comprises:

[0067] S101, providing an epitaxial layer 20;

[0068] S102, forming a plurality of array-arranged body regions 30 in the epitaxial layer 20 by ion implantation;

[0069] S103, forming an N+ source region 40 in the middle region of the body region 30 by ion implantation;

[0070] S104, forming a P+ region 50 in the middle region of the N+ source region 40 by ion implantation;

[0071] S105, forming an N+ region 60 between adjacent body regions 30 by ion implantation; forming a stepped P region 70 in the N+ region 60 by ion implantation;

[0072] Alternatively, an N+ region 60 is formed between the diagonal body regions 30 by ion implantation; and a stepped P region 70 is formed in the N+ region 60 by ion implantation.

[0073] Specifically, ion implantation is performed between adjacent body regions 30 to form an N+ region 60, ion implantation is performed in the N+ region 60 to form a first P region 71, and ion implantation is performed on the side of the first P region 71 to form a second P region 72; or, ion implantation is performed between diagonal body regions 30 to form an N+ region 60, ion implantation is performed in the N+ region 60 to form a first P region 71, and ion implantation is performed on the side of the first P region 71 to form a second P region 72.

[0074] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0076] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A split-gate SiC MOSFET device, characterized in that: include: A plurality of array-arranged cellular structures; the cellular structure comprises a body region arranged in an epitaxial layer, an N+ source region is arranged in the middle region of the body region, and a P+ region is arranged in the middle region of the N+ source region; wherein a portion of the upper surface of the body region, a portion of the upper surface of the N+ source region, and an upper surface of the P+ region are exposed; An N+ region is disposed between adjacent cellular structures, and a stepped P region is disposed on the upper surface of the N+ region; And / or, an N+ region is disposed between the diagonal cellular structures, and a stepped P region is disposed on an upper surface of the N+ region.

2. The split-gate SiC MOSFET device according to claim 1, characterized in that: Also includes: a gate dielectric layer, disposed on the upper surface of the epitaxial layer, covering the exposed upper surface of the body region, contacting a portion of the upper surface of the exposed N+ source region, and contacting a portion of the upper surface of the stepped P region; The gate is arranged on the upper surface of the gate dielectric layer, and along the direction perpendicular to the epitaxial layer, the orthographic projection of the gate overlaps with the orthographic projection of the gate dielectric layer.

3. The split-gate SiC MOSFET device according to claim 2, characterized in that: Along the direction perpendicular to the epitaxial layer, the orthographic projection of the gate is a ring-shaped structure, and the orthographic projections of adjacent gates overlap with the orthographic projection of the same stepped P region.

4. The split-gate SiC MOSFET device according to claim 1, characterized in that: The stepped P region includes a first P region and a second P region, the first P region is located on the upper surface of the N+ region, the second P region is located on both sides of the first P region along a direction parallel to the epitaxial layer, and along a direction perpendicular to the epitaxial layer, the orthographic projection of the first P region overlaps with the orthographic projection of the N+ region, and the orthographic projection of the second P region does not overlap with the orthographic projection of the N+ region; Along a direction perpendicular to the epitaxial layer, a height of the first P region is greater than a height of the second P region.

5. The split-gate SiC MOSFET device according to claim 4, characterized in that: The doping concentration of the first P region is lower than the doping concentration of the second P region.

6. The split-gate SiC MOSFET device according to claim 4, characterized in that: The doping concentration of the first P region is 1E16-1E20cm 2 The doping concentration of the second P region is 1E16-1E18cm 2 .

7. The split-gate SiC MOSFET device according to claim 1, characterized in that: Along the direction perpendicular to the epitaxial layer, the orthographic projection of the stepped P region presents a grid shape and is arranged between adjacent cellular structures and between diagonal cellular structures.

8. The split-gate SiC MOSFET device according to claim 1, characterized in that: Along the direction perpendicular to the epitaxial layer, the orthographic projection of the stepped P region is in the shape of discontinuous strips and is arranged between adjacent cellular structures.

9. The split-gate SiC MOSFET device according to claim 1, characterized in that: Along the direction perpendicular to the epitaxial layer, the orthographic projection of the stepped P region is in a point shape and is arranged between the diagonal cellular structures.

10. A method for preparing a split-gate SiC MOSFET device, used to prepare the split-gate SiC MOSFET device according to any one of claims 1 to 9, characterized in that: include: providing an epitaxial layer; By means of ion implantation, a plurality of array-arranged body regions are formed in the epitaxial layer; Forming an N+ source region in the middle region of the body region by ion implantation; Forming a P+ region in the middle region of the N+ source region by ion implantation; By means of ion implantation, an N+ region is formed between adjacent body regions; by means of ion implantation, a stepped P region is formed in the N+ region; And / or, by means of ion implantation, an N+ region is formed between the diagonal body regions; by means of ion implantation, a stepped P region is formed in the N+ region.

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