Semiconductor device and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method according to one embodiment of the present disclosure includes: forming a plurality of semiconductor nanostructures vertically stacked over a substrate; forming a dielectric structure suspended over a topmost one of the semiconductor nanostructures; forming a plurality of internal spacers interleaved with the semiconductor nanostructures; forming an epitaxial feature adjoining the semiconductor nanostructure; and forming a gate structure wrapping each of the semiconductor nanostructure and the dielectric structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology moves toward smaller nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that can extend around the channel region to provide access to the channel region on all four sides.

[0004] To improve the performance of GAA transistors, efforts are underway to develop structures in the channel region that improve the uniformity of metal gate height and channel member thickness.While conventional channel region structures are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack on a substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; depositing a dielectric structure above the stack; patterning the dielectric structure and the stack to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer on a sidewall of the dummy gate stack; recessing the fin-shaped structure in the source / drain region to form a source / drain exposing the sidewalls of the channel layer and the sacrificial layer; groove; recessing the sacrificial layer partially to form a plurality of internal spacer cavities; forming a plurality of internal spacers in the internal spacer cavities; forming an epitaxial component in the source / drain trench, the epitaxial component adjacent to the channel layer; after forming the epitaxial component, removing the pseudo gate stack to form a gate trench; releasing the channel layer in the channel region as a plurality of channel components by removing the sacrificial layer, the electrical structure suspended above the channel layer in the channel region; and forming a metal gate structure in the gate trench, the metal gate structure encapsulating each of the channel components and the dielectric structure.

[0006] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of semiconductor nanostructures stacked vertically on a substrate; forming a dielectric structure suspended above a topmost one of the semiconductor nanostructures; forming a plurality of internal spacers interlaced with the semiconductor nanostructures; forming an epitaxial component adjacent to the semiconductor nanostructures; and forming a gate structure encapsulating each of the semiconductor nanostructures and the dielectric structure.

[0007] Still other embodiments of the present application provide a semiconductor device, comprising: a plurality of semiconductor nanostructures disposed above a substrate; a dielectric structure located above a topmost one of the semiconductor nanostructures; a plurality of internal spacers interlaced with the semiconductor nanostructures; a metal gate structure wrapping each of the semiconductor nanostructures, wherein a bottom surface of the dielectric structure is located below a top surface of the metal gate structure; a gate spacer disposed on a sidewall of the metal gate structure; and an epitaxial component adjacent to the semiconductor nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0009] Figure 1A and Figure 1BA flowchart of an exemplary method for manufacturing a semiconductor device according to some embodiments of the present disclosure is shown.

[0010] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A and Fig.33A According to some embodiments, Figure 1A and Figure 1B A perspective view of a semiconductor device constructed by the method.

[0011] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.32B and Fig.33B According to some embodiments of the present disclosure, Figure 1A and Figure 1B A cross-sectional view in a YZ plane of a portion of a semiconductor device in a corresponding perspective view during a manufacturing process of the method.

[0012] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C , Fig.26C , Fig.27C , Fig.28C , Fig.29C , Fig. 30C , Fig.31C , Fig.32C and Fig.33C According to some embodiments of the present disclosure, Figure 1A and Figure 1B A cross-sectional view in an XZ plane of a portion of a semiconductor device in a corresponding perspective view during a manufacturing process of the method. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, in the following embodiments of the present disclosure, a component formed on another component that is connected to and / or coupled to another component may include an embodiment in which the components are directly contacted, and may also include an embodiment in which an additional component is formed between the components so that the components may not be directly contacted. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to facilitate understanding of the relationship between one component and another component of the embodiments of the present disclosure. Spatial relative terms are intended to cover different orientations of devices including components. Further, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a numerical value within a reasonable range including the described numerical value, such as within + / -10% of the described numerical value or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0015] Embodiments of the present disclosure provide a semiconductor device having a dielectric structure suspended over a vertically stacked semiconductor nanostructure in a channel region of a gate-all-around (GAA) transistor.

[0016] The channel region of the GAA transistor can be arranged in a semiconductor nanostructure (also referred to as a channel member), such as a nanowire channel member, a strip channel member, a nanosheet channel member, a columnar channel member, a rod-shaped channel member and / or other suitable channel configurations. Depending on the shape of the channel member, the GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Regardless of the shape, each of the channel members of the GAA transistor extends between two epitaxial components in two opposing source / drain regions and is coupled to two epitaxial components in two opposing source / drain regions. Epitaxial components are also referred to as source / drain components or source / drain epitaxial components. The source / drain region may refer to a source or a drain, individually or collectively depending on the context. During the replacement gate process, the dummy gate stack is removed to form a gate trench exposing the channel layer, which is then released by removing the staggered sacrificial layers to become a channel member, and then a metal gate structure is deposited over and between the channel members to wrap the channel members, and then a planarization process, such as a chemical mechanical planarization (CMP) process, is performed to recess the metal gate structure. During the removal of the dummy gate stack, the topmost one of the channel layers may suffer some etching losses from above due to limited etching contrast. Therefore, the topmost one of the channel members may become thinner than the other channel members below, which causes inconsistent channel member thickness. Process variations during planarization of the metal gate structure may also cause inconsistent metal gate heights.

[0017] The present disclosure provides an embodiment of a semiconductor device, wherein a dielectric structure is provided above a stack of channel components in a channel region. In some embodiments, the dielectric structure may be formed by a hard mask layer. This additional dielectric structure in the channel region provides etching protection during the removal of the dummy gate stack. The dielectric structure is also used as a planarization stop layer to define a uniform top surface of the metal gate structure during a metal gate planarization process. Therefore, the uniformity of the metal gate height and the channel component thickness is improved.

[0018] Figure 1A A flow chart of a method 100 for fabricating a semiconductor device according to various embodiments of the present disclosure is shown. Figure 1B 100. Additional processing is contemplated by the disclosed embodiments. Additional operations may be provided before, during, and after the method 100, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 100. FIG. 2A to FIG. 33C describe Figure 1A and Figure 1B , FIG. 2A to FIG. 33CVarious perspective and cross-sectional views of a semiconductor device (or device) 200 according to some embodiments are shown in various steps of fabrication according to method 100. In some embodiments, device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. For clarity, the device 200 has been simplified. FIG. 2A to FIG. 33C , to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 200.

[0019] In operation 102, method 100 ( Figure 1A ) provides a device 200 having a substrate 202, a stack 204 disposed on the substrate 202, a first hard mask layer 210 disposed on the stack 204, and a second hard mask layer 212 disposed on the first hard mask layer 210, such as FIG. 2A to FIG. 2C as shown in . Figure 2A A perspective view of the device 200 is shown, and Figure 2B and Figure 2C The device 200 is shown along Figure 2A Partial cross-sectional view of line AA and line BB in FIG. In particular, line AA is a cut along the longitudinal direction (direction "Y" or Y direction) of the gate structure to be formed, and line BB is a cut along the longitudinal direction (direction "X" or X direction) of the channel member to be formed. FIG. 3A to FIG. 31C The AA line and the BB line in are configured similarly.

[0020] In some embodiments, substrate 202 is a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various doping configurations depending on design requirements as known in the art. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenide (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0021] In some embodiments, the stack 204 includes sacrificial layers 206 of a first semiconductor composition interleaved with channel layers 208 of a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si). It should be noted that the four (4) layers of sacrificial layers 206 and the three (3) layers of channel layers 208 are arranged alternately, as shown in FIG. Figure 2A , which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 1 and 20.

[0022] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness between about 3 nm and about 10 nm, and all channel layers 208 may have a substantially uniform second thickness between about 3 nm and about 8 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each of the channel layers 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may be eventually removed and used to define the vertical distance between adjacent channel regions for a subsequently formed multi-gate device, and the thickness of each of the sacrificial layers 206 is selected based on device performance considerations.

[0023] In the depicted embodiment, the stack 204 also includes a top sacrificial layer 208T disposed on the topmost one of the sacrificial layers 206. In some examples, the channel layer 208 and the top sacrificial layer 208T have substantially the same composition, such as silicon (Si). The top sacrificial layer 208T is used to protect the stack 204 from damage during the manufacturing process. The top sacrificial layer 208T can be thinner than any one of the channel layer 208 and the sacrificial layer 206. In some examples, the thickness of the top sacrificial layer 208T can be between about 1 nm and about 2 nm.

[0024] The semiconductor layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and / or other suitable epitaxial growth processes. Thus, stack 204 is also referred to as epitaxial stack 204, and layers 206 and 208 are also referred to as epitaxial layers 206 and 208. As noted above, in at least some instances, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, channel layer 208 includes an epitaxially grown silicon (Si) layer, and top sacrificial layer 208T includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206, channel layer 208, and top sacrificial layer 208T are substantially free of dopants, where, for example, no intentional doping is performed during the epitaxial growth process for stack 204. In some embodiments, the top surface of substrate 202 is located in the (100) crystal plane, and thus each layer of stack 204 has a (100) top surface. In some alternative embodiments, the top surface of the substrate lies in the (110) crystal plane, and thus each layer of the stack 204 has a (110) top surface.

[0025] Still reference FIG. 2A to FIG. 2C, the first hard mask layer 210 may include a metal oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide or other suitable metal oxides. Although not explicitly shown, the first hard mask layer 210 may be a single layer or multiple layers, such as a double layer structure composed of two different materials. In some embodiments, the first hard mask layer 210 may be deposited using chemical vapor deposition (CVD) (including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD)), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes. As described in further detail below, the first hard mask layer 210 will be patterned as a dielectric component suspended above the channel member in the channel region to protect the topmost channel member from etching loss and improve the metal gate height uniformity by also serving as a planarization stop layer. In some embodiments, the first hard mask layer 210 has a thickness ranging from about 2 nm to about 20 nm. This range is not arbitrary or trivial. If the thickness is less than about 2 nm, the resulting dielectric component will be too thin to effectively serve as a planarization stop layer; if the thickness is greater than about 20 nm, the remaining portion of the dielectric component in the final structure will be too thick, which increases the metal gate height, which in turn results in increased parasitic capacitance that can reduce circuit speed.

[0026] The second hard mask layer 212 is deposited on the first hard mask layer 210. In some embodiments, the second hard mask layer 212 can be deposited using CVD, LPCVD, PECVD, PVD, ALD or other suitable methods. The second hard mask layer 212 can be a single layer or multiple layers. When the second hard mask layer 212 is multiple layers, the second hard mask layer 212 can include a pad oxide layer and a pad nitride layer. The pad oxide layer can be made of silicon oxide, and the pad nitride layer can be made of silicon nitride. In various embodiments, the first hard mask layer 210 and the second hard mask layer 212 include different material compositions, which allows the second hard mask layer 212 to be removed in a selective etching process without (or minimal) etching loss to the first hard mask layer 210. In some embodiments, the second hard mask layer 212 has a thickness ranging from about 2nm to about 20nm. In further advancement of some embodiments, the thickness of the second hard mask layer 212 is greater than the thickness of the first hard mask layer 210. Alternatively, the thickness of the second hard mask layer 212 may be smaller than the thickness of the first hard mask layer 210 .

[0027] In operation 104, method 100 ( Figure 1A ) patterning the stack 204 to form semiconductor fins 214 (also referred to as fins 214), such as FIG. 3A to FIG. 3CAs shown in . The fin 214 can be patterned by the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. The second hard mask layer 212 is patterned into a mask pattern. By patterning the opening defined in the second hard mask layer 212, the etching process forms a groove extending sequentially through the first hard mask layer 210, the stack 204 and the top portion of the substrate 202. The groove defines the fin 214. In some embodiments, a double patterning or multiple patterning process can be used to define a fin-shaped structure having, for example, a pitch that is less than the pitch that can be obtained using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins 214 by etching the stack 204 and the top portion of the substrate 202. The patterned top portion of the substrate 202 is also represented as the fin-shaped base 214B. As the context requires, the fin-shaped base 214B may still be considered as the top portion of the substrate 202. In the depicted embodiment, the fin 214 (which includes the patterned stack 204 and the fin-shaped base 214B) extends vertically in the Z direction and longitudinally in the X direction. In some instances, the width of the fin 214 along the Y direction is measured between about 6nm and about 80nm, and the distance between the opposing sidewalls of two adjacent fins 214 is measured along the Y direction between about 6nm and about 115nm. In FIG. 3A to FIG. 3C In FIG. 2 , three (3) fins 214 are spaced apart along the Y direction. However, the number of fins 214 is not limited to three, and may be as small as one, two, or more than three.

[0028] In operation 106, method 100 ( Figure 1A ) A dielectric material is deposited in the trenches between adjacent fins 214 to form isolation features 218, such as FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C . The isolation feature 218 may include one or more dielectric layers. Suitable dielectric materials for the isolation feature 218 may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique, including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin coating techniques. Then, a planarization operation, such as a CMP process, is performed to expose the top surface of the second hard mask layer 212, such as FIG. 4A to FIG. 4CSubsequently, a selective etching process is performed to remove the second hard mask layer 212, as shown in FIG. 5A to FIG. 5C . The selective etching process is adjusted to be selective to the material in the patterned second hard mask layer 212, and the patterned first hard mask layer 210 and the isolation features 218 remain substantially intact. After the patterned first hard mask layer 210 is exposed, the isolation features 218 are recessed to form shallow trench isolation (STI) features (hereinafter also referred to as STI features 218). Any suitable etching technique may be used to recess the isolation features 218, including dry etching, wet etching, RIE, and / or other etching methods, and in an exemplary embodiment, an anisotropic dry etch is used to selectively remove the dielectric material of the isolation features 218 without etching the fins 214 (including the first hard mask layer 210), as shown. FIG. 6A to FIG. 6C . In the depicted embodiment, the top surface of the STI feature 218 can be located below the bottom surface of the stack 204. Alternatively, according to some other embodiments, the top surface of the STI feature 218 can be coplanar with the bottom surface of the stack 204. At the end of operation 106, because the patterned second hard mask layer 212 has been removed and the patterned first hard mask layer 210 still remains, the patterned first hard mask layer 210 can also be simply referred to as a hard mask feature (or just "hard mask") 210, a dielectric feature 210, a dielectric structure 210, or a dielectric nanostructure 210.

[0029] In operation 108, method 100 ( Figure 1A ) to form a sacrificial (dummy) gate structure 226, such as 7A to 7CAs shown in . In the illustrated embodiment, a sacrificial gate structure 226 is shown, but the number of sacrificial gate structures 226 is not limited to one, two or more sacrificial gate structures, which are arranged in the X direction. The sacrificial gate structure 226 is formed above the portion of the fin 214 that will become the channel region. The sacrificial gate structure 226 defines the channel region of the transistor to be formed. The sacrificial gate structure 226 includes a sacrificial gate dielectric layer 228 and a sacrificial gate electrode layer 230. The sacrificial gate structure 226 is formed by first blanket depositing a sacrificial gate dielectric layer 228 above the fin 214. Then, a sacrificial gate electrode layer 230 is deposited on the sacrificial gate dielectric layer 228 and above the fin 214. The sacrificial gate electrode layer 230 includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer 230 is subjected to a planarization operation. The sacrificial gate dielectric layer 228 and the sacrificial gate electrode layer 230 can be deposited using CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes. Subsequently, a mask layer 232 is formed over the sacrificial gate electrode layer 230. The mask layer 232 may include a pad silicon oxide layer 232A and a silicon nitride mask layer 232B. Subsequently, a patterning operation is performed on the mask layer 232, and the sacrificial gate dielectric layer and the sacrificial gate electrode layer are patterned into a sacrificial gate structure 226. By patterning the sacrificial gate structure 226, the fin 214 is partially exposed on opposite sides of the sacrificial gate structure 226, thereby defining a source / drain (S / D) region.

[0030] In operation 110, method 100 ( Figure 1A ) A gate spacer 234 is formed on the sidewalls of the sacrificial gate structure 226 and the sidewalls of the fin 214, such as FIG. 8A to FIG. 8C . The gate spacer 234 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN and / or a combination thereof. In some embodiments, the gate spacer 234 includes multiple layers, such as a main spacer wall, a liner layer, etc. For example, the gate spacer 234 may be formed by blanket depositing a dielectric material layer over the sacrificial gate structure 226 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes in a conformal manner. The gate spacer 234 may be a single layer or multiple layers. In one embodiment, the gate spacer 234 includes a first layer and a second layer disposed above the first layer. The first layer may include silicon oxynitride, and the second layer may include silicon nitride. In some instances, the thickness of the gate spacer 234 along the X direction is measured between about 3nm and about 8nm.

[0031] In operation 112, method 100 ( Figure 1A) to recess a portion of the fin 214 to form an S / D trench (or S / D recess) 236 in the S / D region, such as 9A to 9C . The stacked epitaxial layers 206 and 208 and the hard mask 210 are etched down in the S / D region. In many embodiments, operation 112 forms the S / D trench 236 by a suitable etching process, such as a dry etching process, a wet etching process, or a RIE process. The etching process in operation 112 can be implemented using an etchant including a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), other suitable gases, or a combination thereof. The etchant is selected so that the top of the fin-shaped base 214B is also recessed, and the top portion of the sidewall of the STI component 218 is exposed in the S / D trench 236. In the depicted embodiment, at the end of operation 112, the portion of the gate spacer 234 previously deposited on the sidewall of the fin 214 remains in the S / D region, which is also referred to as a fin spacer or a source / drain spacer.

[0032] In operation 114, method 100 ( Figure 1A ) to form an internal spacer 240 adjacent to the end portion of the sacrificial layer 206, such as FIG. 10A to FIG. 10C and FIG. 11A to FIG. 11C Operation 114 may first laterally etch the end portion of epitaxial layer 206 to form a cavity 238 to be filled with dielectric material as an internal spacer 240, as shown in FIG. FIG. 10A to FIG. 10C . The sacrificial layer 206 may be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. Optionally, operation 114 may first selectively oxidize the lateral ends of the sacrificial layer 206 exposed in the S / D trench 236 to increase the etching selectivity between the epitaxial layers 206 and 208. In some instances, the oxidation process may be implemented by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. The cavity 238 also exposes end portions of the channel layer 208 and the top sacrificial layer 208T. Due to limited etching selectivity, the end portions of the channel layer 208 and the top sacrificial layer 208T may suffer some etching loss. For example, the end portions of the channel layer 208 may become thinner than the center portion in the Z direction, and the end portions of the top sacrificial layer 208T may be recessed in the X direction, so that the bottom surface of the hard mask 210 is exposed in the cavity 238, as shown in FIG. Fig. 10C Next, operation 114 forms internal spacers 240 on the recessed lateral ends of the upper epitaxial layer 206, such as FIG. 11A to FIG. 11C. For example, operation 114 may include blanket depositing an internal spacer material layer in the S / D groove 236. In particular, the internal spacer material layer is deposited on the recessed lateral end of the upper sacrificial layer 206 exposed in the cavity 238. The internal spacer material layer may include silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) or other suitable dielectric materials. In some embodiments, the internal spacer material layer includes the same material composition as in the hard mask 210. In some embodiments, the internal spacer material layer includes a material composition different from the hard mask 210. In some embodiments, the internal spacer material layer is deposited as a conformal layer having a substantially uniform thickness on different surfaces. The internal spacer material layer can be formed by ALD or any other suitable method. By conformally forming the internal spacer material layer, the volume of the cavity is reduced or completely filled. After depositing the internal spacer material layer, an etching operation is performed to partially remove the internal spacer material layer from the S / D groove 236. In particular, the inner spacer material layer is removed from the sidewalls of the sacrificial layer 206. By this etching, the inner spacer material layer is substantially retained within the cavity because of the small volume of the cavity. Typically, plasma dry etching etches layers faster in wide and flat areas than in concave (e.g., holes, grooves, and / or slits) portions. Therefore, the inner spacer material layer can remain inside the cavity 238. The remaining portion of the inner spacer material layer inside the cavity provides isolation between the metal gate structure to be formed and the S / D epitaxial component to be formed, which is referred to as the inner spacer 240.

[0033] In operation 116, method 100 ( Figure 1A ) forming an epitaxial component in the S / D trench 236, such as a buffer epitaxial layer 242 and a doped epitaxial layer 246 disposed above the buffer epitaxial layer 242, as shown in FIG. FIG. 12A to FIG. 12C . The buffer epitaxial layer 242 is deposited in the bottom of the S / D trench 236. In some embodiments, the buffer epitaxial layer 242 includes the same material as the substrate 202 and the channel layer 208, such as silicon (Si), except for the doping conditions (doping elements and / or doping concentrations). For example, the buffer epitaxial layer 242 is made of undoped silicon, the substrate 202 is made of doped silicon, and the channel layer 208 is made of undoped or doped silicon. In some embodiments, the buffer epitaxial layer 242 includes the same material as the sacrificial layer 206, such as silicon germanium (SiGe), wherein the germanium (Ge) content is the same as or different from each other. In some embodiments, the buffer epitaxial layer 242 includes Si x Ge 1-x, where x is between about 0.1 and 1. The germanium content range is not trivial. When the germanium content is greater than about 90%, the lattice mismatch between silicon and germanium may cause too many defects at the interface between the buffer epitaxial layer 242 and the substrate 202. In other embodiments, the buffer epitaxial layer 242, the channel layer 208, and the sacrificial layer 206 are made of semiconductor materials that are different from each other. In various embodiments, the buffer epitaxial layer 242 is free of dopants, where, for example, no intentional doping is performed during the epitaxial growth process. In comparison, in one example, the substrate 202 is lightly doped (e.g., an n-type dopant in a p-type region for forming a PFET or a p-type dopant in an n-type region for forming an NFET), and therefore has a higher doping concentration than the buffer epitaxial layer 242. The buffer epitaxial layer 242 without dopants provides a high resistance path from the S / D region to the substrate 202, thereby suppressing leakage current from entering the substrate 202.

[0034] The doped epitaxial layer 246 is formed on the buffer epitaxial layer 242. The channel layer 208 connects the two doped epitaxial layers 246 in the two opposite source / drain regions. The doped epitaxial layer 246 is also referred to as an S / D epitaxial component. In some embodiments, a dielectric film (not shown) can be deposited on the top surface of the buffer epitaxial layer 242 to separate the doped epitaxial layer 246 from the buffer epitaxial layer 242 so that the doped epitaxial layer 246 does not contact the buffer epitaxial layer 242. In other words, the bottom surface of the doped epitaxial layer 246 can be located on the top surface of the dielectric film. The dielectric film also suppresses leakage current from the source / drain region. Alternatively, the bottom surface of the doped epitaxial layer 246 can be directly located on the top surface of the buffer epitaxial layer 242, as shown in the depicted embodiment. In some embodiments, the doped epitaxial layer 246 includes an epitaxially grown semiconductor material, such as epitaxially grown silicon, germanium, or silicon germanium. The doped epitaxial layer 246 can be formed by any epitaxial process, including chemical vapor deposition (CVD) technology (e.g., vapor phase epitaxy and / or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The doped epitaxial layer 246 can be doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type transistors, the doped epitaxial layer 246 includes silicon and can be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:CS / D epitaxial components, Si:PS / D epitaxial components, or Si:C:PS / D epitaxial components). In some embodiments, for p-type transistors, the doped epitaxial layer 246 includes silicon germanium or germanium and can be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:BS / D epitaxial components). The doped epitaxial layer 246 can include multiple epitaxial semiconductor layers with different dopant density levels. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate dopants in the doped epitaxial layer 246. In the depicted embodiment, the top surface of the doped epitaxial layer 246 is below the bottom surface of the top sacrificial layer 208T. The topmost inner spacer 240 separates the doped epitaxial layer 246 from the top sacrificial layer 208T without the doped epitaxial layer 246 contacting the top sacrificial layer 208T. The top surface of the doped epitaxial layer 246 intersects the sidewalls of the topmost inner spacer 240.

[0035] In operation 118, method 100 ( Figure 1A ) A contact etch stop layer (CESL) 248 is formed over the doped epitaxial feature 246, and an interlayer dielectric (ILD) layer 250 is formed over the CESL layer 248, as shown in FIG. FIG. 13A to FIG. 13C and FIG. 14A to FIG. 14CAs shown in . The CESL layer 248 may include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials; and may be formed by CVD, PVD (physical vapor deposition), ALD, or other suitable methods. The ILD layer 250 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 250 may be formed by PECVD or FCVD (flowable CVD) or other suitable methods. In some embodiments, forming the ILD layer 250 also includes performing a CMP process to planarize the top surface of the device 200, thereby removing the mask layer 232 above the top portion of the sacrificial gate structure 226, such as FIG. 14A to FIG. 14C In the depicted embodiment, the CESL 248 and the ILD layer 250 are also disposed on the sidewalls of the hard mask 210 and the topmost inner spacer 240 such that the bottom surfaces of the CESL 248 and the ILD layer 250 are below the bottom surface of the top sacrificial layer 208T.

[0036] In operation 124, method 100 ( Figure 1A ) removes the sacrificial gate structure 226 to form a gate trench 252 in an etching process, such as FIG. 15A to FIG. 15C . The removal of the sacrificial gate structure 226 may include one or more etching processes that are selective to the material of the sacrificial gate structure 226. For example, the removal of the sacrificial gate structure 226 may be implemented using selective wet etching, selective dry etching, or a combination thereof that is selective to the sacrificial gate structure 226. In one embodiment, the etching process is reactive ion etching (RIE). After removing the sacrificial gate structure 226, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region and the hard mask 210 are exposed in the gate trench 252. In some embodiments where anisotropic dry etching is applied, the hard mask 210 protects the underlying epitaxial layers 206 and 208 from etching losses. Due to limited etching contrast, at the end of operation 124, the thickness of the hard mask 210 can be reduced by about 5% to about 20%.

[0037] In operation 126, method 100 ( Figure 1A ) The sacrificial layer 206 is selectively removed from the gate trench 252 in an etching process, such as FIG. 16A to FIG. 16C. The selective removal of sacrificial layer 206 releases channel layer 208 to form channel member (also numbered 208). Channel member 208 may also be referred to as nanostructure 208 or semiconductor nanostructure 208. Due to the etching protection from hard mask 210 (or dielectric structure 210), the topmost channel member 208 and other channel members 208 below have substantially the same thickness. Hard mask 210 and channel member 208 (at least the topmost channel member 208) may have substantially the same width measured in the Y direction. In the depicted embodiment, at the end of operation 126, the thickness of hard mask 210 may be greater than the thickness of channel member 208. Alternatively, at the end of operation 126, the thickness of hard mask 210 may be equal to or less than the thickness of channel member 208. The selective removal of sacrificial layer 206 also leaves a gap between channel members 208. The selective removal of sacrificial layer 206 may be implemented by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (eg, ammonium hydroxide-hydrogen peroxide-water mixture). The selective removal of sacrificial layer 206 also removes top sacrificial layer 208T.

[0038] In operation 130, method 100 ( Figure 1A ) forming a metal gate structure 254 in the gate trench 252, such as 17A to 17C In the channel region, a metal gate structure 254 wraps around each of the channel members 208 and the hard mask 210 . The inner spacer 240 separates the metal gate structure 254 from the doped epitaxial feature 246 so that the metal gate structure 254 does not contact the doped epitaxial feature 246 .

[0039] The metal gate structure 254 includes a gate dielectric layer 256 that wraps each of the channel components 208 in the channel region and a gate electrode layer 258 formed on the gate dielectric layer 256. The gate dielectric layer 256 also wraps the hard mask 210. In some embodiments, the gate dielectric layer 256 includes one or more dielectric material layers. In further advancement of some embodiments, the gate dielectric layer 256 includes an interface layer 256A and a high-k dielectric layer 256B formed on the interface layer 256A. The interface layer 256A can be formed by an oxidation process that oxidizes the exposed semiconductor surface of the channel component 208 and the exposed semiconductor surface of the fin-shaped substrate 214B. That is, the exposed dielectric surface of the STI component 218 and the hard mask 210 may not be directly covered by the interface layer 256A. Then, the high-k dielectric layer 256B is deposited on the interface layer 256A using ALD, CVD and / or other suitable methods. The exposed dielectric surfaces of the STI features 218 and the hard mask 210 are in contact with the high-k dielectric layer 256B instead. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In one embodiment, the high-k dielectric layer 256B is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed around each channel component.

[0040] The gate electrode layer 258 is formed on the gate dielectric layer 256 to wrap each of the channel members 208 and the hard mask 210. The gate electrode layer 258 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 258 can be formed by CVD, ALD, electroplating or other suitable methods. In certain embodiments of the present disclosure, one or more work function adjustment layers are interposed between the gate dielectric layer and the gate electrode layer. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaalC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as work function adjustment layers, and for p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as work function adjustment layers. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, the work function adjustment layer can be formed separately for n-type transistors and p-type transistors that can use different metal layers.

[0041] In operation 132, method 100 ( Figure 1A ) performing a planarization process, such as a CMP process, to remove excess dielectric material and conductive material and expose the hard mask 210, such as 18A to 18C. Conventionally, it is difficult to control the amount of height reduction during the planarization process without a planarization stop layer in the channel region. In order to leave sufficient process margin, the remaining metal gate height may often need to be greater than the actual required height, which increases parasitic capacitance and reduces circuit speed. In addition, conventional planarization processes applied on large surfaces, such as long metal gate structures extending across multiple fins 214 in the Y direction, may result in a curved recessed top surface. In comparison, by using the hard mask 210 as a planarization stop layer, the metal gate height can be easily controlled with a more uniform flat top surface. The planarization process removes the top portion of the hard mask 210 and exposes the dielectric material of the hard mask 210 and the high-k dielectric layer 256B on the recessed top surface of the device 200. In the depicted embodiment, at the end of operation 132, the previously larger thickness of the hard mask 210 can now become less than the thickness of the channel member 208. Alternatively, according to some other embodiments, at the end of operation 132, the thickness of hard mask 210 may become equal to or remain greater than the thickness of channel member 208. In some embodiments, at the end of operation 132, hard mask 210 has a thickness ranging from about 1 nm to about 18 nm.

[0042] In operation 134, method 100 ( Figure 1A ) forms a dielectric member 260 that divides the metal gate structure 254 into two isolation segments, such as FIG. 19A to FIG. 19C . Each of the segments of the metal gate structure 254 serves as a metal gate for a corresponding transistor. Because the dielectric component 260 provides isolation between the two segments of the metal gate structure 254, it is also referred to as an isolation component 260. In order to form the isolation component 260, operation 134 may first form a trench in an etching process. The etching process may use one or more etchants or a mixture of etchants to etch the various layers in the gate electrode layer 258 and the high-k dielectric layer 256B, such as a dry etching process with an etchant having atoms of chlorine, fluorine, bromine, oxygen, hydrogen, carbon, or a combination thereof. In the depicted embodiment, in order to ensure isolation between the segmented segments of the metal gate structure 254, operation 134 implements some overetching to extend the trench into the STI component 218. Such overetching is carefully controlled so as not to expose the substrate 202. Subsequently, operation 134 fills the trench with one or more dielectric materials to form the isolation component 260, and implements a planarization process, such as a CMP process, to planarize the top surface of the device 200. The one or more dielectric materials in the trenches form isolation features 260. The one or more dielectric materials may be deposited using CVD, PVD, ALD, or other suitable methods.

[0043] In some embodiments, the isolation component 260 includes a uniform dielectric material layer (e.g., silicon oxide or silicon nitride). In some other embodiments, the isolation component 260 includes multiple dielectric layers. For example, due to the high aspect ratio of the trench, the deposition of one or more dielectric materials may include multiple deposition steps. For example, a first dielectric material is deposited into the trench and etched back to form the lower portion of the isolation component 260. The etch back process is to ensure that there is substantially no void trapped in the trench. Subsequently, a second dielectric material is deposited into the trench to form the upper portion of the isolation component 260. The first dielectric material and the second dielectric material may be the same, such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). Alternatively, the first dielectric material and the second dielectric material may be different, such as the first dielectric material is an oxide, and the second dielectric material is a nitride, or vice versa. Whether the first dielectric material and the second dielectric material are the same or different, the interface between the first dielectric material and the second dielectric material may be discernible due to two different deposition steps.

[0044] In some other embodiments, instead of the lower part and the upper part, the isolation part 260 includes an outer part and an inner part. The outer part of the isolation part 260 is first formed, such as by a conformal deposition process. Subsequently, the inner part of the isolation part 260 is formed, and the inner part is wrapped by the outer part. The inner part and the outer part of the isolation part 260 can include different material compositions. For example, the outer part of the isolation part 260 can include an oxide (for example, silicon oxide), and the inner part of the isolation part 260 can include a nitride (for example, silicon nitride). The inner part of the isolation part 260 is a nitride that makes the isolation part 260 more etch-resistant in a later etching and / or flattening process. Optionally, because the metal material of the metal gate structure 254 contacts the outer part of the isolation part 260, the outer part may not contain active chemical components, such as oxygen (O). For example, the outer part of the isolation part 260 may include silicon nitride, and does not contain oxygen or oxide. In some embodiments, the isolation part 260 may include some oxides in its interior.

[0045] In operation 136, method 100 ( Figure 1A ) deposits an etch stop layer (ESL) 270 and deposits a dielectric layer 272 over the ESL 270, such as FIG. 20A to FIG. 20C. In some embodiments, ESL 270 may include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials; and may be formed by CVD, PVD, ALD, or other suitable methods. ESL 270 covers the exposed top surfaces of hard mask 210 and gate electrode layer 258. In some embodiments, dielectric layer 272 is another ILD layer, and may include TEOS oxide, undoped silicate glass, or doped silicon oxide, such as BPSG, FSG, PSG, BSG, and / or other suitable dielectric materials. Dielectric layer 272 may be formed by PECVD, FCVD, or other suitable methods.

[0046] In operation 138, method 100 ( Figure 1A ) A gate plug (or gate via) 274 is formed on the segmented gate segment of the metal gate structure 254. Each of the gate plugs 274 extends through the dielectric layer 272 and the ESL 270 to be bonded on the gate electrode layer 258. If the gate plug 274 is located directly above the hard mask 210, the gate plug 274 also extends through the hard mask 210 and the underlying high-k dielectric layer 256B to contact the gate electrode layer 258. In the depicted embodiment, the gate plugs 274 include a first type of gate plug 274A extending through the dielectric layer 272 and the ESL 270, and a second type of gate plug 274B extending through the dielectric layer 272, the ESL 270, the hard mask 210, and the high-k dielectric layer 256B below the hard mask 210. In some embodiments, the longer gate plug 274B has a bottom surface that is about 2 nm to about 25 nm lower than the bottom surface of the shorter gate plug 274A. The formation of the gate plug 274 includes forming a plug hole through the corresponding dielectric layer by an etching process, and depositing a conductive material in the plug hole as the gate plug 274. In an embodiment, the conductive material includes a barrier layer (such as TaN or TiN) and a metal filling layer (such as Al, Cu or W). The layers in the conductive material can be deposited using CVD, PVD, PECVD, ALD, plating or other suitable methods.

[0047] In operation 140, method 100 ( Figure 1A ) Further steps are performed to complete the manufacture of the device 200. For example, the method 100 can form metal interconnects that electrically connect the source, drain, and gate plugs of each transistor to form a complete IC.

[0048] Reference now Figure 1B , Figure 1B1 shows an alternative embodiment of the method 100. In an alternative embodiment of the method 100, after forming the CESL 248 and the ILD layer 250 in operation 118, instead of proceeding to operation 124 to remove the sacrificial gate structure 226, the method 100 proceeds to operation 120 to etch the sacrificial gate structure 226 to form the trench 280, as shown in FIG. FIG. 22A to FIG. 22C . In some embodiments, operation 120 uses a photolithography process, which includes: forming a resist layer (e.g., by spin coating) above the device 200; performing a pre-exposure baking process; performing an exposure process using a mask; performing a post-exposure baking process; and performing a development process. After development, the developed resist layer includes a resist pattern defining an opening having a width W1 above two adjacent fins 214. The width W1 is greater than the spacing W2 between the two adjacent fins 214. The etching process can use one or more etchants or a mixture of etchants to etch the sacrificial gate electrode layer 230 and the sacrificial gate dielectric layer 228 through the opening defined in the developed resist layer, and extend to the area between the two adjacent fins 214, without (or minimal) etching loss to the epitaxial stack 204 and the STI component 218. Because the selective etching process is self-aligned to be confined to the area between the two adjacent fins 214, operation 120 is not sensitive to the exact location of the opening having a relatively large width W1. The resulting trench 280 has a relatively large width W1 in its top portion and a relatively small width W2 in its bottom portion. The trench 280 exposes the top surface of the STI feature 218 but does not extend into the STI feature 218. Due to the limited etching contrast, the hard mask 210 may suffer some etching loss, so that the corner portion of the hard mask 210 may be recessed, as shown in the depicted embodiment.

[0049] In operation 122, method 100 ( Figure 1B ) The trench 280 is filled with one or more dielectric materials to form an isolation feature 282, such as FIG. 23A to FIG. 23C The dielectric material or materials of isolation feature 282 and their deposition may be substantially similar to isolation feature 260 as discussed above, such as by a multi-step deposition process in forming lower and upper portions of isolation feature 282 or outer and inner portions of isolation feature 282. In the depicted embodiment, as shown in FIG. Fig. 23BAs shown in , one or more dielectric materials of isolation component 282 include a dielectric liner 284 deposited on the sidewall and bottom surface of trench 280 and a dielectric inner layer 286 filling the remaining opening of trench 280. Dielectric liner 284 may include some oxides, SiN, SiCN, SiOC, SiOCN or other suitable dielectric materials. Dielectric inner layer 286 may include SiN, SiCN, SiOC, SiOCN or other suitable dielectric materials. In one embodiment, dielectric liner 284 may include silicon nitride and does not contain oxygen or oxide to avoid oxidation of the metal layer in the metal gate structure to be formed.

[0050] In operation 124, method 100 ( Figure 1B ) removes the sacrificial gate structure 226 to form a gate trench 252 in an etching process, such as FIG. 24A to FIG. 24C . The removal of the sacrificial gate structure 226 may include one or more etching processes that are selective to the material of the sacrificial gate structure 226. For example, the removal of the sacrificial gate structure 226 may be implemented using selective wet etching, selective dry etching, or a combination thereof that is selective to the sacrificial gate structure 226. In one embodiment, the etching process is reactive ion etching (RIE). After removing the sacrificial gate structure 226, in the channel region, the sidewalls of the channel layer 208 and the sacrificial layer 206 and the hard mask 210 are exposed in the gate trench 252. The exposed portion of the dielectric liner 284 may also be removed, thereby exposing the top portion of the dielectric inner layer 286 above the hard mask 210. In some embodiments where anisotropic dry etching is applied, the hard mask 210 protects the underlying epitaxial layers 206 and 208 from etching losses. Due to limited etching contrast, the thickness of the hard mask 210 may be reduced by about 5% to about 20% at the end of operation 124.

[0051] In operation 126, method 100 ( Figure 1B ) The sacrificial layer 206 is selectively removed from the gate trench 252 in an etching process, such as FIG. 25A to FIG. 25C . The selective removal of sacrificial layer 206 releases channel member 208. The selective removal of sacrificial layer 206 also leaves a gap between channel members 208. The dielectric liner 284 of isolation component 282 is also exposed in the gap. The selective removal of sacrificial layer 206 can be implemented by selective dry etching, selective wet etching or other selective etching processes. The selective removal of sacrificial layer 206 also removes the top sacrificial layer 208T.

[0052] In operation 128, method 100 ( Figure 1B ) trimming the exposed dielectric liner 284 of the CMG component 282 to expand the gap between adjacent channel members 208, such as FIG. 26A to FIG. 26C. The trimming of dielectric liner 284 can be implemented by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). The trimming of dielectric liner 284 exposes the sidewalls of dielectric inner layer 286 in the gap between adjacent channel members 208. The exposed sidewalls of dielectric inner layer 286 may have a vertical length of about 0nm to about 5nm between the adjacent remaining segments of dielectric liner 284. The first portion of dielectric liner 284 is stacked laterally between channel member 208 and dielectric inner layer 286 because the etchant may be difficult to reach this portion of dielectric liner 284. Similarly, a second portion of the dielectric liner 284 is vertically stacked between the STI features 218 and the dielectric inner layer 286 , and a third portion of the dielectric liner 284 is laterally stacked between the hard mask 210 and the dielectric inner layer 286 .

[0053] In operation 130, method 100 ( Figure 1B ) forming a metal gate structure 254 in the gate trench 252, such as FIG. 27A to FIG. 27C . In the channel region, the metal gate structure 254 wraps around each of the channel members 208 and the hard mask 210. The internal spacer 240 separates the metal gate structure 254 from the doped epitaxial member 246 so that the metal gate structure 254 does not contact the doped epitaxial member 246. The interface layer 256A and the high-k dielectric layer 256B fill the space between the channel member 208 and the dielectric inner layer 286, which survives the trimming process in operation 128. The isolation member 282 divides the metal gate structure 254 into two isolated segments. With the isolation member 260 ( Fig.21A and Fig. 21B ) are different, such as Fig.27B The isolation features 282 depicted in FIG. 2 are not partially embedded in the STI features 218 .

[0054] In operation 132, method 100 ( Figure 1B ) performing a planarization process, such as a CMP process, to remove excess dielectric material and conductive material and expose the hard mask 210, as also shown in FIG. FIG. 27A to FIG. 27C . By using the hard mask 210 as a planarization stop layer, the metal gate height can be easily controlled with a more uniform flat top surface. The planarization process removes the top portion of the hard mask 210 and exposes the dielectric material of the hard mask 210, as well as the high-k dielectric layer 256B and the isolation features 282. In the depicted embodiment, the top portion of the isolation features 282 having the larger width W1 is completely removed by the planarization process, and the bottom portion of the isolation features 282 having the smaller width W2 remains.

[0055] After operation 132, an optional embodiment of method 100 proceeds to operation 136 ( Figure 1A ), wherein an etch stop layer (ESL) 270 and a dielectric layer 272 are deposited, and then proceeding to operation 138 ( Figure 1A ), wherein a gate plug 274 is formed, such as FIG. 28A to FIG. 28C Also in operation 140, method 100 ( Figure 1A ) Further steps are performed to complete the manufacture of the device 200. For example, the method 100 can form metal interconnects that electrically connect the source, drain, and gate plugs of each transistor to form a complete IC.

[0056] FIG. 29A to FIG. 29C An alternative embodiment of the device 200 is shown at the end of operation 138, wherein the dielectric liner 284 is not trimmed (e.g., operation 128 is skipped). Therefore, the dielectric liner 284 separates the dielectric inner layer 286 from the high-k dielectric layer 256B without the dielectric inner layer 286 contacting the high-k dielectric layer 256B. The interface layer 256A and the high-k dielectric layer 256B are also not laterally positioned between the channel member and the isolation feature 282.

[0057] FIG. 30A to FIG. 30C Another alternative embodiment of the device 200 at the end of operation 138 is shown, where a top portion of the isolation feature 282 is retained by controlling the amount of metal gate height reduction during the planarization process in operation 132. Thus, the isolation feature 282 has a top portion with a larger width W1 and a bottom portion with a smaller width W2.

[0058] FIG. 31A to FIG. 31C Another alternative embodiment of the device 200 at the end of operation 138 is shown, in which the dielectric liner 284 is not trimmed (e.g., operation 128 is skipped) and the top portion of the isolation feature 282 remains. Therefore, the dielectric liner 284 separates the dielectric inner layer 286 from the high-k dielectric layer 256B without the dielectric inner layer 286 contacting the high-k dielectric layer 256B. The interface layer 256A and the high-k dielectric layer 256B are also not laterally positioned between the channel member and the isolation feature 282. In addition, the isolation feature 282 has: a top portion having a larger width W1 and a bottom portion having a smaller width W2.

[0059] FIG. 32A to FIG. 32C Another alternative embodiment of the device 200 is shown in which the isolation features 282 do not extend the entire lateral distance between the channel members 208. That is, the isolation features 282 are spaced apart from the channel members 208 with the high-k dielectric layer 256B and the gate electrode layer 258 therebetween. The resulting structure is similar to FIG. 21A to FIG. 21COne of the differences is that since the metal gate structure 254 is formed after the isolation feature 282 is formed, the high-k dielectric layer 256B is deposited on the sidewalls of the isolation feature 282. In the depicted embodiment, the isolation feature 282 is also partially embedded in the STI feature 218.

[0060] FIG. 33A to FIG. 33C Another alternative embodiment of device 200 is shown, in which a portion of high-k dielectric layer 256B is interposed between the topmost inner spacer 240 and the bottom surface of hard mask 210 ( Fig.33C This may be due to the high etch selectivity in operation 114, so that the top sacrificial layer 208T is not recessed in the X direction (with respect to Fig. 10C ), and the metal gate structure 254 later occupies the interval reversed by the top sacrificial layer 208T. In such an embodiment, the high-k dielectric layer 256B can contact the CESL 248, such as Fig.33C A high-k dielectric layer 256B in contact with the CESL 248 and separating the topmost inner spacer 240 from the bottom surface of the hard mask 210 may also be present as shown in FIG. FIG. 21A to FIG. 21C and FIG. 28A to FIG. 32C In the other embodiments described in .

[0061] Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form a dielectric structure suspended above a vertically stacked channel member in a channel region of a multi-gate transistor. This advantageously improves the uniformity of channel member thickness and metal gate height. In addition, embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0062] In one exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a stack on a substrate, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers; depositing a dielectric structure on the stack; patterning the dielectric structure and the stack to form a fin-shaped structure, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer on a sidewall of the dummy gate stack; recessing the fin-shaped structure in the source / drain region to form a source / drain trench exposing the sidewalls of the channel layer and the sacrificial layer; and The method further comprises recessing a portion of the layer to form a plurality of internal spacer cavities; forming a plurality of internal spacers in the internal spacer cavities; forming an epitaxial component in the source / drain trench, the epitaxial component being adjacent to the channel layer; after forming the epitaxial component, removing the dummy gate stack to form a gate trench; releasing the channel layer in the channel region as a plurality of channel members by removing the sacrificial layer, the electrical structure being suspended above the channel layer in the channel region; and forming a metal gate structure in the gate trench, the metal gate structure encapsulating each of the channel members and the dielectric structure. In some embodiments, the method further comprises: recessing the metal gate structure to expose the dielectric structure. In some embodiments, the method further comprises: forming a gate plug extending through the dielectric structure and contacting the metal gate structure. In some embodiments, after releasing the channel layer, the dielectric structure and the topmost one of the channel members have the same width. In some embodiments, the metal gate structure is in contact with the dielectric structure. In some embodiments, the method further comprises: depositing a hard mask layer over the dielectric structure; patterning the hard mask layer, wherein the fin-shaped structure comprises the hard mask layer; depositing an isolation feature on the sidewalls of the stack, the dielectric structure, and the hard mask layer; selectively removing the hard mask layer to expose the dielectric structure; and recessing the isolation feature. In some embodiments, the method further comprises: forming an isolation feature. The isolation feature separates the metal gate structure into two isolation segments. In some embodiments, the isolation feature comprises a bottom portion and a top portion having a discernible interface therebetween. In some embodiments, the isolation feature comprises an outer layer of a first dielectric material and an inner layer of a second dielectric material different from the first dielectric material.

[0063] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a plurality of semiconductor nanostructures stacked vertically on a substrate; forming a dielectric structure suspended above the topmost one of the semiconductor nanostructures; forming a plurality of internal spacers interlaced with the semiconductor nanostructure; forming an epitaxial component adjacent to the semiconductor nanostructure; and forming a gate structure that wraps each of the semiconductor nanostructure and the dielectric structure. In some embodiments, the method also includes: flattening the gate structure to expose the dielectric structure; depositing an interlayer dielectric layer above the dielectric structure; and forming a gate plug extending through the interlayer dielectric layer and the dielectric structure. In some embodiments, the gate structure includes an interface layer, a high-k dielectric layer, and a gate electrode layer. The interface layer contacts the semiconductor nanostructure. The high-k dielectric layer contacts the dielectric structure. In some embodiments, the method also includes: depositing a dielectric layer on the top surface of the epitaxial component. The gate structure contacts the dielectric layer. In some embodiments, the method also includes: forming an isolation component that separates the gate structure into two isolation segments. The isolation component is a double-layer structure including a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer include different material compositions.

[0064] In another exemplary aspect, the disclosed embodiments relate to a semiconductor device. The semiconductor device includes: a plurality of semiconductor nanostructures disposed above a substrate; a dielectric structure located above the topmost one of the semiconductor nanostructures; a plurality of internal spacers interlaced with the semiconductor nanostructures; a metal gate structure wrapping each of the semiconductor nanostructures, the bottom surface of the dielectric structure being located below the top surface of the metal gate structure; a gate spacer disposed on the sidewall of the metal gate structure; and an epitaxial component adjacent to the semiconductor nanostructure. In some embodiments, the top surface of the metal gate structure and the top surface of the dielectric structure are coplanar. In some embodiments, the semiconductor device further includes: a gate plug extending through the dielectric structure and contacting the metal gate structure. In some embodiments, the metal gate structure contacts the sidewall and bottom surface of the dielectric structure. In some embodiments, the semiconductor nanostructure is a first semiconductor nanostructure, and the metal gate structure is a first metal gate structure, and the semiconductor device further includes: a plurality of second semiconductor nanostructures; a second metal gate structure wrapping each of the second semiconductor nanostructures; and an isolation component separating the first metal gate structure from the second metal gate structure. In some embodiments, the isolation component includes a first dielectric layer and a second dielectric layer. A portion of the first dielectric layer is located below the second dielectric layer. The first dielectric layer and the second dielectric layer include different material compositions.

[0065] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack on a substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; depositing a dielectric structure above the stack; patterning the dielectric structure and the stack to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer on a sidewall of the dummy gate stack; recessing the fin-shaped structure in the source / drain region to form a source / drain exposing the sidewalls of the channel layer and the sacrificial layer; groove; recessing the sacrificial layer partially to form a plurality of internal spacer cavities; forming a plurality of internal spacers in the internal spacer cavities; forming an epitaxial component in the source / drain trench, the epitaxial component adjacent to the channel layer; after forming the epitaxial component, removing the pseudo gate stack to form a gate trench; releasing the channel layer in the channel region as a plurality of channel components by removing the sacrificial layer, the electrical structure suspended above the channel layer in the channel region; and forming a metal gate structure in the gate trench, the metal gate structure encapsulating each of the channel components and the dielectric structure.

[0066] In some embodiments, the method further comprises: recessing the metal gate structure to expose the dielectric structure. In some embodiments, the method further comprises: forming a gate plug extending through the dielectric structure and contacting the metal gate structure. In some embodiments, after releasing the channel layer, the dielectric structure and the topmost one of the channel members have the same width. In some embodiments, the metal gate structure contacts the dielectric structure. In some embodiments, the method further comprises: depositing a hard mask layer over the dielectric structure; patterning the hard mask layer, wherein the fin-shaped structure comprises the hard mask layer; depositing isolation features on the sidewalls of the stack, the dielectric structure, and the hard mask layer; selectively removing the hard mask layer to expose the dielectric structure; and recessing the isolation features. In some embodiments, the method further comprises: forming an isolation feature, wherein the isolation feature separates the metal gate structure into two isolation segments. In some embodiments, the isolation feature comprises a bottom portion and a top portion having a discernible interface therebetween. In some embodiments, the isolation feature comprises an outer layer of a first dielectric material and an inner layer of a second dielectric material different from the first dielectric material.

[0067] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of semiconductor nanostructures stacked vertically on a substrate; forming a dielectric structure suspended above a topmost one of the semiconductor nanostructures; forming a plurality of internal spacers interlaced with the semiconductor nanostructures; forming an epitaxial component adjacent to the semiconductor nanostructures; and forming a gate structure encapsulating each of the semiconductor nanostructures and the dielectric structure.

[0068] In some embodiments, the method further includes: planarizing the gate structure to expose the dielectric structure; depositing an interlayer dielectric layer over the dielectric structure; and forming a gate plug extending through the interlayer dielectric layer and the dielectric structure. In some embodiments, the gate structure includes an interface layer, a high-k dielectric layer, and a gate electrode layer, the interface layer is in contact with the semiconductor nanostructure, and the high-k dielectric layer is in contact with the dielectric structure. In some embodiments, the method further includes: depositing a dielectric layer on a top surface of the epitaxial component, wherein the gate structure is in contact with the dielectric layer. In some embodiments, the method further includes: forming an isolation component that separates the gate structure into two isolation segments, wherein the isolation component is a double-layer structure including a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer and the second dielectric layer include different material compositions.

[0069] Still other embodiments of the present application provide a semiconductor device, comprising: a plurality of semiconductor nanostructures disposed above a substrate; a dielectric structure located above a topmost one of the semiconductor nanostructures; a plurality of internal spacers interlaced with the semiconductor nanostructures; a metal gate structure wrapping each of the semiconductor nanostructures, wherein a bottom surface of the dielectric structure is located below a top surface of the metal gate structure; a gate spacer disposed on a sidewall of the metal gate structure; and an epitaxial component adjacent to the semiconductor nanostructure.

[0070] In some embodiments, the top surface of the metal gate structure and the top surface of the dielectric structure are coplanar. In some embodiments, the semiconductor device further comprises: a gate plug extending through the dielectric structure and contacting the metal gate structure. In some embodiments, the metal gate structure contacts the sidewalls and the bottom surface of the dielectric structure. In some embodiments, the semiconductor nanostructure is a first semiconductor nanostructure, and the metal gate structure is a first metal gate structure, and the semiconductor device further comprises: a plurality of second semiconductor nanostructures; a second metal gate structure encapsulating each of the second semiconductor nanostructures; and an isolation component separating the first metal gate structure from the second metal gate structure. In some embodiments, the isolation component comprises a first dielectric layer and a second dielectric layer, a portion of the first dielectric layer is located below the second dielectric layer, and the first dielectric layer and the second dielectric layer comprise different material compositions.

[0071] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; depositing a dielectric structure over the stack; patterning the dielectric structure and the stack to form a fin structure, the fin structure including a channel region and a source / drain region; forming a dummy gate stack over the channel region of the fin structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing the fin structure in the source / drain region to form a source / drain trench exposing sidewalls of the channel layer and the sacrificial layer; recessing the sacrificial layer portion to form a plurality of internal spacer cavities; forming a plurality of internal spacers in the internal spacer cavity; forming an epitaxial feature in the source / drain trench, the epitaxial feature adjoining the channel layer; After forming the epitaxial component, removing the dummy gate stack to form a gate trench; releasing the channel layer in the channel region as a plurality of channel components by removing the sacrificial layer, the electrical structure being suspended above the channel layer in the channel region; as well as A metal gate structure is formed in the gate trench, the metal gate structure encapsulating each of the channel member and the dielectric structure.

2. The method according to claim 1, further comprising: The metal gate structure is recessed to expose the dielectric structure.

3. The method according to claim 2, further comprising: A gate plug is formed extending through the dielectric structure and contacting the metal gate structure.

4. The method according to claim 1, wherein: After releasing the channel layer, the dielectric structure and a topmost one of the channel members have the same width.

5. The method according to claim 1, wherein: The metal gate structure contacts the dielectric structure.

6. The method according to claim 1, further comprising: depositing a hard mask layer over the dielectric structure; patterning the hard mask layer, wherein the fin-shaped structure includes the hard mask layer; depositing isolation features on sidewalls of the stack, the dielectric structure, and the hard mask layer; selectively removing the hard mask layer to expose the dielectric structure; and The isolation member is recessed.

7. The method according to claim 1, further comprising: An isolation feature is formed, wherein the isolation feature separates the metal gate structure into two isolation segments.

8. The method according to claim 7, wherein: The isolation member includes a bottom portion and a top portion having a discernible interface therebetween.

9. A method of forming a semiconductor device, comprising: forming a plurality of semiconductor nanostructures stacked vertically on a substrate; forming a dielectric structure suspended over a topmost one of the semiconductor nanostructures; forming a plurality of internal spacers interlaced with the semiconductor nanostructures; forming an epitaxial feature adjacent to the semiconductor nanostructure; as well as A gate structure is formed that wraps around each of the semiconductor nanostructure and the dielectric structure.

10. A semiconductor device comprising: a plurality of semiconductor nanostructures disposed above a substrate; a dielectric structure disposed on a topmost one of the semiconductor nanostructures; a plurality of internal spacers interlaced with the semiconductor nanostructures; a metal gate structure encapsulating each of the semiconductor nanostructures, wherein a bottom surface of the dielectric structure is below a top surface of the metal gate structure; a gate spacer disposed on a sidewall of the metal gate structure; and An epitaxial feature is adjacent to the semiconductor nanostructure.

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