Semiconductor device and forming method thereof

Abstract

Embodiments provide a bipolar junction transistor (BJT) formed from a GAA or FinFET transistor and a method of forming the BJT. The BJT includes a dielectric isolation structure formed between the gates of the GAA or FinFET transistor. The dielectric isolation structure reduces a pitch between transistors of adjacent terminals of the BJT. The dielectric isolation structure allows the BJT to use a nominal gate pitch (Lg) as a logic device, thereby being compatible with a GAA or FinFET process. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

[0004] A bipolar junction transistor (BJT) includes a base, a collector, and an emitter. A BJT is formed by two pn junctions placed back to back, with one region being a common region for both junctions. This arrangement forms a PNP or NPN bipolar junction transistor. In a BJT, the current flowing through the emitter and collector is controlled by the voltage between the base and emitter. As the semiconductor industry moves to nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, various techniques have been implemented to improve BJT device performance. Summary of the invention

[0005] An embodiment of the present disclosure provides a semiconductor device, comprising: a first well, located in a semiconductor substrate, and having a first type of dopant; a second well, located in the semiconductor substrate, and having a second type of dopant different from the first type, wherein the first well intersects with the second well; a first transistor, having a first epitaxial region located above the first well, wherein the first epitaxial region has the second type of dopant; a second transistor, having a second epitaxial region located above the first well, wherein the second epitaxial region has the first type of dopant; a third transistor, having a third epitaxial region located above the second well, wherein the third epitaxial region has the second type of dopant, wherein the second epitaxial region is arranged between the first epitaxial region and the third epitaxial region; and a first dielectric isolation structure, arranged between the second transistor and the third transistor.

[0006] Another embodiment of the present disclosure provides a semiconductor device, comprising: a plurality of fin structures extending along a first direction on a substrate, wherein the plurality of fin structures include a first fin structure, a second fin structure and a third fin structure; a first epitaxial region located above the first fin structure, the first epitaxial region providing an emitter terminal for a first bipolar junction transistor (BJT) and a second bipolar junction transistor; a second epitaxial region located above the second fin structure and providing a base terminal for the first bipolar junction transistor; a third epitaxial region located above the third fin structure and providing a collector terminal for the first bipolar junction transistor; a first gate structure arranged across the plurality of fin structures along a second direction; and a first dielectric isolation structure arranged between the second fin structure and the third fin structure and across the first gate structure, wherein the first dielectric isolation structure divides the first gate structure into a first gate portion arranged above the first fin structure and the second fin structure and a second gate portion arranged above the third fin structure.

[0007] Another embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming a first well, a second well, and a third well in a substrate, wherein the first well and the third well are doped with a first type of dopant, the second well is doped with a second type of dopant, and the second well is arranged between the first well and the third well along a first direction and intersects with the first well and the third well; forming a plurality of fin structures above the first well, the second well, and the third well, wherein the plurality of fin structures extend along the first direction; forming a dielectric material around lower portions of the plurality of fin structures; forming a plurality of sacrificial gate structures, the plurality of sacrificial gate structures are along a second direction and span the plurality of fin structures; recessing the plurality of fin structures exposed by the plurality of sacrificial gate structures; forming epitaxial regions from the plurality of fin structures; forming a replacement gate structure; and forming a dielectric isolation structure between the epitaxial regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A plan view of a bipolar junction transistor device according to an embodiment of the present disclosure is shown.

[0010] Figure 2 is a schematic partial perspective view of a bipolar junction transistor device according to some embodiments.

[0011] FIG. 2A to FIG. 2E yes Figure 2Schematic cross-sectional view of a bipolar junction transistor device.

[0012] Figure 3 is a flow chart of a method for forming a bipolar junction transistor device according to an embodiment of the present disclosure.

[0013] Figures 4 to 10 , FIG. 10A to FIG. 10C , Fig.11 , FIG. 11A to FIG. 11C , Fig.12 , FIG. 12A to FIG. 12C , Fig.13 , FIG. 13A to FIG. 13C , Fig.14 , FIG. 14A to FIG. 14C , Fig.15 , FIG. 15A to FIG. 15C and FIG. 16A to FIG. 16C Various views are shown of intermediate stages in the fabrication of a bipolar junction transistor in accordance with some embodiments.

[0014] Fig.17 , Fig.18 , 18A to 18C and FIG. 19A to FIG. 19C A bipolar junction transistor device according to some embodiments is shown.

[0015] Fig. 20 and FIG. 21A to FIG. 21C A bipolar junction transistor device according to some embodiments is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] The foregoing generally summarizes some aspects of the embodiments described in the present disclosure. Although some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, FinFETs, horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. It will be readily appreciated by those of ordinary skill in the art that other modifications are contemplated within the scope of the present disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than described herein. In the present disclosure, source / drain regions refer to source and / or drain. Source and drain may be used interchangeably.

[0019] Embodiments provide a BJT formed by a GAA or FinFET transistor and a method for forming the BJT. In some embodiments, the BJT includes a dielectric isolation structure formed between the gates of the GAA or FinFET transistor. The dielectric isolation structure can be formed using a cut metal gate process, which can be used to manufacture GAA or FinFET transistors. The BJT according to the present disclosure can be formed using a GAA or FinFET process, and therefore can be formed together with a logic device during the same process. The dielectric isolation structure reduces the spacing between transistors of adjacent terminals of the BJT. The dielectric isolation structure allows the BJT to use a nominal gate spacing (Lg) as a logic device, thereby being compatible with the GAA or FinFET process.

[0020] In some embodiments, the BJT includes a series of p-type GAA / FinFET transistors connected together to form a BJT collector terminal, a series of n-type GAA / FinFET transistors connected together to form a BJT base terminal, and a series of p-type GAA / FinFET transistors connected together to form a BJT emitter terminal. The source / drain region of each of these series of GAA / FinFET transistors can be electrically coupled together or electrically coupled to the gate electrode of the GAA / FinFET transistor. When properly contacted with each other through the substrate, a lateral BJT transistor is formed. For example, in this case, the BJT transistor is a PNP BJT transistor. Alternatively, the BJT according to the present disclosure can be an NPN BJT, including a series of n-type GAA / FinFET transistors connected together to form a BJT collector terminal, a series of p-type GAA / FinFET transistors connected together to form a BJT base terminal, and a series of n-type GAA / FinFET transistors connected together to form a BJT emitter terminal.

[0021] The gate structure of the GAA / FinFET transistor may include a metal gate structure formed in the same process as the GAA / FinFET transistor in the logic device. The gate structure may span terminals, wherein a dielectric isolation structure is formed between certain terminals. For example, a dielectric isolation structure is formed between the gate structure between the collector terminal and the base terminal.

[0022] Figure 1 1 is a schematic top view of a semiconductor device 100 after an intermediate stage of fabrication according to some embodiments. In particular, the semiconductor device 100 includes two lateral BJTs 12 and 14. The BJT 12 includes an emitter terminal 106, a base terminal 108, and a collector terminal 112, and the BJT 14 includes an emitter terminal 106, a base terminal 110, and a collector terminal 114. Figure 1 , the active area of ​​the semiconductor device 100 is defined by a length L1 and a width W1. The total length L1 of the BJTs 12, 14 may be between about 1 μm and about 5 μm. The width W1 may be between about 1.0 μm and 3.5 μm.

[0023] In some embodiments, BJT 12 and BJT 14 in semiconductor device 100 may be used as two separate BJTs that share a common emitter terminal 106. In some embodiments, BJT 12 and 14 may be effectively used as a single BJT. For example, base terminal 108 of BJT 12 and base terminal 110 of BJT 14 may be coupled together in a metallization layer, and collector terminal 112 of BJT 12 and collector terminal 114 of BJT 14 may be coupled together in a metallization layer. BJT 12 and BJT 14 are connected together and effectively used as a single BJT having a length of approximately 2×L1.

[0024] Each terminal 106, 108, 110, 112, 114 includes one or more fin structures and one or more gate structures formed across the one or more fin structures. The fin structure may include multiple channel layers. Figure 1 As shown, emitter terminal 106 includes fin structure 206 , base terminal 108 includes fin structure 208 , collector terminal 112 includes fin structure 212 , base terminal 110 includes fin structure 210 , and collector terminal 114 includes fin structure 214 .

[0025] In some embodiments, the number of fin structures 206 for the emitter terminal 106 may range between 4 and 6. In some embodiments, the number of fin structures 208, 210 for the base terminals 108, 110 may range between 2 and 4. In some embodiments, the number of fin structures 212, 214 for the collector terminals 112, 114 may range between 2 and 4.

[0026] A plurality of gate structures 250 are formed over the fin structures 206, 208, 210, 212, and 214. In some embodiments, the number of gate structures 250 may range between 1 and 100, such as between 20 and 80.

[0027] In some embodiments, dielectric isolation structures 252 are formed on gate structure 250 between fin structures 208 and 212 and between fin structures 210 and 214. In some embodiments, semiconductor device 100 may include dielectric isolation structures 254 formed on gate structure 250 between fin structures 206 and 208 and between fin structures 206 and 210. Dielectric isolation structures 252, 254 may be formed using a cut metal gate process. Dielectric isolation structures 252, 254 cut gate structure 250 into electrically isolated gate portions 310, 320, 330, 340, 350. Gate structure portions 310, 320, 330, 340, and 350 are located above fin structures 212, 208, 206, 210, 214.

[0028] Epitaxial emitter regions 256 are formed over fin structures 206 between gate structures 250. Epitaxial base regions 258 are formed over fin structures 208 between gate structures 250. Epitaxial base regions 260 are formed over fin structures 210 between gate structures 250. Epitaxial collector regions 262 are formed over fin structures 212 between gate structures 250. Epitaxial collector regions 264 are formed over fin structures 214 between gate structures 250. Epitaxial regions 256, 258, 260, 262, and 264 are similar to epitaxial source / drain regions of a GAA transistor or a FinFET transistor.

[0029] In some embodiments, epitaxial emitter regions 256 are electrically coupled together to form emitter terminal 106. In some embodiments, epitaxial emitter regions 256 can be electrically coupled together by connecting gate structure portion 330 in a metallization layer. Similarly, epitaxial base regions 258 are electrically coupled together via gate structure portion 320 to form base terminal 108, epitaxial base regions 260 are electrically coupled together via gate structure portion 340 to form base terminal 110, epitaxial collector regions 262 are electrically coupled together via gate structure portion 310 to form collector terminal 112, and epitaxial collector regions 264 are electrically coupled together via gate structure portion 350 to form collector terminal 114.

[0030] Alternatively, the dielectric isolation structure 254 may be omitted, allowing the emitter terminal 106 to be electrically connected to the base terminals 108 , 110 through the gate structure 250 .

[0031] In some embodiments, the active area defined by the width W1 and the length L1 may be surrounded by a non-active area. A shallow trench isolation region (STI) 240 may surround the active area. The STI 240 also extends between the fin structures 212, 208, 206, 210, and 214. In some embodiments, a non-active gate 360 ​​is formed in the non-active area. The non-active gate 360 ​​may be a dummy gate, a polysilicon gate, or a metal gate. In the case where the gate is a metal gate or a polysilicon gate, a conductive member is not formed to reach the non-active gate 360, so that the non-active gate 360 ​​is electrically floating during operation.

[0032] In the examples described herein, the BJTs 12, 14 are PNP-type BJTs. The emitter terminal 106 is an emitter terminal doped with a p-type dopant, the base terminals 108, 110 are n-wells doped with an n-type dopant, and the collector terminals 112, 114 are p-wells 112 and 114 doped with a p-type dopant. Fin structures 212, 208, 206, 210, and 214 are formed by these doped well regions. Alternatively, the BJTs 12, 14 may be NPN-type BJTs.

[0033] Figure 1 It is also shown that the gate structure portion 320 above the fin structure 208 and the gate structure portion 330 above the fin structure 206 are laterally separated by the dielectric isolation structure 254. In some embodiments, the dielectric isolation structure 254 has a width W2, which is the end-to-end distance between the gate structure portions 330 and 320. In some embodiments, the width W2 is in the range between 45nm and 80nm. The gate structure portion 320 above the fin structure 208 and the gate structure portion 310 above the fin structure 212 are laterally separated by the dielectric isolation structure 252. In some embodiments, the dielectric isolation structure 252 has a width W3, which is the end-to-end distance between the gate structure portions 320 and 310. In some embodiments, the width W3 is in the range between 45nm and 80nm. Similarly, the end-to-end distance between the gate structure portions 330 and 340 is the width W2, which is in the range between 45nm and 80nm. The end-to-end distance between gate structure portions 340 and 350 is width W3, which is in a range between 45 nm and 80 nm.

[0034] Figure 1 The dashed-line frame 10 in FIG. 1 includes a portion of the semiconductor device 100 defined by the dashed-line frame 10 . Figure 2 Schematically shows the Figure 11 is a perspective view of a portion of a semiconductor device 100 marked by a dashed box 10 in FIG. 1 , which for simplicity is referred to as semiconductor device 10 or BJT 10 . It should be understood that these views of semiconductor device 10 may be used to represent any embodiments consistent with those discussed herein. Figure 2 The cross sections mentioned in the following figure are also provided. In particular, FIG. 2A to FIG. 2E Along the Figure 2 Schematic cross-sectional view of the semiconductor device 10 along lines AA, BB, CC, DD, and EE in FIG.

[0035] The semiconductor device 10 is similar to Figure 1 , except that the semiconductor device 10 does not include the dielectric isolation structure 254, leaving the gate structure of the emitter terminal 106 coupled to the gate structures of the base terminals 108, 110. The semiconductor device 10 may be a BJT with a GAA transistor or a BJT with a FinFET transistor. Figure 2C , Figure 2D , Figure 2E The cross sections of a GAA transistor and a FinFET transistor are schematically shown.

[0036] like FIG. 2A to FIG. 2E As shown, dielectric isolation structure 252 separates gate structure 250 between collector terminal 112 / 114 and base terminal 108 / 110. Gate structures of emitter terminal 106 and base terminal 108, 110 are connected. Terminal contacts 422, 424, 426, 428 and 430 and gate contacts 452, 454, 458 and 460 are disposed over the epitaxial region and gate structure. Connecting features 512, 514, 516, 518 and 520 are disposed over to provide wiring and connections.

[0037] In some embodiments, Figure 2A As shown, connecting members 512, 514, 518 and 520 couple gate contacts 452, 454, 458, 460 to each other, respectively. Figure 2B As shown, connecting features 512, 514, 516, 518 and 520 respectively couple terminal contacts 422, 424, 426, 428 and 430 between different epitaxial regions. As for emitter terminal 106, the gate structure of emitter terminal 106 is electrically coupled to base terminals 108 and 110.

[0038] like Figure 2C As shown, for the emitter terminal 106, the connection member 516 is electrically coupled to the terminal contact 426, while the gate structure 330 is connected to the base terminal 108 / 110. Figure 2DAs shown, for base terminal 108, connection member 514 electrically couples gate contact 454 with terminal contact 424. Similarly, for base terminal 110, connection member 518 electrically couples gate contact 458 with terminal contact 428. Figure 2E As shown, for the collector terminal 112, the connection member 512 can electrically couple the gate contact 452 with the terminal contact 422. Similarly, for the collector terminal 114, the connection member 520 can electrically couple the gate contact 460 with the terminal contact 430.

[0039] In other words, for collector terminals and base terminals, the gate electrode is coupled to adjacent epitaxial regions. For example, connection feature 512 may couple gate contact 452 with terminal contact 422, thereby coupling epitaxial collector region 262 on fin structure 212 with gate structure portion 310. Similarly, connection feature 514 may couple epitaxial base region 258 on fin structure 208 with gate structure portion 330, connection feature 518 may couple epitaxial base region 260 on fin structure 210 with gate structure portion 330, and connection feature 520 may couple epitaxial collector region 264 on fin structure 214 with gate structure portion 350.

[0040] Figure 3 is a flow chart of a method 400 for forming a bipolar junction transistor device according to an embodiment of the present disclosure. Figures 4 to 10 , FIG. 10A to FIG. 10C , Fig.11 , FIG. 11A to FIG. 11C , Fig.12 , FIG. 12A to FIG. 12C , Fig.13 , FIG. 13A to FIG. 13C , Fig.14 , FIG. 14A to FIG. 14C , Fig.15 , FIG. 15A to FIG. 15C and FIG. 16A to FIG. 16C Various views are shown of intermediate stages in the fabrication of a semiconductor device 10 in accordance with some embodiments.

[0041] In operation 402, as Figures 4 to 9 As shown, Figures 4 to 9 is a perspective view of the semiconductor device 10 , where a plurality of semiconductor fin structures 205 are formed over a substrate 102 and over shallow trench isolations STI 240 formed around lower portions of the fin structures 250 .

[0042] exist Figure 4In the embodiment of the present invention, a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the semiconductor substrate 102 may be a bulk silicon substrate. In other embodiments, the semiconductor substrate 102 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The semiconductor substrate 102 may be a p-type substrate, that is, the semiconductor substrate 102 may be doped with a p-type dopant (also referred to as an impurity). The semiconductor substrate 102 may also include an additional doped well, which may be doped with an n-type or p-type dopant, depending on the design requirements, to form a well region including an n-type doped well and a p-type doped well. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination thereof.

[0043] In some embodiments, semiconductor substrate 102 includes a deep n-well 104. For example, n-well 104 is doped with n-type dopants and is located below other wells formed in substrate 102. N-well 104 also spans the underside of other wells formed in substrate 102 at the surface of substrate 102. N-well 104 can be formed by masking areas of substrate 102 that are not to be implanted and performing deep implantation of n-type impurities. N-type impurities may include phosphorus, arsenic, antimony, etc., or combinations thereof, implanted into n-well 104 to a depth equal to or less than 1019 cm -3 concentration, such as about 10 16 cm -3 and about 10 19 cm -3 However, other concentrations may be used and are contemplated.

[0044] The emitter terminal 106 is formed to span the width of the central portion of the n-well 104. The base terminal 108 and the base terminal 110 are formed on both sides of the emitter terminal 106. The collector terminal 112 and the collector terminal 114 are formed on one side of the base terminal 108 and the base terminal 110, respectively. The emitter terminal 106 will be used as a pair of BJTs (e.g., Figure 112 and BJT 14). In some embodiments, the collector terminals 112, 114 and base terminals 108, 110 of the pair of BJTs may also be coupled together to effectively form a single BJT. Base terminal 108 and base terminal 110 will serve as the respective bases of each of the pair of BJTs, and collector terminal 112 and collector terminal 114 will serve as the respective collectors of each of the pair of BJTs.

[0045] In some embodiments, an epitaxial material (epitaxial layer or epitaxial material stack) is formed over a substrate for forming a fin structure thereon. In some embodiments, a semiconductor stack 130 is formed over a semiconductor substrate 102 using a GAA process. The semiconductor stack 130 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices, such as nanosheet channel FETs. In some embodiments, the semiconductor stack 130 includes a first semiconductor layer 132 between a second semiconductor layer 134. The first semiconductor layer 132 and the second semiconductor layer 134 have different oxidation rates and / or etching selectivities. At a later manufacturing stage, portions of the semiconductor layer 134 form nanosheet channels in a multi-gate device (including transistors for BJTs). As shown in the example, three first semiconductor layers 132 and three second semiconductor layers 134 are arranged alternately. Depending on the desired number of channels in the semiconductor device to be formed, more or fewer semiconductor layers 132 and 134 may be included in the semiconductor stack 130. In some embodiments, the number of semiconductor layers 132, 134 is between 1 and 10.

[0046] The semiconductor layers 132, 134 may be formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor layers 132 and 134 are made of materials having different lattice constants. In some embodiments, the first semiconductor layer 132 includes an epitaxially grown silicon germanium (SiGe) layer, and the second semiconductor layer 134 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the semiconductor layers 132 and 134 may include other materials, such as Ge; compound semiconductors such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the semiconductor stack 130 may have the same type of dopant as the terminal below.

[0047] In some embodiments, each second semiconductor layer 134 has a thickness in a range between about 5 nm and about 30 nm. In other embodiments, each second semiconductor layer 134 has a thickness in a range between about 10 nm and about 20 nm. In some embodiments, each second semiconductor layer 134 has a thickness in a range between about 6 nm and about 12 nm. In some embodiments, the thickness of the second semiconductor layer 134 in the semiconductor stack 130 is uniform. The first semiconductor layer 132 in the channel region may eventually be removed and used to define the vertical distance between adjacent channel regions for the subsequently formed multi-gate device. In some embodiments, the thickness of the first semiconductor layer 132 is equal to or greater than the thickness of the second semiconductor layer 134. In some embodiments, each semiconductor layer 132 has a thickness in a range between about 5 nm and about 50 nm. In other embodiments, each first semiconductor layer 132 has a thickness in a range between about 10 nm and about 30 nm.

[0048] like Figure 5 As shown, a liner layer 120 and a mask layer 125 are sequentially formed on the semiconductor stack 130. The liner layer 120 may be, for example, a silicon oxide film formed by a thermal oxidation process. The liner layer 120 may be used as an adhesive layer between the semiconductor stack 130 and the mask layer 125. The liner layer 120 may also be used as an etch stop layer for etching the mask layer 125. For example, the mask layer 125 may be a silicon nitride layer formed by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer 125 may be used as a hard mask during a subsequent etching process.

[0049] exist Figure 6 In the embodiment of the present invention, a plurality of fin structures 205 are formed. The mask layer 125 may be patterned using photolithography techniques. The liner layer 120 may be etched based on the pattern of the mask layer 125 using the mask layer as an etching mask, thereby exposing the upper surface of the semiconductor stack 130. The upper surface of the semiconductor stack 130 is not covered by the mask layer 125. The semiconductor stack 130 and the terminals 106, 108, 110, 112, and 114 are then etched to form trenches and the fin structure 205 therebetween. The fin structure 206 is formed on and in the emitter terminal 106, the fin structure 208 is formed on and in the base terminal 108, the fin structure 210 is formed on and in the base terminal 110, the fin structure 212 is formed on and in the collector terminal 112, and the fin structure 214 is formed on and in the collector terminal 114. Depending on the design, the number of fins and trenches may vary. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The active area may also be defined, as described above with respect to Figure 1As described above, the substrate is etched to form ends of the fin structures 206, 208, 210, 212, and 214. In some embodiments, the fin structures 206, 208, 210, 212, and 214 may be formed first and then cut into desired lengths (eg, length L1) in a subsequent process.

[0050] The fin structures 206, 208, 210, 212, and 214 may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns having, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fin.

[0051] The height of the fin structures 206, 208, 210, 212, and 214 may be between about 100 nm and about 150 nm, but other values ​​may also be used and contemplated. The pitch between the fins of the fin structures 206, 208, 210, 212, and 214 may be between about 15 nm and about 80 nm. The spacing between the sidewall of one fin and the sidewall of an adjacent fin structure may be between 40 nm and 100 nm. Other dimensions are contemplated and may be used for the fins.

[0052] exist Figure 7In the embodiment, the insulating material 230 is formed over the fin structures 206, 208, 210, 212, and 214, and fills the trenches between the fin structures 206, 208, 210, 212, and 214. The insulating material 230 may be an oxide (such as silicon oxide), a nitride (such as silicon nitride), or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 230 is silicon oxide formed by an FCVD process. Once the insulating material 230 is formed, an annealing process may be performed. In an embodiment, the insulating material 230 is formed such that excess insulating material 230 covers the fin structures 206, 208, 210, 212, and 214. Although the insulating material 230 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner may first be formed along the surfaces of substrate 102 and fin structures 206, 208, 210, 212, and 214. Thereafter, a fill material, such as those discussed above, may be formed over the liner.

[0053] exist Figure 8 In the embodiment, a removal process is applied to the insulating material 230 to remove excess insulating material 230 above the fin structures 206, 208, 210, 212, and 214. In some embodiments, a planarization process (such as chemical mechanical polishing (CMP)), an etch back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin structures 206, 208, 210, 212, and 214 such that after the planarization process is completed, the fin structures 206, 208, 210, 212, and 214 are flush with the top surface of the insulating material 230. In embodiments where a mask remains on the fin structures 206, 208, 210, 212, and 214, the planarization process may expose the mask or remove the mask such that after the planarization process is completed, the mask or the fin structures 206, 208, 210, 212, and 214 are flush with the top surface of the insulating material 230.

[0054] exist Fig. 9 In the embodiment, the insulating material 230 is recessed to form a shallow trench isolation (STI) region 240. The insulating material 230 is recessed so that upper portions of the fin structures 206, 208, 210, 212, and 214 protrude from between adjacent STI regions 240. Fig. 9As shown, portions of the semiconductor stack 130 of the fin structures 206, 208, 210, 212, and 214 are exposed above the STI region 240. In addition, the top surface of the STI region 240 may have a flat surface, a convex surface, a concave surface, or a combination thereof as shown. The top surface of the STI region 240 may be formed to be flat, convex, and / or concave by appropriate etching. The STI region 240 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material 230 (e.g., etching the material of the insulating material 230 at a faster rate than the material of the fin structures 206, 208, 210, 212, and 214). For example, the oxide may be removed using, for example, dilute hydrofluoric acid (dHF).

[0055] about Figures 4 to 9 The process described is only one example of how fin structures 206, 208, 210, 212, and 214 may be formed. In some embodiments, fin structures 206, 208, 210, 212, and 214 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of substrate 102, and a trench may be etched through the dielectric layer to expose substrate 102 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form fins 206, 208, 210, 212, and 214. Additionally, in some embodiments, a heteroepitaxial structure may be used for fins 206, 208, 210, 212, and 214. For example, a heteroepitaxial structure may be used. Figure 6 The fins 206, 208, 210, 212, and 214 in the substrate 102 are recessed, and a material different from the fins 206, 208, 210, 212, and 214 can be epitaxially grown over the recessed fins 206, 208, 210, 212, and 214. In such an embodiment, the fins 206, 208, 210, 212, and 214 include the recessed material and the epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 102, and a trench can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trench using a material different from the substrate 102, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 206, 208, 210, 212, and 214. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implants, although in situ and implant doping may be used together.

[0056] Furthermore, it may be advantageous to epitaxially grow a different material in the base terminal 108 and the base terminal 110 than in the emitter terminal 106, the collector terminal 112, and the collector terminal 114. In various embodiments, the upper portions of the fin structures 206, 208, 210, 212, and 214 may be made of silicon germanium (SiGe). x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0057] In some embodiments, the grown material of the epitaxial fin structures 206 , 208 , 210 , 212 , and 214 may be doped in situ during growth, which may avoid implantation, but in situ doping and implantation doping may be used together.

[0058] Regardless of the process used to form the fin structures 206, 208, 210, 212, and 214, in some embodiments, the fin structures 206, 208, 210, 212, and 214 may be further doped in a separate process to increase the dopant concentration in the fin structures 206, 208, 210, 212, and 214. In some embodiments, the upper portions of the fin structures 206, 208, 210, 212, and 214 may be suitably doped to about 10% of the additional p-type or n-type impurities. 19 cm -3 to about 10 21 cm -3 A mask may be used to protect portions of fin structures 206 , 208 , 210 , 212 , and 214 while implanting other regions.

[0059] In operation 404, if Fig.10 and FIG. 10A to FIG. 10C As shown, a sacrificial gate structure 250 ′ is formed over the fin structure 205 . Fig.10 is a schematic perspective view of the semiconductor device 10 . FIG. 10A to FIG. 10C It is along Fig.10 1 is a schematic cross-sectional view of the semiconductor device 10 along the lines AA, BB, and CC in FIG. A sacrificial gate structure 250' is formed over the fin structure 205. The sacrificial gate structure 250' may include a sacrificial gate dielectric layer, a sacrificial gate electrode layer, and a sidewall spacer 270. The sacrificial gate structure 250' is formed over a portion of the fin structure 205 that will become a channel region.

[0060] A sacrificial gate dielectric layer is formed over the fin structure 205 by blanket deposition. The sacrificial gate dielectric layer includes one or more layers of insulating material, such as a silicon oxide-based material. In some embodiments, silicon oxide formed by CVD is used. In some embodiments, the sacrificial gate dielectric layer has a thickness in a range between about 1 nm and about 5 nm. Then, a sacrificial gate electrode layer is blanket deposited on the sacrificial gate dielectric layer and over the fin structure 205. The sacrificial gate electrode layer includes silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range between about 100 nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate electrode layer can be deposited using CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes.

[0061] Subsequently, a liner layer and a mask layer are formed over the sacrificial gate electrode layer. The liner layer may include silicon nitride. The mask layer may include silicon oxide. Next, a patterning operation is performed on the mask layer, the liner layer, the sacrificial gate electrode layer, and the sacrificial gate dielectric layer to form a sacrificial gate structure.

[0062] After forming the sacrificial gate structure 250', a sidewall spacer 270 is formed by blanket deposition of an insulating material followed by anisotropic etching to remove the insulating material from the horizontal surface. The sidewall spacer 270 may have a thickness in a range between about 2 nm and about 10 nm. In some embodiments, the insulating material of the sidewall spacer 270 is a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN and combinations thereof.

[0063] In operation 406, if Fig.11 , FIG. 11A to FIG. 11C and Fig.12 , FIG. 12A to FIG. 12C As shown, source / drain regions 256, 258, 260, 262, 264 are formed. Fig.11 is a schematic perspective view of the semiconductor device 10 . FIG. 11A to FIG. 11C It is along Fig.11 Schematic cross-sectional view of the semiconductor device 10 along lines AA, BB, and CC in FIG. Fig.12 is a schematic perspective view of the semiconductor device 10 . FIG. 12A to FIG. 12C It is along Fig.12 Schematic cross-sectional view of the semiconductor device 10 along lines AA, BB, and CC in FIG.

[0064] like Fig.11 , FIG. 11A to FIG. 11CAs shown, recesses are formed in the fin structures 206, 208, 210, 212, and 214 between the sacrificial gate structures 250'. The recesses may be formed by etching the fin structures 206, 208, 210, 212, and 214. In some embodiments, the fin structures 206, 208, 210, 212, and 214 may be etched such that after etching, the upper surfaces of the fin structures 206, 208, 210, 212, and 214 are lower than the upper surface of the STI 240. In other embodiments, the fin structures 206, 208, 210, 212, and 214 may be etched such that the upper surfaces of the fin structures 206, 208, 210, 212, and 214 still protrude from the upper surface of the STI 240 after etching. Portions of the semiconductor stack 130 are etched away from the fin structures 206, 208, 210, 212, and 214.

[0065] Then, if Fig.11 and Fig. 11C As shown, an internal spacer 272 is formed on the exposed end of the first semiconductor layer 132 under the sacrificial gate structure 250'. The internal spacer 272 is formed on the exposed end of the first semiconductor layer 132 under the sacrificial gate structure 250'. First, the first semiconductor layer 132 exposed to the groove is horizontally etched along the X direction to form a cavity. In some embodiments, the first semiconductor layer 132 can be selectively etched by using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP) or potassium hydroxide (KOH) solution. In some embodiments, the etching amount of the first semiconductor layer 132 is in the range between about 2nm and about 10nm along the X direction. After the cavity is formed in the first semiconductor layer 132, the internal spacer 272 can be formed in the cavity by conformal deposition and then partially removing the insulating layer. The insulating layer can be formed by ALD or any other suitable method. In some embodiments, the insulating layer may include one of silicon nitride (SiN) and silicon oxide (SiO2) and have a thickness in the range of about 0.5 nm to about 3.0 nm. A subsequent etching process removes most of the insulating layer except for the interior of the cavity, resulting in an internal spacer 272.

[0066] like Fig.12 , FIG. 12A to FIG. 12CAs shown, epitaxial collector regions 262, 264, epitaxial base regions 258, 260, and epitaxial emitter region 256 are formed in the recesses and over the fin structures 212, 214, 210, 208, and 206. The epitaxial collector regions 262, 264, epitaxial base regions 258, 260, and epitaxial emitter region 256 are formed from the fin structures 212, 214, 210, 208, and 206 such that the sacrificial gate structure 250' is disposed between respective adjacent pairs of epitaxial collector regions 262, 264, epitaxial base regions 258, 260, and epitaxial emitter region 256.

[0067] In some embodiments, epitaxial collector regions 262, 264 and epitaxial emitter region 256 are formed in a first epitaxial process because they share the same conductivity, and epitaxial base regions 258, 260 are formed in a second epitaxial process because they share the same conductivity, although the first epitaxial process or the second epitaxial process may be performed first.

[0068] When forming the epitaxial collector regions 262, 264 and the epitaxial emitter region 256, a mask may be formed over the structure and patterned to protect areas where the epitaxial collector regions 262, 264 and the epitaxial emitter region 256 are not formed, including areas of the epitaxial base regions 258, 260. The epitaxial collector regions 262, 264 and the epitaxial emitter region 256 may then be selectively grown from the corresponding fin structures. The epitaxial collector regions 262, 264 may be grown from the fins 212 and 214, and the epitaxial emitter region 256 may be grown from the fin 206. In some embodiments, the epitaxial emitter region 256 and the epitaxial collector regions 262, 264 are silicon germanium (SiGe) epitaxially grown by a CVD process and may be in-situ doped with p-type dopants during the epitaxial process. In some embodiments, the epitaxial emitter region 256 and the epitaxial collector regions 262, 264 may be doped with p-type dopants subsequently or using an implantation process. The p-type dopant used for epitaxial collector regions 262 , 264 and epitaxial emitter region 256 may be any of the p-type impurities (or dopants) discussed previously.

[0069] When forming the epitaxial base regions 258, 260, a mask may be formed over the structure and patterned to protect areas where the epitaxial base regions 258, 260 are not formed, including the epitaxial collector regions 262, 264 and the epitaxial emitter region 256. The epitaxial base regions 258, 260 may then be selectively grown from the fin structures 208 and 210. In some embodiments, the epitaxial base regions 258, 260 are silicon (Si), silicon phosphide (SiP), or silicon carbide (SiC) epitaxially grown by a CVD process and may be in-situ doped with n-type dopants during the epitaxial process. In some embodiments, the epitaxial base regions 258, 260 may be doped with n-type dopants subsequently or using an implantation process. The n-type dopant for the epitaxial base regions 258, 260 may be any of the n-type impurities (or dopants) discussed previously.

[0070] As a result of the epitaxial process used to form epitaxial collector regions 262, 264, epitaxial base regions 258, 260, and epitaxial emitter region 256, the upper surfaces of these epitaxial regions have facets that extend laterally outward beyond the sidewalls of fin structures 206, 208, 210, 212, and 214. In some embodiments, these facets result in adjacent epitaxial regions from separate fin structures being merged, such as Fig.12 Shown are epitaxial collector regions 262, 264, epitaxial base regions 258, 260, and epitaxial emitter region 256. In other embodiments, adjacent epitaxial regions from separate fin structures may remain separated after the epitaxial growth process.

[0071] After growing the epitaxial collector regions 262, 264, the epitaxial base regions 258, 260, and the epitaxial emitter region 256, the dopant concentration for each of the p-type and n-type dopants in the epitaxial regions may be about 10 19 cm -3 and about 10 21 cm -3 Annealing may be performed in one or more annealing processes to activate the dopants.

[0072] In operation 408, Fig.13 and FIG. 13A to FIG. 13C As shown, a first inter-layer dielectric (ILD) 88 is deposited over the epitaxial regions 256 , 258 , 260 , 262 , 264 . Fig.13 is a schematic perspective view of the semiconductor device 10 . FIG. 13A to FIG. 13C It is along Fig.13 Schematic cross-sectional view of the semiconductor device 10 along lines AA, BB, and CC in FIG.

[0073] The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial collector regions 262, 264, the epitaxial base regions 258, 260, the epitaxial emitter regions 256, the STI regions 240, and the sidewall gate spacers 272. The CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etching rate different from that of the material of the first ILD 88 above. A planarization process, such as CMP, may be performed to make the top surface of the first ILD 88 flush with the top surface of the sacrificial gate structure 250'.

[0074] In operation 410, as Fig.13 and FIG. 13A to FIG. 13C As shown, the sacrificial gate structure 250' is removed and a replacement gate structure 250 is formed. The replacement gate structure 250 may be formed by removing the sacrificial gate structure 250', the semiconductor layer 132, and then depositing a gate dielectric layer and a gate electrode layer.

[0075] First, the sacrificial gate structure 250 ′ and the underlying fin structure 205 are removed using a suitable etching method. The first semiconductor layer 132 is removed to expose the semiconductor layer 134 .

[0076] A replacement gate dielectric layer is then conformally deposited on exposed surfaces such as the semiconductor layer 134, the emitter terminal 106, the base terminals 108, 110, the collector terminals 112, 114, the sidewall spacers 270, and the internal spacers 272. The replacement gate dielectric layer can be silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the replacement gate dielectric layer can include a high-k dielectric material, and in these embodiments, the replacement gate dielectric layer can have a k value greater than about 7.0 and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the replacement gate dielectric layer can include molecular beam deposition (MBD), ALD, PECVD, etc.

[0077] A replacement gate electrode layer is deposited over the gate dielectric layer and fills the remainder of the recess. The replacement gate electrode may include polysilicon or a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. The replacement gate electrode may include any number of liner layers, any number of work function adjustment layers, and filler materials. After the recess is filled, a planarization process such as CMP may be performed to remove excess portions of the material of the replacement gate dielectric layer and the replacement gate electrode that are located above the top surface of the ILD 88.

[0078] In operation 410, as Fig.14 and FIG. 14A to FIG. 14C As shown, a mask layer 91 is deposited over the replacement gate structure 250 , and a dielectric isolation pattern is formed in the mask layer 91 . Fig.14 is a schematic perspective view of the semiconductor device 10 . FIG. 14A to FIG. 14C It is along Fig.14 Schematic cross-sectional view of the semiconductor device 10 along lines AA, BB, and CC in FIG.

[0079] After operation 412, the replacement gate structure 250 is a continuous structure across the terminals 212, 210, 206, 208, 214. The terminals 212, 210, 206, 208, 214 may be electrically coupled together through a gate electrode layer in the gate structure 250. A cutting process may be performed to cut the continuous gate structure 250 into a plurality of portions to isolate the terminals 212, 210, 206, 208, 214. In some embodiments, a dielectric isolation process may be performed to cut the replacement gate structure 250 into a plurality of portions.

[0080] In some embodiments, a mask layer 91 may be deposited over the ILD 88 and over the top surface of the continuous gate structure 250. The mask layer 91 is then patterned using an acceptable photolithography technique to form an opening 92, thereby exposing a portion of the continuous gate structure 250. In some embodiments, the opening 92 may be a continuous opening along the x-direction or perpendicular to the gate structure 250. The opening 92 may be disposed between the collector terminal 212 / 214 and the base terminal 208 / 210. Optionally, in operation 412, additional openings may be formed according to the circuit design or to prevent pattern loading during the process. For example, additional openings may be formed between the base terminals 208 / 210 to avoid pattern loading, or additional openings may be formed on the boundaries of the active area (e.g., outside the collector terminals 212, 214).

[0081] In some embodiments, Fig.14As shown, the openings 92 extend across the entire length of the BJTs 12, 14. In other embodiments, the openings 92 may be segmented along the x-direction, with each opening 92 extending across several gate structures 250. For example, each opening may extend across a separate gate structure 250. In some embodiments, the cut pattern in the mask layer 91 may include a combination of openings having various lengths.

[0082] In operation 414, as Fig.15 and FIG. 15A to FIG. 15C As shown, a dielectric isolation structure 252 is formed. Fig.15 is a schematic perspective view of the semiconductor device 10 . FIG. 15A to FIG. 15C It is along Fig.15 Schematic cross-sectional view of the semiconductor device 10 along lines AA, BB, and CC in FIG.

[0083] A dielectric isolation structure 252 is formed using a cut pattern formed in mask layer 91. A series of etching processes may be performed to remove material from the exposed portion of gate structure 250. In some embodiments, other materials exposed to opening 92, such as ILD 88, CESL 87, and any epitaxial base regions 258 / 260 and epitaxial collector regions 262 / 264, may also be removed. The etching process creates a trench 94 on gate structure 250. In some embodiments, the bottom of trench 94 terminates within STI 240. That is, trench 94 does not reach the underlying p-well or n-well.

[0084] The trench 94 may be formed in one or more layers of insulating material using any acceptable technique. In some embodiments, the insulating material may include a dielectric material such as silicon oxide, silicon nitride, PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, such as CVD and PECVD. A planarization process is then performed to expose the remaining gate structure 250.

[0085] The dielectric isolation structure 252 divides the continuous gate structure 250 into a plurality of portions, such as a gate portion 330 over the emitter terminal 106 and the base terminals 108, 110, and gate regions 310, 350 over the collector terminals 112, 114. The insulating material of the dielectric isolation structure 252 is in contact with the gate portions 330, 310, 350. The dielectric isolation structure 252 is also in contact with the first IDL 88, the ECSL 87, and the STI region 240.

[0086] As discussed above, the dielectric isolation structure 252 extends into the STI region 240. In some embodiments, the bottom surface 252b of the dielectric isolation structure 252 is disposed in the STI region 240. The dielectric isolation structure 252 does not extend into the well region below the STI region 240. The dielectric isolation structure 252 may have a depth D1 along the z-direction. In some embodiments, the depth D1 is in a range between about 120 nm and 200 nm. The bottom surface 252b and the bottom surface 240b of the STI region 240 are separated by a distance D2. In some embodiments, the distance D2 is in a range between about 5 nm and about 30 nm. The dielectric isolation structure 252 extends into the STI region 240 to ensure that the dielectric isolation structure 252 disconnects the gate structure portion on the opposite side.

[0087] Positioning the dielectric isolation structure 252 above the bottom surface 240b of the STI region 240 prevents degradation of the Nf (forward current emission coefficient) of the BJT. It has been observed that Nf_ie increases with the depth of the dielectric isolation structure 252. Inclusion of dielectric materials such as SiN in the well portion of the terminal can lead to degradation of Nf_ie.

[0088] The introduction of the dielectric isolation structure reduces the current leakage Ig from the emitter terminal to the base terminal. By using a thinner dielectric isolation structure in the gate structure, ie, positioning the dielectric isolation structure in the STI region, the BJT according to the present disclosure prevents dielectric isolation induced charges in the terminals.

[0089] When a BJT is formed using a dielectric isolation process, the voltage of the gate structure at the emitter terminal shows a strong influence on the BJT performance. When the gate structure at the emitter terminal is connected to the epitaxial region, the gate structure accumulates a large amount of charge, resulting in Ib (base current) recombination. Figure 2 and Fig.15 As shown, to minimize gate charge effects, the gate electrode of the emitter terminal may be connected to the base terminal, which may be achieved by connecting the gate structure 250 between the emitter terminal 106 and the base terminals 110 , 108 .

[0090] Alternatively, if Fig.17 and FIG. 19A to FIG. 19C As discussed, when a dielectric isolation structure is provided between the emitter terminal 106 and the base terminals 108 / 110 , the gate electrode above the emitter terminal 106 may be connected to the base terminal 108 / 110 via a connection at an interconnect layer, such as the M1 layer.

[0091] In operation 416, if FIG. 16A to FIG. 16CAs shown, contact features are formed to provide electrical connections to the gate structure and the epitaxial region. Conductive features are formed to connect the epitaxial region and the gate structure portion and to route the BJT 10. In some embodiments, gate contacts 452, 454, 458, and 460 and terminal contacts 422, 424, 426, 428, and 430 are formed through one or more ILD layers.

[0092] For example, a second ILD layer may be deposited over the first ILD layer 88. An opening for a terminal contact may be formed through the first ILD and the second ILD, and an opening for a gate contact may be formed through the second ILD. Acceptable photolithography and etching techniques may be used to form the opening. A liner (such as a diffusion barrier, an adhesive layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the ILD layer. The remaining liner and conductive material form terminal contacts 422, 424, 426, 428, and 430 and gate contacts 452, 454, 458, and 460. An annealing process may be performed to form silicide at interfaces between epitaxial collector regions 262 , 264 , epitaxial base regions 258 , 260 , and epitaxial emitter region 256 and corresponding terminal contacts.

[0093] Terminal contacts 422 and 430 are physically and electrically coupled to respective epitaxial collector regions 262, 264, terminal contacts 424 and 428 are physically and electrically coupled to respective epitaxial base regions 258, 260, and terminal contact 426 is physically and electrically coupled to epitaxial emitter region 256. Gate contacts 452, 454, 458, and 460 are physically and electrically coupled to gate structure portions 310, 330, and 350. Terminal contacts 422, 424, 426, 428, and 430 and gate contacts 452, 454, 458, and 460 may be formed in different processes, or may be formed in the same process.

[0094] The metallization layer includes a third ILD and connection components 512, 514, 516, 518, and 520. In some embodiments, the third ILD is a flowable film formed by a flowable CVD method. In some embodiments, the third ILD is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD and PECVD. In some embodiments, the connection components 512, 514, 516, 518, and 520 couple the gate contacts 452, 454, 458, and 460 to each other, respectively.

[0095] Fig.17 , Fig.18 , 18A to 18C and FIG. 19A to FIG. 19C A BJT device 10 a is shown in accordance with some embodiments. Fig.17 is a schematic perspective view of the BJT device 10 a after operation 414 when forming the dielectric isolation structures 252 , 254 . Fig.18 is a schematic diagram of the BTJ device 10 a with the dielectric material removed to illustrate the gate structure 250 and the dielectric isolation structures 252 , 254 . 18A to 18C Schematically shown are details of dielectric isolation structures 252, 254 in the BJT device 10a. The BJT device 10a is similar to the BJT device 10 described above, except that the BJT device 10a includes an additional dielectric isolation structure 254 disposed between the emitter terminal 106 and the base terminals 110, 112. The additional dielectric isolation structure 254 in the BJT device 10a reduces pattern loading during processing. The dielectric isolation structures 254 and 252 divide the continuous gate structure 250 into gate structure portions 310, 320, 330, 340, 350 corresponding to the terminals 112, 108, 106, 110, 114.

[0096] FIG. 19A to FIG. 19C The connection features of the BTJ device 10a are schematically shown. Gate contacts 452, 454, 456, 458, and 460 and terminal contacts 422, 424, 426, 428, and 430 are formed through one or more ILD layers.

[0097] Terminal contacts 422 and 430 are physically and electrically coupled to respective epitaxial collector regions 262, 264, terminal contacts 424 and 428 are physically and electrically coupled to respective epitaxial base regions 258, 260, and terminal contact 426 is physically and electrically coupled to epitaxial emitter region 256. Gate contacts 452, 454, 456, 458, and 460 are physically and electrically coupled to gate structure portions 310, 320, 330, 340, and 350. Terminal contacts 422, 424, 426, 428, and 430 and gate contacts 452, 454, 456, 458, and 460 may be formed in different processes, or may be formed in the same process.

[0098] In some embodiments, connection features 512, 514, 516, 518, and 520 couple terminal contacts 422, 424, 426, 428, and 430 to each other, respectively. Thus, in some embodiments, connection features 512, 514, 516, 518, and 520 may respectively electrically couple gate contact 452 to terminal contact 422, gate contact 454 to terminal contact 424, gate contact 456 to terminal contact 426, gate contact 458 to terminal contact 428, and gate contact 460 to terminal contact 430. In other words, the gate electrodes of each gate structure portion 310-350 may be coupled to their adjacent epitaxial regions. For example, connection feature 512 may couple gate contact 452 with terminal contact 422, thereby coupling epitaxial collector region 262 on fin structure 212 with gate structure portion 310. Similarly, connection feature 514 may couple epitaxial base region 258 on fin structure 208 with gate structure portion 320, connection feature 516 may couple epitaxial emitter region 256 on fin structure 206 with gate structure portion 330, connection feature 518 may couple epitaxial base region 260 on fin structure 210 with gate structure portion 340, and connection feature 520 may couple epitaxial collector region 264 on fin structure 214 with gate structure portion 350.

[0099] BJT device 10a further includes connection feature 616 formed in a metallization layer over connection features 512, 514, 516, 518, and 520. Connection feature 616 couples connection features 516 and 518, thereby connecting gate structure portion 330 and gate structure portion 320. Connection feature 616 connects gate structure portion 330 of emitter terminal 108 with base terminal 108.

[0100] Fig. 20 and FIG. 21A to FIG. 21C A BTJ device 10b is schematically illustrated in accordance with some embodiments. The BTJ device 10b is similar to the BTJ device 10a, except that the BTJ device 10b includes segmented dielectric isolation structures 252s and 254s. The dielectric isolation structures 252s and 254s may be formed using a pattern having openings 93 aligned with the gate structure 250. Each opening 93 may extend across a single gate structure 250, and as a result, the dielectric isolation structures 252s, 254s do not extend into the epitaxial region.

[0101] Although the following description corresponds to the formation of a specific arrangement for a p-type BJT (PNP BJT or pBJT), it should be understood that the following process can be used to form variations of the above arrangement while remaining within the scope of the embodiments. For example, more or less gate structures, more or less fins, lengths or widths, spacings, polarities (types), and dopant concentrations, etc. can be adjusted as needed.

[0102] Embodiments advantageously use a GAA or FinFET process to form a BJT device. The BJT according to the present disclosure includes a dielectric isolation structure to isolate the gate structure of the terminal. The use of a dielectric isolation structure allows the BJT to be manufactured together with a logic device (such as a GAA logic device). The use of a dielectric isolation structure can reduce emitter to base current leakage. The BJT according to the present disclosure connects the gate electrode of the emitter terminal to the base terminal, thereby minimizing the metal gate charge effect. The dielectric isolation structure according to the present disclosure terminates in the STI region, preventing the deep dielectric isolation structure from causing substrate fixed charge.

[0103] It will be appreciated that not all advantages are necessarily discussed herein, that no particular advantage is required of all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0104] Some embodiments of the present disclosure relate to a device, which includes: a first well, located in a semiconductor substrate, and having a first type of dopant; a second well, located in the semiconductor substrate, and having a second type of dopant different from the first type, wherein the first well intersects the second well; a first transistor, having a first epitaxial region located above the first well, wherein the first epitaxial region has the second type of dopant; a second transistor, having a second epitaxial region located above the first well, wherein the second epitaxial region has the first type of dopant; a third transistor, having a third epitaxial region located above the second well, wherein the third epitaxial region has the second type of dopant, wherein the second epitaxial region is arranged between the first epitaxial region and the third epitaxial region; and a first dielectric isolation structure arranged between the second transistor and the third transistor.

[0105] In some embodiments, the first transistor includes a first gate structure disposed adjacent to the first epitaxial region, the second transistor includes a second gate structure disposed adjacent to the second epitaxial region, and the third transistor includes a third gate structure disposed adjacent to the third epitaxial region, and the first dielectric isolation structure is disposed between the second gate structure and the third gate structure.

[0106] In some embodiments, the first transistor includes a first gate structure disposed adjacent to the first epitaxial region, the second transistor includes a second gate structure disposed adjacent to the second epitaxial region, and the third transistor includes a third gate structure disposed adjacent to the third epitaxial region, and the first dielectric isolation structure is disposed between the second gate structure and the third gate structure, wherein the first dielectric isolation structure extends across the second transistor and the third transistor.

[0107] In some embodiments, the first transistor includes a first gate structure arranged adjacent to the first epitaxial region, the second transistor includes a second gate structure arranged adjacent to the second epitaxial region, and the third transistor includes a third gate structure arranged adjacent to the third epitaxial region, and the first dielectric isolation structure is arranged between the second gate structure and the third gate structure, and the semiconductor device also includes: a first fin structure arranged above the first well, wherein the first gate structure is formed above the first fin structure; a second fin structure arranged above the first well, wherein the second gate structure is formed above the second fin structure; a third fin structure arranged above the second well, wherein the third gate structure is formed above the third fin structure; and an isolation region arranged above the first well and the second well and around the first fin structure, the second fin structure and the third fin structure, wherein a bottom surface of the first dielectric isolation structure is located within the isolation region.

[0108] In some embodiments, the first transistor includes a first gate structure disposed adjacent to the first epitaxial region, the second transistor includes a second gate structure disposed adjacent to the second epitaxial region, and the third transistor includes a third gate structure disposed adjacent to the third epitaxial region, and the first dielectric isolation structure is disposed between the second gate structure and the third gate structure, wherein the first gate structure, the second gate structure, and the third gate structure include multiple channel layers.

[0109] In some embodiments, the first transistor includes a first gate structure disposed adjacent to the first epitaxial region, the second transistor includes a second gate structure disposed adjacent to the second epitaxial region, and the third transistor includes a third gate structure disposed adjacent to the third epitaxial region, and the first dielectric isolation structure is disposed between the second gate structure and the third gate structure, wherein the first gate structure, the second gate structure, and the third gate structure include a fin field effect transistor channel.

[0110] In some embodiments, the first transistor includes a first gate structure disposed adjacent to the first epitaxial region, the second transistor includes a second gate structure disposed adjacent to the second epitaxial region, and the third transistor includes a third gate structure disposed adjacent to the third epitaxial region, and the first dielectric isolation structure is disposed between the second gate structure and the third gate structure, wherein the first gate structure and the second gate structure are connected.

[0111] In some embodiments, the semiconductor device further includes a second dielectric isolation structure disposed between the first transistor and the second transistor.

[0112] Some embodiments of the present disclosure relate to a device, comprising: a plurality of fin structures extending along a first direction on a substrate, wherein the plurality of fin structures include a first fin structure, a second fin structure, and a third fin structure; a first epitaxial region located above the first fin structure, the first epitaxial region providing an emitter terminal for a first bipolar junction transistor (BJT) and a second BJT; a second epitaxial region located above the second fin structure and providing a base terminal for the first BJT; a third epitaxial region located above the third fin structure and providing a collector terminal for the first BJT; a gate structure arranged across the plurality of fin structures along the second direction; and a first dielectric isolation structure arranged between the second fin structure and the third fin structure and across the gate structure.

[0113] In some embodiments, the semiconductor device further includes: a first terminal contact in contact with the first epitaxial region, wherein the first terminal contacts are electrically connected to each other.

[0114] In some embodiments, the semiconductor device also includes: a first terminal contact, contacting the first epitaxial region, wherein the first terminal contacts are electrically connected to each other; a second terminal contact, contacting the second epitaxial region, wherein the second terminal contacts are electrically connected to each other and to the first gate portion.

[0115] In some embodiments, the semiconductor device also includes: a first terminal contact, contacting the first epitaxial region, wherein the first terminal contacts are electrically connected to each other; a second terminal contact, contacting the second epitaxial region, wherein the second terminal contacts are electrically connected to each other and to the first gate portion; and a third terminal contact, contacting the third epitaxial region, wherein the third terminal contacts are electrically connected to each other and to the second gate portion.

[0116] In some embodiments, the semiconductor device also includes: a first terminal contact, contacting the first epitaxial region, wherein the first terminal contacts are electrically connected to each other; a second terminal contact, contacting the second epitaxial region, wherein the second terminal contacts are electrically connected to each other and to the first gate portion; a third terminal contact, contacting the third epitaxial region, wherein the third terminal contacts are electrically connected to each other and to the second gate portion; and a second gate structure, arranged across the multiple fin structures along the second direction, wherein a first dielectric isolation structure divides the second gate structure into a third gate portion arranged above the first fin structure and the second fin structure and a fourth gate portion arranged above the third fin structure.

[0117] In some embodiments, the semiconductor device also includes: a first terminal contact, contacting the first epitaxial region, wherein the first terminal contacts are electrically connected to each other; a second terminal contact, contacting the second epitaxial region, wherein the second terminal contacts are electrically connected to each other and to the first gate portion; a third terminal contact, contacting the third epitaxial region, wherein the third terminal contacts are electrically connected to each other and to the second gate portion; a second gate structure, arranged across the multiple fin structures along the second direction, wherein a first dielectric isolation structure divides the second gate structure into a third gate portion arranged above the first fin structure and the second fin structure and a fourth gate portion arranged above the third fin structure; and a first gate contact component, electrically connecting the first gate portion and the third gate portion.

[0118] In some embodiments, the semiconductor device also includes: a first terminal contact, contacting the first epitaxial region, wherein the first terminal contacts are electrically connected to each other; a second terminal contact, contacting the second epitaxial region, wherein the second terminal contacts are electrically connected to each other and to the first gate portion; a third terminal contact, contacting the third epitaxial region, wherein the third terminal contacts are electrically connected to each other and to the second gate portion; a second gate structure, arranged across the multiple fin structures along the second direction, wherein a first dielectric isolation structure divides the second gate structure into a third gate portion arranged above the first fin structure and the second fin structure and a fourth gate portion arranged above the third fin structure; a first gate contact component, electrically connecting the first gate portion and the third gate portion, wherein the fourth gate portion is electrically connected to the second gate portion.

[0119] Some embodiments of the present disclosure relate to a method, comprising: forming a first well, a second well, and a third well in a substrate, wherein the first well and the third well are doped with a first type of dopant, the second well is doped with a second type of dopant, and the second well is arranged between the first well and the third well along a first direction and intersects with the first well and the third well; forming a plurality of fin structures above the first well, the second well, and the third well, wherein the plurality of fin structures extend along the first direction; forming a dielectric material around lower portions of the plurality of fin structures; forming a plurality of sacrificial gate structures, the plurality of sacrificial gate structures are along a second direction and span the plurality of fin structures; recessing a plurality of fin structures exposed by the plurality of sacrificial gate structures; forming epitaxial regions from the plurality of fin structures; forming a replacement gate structure; and forming a dielectric isolation structure between the epitaxial regions.

[0120] In some embodiments, forming the epitaxial region includes: forming an epitaxial emitter region above the first well; forming a first epitaxial base region above the first well; forming a second epitaxial base region above the first well, wherein the first epitaxial base region and the second epitaxial base region are located on opposite sides of the epitaxial emitter region; forming a first epitaxial collector region above the second well; and forming a second epitaxial collector region above the third well.

[0121] In some embodiments, forming the epitaxial region includes: forming an epitaxial emitter region above the first well; forming a first epitaxial base region above the first well; forming a second epitaxial base region above the first well, wherein the first epitaxial base region and the second epitaxial base region are located on opposite sides of the epitaxial emitter region; forming a first epitaxial collector region above the second well; and forming a second epitaxial collector region above the third well, wherein forming the dielectric isolation structure includes: forming a first metal gate structure between the first epitaxial collector region and the first epitaxial base region, and forming a second metal gate structure between the second epitaxial collector region and the second epitaxial base region.

[0122] In some embodiments, forming the epitaxial region includes: forming an epitaxial emitter region above the first well; forming a first epitaxial base region above the first well; forming a second epitaxial base region above the first well, wherein the first epitaxial base region and the second epitaxial base region are located on opposite sides of the epitaxial emitter region; forming a first epitaxial collector region above the second well; and forming a second epitaxial collector region above the third well, wherein forming the dielectric isolation structure includes: forming a first metal gate structure between the first epitaxial collector region and the first epitaxial base region, and forming a second metal gate structure between the second epitaxial collector region and the second epitaxial base region, wherein forming the dielectric isolation structure also includes: forming a third metal gate structure between the epitaxial emitter region and the first epitaxial base region; and forming a fourth metal gate structure between the second epitaxial collector region and the epitaxial emitter region.

[0123] In some embodiments, forming the epitaxial region includes: forming an epitaxial emitter region above the first well; forming a first epitaxial base region above the first well; forming a second epitaxial base region above the first well, wherein the first epitaxial base region and the second epitaxial base region are located on opposite sides of the epitaxial emitter region; forming a first epitaxial collector region above the second well; and forming a second epitaxial collector region above the third well, wherein forming the dielectric isolation structure includes: forming a first metal gate structure between the first epitaxial collector region and the first epitaxial base region, and forming a second metal gate structure between the second epitaxial collector region and the second epitaxial base region, wherein forming the dielectric isolation structure also includes: forming a third metal gate structure between the epitaxial emitter region and the first epitaxial base region; and forming a fourth metal gate structure between the second epitaxial collector region and the epitaxial emitter region, wherein the bottom surface of the dielectric isolation structure is located in the shallow trench isolation region.

[0124] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A first well, located in the semiconductor substrate, having a first type of dopant; a second well located in the semiconductor substrate and having a second type of dopant different from the first type, wherein the first well intersects the second well; a first transistor having a first epitaxial region located above the first well, wherein the first epitaxial region has a dopant of the second type; a second transistor having a second epitaxial region located above the first well, wherein the second epitaxial region has a dopant of the first type; a third transistor having a third epitaxial region located above the second well, wherein the third epitaxial region has dopants of the second type, wherein the second epitaxial region is disposed between the first epitaxial region and the third epitaxial region; and A first dielectric isolation structure is disposed between the second transistor and the third transistor.

2. The semiconductor device according to claim 1, wherein The first transistor includes a first gate structure disposed adjacent to the first epitaxial region, the second transistor includes a second gate structure disposed adjacent to the second epitaxial region, and the third transistor includes a third gate structure disposed adjacent to the third epitaxial region, and the first dielectric isolation structure is disposed between the second gate structure and the third gate structure.

3. The semiconductor device according to claim 2, wherein: The first dielectric isolation structure extends across the second transistor and the third transistor.

4. The semiconductor device according to claim 2, further comprising: a first fin structure disposed above the first well, wherein the first gate structure is formed above the first fin structure; a second fin structure disposed above the first well, wherein the second gate structure is formed above the second fin structure; a third fin structure disposed above the second well, wherein the third gate structure is formed above the third fin structure; and An isolation region is disposed above the first well and the second well and around the first fin structure, the second fin structure and the third fin structure, wherein a bottom surface of the first dielectric isolation structure is located within the isolation region.

5. The semiconductor device according to claim 2, wherein: The first gate structure, the second gate structure, and the third gate structure include a plurality of channel layers.

6. The semiconductor device according to claim 2, wherein: The first gate structure, the second gate structure, and the third gate structure include FinFET channels.

7. The semiconductor device according to claim 2, wherein: The first gate structure is connected to the second gate structure. 8 . The semiconductor device according to claim 1 , further comprising a second dielectric isolation structure disposed between the first transistor and the second transistor.

9. A semiconductor device comprising: A plurality of fin structures extending along a first direction on the substrate, wherein the plurality of fin structures include a first fin structure, a second fin structure and a third fin structure; a first epitaxial region located above the first fin structure, the first epitaxial region providing emitter terminals for a first bipolar junction transistor (BJT) and a second bipolar junction transistor; a second epitaxial region, located above the second fin structure and providing a base terminal for the first bipolar junction transistor; a third epitaxial region located above the third fin structure and providing a collector terminal for the first bipolar junction transistor; A first gate structure is disposed across the plurality of fin structures along a second direction; and A first dielectric isolation structure is arranged between the second fin structure and the third fin structure and spans the first gate structure, wherein the first dielectric isolation structure divides the first gate structure into a first gate portion arranged above the first fin structure and the second fin structure and a second gate portion arranged above the third fin structure.

10. A method of forming a semiconductor device, comprising: Forming a first well, a second well and a third well in a substrate, wherein the first well and the third well are doped with a first type of dopant, the second well is doped with a second type of dopant, and the second well is disposed between the first well and the third well along a first direction and intersects with the first well and the third well; forming a plurality of fin structures above the first well, the second well, and the third well, wherein the plurality of fin structures extend along the first direction; forming a dielectric material around lower portions of the plurality of fin structures; forming a plurality of sacrificial gate structures along a second direction and across the plurality of fin structures; recessing the plurality of fin structures exposed by the plurality of sacrificial gate structures; forming an epitaxial region from the plurality of fin structures; forming a replacement gate structure; and A dielectric isolation structure is formed between the epitaxial regions.

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