Three-dimensional semiconductor device

Abstract

Disclosed is a three-dimensional semiconductor device, comprising: a substrate comprising a first region and a second region; a first active portion on the first region and including a first lower channel pattern and a first lower source / drain pattern; a second active portion on the first active portion and including a first upper channel pattern and a first upper source / drain pattern; a third active portion on the second region and including a second lower channel pattern and a second lower source / drain pattern; a fourth active portion on the third active portion and including a second upper channel pattern and a second upper source / drain pattern; and a gate electrode on the first and second lower channel patterns and the first and second upper channel patterns. A first width of the first lower channel pattern in the first direction is greater than a second width of the second lower channel pattern in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0147193 filed on October 30, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a three-dimensional semiconductor device, and more particularly, to a three-dimensional semiconductor device including a field effect transistor. Background Art

[0004] A semiconductor device includes an integrated circuit including a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rules of semiconductor devices are gradually reduced, the size of MOSFET is also reduced. The reduction of MOSFET may deteriorate the operating characteristics of the semiconductor device. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices with excellent performance while overcoming the limitations caused by the high integration of semiconductor devices. Summary of the invention

[0005] Some embodiments of the inventive concept provide a three-dimensional semiconductor device having increased integration and improved electrical characteristics.

[0006] According to some embodiments of the present inventive concept, a three-dimensional semiconductor device may include: a substrate including a first region and a second region; a first active portion on the first region, wherein the first active portion includes a first lower channel pattern and a first lower source / drain pattern connected to the first lower channel pattern; a second active portion on the first active portion, wherein the second active portion includes a first upper channel pattern and a first upper source / drain pattern connected to the first upper channel pattern; a third active portion on the second region, wherein the third active portion includes a second lower channel pattern and a second lower source / drain pattern connected to the second lower channel pattern; a fourth active portion on the third active portion, wherein the fourth active portion includes a second upper channel pattern and a second upper source / drain pattern connected to the second upper channel pattern; and a gate electrode on the first lower channel pattern and the second lower channel pattern and the first upper channel pattern and the second upper channel pattern. A first width of the first lower channel pattern in the first direction may be greater than a second width of the second lower channel pattern in the first direction.

[0007] According to some embodiments of the present inventive concept, a three-dimensional semiconductor device may include: a first active portion on a substrate, wherein the first active portion includes a first lower channel pattern, a second lower channel pattern horizontally spaced apart from the first lower channel pattern, a first lower source / drain pattern connected to the first lower channel pattern, and a second lower source / drain pattern connected to the second lower channel pattern; a second active portion on the first active portion, wherein the second active portion includes a first upper channel pattern, a second upper channel pattern horizontally spaced apart from the first upper channel pattern, a first upper source / drain pattern connected to the first upper channel pattern, and a second upper source / drain pattern connected to the second upper channel pattern; a gate electrode on the first lower channel pattern and the second lower channel pattern and the first upper channel pattern and the second upper channel pattern; a lower active contact electrically connected to the first lower source / drain pattern and the second lower source / drain pattern; and a first upper active contact electrically connected to the first upper source / drain pattern and the second upper source / drain pattern. The first upper active contact may have a strip shape extending in a first direction. The width of the first upper active contact in the first direction may be greater than a maximum width of each of the first upper source / drain pattern and the second upper source / drain pattern.

[0008] According to some embodiments of the present invention, a three-dimensional semiconductor device may include: a substrate including a first region, a second region, and a third region; a first single-height unit on the first region, wherein the first single-height unit includes a first active portion and a second active portion stacked on the first active portion; a plurality of second single-height units on the second region and a dummy region between the plurality of second single-height units, wherein each of the plurality of second single-height units includes a third active portion and a fourth active portion stacked on the third active portion; a double-height unit on the third region, wherein the double-height unit includes a fifth active portion, a sixth active portion stacked on the fifth active portion, a seventh active portion, and an eighth active portion stacked on the seventh active portion; a plurality of first gate electrodes on the first active portion and the second active portion; on the active portion, wherein each of the plurality of first gate electrodes has a strip extending in the first direction; on the first active contact portion, between the plurality of first gate electrodes, wherein the first active contact portion has a strip extending in the first direction; on the third active portion and the fourth active portion, wherein each of the plurality of second gate electrodes has a strip extending in the first direction; on the second active contact portion, between the plurality of second gate electrodes, wherein the second active contact portion has a strip extending in the first direction; on the fifth active portion and the sixth active portion, wherein each of the plurality of third gate electrodes has a strip extending in the first direction; and on the third active contact portion, between the plurality of third gate electrodes, wherein the third active contact portion has a strip extending in the first direction. The first height of the first single height unit in the first direction may be in the range of 1.5 times to 2.5 times the second height of the second single height unit in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A conceptual diagram representing a logic cell of a semiconductor device according to a comparative example of the inventive concept is shown. Figure 1B and Figure 2 A cross-sectional view representing a conceptual diagram of a logic cell of a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0010] Figure 3 A plan view of a three-dimensional semiconductor device according to some embodiments of the inventive concept is shown.

[0011] FIG. 4A to FIG. 4E Shown according to Figure 3 Cross-sectional views of three-dimensional semiconductor devices of some embodiments.

[0012] Figure 5 and Figure 6 A plan view of a logic cell of a three-dimensional semiconductor device according to some embodiments of the inventive concept is shown.

[0013] 7A to 7C Diagrams representing methods of manufacturing a three-dimensional semiconductor device according to some embodiments of the inventive concept are shown.

[0014] FIG. 8A to FIG. 8E Diagrams representing methods of manufacturing a three-dimensional semiconductor device according to some embodiments of the inventive concept are shown.

[0015] 9A to 9C Diagrams representing methods of manufacturing a three-dimensional semiconductor device according to some embodiments of the inventive concept are shown.

[0016] FIG. 10A to FIG. 10E Diagrams representing methods of manufacturing a three-dimensional semiconductor device according to some embodiments of the inventive concept are shown. DETAILED DESCRIPTION

[0017] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein. It should also be emphasized that the present disclosure provides details of alternative examples, but the enumeration of such alternatives is not exhaustive. In addition, any consistency of details between the various examples should not be construed as requiring such details. The language of the claims should be referenced in determining the requirements of the present invention.

[0018] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0019] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as " / ".

[0020] Figure 1A A conceptual diagram representing a logic cell of a semiconductor device according to a comparative example for comparison with the present inventive concept is shown. Figure 1A A logic cell of a two-dimensional device according to a comparative example is depicted.

[0021] Reference Figure 1A, a single height cell SHC' may be provided. For example, the substrate 100 may be provided with a first power line POR1 and a second power line POR2 thereon. One of the first power line POR1 and the second power line POR2 may be provided with a drain voltage (VDD) or a power supply voltage. The other of the first power line POR1 and the second power line POR2 may be provided with a source voltage (VSS) or a ground voltage. For example, a source voltage (VSS) may be applied to the first power line POR1, and a drain voltage (VDD) may be applied to the second power line POR2.

[0022] The single height cell SHC' may be defined between the first power line POR1 and the second power line POR2. The single height cell SHC' may include a first active portion AR1 and a second active portion AR2. One of the first active portion AR1 and the second active portion AR2 may be a PMOSFET region, and the other of the first active portion AR1 and the second active portion AR2 may be an NMOSFET region. For example, the first active portion AR1 may be an NMOSFET region, and the second active portion AR2 may be a PMOSFET region. For example, the single height cell SHC' may have a complementary metal oxide semiconductor (CMOS) structure disposed between the first power line POR1 and the second power line POR2.

[0023] The semiconductor device according to the comparative example may be a two-dimensional device in which transistors of a front end of line (FEOL) layer are two-dimensionally arranged. For example, an NMOSFET on the first active portion AR1 may be formed to be spaced apart from a PMOSFET on the second active portion AR2 in the first direction D1.

[0024] Each of the first active portion AR1 and the second active portion AR2 may have a first distance WD1 in the first direction D1. The first length HE1 may be defined as a length of the single height cell SHC' according to the comparative example in the first direction D1. The first length HE1 may be the same as a distance (eg, a spacing) between the first power line POR1 and the second power line POR2.

[0025] As used herein, terms such as "same," "equal," "planar," "coplanar," "parallel," and "perpendicular" encompass identical or nearly identical, including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. Terms such as "about" or "approximately" may reflect an amount, size, orientation, or layout that varies only in a small relative manner, and / or in a manner that does not significantly change the operation, function, or structure of certain elements. For example, a range of "about 0.1 to about 1" may encompass ranges such as 0%-5% deviations around 0.1 and 0% to 5% deviations around 1, especially if such deviations maintain the same effect as the listed ranges.

[0026] The single height cell SHC' may constitute a logic unit. In this specification, a logic unit may refer to a logic device (e.g., AND, OR, XOR, XNOR, and inverter) that performs a specific function. For example, a logic unit may include transistors for constituting a logic device, and may also include wiring lines that electrically connect the transistors to each other.

[0027] It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, the element may be directly connected or coupled to or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to or "contacting" or "in contact with" another element (or using any form of the word "contact"), there are no intervening elements at the point of contact.

[0028] Elements described as "electrically connected" are configured so that electrical signals can be passed from one element to another. Thus, a passive conductive component (e.g., a wire, a pad, an internal wire, etc.) that is physically connected to a passive electrically insulating component (e.g., a prepreg layer of a printed circuit board, an electrically insulating adhesive connecting two devices, an electrically insulating bottom filler or mold layer, etc.) is not electrically connected to the component. In addition, elements that are "directly electrically connected" to each other are electrically connected through one or more passive elements (e.g., wires, pads, internal wires, through-holes, etc.). Thus, directly electrically connected components do not include components that are electrically connected through active components (e.g., transistors or diodes). Directly electrically connected elements can be directly physically connected and directly electrically connected.

[0029] Because the single height cell SHC' according to the comparative example includes a two-dimensional device, the first active portion AR1 and the second active portion AR2 may be disposed to be spaced apart from each other in the first direction D1 without overlapping each other. Therefore, the first length HE1 of the single height cell SHC' may need to be sufficient to include all the first active portions AR1 and the second active portions AR2 spaced apart from each other in the first direction D1. As a result, the first length HE1 of the single height cell SHC' according to the comparative example may need to be relatively large. Therefore, the single height cell SHC' according to the comparative example may have a relatively large area.

[0030] Figure 1B and Figure 2 A conceptual diagram representing a logic cell of a semiconductor device according to some embodiments of the inventive concept is shown. Figure 1B and Figure 2 Logic cells of a three-dimensional device according to some embodiments of the inventive concept are depicted.

[0031] Reference Figure 1B , a single height cell SHC including a three-dimensional device such as a stacked transistor can be provided. For example, the substrate 100 may be provided with a first power line POR1 and a second power line POR2 thereon. The single height cell SHC may be defined between the first power line POR1 and the second power line POR2.

[0032] The single height cell SHC may include a first active portion AR1 and a second active portion AR2. One of the first active portion AR1 and the second active portion AR2 may be a PMOSFET region, and the other of the first active portion AR1 and the second active portion AR2 may be an NMOSFET region.

[0033] The semiconductor device according to some embodiments may be a three-dimensional device in which transistors of a front end of line (FEOL) layer are vertically stacked. The substrate 100 may be provided with a first active portion AR1 as a bottom layer thereon, and the first active portion AR1 may be provided with a second active portion AR2 as a top layer thereon. For example, the substrate 100 may be provided with an NMOSFET of the first active portion AR1 thereon, and a PMOSFET of the second active portion AR2 may be stacked on the NMOSFET. The first active portion AR1 and the second active portion AR2 may be spaced apart from each other in the vertical direction or the third direction D3.

[0034] Each of the first active portion AR1 and the second active portion AR2 may have a first distance WD1 in the first direction D1. The second length HE2 may be defined as a length of the single height cell SHC according to the present embodiment in the first direction D1.

[0035] Since the single height cell SHC according to the present embodiment includes a three-dimensional device such as a stacked transistor, the first active portion AR1 and the second active portion AR2 may overlap each other in the vertical direction or the third direction. Therefore, the second length HE2 of the single height cell SHC may only need to be a length sufficient to cover the first distance WD1, however, Figure 1A The first length HE1 of the comparative example may need to have a length sufficient to cover the first distance WD1 of both the first active portion AR1 and the second active portion AR2. As a result, the second length HE2 of the single height cell SHC according to the present embodiment may be smaller than that in the above Figure 1A The first length HE1 of the single height unit SHC' discussed in Figure 1A Compared with the comparative example, the single height cell SHC according to the present embodiment can have a relatively small area. As a result, for the three-dimensional semiconductor device according to the present embodiment, the area of ​​the logic unit can be reduced and the integration degree of the device can be increased.

[0036] Reference Figure 2 , a double height cell DHC may be provided. For example, the substrate 100 may be provided with a first power line POR1, a second power line POR2, and a third power line POR3 thereon. The first power line POR1 may be provided between the second power line POR2 and the third power line POR3. The third power line POR3 may be a path to which a source voltage (VSS) is provided.

[0037] The double height cell DHC may be defined between the second power line POR2 and the third power line POR3. The double height cell DHC may include two first active portions AR1 and two second active portions AR2.

[0038] The semiconductor device according to the present embodiment may be a three-dimensional device in which transistors of a front end of line (FEOL) layer are vertically stacked. The substrate 100 may be provided with a first active portion AR1 as a bottom layer thereon, and the first active portion AR1 may be correspondingly provided with a second active portion AR2 as a top layer thereon. The first active portion AR1 and the second active portion AR2 may be spaced apart from each other in a vertical direction or a third direction D3.

[0039] The first active portion AR1 and the second active portion AR2 may each have a first distance WD1 in the first direction D1. The double height unit DHC according to the present embodiment may have a third length HE3 in the first direction D1. The third length HE3 may be the same as the distance between the second power line POR2 and the third power line POR3. The third length HE3 may be Figure 1BThe two first active portions AR1 of the double height cell DHC may be connected in common to serve as one active portion.

[0040] In the present invention, Figure 2 The double height cell DHC shown may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple height cell having a cell length approximately three times that of the single height cell SHC.

[0041] Figure 3 is a plan view illustrating a three-dimensional semiconductor device according to some embodiments of the inventive concept. Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Along Figure 3 Cross-sectional views taken along line AA', line BB', line CC', line DD' and line EE'. Figure 3 and FIG. 4A to FIG. 4C The illustrated three-dimensional semiconductor device may include a detailed example of a single-height cell. Figure 3 , Figure 4D and Figure 4E The illustrated three-dimensional semiconductor device may include a detailed example of a double-height cell.

[0042] Reference Figure 3 , a substrate 100 including a first region RG1, a second region RG2, and a third region RG3 may be provided. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate formed of and / or including silicon, germanium, or silicon-germanium. For example, the substrate 100 may be a silicon substrate.

[0043] In an embodiment of the present invention, the first region RG1, the second region RG2, and the third region RG3 may each be a unit region on which a logic unit included in a logic circuit is disposed. The first region RG1, the second region RG2, and the third region RG3 may include logic devices (e.g., AND, OR, XOR, XNOR, and inverters), each of which is configured to be consistent with the designed layout and perform a specific function. The first region RG1, the second region RG2, and the third region RG3 may be configured on a semiconductor device having a single-height cell, a double-height cell, or a combination thereof, and may be configured to be consistent with the layout.

[0044] The first single height cell SHC1 may be disposed in the first region RG1. The first height H1 may be defined as a length of the first single height cell SHC1 in the first direction D1. The first height H1 may be greater than a first area width EW1 of each of the first active portion AR1 and the second active portion AR2 in the first direction D1. The first height H1 may be greater than a second height H2 to be discussed below. For example, the first height H1 may be in a range of 1.5 to 2.5 times the second height H2.

[0045] The second single height cells SHC2 may be disposed in the second region RG2. Each second single height cell SHC2 may correspond to Figure 1B The second single height cells SHC2 may be spaced apart from each other in the first direction D1. The second height H2 may be defined as a length of the second single height cell SHC2 in the first direction D1. The second height H2 may be greater than a second region width EW2 of each of the third active portion AR3 and the fourth active portion AR4 in the first direction D1. The dummy region DMR may be disposed between the second single height cells SHC2.

[0046] As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as another component but does not have the same substantial function as another component and may exist in a device only as a pattern. For example, a dummy component may not contribute to a logic function in a logic circuit.

[0047] The first double height unit DHC1 may be disposed in the third region RG3. The first double height unit DHC1 may correspond to Figure 2 The third height H3 may be defined as the length of the first double height unit DHC1 in the first direction D1. The third height H3 may be greater than the third area width EW3 of each of the fifth active portion AR5 and the sixth active portion AR6 in the first direction D1. The third height H3 may be greater than the second height H2 and equal to the first height H1. Alternatively, the third height H3 may be less than the first height H1.

[0048] In some embodiments of the present inventive concept, the first region RG1, the second region RG2, and the third region RG3 may be provided with a first single height cell SHC1 and a second single height cell SHC2, a first double height cell DHC1, or a combination thereof. For example, the transistor of the first single height cell SHC1 on the first region RG1 may be an extra gate (EG) device, and the transistor of the second single height cell SHC2 on the second region RG2 may be a single gate (SG) device. In another example, the transistor on the first region RG1 may include a long gate transistor (or a long channel transistor) having a relatively large gate length (or channel length). The first region RG1 may include a transistor having a relatively large effective channel width or an effective nanosheet width.

[0049] The following will refer to Figure 3 and FIG. 4A to FIG. 4C The three-dimensional transistor of the first region RG1 is discussed in detail. The first single height cell SHC1 may be disposed on a substrate 100. The substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The first surface 100a may be a front surface of the substrate 100, and the second surface 100b may be a rear surface of the substrate 100. In an embodiment of the present inventive concept, the substrate 100 may be a semiconductor substrate formed of and / or including silicon, germanium, or silicon germanium. In another embodiment of the present inventive concept, the substrate 100 may be a dielectric substrate formed of and / or including a silicon-based dielectric material (e.g., silicon oxide and / or silicon nitride).

[0050] The first single height cell SHC1 may be used as a logic unit and may include a first active portion AR1 and a second active portion AR2 sequentially stacked on a substrate 100. One of the first active portion AR1 and the second active portion AR2 may be a PMOSFET region, and the other of the first active portion AR1 and the second active portion AR2 may be an NMOSFET region. The first active portion AR1 may be disposed on a bottom layer of a front end of line (FEOL) layer, and the second active portion AR2 may be disposed on a top layer of the front end of line (FEOL) layer. The NMOSFET and PMOSFET of the first active portion AR1 and the second active portion AR2 may be vertically stacked to constitute a three-dimensional stacked transistor. In an embodiment, the first active portion AR1 may be an NMOSFET region, and the second active portion AR2 may be a PMOSFET region.

[0051] The active pattern AP may be defined by a trench formed at an upper portion of the substrate 100. The active pattern AP may be a vertical protrusion of the substrate 100. The active pattern AP may be provided thereon with first and second active portions AR1 and AR2 sequentially stacked.

[0052] The device isolation layer ST may fill the trench. The device isolation layer ST may define a first single height cell SHC1. When viewed in a plan view, the first single height cell SHC1 may be defined between device isolation layers ST adjacent to each other along the first direction D1. The top surface of the device isolation layer ST may be coplanar with or lower than the top surface of the active pattern AP. The device isolation layer ST may not cover any of the first lower channel pattern LCH1 and the first upper channel pattern UCH1 to be discussed below. The device isolation layer ST may be formed of and / or include a silicon-based dielectric material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0053] The active pattern AP may be provided thereon with a first active portion AR1 including a first lower channel pattern LCH1 and a first lower source / drain pattern LSD1. The first lower channel pattern LCH1 may be interposed between a pair of first lower source / drain patterns LSD1. The first lower channel pattern LCH1 may connect the pair of first lower source / drain patterns LSD1 to each other.

[0054] The first lower channel pattern LCH1 may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2, which are stacked while being spaced apart from each other. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of and / or include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of and / or include crystalline silicon. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be a nanosheet. The first lower channel pattern LCH1 may also include one or more semiconductor patterns, which are stacked while being spaced apart from the second semiconductor pattern SP2.

[0055] The first lower source / drain patterns LSD1 may be disposed at the top surface of the lower active contact portion LAC to be discussed below. Each of the first lower source / drain patterns LSD1 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of the first lower source / drain pattern LSD1 may be higher than the top surface of the second semiconductor pattern SP2 of the first lower channel pattern LCH1.

[0056] The first lower source / drain pattern LSD1 may be doped with impurities to have a first conductivity type. The first conductivity type may be an n-type or a p-type. In the present embodiment, the first conductivity type may be an n-type. The first lower source / drain pattern LSD1 may be formed of and / or include one or more of silicon (Si) and silicon-germanium (SiGe).

[0057] The first interlayer dielectric layer 110 may be disposed on the first lower source / drain pattern LSD1. The first interlayer dielectric layer 110 may cover the first lower source / drain pattern LSD1.

[0058] The lower active contact LAC may be disposed below the first lower source / drain pattern LSD1. The lower active contact LAC may be electrically connected to the first lower source / drain pattern LSD1. The lower active contact LAC may be buried in the substrate 100. The lower active contact LAC may extend vertically from the second surface 100b of the substrate 100 to the first surface 100a of the substrate 100. The lower active contact LAC may be formed of and / or include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). The lower active contact LAC may be covered by the first interlayer dielectric layer 110.

[0059] The lower active contact LAC may include a horizontal portion extending in the first direction D1, and a protruding portion contacting a corresponding lower source / drain pattern among the first lower source / drain pattern LSD1, the second lower source / drain pattern LSD2, and the third lower source / drain pattern LSD3, which will be discussed below. A width of the horizontal portion in the first direction D1 may be greater than a maximum width of each of the first lower source / drain pattern LSD1, the second lower source / drain pattern LSD2, and the third lower source / drain pattern LSD3 in the first direction D1.

[0060] The first interlayer dielectric layer 110 may be provided with the second interlayer dielectric layer 120 and the second active portion AR2 thereon. The second active portion AR2 may include a first upper channel pattern UCH1 and a first upper source / drain pattern USD1. The first upper channel pattern UCH1 may vertically overlap with the first lower channel pattern LCH1 in correspondence. The first upper source / drain pattern USD1 may vertically overlap with the first lower source / drain pattern LSD1 in correspondence. The first upper channel pattern UCH1 may be between a pair of first upper source / drain patterns USD1. The first upper channel pattern UCH1 may connect the pair of first upper source / drain patterns USD1 to each other.

[0061] The first upper channel pattern UCH1 may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4, which are stacked while being spaced apart from each other. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the first upper channel pattern UCH1 may include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first lower channel pattern LCH1. Each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be a nanosheet. For example, the first upper channel pattern UCH1 may further include one or more semiconductor patterns, which are stacked while being spaced apart from the fourth semiconductor pattern SP4.

[0062] At least one dummy channel pattern DSP may be interposed between the first lower channel pattern LCH1 and the first upper channel pattern UCH1 covering the first lower channel pattern LCH1. A seed layer SDL may be interposed between the dummy channel pattern DSP and the first upper channel pattern UCH1.

[0063] The dummy channel pattern DSP may be spaced apart from the first lower source / drain pattern LSD1 and the first upper source / drain pattern USD1. For example, the dummy channel pattern DSP may not be connected to any source / drain pattern. The dummy channel pattern DSP may be formed of and / or include a semiconductor material (e.g., silicon (Si), germanium (Ge), or silicon-germanium (SiGe)) or a silicon-based dielectric material (e.g., silicon oxide or silicon nitride). In an embodiment of the inventive concept, the dummy channel pattern DSP may include a silicon-based dielectric material.

[0064] The first upper source / drain pattern USD1 may be disposed at the top surface of the first interlayer dielectric layer 110. Each of the first upper source / drain patterns USD1 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of the first upper source / drain pattern USD1 may be higher than the top surface of the fourth semiconductor pattern SP4 of the first upper channel pattern UCH1.

[0065] The first upper source / drain pattern USD1 may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the first lower source / drain pattern LSD1. The second conductivity type may be a p-type. The first upper source / drain pattern USD1 may be formed of and / or include one or more of silicon-germanium (SiGe) and silicon (Si).

[0066] Return to reference Figure 3, a plurality of first gate electrodes GE1 may be disposed in the first single height cell SHC1 on the first region RG1. For example, the first gate electrode GE1 may be disposed on the stacked first lower channel pattern LCH1 and the first upper channel pattern UCH1. When viewed in a plane, the first gate electrode GE1 may have a bar shape extending along the first direction D1. The first gate electrode GE1 may vertically overlap the stacked first lower channel pattern LCH1 and the first upper channel pattern UCH1.

[0067] The first gate electrode GE1 may extend from the top surface of the device isolation layer ST (or the top surface of the active pattern AP) to the gate capping pattern GP in a vertical direction (e.g., a third direction D3). The first gate electrode GE1 may extend from the first lower channel pattern LCH1 of the first active portion AR1 to the first upper channel pattern UCH1 of the second active portion AR2 in the third direction D3. The first gate electrode GE1 may extend from the lowermost first semiconductor pattern SP1 to the uppermost fourth semiconductor pattern SP4 in the third direction D3.

[0068] The first gate electrode GE1 may be disposed at the top surface, the bottom surface, and the opposite sidewalls of each of the first to fourth semiconductor patterns SP1 to SP4. In this sense, the transistor according to the present embodiment may be a three-dimensional field effect transistor (eg, MBCFET or GAAFET) in which the first gate electrode GE1 three-dimensionally surrounds a channel.

[0069] The first gate electrode GE1 may include a lower gate electrode LGE disposed in a bottom layer of a front end of line (FEOL) layer or in a first active portion AR1, and may also include an upper gate electrode UGE disposed in a top layer of the FEOL layer or in a second active portion AR2. The lower gate electrode LGE and the upper gate electrode UGE may overlap each other vertically. In an embodiment of the inventive concept, the lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. For example, the first gate electrode GE1 according to the present embodiment may be a common gate electrode, wherein the lower gate electrode LGE on the first lower channel pattern LCH1 is connected to the upper gate electrode UGE on the first upper channel pattern UCH1.

[0070] The lower gate electrode LGE may include a first internal electrode PO1 between the active pattern AP and the first semiconductor pattern SP1 , a second internal electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 , and a third internal electrode PO3 between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0071] The upper gate electrode UGE may include a fourth internal electrode PO4 between the dummy channel pattern DSP (or the seed layer SDL) and the third semiconductor pattern SP3 , a fifth internal electrode PO5 between the third and fourth semiconductor patterns SP3 and SP4 , and an external electrode PO6 on the fourth semiconductor pattern SP4 .

[0072] A pair of gate spacers GS may be disposed on opposite side walls of the first gate electrode GE1. A pair of gate spacers GS may be disposed on opposite side walls of the outer electrode PO6. The gate spacer GS may extend along the first gate electrode GE1 in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the first gate electrode GE1. The top surface of the gate spacer GS may be coplanar with the top surface of the second interlayer dielectric layer 120. The gate spacer GS may be formed of at least one material selected from SiCN, SiCON, and SiN and / or include at least one material selected from SiCN, SiCON, and SiN. Alternatively, the gate spacers GS may each include a multilayer formed of at least two materials selected from SiCN, SiCON, and SiN and / or include at least two materials selected from SiCN, SiCON, and SiN.

[0073] The gate capping pattern GP may be disposed at a top surface of the first gate electrode GE1. The gate capping pattern GP may extend along the first gate electrode GE1 in the first direction D1. The gate capping pattern GP may be formed of and / or include at least one material selected from SiON, SiCN, SiCON, and SiN.

[0074] The gate dielectric layer GI may be interposed between the first gate electrode GE1 and the first to fourth semiconductor patterns SP1 to SP4. The gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. In an embodiment of the inventive concept, the gate dielectric layer GI may include a silicon oxide layer directly covering the surface of the semiconductor patterns SP1 to SP4, and a high-k dielectric layer on the silicon oxide layer. For example, the gate dielectric layer GI may include a multilayer of a silicon oxide layer and a high-k dielectric layer.

[0075] The high-k dielectric layer may be formed of and / or include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one material selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0076] The lower gate electrode LGE may include a first work function metal pattern on the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The upper gate electrode UGE may include a second work function metal pattern on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. For example, each of the first work function metal pattern and the second work function metal pattern may be formed of nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and / or include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). The first work function metal pattern and the second work function metal pattern may have different work functions from each other. The first gate electrode GE1 may be formed of and / or include a low resistance metal (e.g., at least one selected from tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)) on the first work function metal pattern and the second work function metal pattern. For example, the outer electrode PO6 may include a low resistance metal.

[0077] The gate cutting pattern GCP may penetrate the first gate electrode GE1. The gate cutting pattern GCP may separate the first gate electrode GE1 from another first gate electrode GE1 adjacent to the first gate electrode GE1 in the first direction D1. Figure 4C As shown, a pair of gate cutting patterns GCP may be disposed at opposite ends of the first gate electrode GE1. The gate cutting pattern GCP may be formed of and / or include a dielectric material (eg, a silicon oxide layer, a silicon nitride layer, or a combination thereof).

[0078] The second interlayer dielectric layer 120 may be disposed on the first upper source / drain pattern USD1 and the first gate electrode GE1 . The second interlayer dielectric layer 120 may cover the first upper source / drain pattern USD1 . The third interlayer dielectric layer 130 may cover the second interlayer dielectric layer 120 .

[0079] The third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120. The gate contact GC may be disposed to penetrate the third interlayer dielectric layer 130, the second interlayer dielectric layer 120, and the gate capping pattern GP to be electrically connected to the first gate electrode GE1. The gate contact GC may be formed of and / or include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0080] The first upper active contact UAC1 may be disposed to penetrate the second interlayer dielectric layer 120 and the third interlayer dielectric layer 130 and electrically connected to the first upper source / drain pattern USD1 , respectively. A top surface of the first upper active contact UAC1 may be coplanar with a top surface of the third interlayer dielectric layer 130 .

[0081] The fourth interlayer dielectric layer 140 may be disposed on the third interlayer dielectric layer 130. The first metal layer M1 may be disposed in the fourth interlayer dielectric layer 140. The first metal layer M1 may include an upper line UMI. The first metal layer M1 may include an upper via UVI. The upper via UVI may electrically connect the upper line UMI to the first upper active contact UAC1 or the gate contact GC. Each of the upper line UMI and the upper via UVI may be formed of and / or include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0082] Additional metal layers (e.g., M2, M3, M4, etc.) may be stacked on the first metal layer M1. The first metal layer M1 and the metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 may constitute back-end-of-line (BEOL) layers of the semiconductor device. The metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 may include routing lines for connecting logic cells to each other.

[0083] The lower interlayer dielectric layer 210 may be disposed below the second surface 100b of the substrate 100. A back metal layer BSM may be disposed in the lower interlayer dielectric layer 210. The back metal layer BSM may include a lower line LMI. The back metal layer BSM may also include a lower via LVI. The lower via LVI may electrically connect the lower line LMI to the lower active contact LAC. Each of the lower line LMI and the lower via LVI may be formed of a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo) and / or include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0084] The additional back metal layer may be stacked below the back metal layer BSM. In an embodiment of the inventive concept, the additional back metal layer may include a power delivery network. The power delivery network may include a wiring network for applying a source voltage (VSS) and a drain voltage (VDD) to the back metal layer BSM.

[0085] The source voltage and drain voltage can be applied to the back metal layer BSM through the power delivery network. Back to reference Figure 4B, one of the source voltage and the drain voltage may be applied to the first lower source / drain pattern LSD1 through the lower line LMI, the lower via LVI, and the lower active contact LAC. The other of the source voltage and the drain voltage may be applied to the first metal layer M1 through a power tab unit. The voltage applied to the first metal layer M1 through the power tab unit may be applied to the first upper source / drain pattern USD1 through the upper line UMI, the upper via UVI, and the first upper active contact UAC1.

[0086] The following will refer to Figure 3 The three-dimensional transistor on the second region RG2 is described. Since the second single height cell SHC2 has a structure similar to that of the first single height cell SHC1, the structure described above with reference to FIG. Figure 3 and FIG. 4A to FIG. 4C The technical features of the transistors on the first region RG1 discussed above repeat the detailed description of the technical features.

[0087] The second single height cell SHC2 may be used as a logic unit and may include a third active portion AR3 and a fourth active portion AR4 sequentially stacked on the substrate 100. One of the third active portion AR3 and the fourth active portion AR4 may be a PMOSFET region, and the other of the third active portion AR3 and the fourth active portion AR4 may be an NMOSFET region. The third active portion AR3 may be disposed on a bottom layer of a front end of line (FEOL) layer, and the fourth active portion AR4 may be disposed on a top layer of the front end of line (FEOL) layer. The NMOSFET and PMOSFET of the third active portion AR3 and the fourth active portion AR4 may be vertically stacked to constitute a three-dimensional stacked transistor. In an embodiment, the third active portion AR3 may be an NMOSFET region, and the fourth active portion AR4 may be a PMOSFET region.

[0088] The active pattern may be provided thereon with a third active portion AR3 including a lower channel pattern and a lower source / drain pattern. The lower channel pattern may be interposed between a pair of lower source / drain patterns. The lower channel pattern may connect the pair of lower source / drain patterns to each other.

[0089] The fourth active portion AR4 may include an upper channel pattern and an upper source / drain pattern. The upper channel pattern may vertically overlap with the lower channel pattern correspondingly. The upper source / drain pattern may vertically overlap with the lower source / drain pattern correspondingly. The upper channel pattern may be between a pair of upper source / drain patterns. The upper channel pattern may connect a pair of upper source / drain patterns to each other.

[0090] A plurality of second gate electrodes GE2 may be disposed on the second single height cell SHC2 in the second region RG2. For example, the second gate electrode GE2 may be disposed on the stacked lower channel pattern and the upper channel pattern. When viewed in a plane, the second gate electrode GE2 may have a strip shape extending along the first direction D1. The second gate electrode GE2 may vertically overlap the stacked lower channel pattern and the upper channel pattern.

[0091] The second single height cell SHC2 on the second region RG2 may be provided thereon with a second upper active contact UAC2 correspondingly connected to the upper source / drain pattern. Figure 3 Each of the second upper active contacts UAC2 may have a bar shape extending along the first direction D1 when viewed in a plan view of a view of FIG. 1. The second upper active contacts UAC2 may vertically overlap the stacked lower and upper source / drain patterns.

[0092] The following will refer to Figure 3 , Figure 4D and Figure 4E The three-dimensional transistor on the third region RG3 is described. Figure 3 and FIG. 4A to FIG. 4C The detailed description of the technical features of the transistor on the first region RG1 and the transistor on the second region RG2 discussed above repeats the technical features.

[0093] The first double height cell DHC1 of the third region RG3, which may be used as a logic cell, may include fifth and sixth active portions AR5 and AR6 sequentially stacked on the substrate 100. The first double height cell DHC1 may include seventh and eighth active portions AR7 and AR8 sequentially stacked on the substrate 100. The seventh and eighth active portions AR7 and AR8 may be spaced apart from the fifth and sixth active portions AR5 and AR6.

[0094] One of the fifth active portion AR5 and the sixth active portion AR6 may be a PMOSFET region, and the other of the fifth active portion AR5 and the sixth active portion AR6 may be an NMOSFET region. The fifth active portion AR5 may be disposed on a bottom layer of a front end of line (FEOL) layer, and the sixth active portion AR6 may be disposed on a top layer of the front end of line (FEOL) layer. The NMOSFET and PMOSFET of the fifth active portion AR5 and the sixth active portion AR6 may be stacked vertically to form a three-dimensional stacked transistor. In an embodiment, the fifth active portion AR5 may be an NMOSFET region, and the sixth active portion AR6 may be a PMOSFET region.

[0095] One of the seventh active portion AR7 and the eighth active portion AR8 may be a PMOSFET region, and the other of the seventh active portion AR7 and the eighth active portion AR8 may be an NMOSFET region. The seventh active portion AR7 may be disposed on a bottom layer of a front end of line (FEOL) layer, and the eighth active portion AR8 may be disposed on a top layer of the front end of line (FEOL) layer. The NMOSFET and PMOSFET of the seventh active portion AR7 and the eighth active portion AR8 may be stacked vertically to form a three-dimensional stacked transistor. In an embodiment, the seventh active portion AR7 may be an NMOSFET region, and the eighth active portion AR8 may be a PMOSFET region.

[0096] In the third active portion RG3, an active pattern AP may be defined by a groove formed on an upper portion of the substrate 100. The active pattern AP may be a vertical protrusion of the substrate 100. The fifth active portion AR5 and the sixth active portion AR6 may be sequentially stacked on one active pattern AP. The seventh active portion AR7 and the eighth active portion AR8 may be sequentially stacked on another active pattern AP.

[0097] The active pattern AP may be provided thereon with a fifth active portion AR5 including a second lower channel pattern LCH2 and a second lower source / drain pattern LSD2. The second lower channel pattern LCH2 may be interposed between a pair of second lower source / drain patterns LSD2. The second lower channel pattern LCH2 may connect the pair of second lower source / drain patterns LSD2 to each other.

[0098] The second lower channel pattern LCH2 may include a fifth semiconductor pattern SP5 and a sixth semiconductor pattern SP6, which are stacked while being spaced apart from each other. The fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6 may be formed of and / or include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Each of the fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6 may be a nanosheet. For example, the second lower channel pattern LCH2 may further include one or more semiconductor patterns, which are stacked while being spaced apart from the sixth semiconductor pattern SP6.

[0099] The second lower source / drain pattern LSD2 may be disposed at the top surface of the lower active contact portion LAC. The second lower source / drain pattern LSD2 may be a pattern formed by the same process used to form the first lower source / drain pattern LSD1. For example, the top surface of the second lower source / drain pattern LSD2 may be higher than the top surface of the sixth semiconductor pattern SP6 of the second lower channel pattern LCH2. The second lower source / drain pattern LSD2 may be doped with impurities to have a first conductivity type. The first conductivity type may be n-type or p-type. In the present embodiment, the first conductivity type may be n-type. The second lower source / drain pattern LSD2 may be formed of and / or include one or more of silicon (Si) and silicon-germanium (SiGe).

[0100] The first interlayer dielectric layer 110 may be provided with a second interlayer dielectric layer 120 and a sixth active portion AR6 thereon. The sixth active portion AR6 may include a second upper channel pattern UCH2 and a second upper source / drain pattern USD2. The second upper channel pattern UCH2 may vertically overlap with the second lower channel pattern LCH2 in correspondence. The second upper source / drain pattern USD2 may vertically overlap with the second lower source / drain pattern LSD2 in correspondence. The second upper channel pattern UCH2 may be between a pair of second upper source / drain patterns USD2. The second upper channel pattern UCH2 may connect a pair of second upper source / drain patterns USD2 to each other.

[0101] The second upper channel pattern UCH2 may include a seventh semiconductor pattern SP7 and an eighth semiconductor pattern SP8, which are stacked while being spaced apart from each other. The seventh semiconductor pattern SP7 and the eighth semiconductor pattern SP8 of the second upper channel pattern UCH2 may include the same semiconductor material as the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the first upper channel pattern UCH1. Each of the seventh semiconductor pattern SP7 and the eighth semiconductor pattern SP8 may be a nanosheet. For example, the second upper channel pattern UCH2 may further include one or more semiconductor patterns, which are stacked while being spaced apart from the eighth semiconductor pattern SP8.

[0102] At least one first dummy channel pattern DSP1 may be interposed between the second lower channel pattern LCH2 and the second upper channel pattern UCH2 covering the second lower channel pattern LCH2. A seed layer SDL may be interposed between the first dummy channel pattern DSP1 and the second upper channel pattern UCH2. The first dummy channel pattern DSP1 may be formed of and / or include the same material as that of the dummy channel pattern DSP. The first dummy channel pattern DSP1 may be spaced apart from the second lower source / drain pattern LSD2 and the second upper source / drain pattern USD2.

[0103] The second upper source / drain pattern USD2 may be disposed at the top surface of the first interlayer dielectric layer 110. Each of the second upper source / drain patterns USD2 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of the second upper source / drain pattern USD2 may be higher than the top surface of the eighth semiconductor pattern SP8 of the second upper channel pattern UCH2.

[0104] The second upper source / drain pattern USD2 may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the second lower source / drain pattern LSD2. The second conductivity type may be a p-type. The second upper source / drain pattern USD2 may be formed of and / or include one or more of silicon-germanium (SiGe) and silicon (Si).

[0105] Another active pattern AP may be provided thereon with a seventh active portion AR7 including a third lower channel pattern LCH3 and a third lower source / drain pattern LSD3. The third lower channel pattern LCH3 may be interposed between a pair of third lower source / drain patterns LSD3. The third lower channel pattern LCH3 may connect the pair of third lower source / drain patterns LSD3 to each other.

[0106] The third lower channel pattern LCH3 may include a ninth semiconductor pattern SP9 and a tenth semiconductor pattern SP10, which are stacked while being spaced apart from each other. The ninth semiconductor pattern SP9 and the tenth semiconductor pattern SP10 may be formed of the same semiconductor material as the fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6 and / or include the same semiconductor material as the fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6. Each of the ninth semiconductor pattern SP9 and the tenth semiconductor pattern SP10 may be a nanosheet. For example, the third lower channel pattern LCH3 may further include one or more semiconductor patterns, which are stacked while being spaced apart from the tenth semiconductor pattern SP10.

[0107] The third lower source / drain pattern LSD3 may be disposed at the top surface of the lower active contact portion LAC. The third lower source / drain pattern LSD3 may be a pattern formed by the same process used to form the first lower source / drain pattern LSD1. For example, the top surface of the third lower source / drain pattern LSD3 may be higher than the top surface of the tenth semiconductor pattern SP10 of the third lower channel pattern LCH3. The third lower source / drain pattern LSD3 may be doped with impurities to have a first conductivity type. The first conductivity type may be an n-type or a p-type. In the present embodiment, the first conductivity type may be an n-type. The third lower source / drain pattern LSD3 may be formed of and / or include one or more of silicon (Si) and silicon-germanium (SiGe).

[0108] The first interlayer dielectric layer 110 may be provided with a second interlayer dielectric layer 120 and an eighth active portion AR8 thereon. The eighth active portion AR8 may include a third upper channel pattern UCH3 and a third upper source / drain pattern USD3. The third upper channel pattern UCH3 may vertically overlap with the third lower channel pattern LCH3 in correspondence. The third upper channel pattern UCH3 may vertically overlap with the third lower source / drain pattern LSD3 in correspondence. The third upper channel pattern UCH3 may be between a pair of third upper source / drain patterns USD3. The third upper channel pattern UCH3 may connect a pair of third upper source / drain patterns USD3 to each other.

[0109] The third upper channel pattern UCH3 may include an eleventh semiconductor pattern SP11 and a twelfth semiconductor pattern SP12, which are stacked while being spaced apart from each other. The eleventh semiconductor pattern SP11 and the twelfth semiconductor pattern SP12 of the third upper channel pattern UCH3 may be formed of the same semiconductor material as the seventh semiconductor pattern SP7 and the eighth semiconductor pattern SP8 of the second upper channel pattern UCH2 and / or include the same semiconductor material as the seventh semiconductor pattern SP7 and the eighth semiconductor pattern SP8 of the second upper channel pattern UCH2. Each of the eleventh semiconductor pattern SP11 and the twelfth semiconductor pattern SP12 may be a nanosheet. For example, the third upper channel pattern UCH3 may also include one or more semiconductor patterns, which are stacked while being spaced apart from the twelfth semiconductor pattern SP12.

[0110] At least one second dummy channel pattern DSP2 may be interposed between the third lower channel pattern LCH3 and the third upper channel pattern UCH3 covering the third lower channel pattern LCH3. A seed layer SDL may be interposed between the second dummy channel pattern DSP2 and the third upper channel pattern UCH3. The second dummy channel pattern DSP2 may be formed of and / or include the same material as that of the dummy channel pattern DSP. The second dummy channel pattern DSP2 may be spaced apart from the third lower source / drain pattern LSD3 and the third upper source / drain pattern USD3.

[0111] The third upper source / drain patterns USD3 may be disposed at the top surface of the first interlayer dielectric layer 110. Each of the third upper source / drain patterns USD3 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of the third upper source / drain patterns USD3 may be higher than the top surface of the twelfth semiconductor pattern SP12 of the third upper channel pattern UCH3.

[0112] The third upper source / drain pattern USD3 may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the third lower source / drain pattern LSD3. The second conductivity type may be a p-type. The third upper source / drain pattern USD3 may be formed of and / or include one or more of silicon-germanium (SiGe) and silicon (Si).

[0113] A plurality of third gate electrodes GE3 may be disposed on the first double height cell DHC1 on the third region RG3. For example, the third gate electrode GE3 may be disposed on the stacked second lower channel pattern LCH2 and the second upper channel pattern UCH2 and the stacked third lower channel pattern LCH3 and the third upper channel pattern UCH3. Figure 3 The third gate electrode GE3 may have a bar shape extending in the first direction D1 when viewed in a plan view of a view of FIG. The third gate electrode GE3 may vertically overlap the stacked second lower channel pattern LCH2 and second upper channel pattern UCH2 and the stacked third lower channel pattern LCH3 and third upper channel pattern UCH3.

[0114] The first double height cell DHC1 on the third region RG3 may be provided thereon with a third upper active contact UAC3 which is electrically connected to the second upper source / drain pattern USD2 and the third upper source / drain pattern USD3, respectively. Figure 3When viewed in a plan view of a view of FIG. 1 , each third active contact UAC3 may have a bar shape extending along the first direction D1. The third upper active contact UAC3 may vertically overlap the stacked second lower source / drain pattern LSD2 and second upper source / drain pattern USD2 and the stacked third lower source / drain pattern LSD3 and third upper source / drain pattern USD3.

[0115] The third upper active contact UAC3 may contact the second upper source / drain pattern USD2 and the third upper source / drain pattern USD3. For example, the third upper active contact UAC3 may be electrically connected to the second upper source / drain pattern USD2 and the third upper source / drain pattern USD3. The width of the third upper active contact UAC3 in the first direction D1 may be greater than the maximum width of each of the second upper source / drain pattern USD2 and the third upper source / drain pattern USD3 in the first direction D1.

[0116] Return to reference Figure 3 , the width of the second upper active contact UAC2 in the first direction D1 may be smaller than the width of the first upper active contact UAC1 in the first direction D1 and the width of the third upper active contact UAC3 in the first direction D1. For example, the width of the first upper active contact UAC1 in the first direction D1 may be the same as the width of the third upper active contact UAC3 in the first direction D1.

[0117] Reference Figure 4C and Figure 4E , the first lower channel patterns LCH1 may each have a first width W1 in the first direction D1. The first width W1 may be defined as referring to a horizontal distance from one side surface (e.g., the first side surface) of the first lower channel pattern LCH1 to another side surface (e.g., the second side surface) of the first lower channel pattern LCH1 that may be opposite to the one side surface. The first width W1 may be the same as a width of each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first direction D1.

[0118] Each of the second lower channel pattern LCH2 and the third lower channel pattern LCH3 may have a second width W2 in the first direction D1. The second width W2 may be defined as a horizontal distance from one side surface (e.g., the first side surface) of the second lower channel pattern LCH2 or the third lower channel pattern LCH3 to another side surface (e.g., the second side surface) of the second lower channel pattern LCH2 or the third lower channel pattern LCH3 that may be opposite to the one side surface of the second lower channel pattern LCH2 or the third lower channel pattern LCH3. The second width W2 may be the same as a width of each of the fifth semiconductor pattern SP5, the sixth semiconductor pattern SP6, the ninth semiconductor pattern SP9, and the tenth semiconductor pattern SP10 in the first direction D1.

[0119] The first upper channel patterns UCH1 may each have a third width W3 in the first direction D1. The third width W3 may be defined as referring to a horizontal distance from one side surface (e.g., the first side surface) of the first upper channel pattern UCH1 to another side surface (e.g., the second side surface) of the first upper channel pattern UCH1 that may be opposite to the one side surface. The third width W3 may be the same as a width of each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 in the first direction D1.

[0120] Each of the second upper channel pattern UCH2 and the third upper channel pattern UCH3 may have a fourth width W4 in the first direction D1. The fourth width W4 may be defined as a horizontal distance from one side surface (e.g., the first side surface) of the second upper channel pattern UCH2 or the third upper channel pattern UCH3 to another side surface (e.g., the second side surface) of the second upper channel pattern UCH2 or the third upper channel pattern UCH3 that may be opposite to the one side surface. The fourth width W4 may be the same as the width of each of the seventh semiconductor pattern SP7, the eighth semiconductor pattern SP8, the eleventh semiconductor pattern SP11, and the twelfth semiconductor pattern SP12 in the first direction D1.

[0121] The first width W1 may be greater than the second width W2. For example, the first width W1 may be 1.5 to 2.5 times greater than the second width W2. The first width W1 may be greater than a width of a lower channel pattern of a second single height cell SHC2 on the second region RG2 in the first direction D1. The first width W1 may be the same as the third width W3. The third width W3 may be greater than a width of an upper channel pattern of a second single height cell SHC2 on the second region RG2 in the first direction D1.

[0122] The second width W2 may be the same as the fourth width W4. The third width W3 may be greater than the fourth width W4. For example, the third width W3 may be 1.5 to 2.5 times greater than the fourth width W4. The second width W2 may be equal to or greater than the width of the lower channel pattern of the second single height cell SHC2 on the second region RG2 in the first direction D1. The fourth width W4 may be equal to or greater than the width of the lower channel pattern of the second single height cell SHC2 on the second region RG2 in the first direction D1.

[0123] The first to fourth widths W1 to W4 may be effective channel widths of transistors in each of the first to third regions RG1 to RG3, respectively. Based on whether the transistor is a logic unit or part of a logic device that performs a specific function, the effective channel width may be changed to optimize the operating speed and performance of the three-dimensional semiconductor device. For example, in a three-dimensional semiconductor device according to the present invention, the effective width of a nanosheet on a logic unit may be changed to improve electrical characteristics.

[0124] Figure 5 and Figure 6 1 shows a cross-sectional view of a three-dimensional semiconductor device according to some embodiments of the present invention. Figure 3 and FIG. 4A to FIG. 4E A detailed description of technical features of transistors of the first single height cell SHC1, the second single height cell SHC2, and the first double height cell DHC1 is discussed, and differences thereof will be explained in detail.

[0125] Reference Figure 5 A substrate 100 including a first region RG1, a second region RG2, and a third region RG3 may be provided. The first region RG1 may have a reference Figure 3 The first single height unit SHC1 discussed. The second region RG2 and the third region RG3 may be provided with reference Figure 1B and Figure 3 The second single height cell SHC2 and the dummy region DMR discussed. For example, the first region RG1 to the third region RG3 may be provided with a combination of the first single height cell SHC1 and the second single height cell SHC2 thereon. In another example, the first single height cell SHC1 may be provided in a region other than the first region RG1, for example, on the second region RG2 or the third region RG3.

[0126] Reference Figure 6 , a substrate 100 including a first region RG1, a second region RG2, and a third region RG3 may be provided. Figure 3 The first single height cell SHC1 discussed may be disposed in each of the first to third regions RG1 to RG3. Figure 6 The transistors of the illustrated first single height cell SHC1 may be extra gate (EG) devices, or may include long gate transistors (or long channel transistors) having a relatively large gate length (or channel length).

[0127] In the three-dimensional semiconductor device according to the present invention, the first region RG1, the second region RG2, and the third region RG3 may be provided with various combinations of logic devices that perform specific functions. Therefore, compared with the two-dimensional semiconductor device, the dummy region between the logic cells may have a small area to increase the integration of the three-dimensional semiconductor device.

[0128] In addition, compared with the single-height unit of two-dimensional or three-dimensional semiconductor devices, the use of Figure 3A single device of the first double height unit DHC1 can additionally obtain a process margin of the metal layer. Therefore, a wiring line can be additionally provided in the metal layer or the width of the metal line can be increased to reduce the resistance of the back end of line (BEOL) layer of the three-dimensional semiconductor device. Therefore, the three-dimensional semiconductor device can have improved electrical characteristics.

[0129] 7A to 10E A diagram showing a method of manufacturing a three-dimensional semiconductor device according to some embodiments of the present inventive concept is shown. For example, Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A Shown along Figure 3 A cross-sectional view taken along line AA'. Figure 7B , Figure 8B , Fig. 9B and Fig. 10B Shown along Figure 3 A cross-sectional view taken along line BB'. Figure 8C and Fig. 10C Shown along Figure 3 A cross-sectional view taken along line CC'. Figure 7C , Fig.8D , Fig. 9C and Fig. 10D Shown along Figure 3 A cross-sectional view taken along line D-D'. Fig. 8E and Fig. 10E Shown along Figure 3 A cross-sectional view taken along line EE'.

[0130] Reference 7A to 10E , will describe the manufacturing according to Figures 3 to 4E For the sake of brevity of description, the technical features previously described may be briefly described or not described at all, but it is understood that the previous description is applicable.

[0131] Reference 7A to 7C , a semiconductor substrate 105 including a first region RG1, a second region RG2, and a third region RG3 may be provided. The semiconductor substrate 105 may be formed of and / or include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the semiconductor substrate 105 may be a single crystal silicon wafer.

[0132] The first sacrificial layers SAL1 and the first active layers ACL1 may be alternately stacked on the semiconductor substrate 105. The first sacrificial layers SAL1 may be formed of and / or include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the first active layer ACL1 may be formed of and / or include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the first sacrificial layers SAL1 may be formed of and / or include silicon-germanium (SiGe), and the first active layer ACL1 may be formed of and / or include silicon (Si). Each of the first sacrificial layers SAL1 may have a germanium concentration in the range of 10 at% to 30 at%, where at% is atomic percentage.

[0133] A separation layer DSL may be formed on the uppermost first sacrificial layer SAL1. In an embodiment of the inventive concept, the thickness of the separation layer DSL may be greater than the thickness of the first sacrificial layer SAL1. The separation layer DSL may be formed of and / or include silicon (Si) or silicon-germanium (SiGe). In an embodiment in which the separation layer DSL is formed of and / or includes silicon-germanium (SiGe), a germanium concentration of the separation layer DSL may be greater than a germanium concentration of the first sacrificial layer SAL1. For example, the separation layer DSL may have a germanium concentration in a range of 40 at % to 90 at %.

[0134] A seed layer SDL may be formed on the separation layer DSL. The seed layer SDL may be formed of and / or include the same material as that of the first active layer ACL1. Second sacrificial layers SAL2 and second active layers ACL2 may be alternately stacked on the seed layer SDL. Each second sacrificial layer SAL2 may be formed of and / or include the same material as that of the first sacrificial layer SAL1, and each second active layer ACL2 may be formed of and / or include the same material as that of the first active layer ACL1. The separation layer DSL may be interposed between the first sacrificial layer SAL1 and the seed layer SDL.

[0135] Reference Figure 7B, a stack pattern STP may be formed by patterning the first and second sacrificial layers SAL1 and SAL2, the first and second active layers ACL1 and ACL2, and the separation layer DSL stacked on each other. Forming the stack pattern STP may include forming a hard mask pattern on the uppermost second active layer ACL2, and etching the stack layers SAL1, SAL2, ACL1, ACL2, SDL, and DSL on the semiconductor substrate 105 using the hard mask pattern as an etching mask. During the formation of the stack pattern STP, an upper portion of the semiconductor substrate 105 may be patterned to form a trench TR defining a single height cell SHC. The stack pattern STP may have a bar shape or a line shape extending along the second direction D2.

[0136] The stack pattern STP may include a lower stack pattern STP1 on the semiconductor substrate 105, an upper stack pattern STP2 on the lower stack pattern STP1, and a separation layer DSL between the lower stack pattern STP1 and the upper stack pattern STP2. The lower stack pattern STP1 may include a first sacrificial layer SAL1 and a first active layer ACL1 alternately stacked. The upper stack pattern STP2 may include a seed layer SDL, and may also include a second sacrificial layer SAL2 and a second active layer ACL2 alternately stacked on the seed layer SDL. A device isolation layer ST filling the trench TR may be formed on the semiconductor substrate 105.

[0137] Reference Figure 7C , a plurality of stack patterns STP may be disposed on the semiconductor substrate 105. The plurality of stack patterns STP may be spaced apart from each other across the device isolation layer ST. For example, the plurality of stack patterns STP may be spaced apart from each other in the first direction D1.

[0138] Reference FIG. 8A to FIG. 8E , a plurality of sacrificial patterns PP may be formed to extend across the stacked pattern STP. Each sacrificial pattern PP may be formed to have a line shape extending along the first direction D1. For example, forming the sacrificial pattern PP may include: forming a sacrificial layer on the front surface of the semiconductor substrate 105, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may be formed of and / or include one or more of amorphous silicon and polycrystalline silicon.

[0139] A pair of gate spacers GS may be formed on opposite sidewalls of the sacrificial pattern PP. For example, a spacer layer may be conformally formed on the front surface of the semiconductor substrate 105. The spacer layer may cover the sacrificial pattern PP and the hard mask pattern MP. The spacer layer may be formed of and / or include at least one material selected from SiCN, SiCON, and SiN. The spacer layer may be anisotropically etched to form the gate spacer GS.

[0140] The gate spacer GS and the hard mask pattern MP may be used as an etching mask to perform an etching process on the stack pattern STP. The etching process may form a recess RS between adjacent sacrificial patterns PP. The recess RS may cause the stack pattern STP to be formed to have a vertical bar shape.

[0141] A sacrificial contact pattern PLH may be formed in the semiconductor substrate 105 exposed by the recess RS. The sacrificial contact pattern PLH may be formed to have a contact shape. The sacrificial contact pattern PLH may be arranged along the second direction D2. The sacrificial contact pattern PLH may be formed of and / or include a material having an etching selectivity relative to the semiconductor substrate 105 (e.g., silicon-germanium (SiGe)). The sacrificial contact pattern PLH may be formed by an epitaxial growth process. The recess RS may expose the sacrificial contact pattern PLH. For example, the recess RS may overlap with the sacrificial contact pattern PLH.

[0142] In some embodiments, the separation layer DSL including silicon-germanium (SiGe) described previously may be replaced with a silicon-based dielectric material. The separation layer DSL exposed by the recess RS may be selectively removed, and the removed region of the separation layer DSL may be filled with a silicon-based dielectric material (eg, silicon nitride).

[0143] Reference 9A to 9C , the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 may be formed in the recess RS. For example, the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 may be formed by performing a first selective epitaxial growth (SEG) process using a sidewall or a seed layer of the lower stack pattern STP1 exposed by the recess RS. The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 may be grown from the first active layer ACL1 exposed by the recess RS. For example, the first SEG process may include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0144] During the first SEG process, impurities may be in-situ doped into the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. Alternatively, after forming the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2, impurities may be implanted into the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 may be doped to have a first conductivity type (e.g., n-type).

[0145] The first active layer ACL1 interposed between the pair of first lower source / drain patterns LSD1 and the pair of second lower source / drain patterns LSD2, respectively, may constitute a first lower channel pattern LCH1 and a second lower channel pattern LCH2. For example, the first active layer ACL1 may be formed in the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first lower channel pattern LCH1. The first active layer ACL1 may be formed as a fifth semiconductor pattern SP5 and a sixth semiconductor pattern SP6 of the second lower channel pattern LCH2. On the first region RG1, the first lower channel pattern LCH1 and the first lower source / drain pattern LSD1 may constitute a first active portion AR1 as a bottom layer of a three-dimensional device. On the third region RG3, the second lower channel pattern LCH2 and the second lower source / drain pattern LSD2 may constitute a fifth active portion AR5 as a bottom layer of the three-dimensional device.

[0146] The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 may each be formed to completely fill the space between the pair of first lower channel patterns LCH1 and between the pair of second lower channel patterns LCH2. For example, the first SEG process may be performed for a sufficient time until the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 fill the space between the pair of first lower channel patterns LCH1 and between the pair of second lower channel patterns LCH2 and connect the pair of first lower channel patterns LCH1 and the pair of second lower channel patterns LCH2 to each other.

[0147] The first interlayer dielectric layer 110 may be formed to cover the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. For example, before forming the first interlayer dielectric layer 110, an etch stop layer may be further formed to conformally cover the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. For example, before forming the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2, a portion of the first interlayer dielectric layer 110 may be first formed under the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2, and after forming the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2, another portion of the first interlayer dielectric layer 110 may be further formed.

[0148] In the recess RS, the first interlayer dielectric layer 110 may cover the sidewalls of the upper stack pattern STP2. Then, the upper portion of the first interlayer dielectric layer 110 may be removed to re-expose the sidewalls of the upper stack pattern STP2 in the recess RS. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 may be formed on the exposed sidewalls of the upper stack pattern STP2. For example, a second SEG process may be performed in which the sidewalls of the upper stack pattern STP2 exposed by the recess RS are used as seed layers to form the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 may be grown from the second active layer ACL2 or the seeds exposed by the recess RS. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 may be doped to have a second conductivity type (e.g., p-type) different from the first conductivity type.

[0149] The second active layer ACL2, each between a pair of first upper source / drain patterns USD1 and a pair of second upper source / drain patterns USD2, may constitute a first upper channel pattern UCH1 or a second upper channel pattern UCH2. For example, the second active layer ACL2 may be formed as a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 of the first upper channel pattern UCH1. The second active layer ACL2 may be formed as a seventh semiconductor pattern SP7 and an eighth semiconductor pattern SP8 of the second upper channel pattern UCH2. On the first region RG1, the first upper channel pattern UCH1 and the first upper source / drain pattern USD1 may constitute a second active portion AR2 as a top layer of a three-dimensional device. On the third region RG3, the second upper channel pattern UCH2 and the second upper source / drain pattern USD2 may constitute a sixth active portion AR6 as a bottom layer of a three-dimensional device. The second SEG process may be performed for a sufficient time to allow the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 to completely fill the space between the pair of first upper channel patterns UCH1 and the pair of second upper channel patterns UCH2.

[0150] The second interlayer dielectric layer 120 may be formed to cover the first and second upper source / drain patterns USD1 and USD2. For example, before forming the second interlayer dielectric layer 120, an etch stop layer may be further formed to conformally cover the first and second upper source / drain patterns USD1 and USD2.

[0151] After that, the second interlayer dielectric layer 120 may be planarized until the top surface of the sacrificial pattern PP is exposed. An etch-back or chemical mechanical polishing (CMP) process may be used to planarize the second interlayer dielectric layer 120. The hard mask pattern MP on the sacrificial pattern PP may be removed during the planarization process. As a result, the top surface of the second interlayer dielectric layer 120 may be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0152] Reference FIG. 10A to FIG. 10E , the exposed sacrificial pattern PP may be selectively removed. Removing the sacrificial pattern PP may include performing a wet etching process using an etchant that selectively etches polysilicon. Removing the sacrificial pattern PP may expose the first sacrificial layer SAL1 and the second sacrificial layer SAL2.

[0153] The first region RG1 may be subjected to an etching process of selectively etching the first sacrificial layer SAL1 and the second sacrificial layer SAL2, so that only the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may be removed while leaving the first to fourth semiconductor patterns SP1 to SP4 and the dummy channel pattern DSP. The third region RG3 may be subjected to an etching process of selectively etching the first to second sacrificial layers SAL1 and SAL2, so that only the first to second sacrificial layers SAL1 and SAL2 may be removed while leaving the fifth to twelfth semiconductor patterns SP5 to SP12 and the first and second dummy channel patterns DSP1 and DSP2.

[0154] The etching process may have a high etching rate relative to silicon-germanium. For example, the etching process may have a high etching rate relative to silicon-germanium having a germanium concentration greater than 10 at%.

[0155] A gate dielectric layer GI may be conformally formed in the region where the sacrificial pattern PP and the first and second sacrificial layers SAL1 and SAL2 are removed. A gate electrode GE may be formed on the gate dielectric layer GI. Forming the gate electrode GE may include forming first to fifth internal electrodes PO1 to PO5 between the first to fourth semiconductor patterns SP1 to SP4, and forming an external electrode PO6 in the region where the sacrificial pattern PP is removed. Before or after forming the gate electrode GE, a cutting pattern CT may also be formed in the region where the sacrificial pattern PP is removed.

[0156] The gate electrode GE may be recessed to have a reduced height. A gate capping pattern GP may be formed on the recessed gate electrode GE. The gate capping pattern GP may undergo a planarization process to allow the gate capping pattern GP to have a top surface coplanar with a top surface of the second interlayer dielectric layer 120. A third interlayer dielectric layer 130 may be formed to cover the gate electrode GE and the second interlayer dielectric layer 120.

[0157] Return to reference Figure 3 and FIG. 4A to FIG. 4E , a first upper active contact UAC1, a second upper active contact UAC2, and a third upper active contact UAC3 may be formed to penetrate the third interlayer dielectric layer 130 and a portion of the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be formed on the first to third upper active contacts UAC1 to UAC3 and the third interlayer dielectric layer 130. A first metal layer M1 including an upper line UMI may be formed in the fourth interlayer dielectric layer 140. An upper via UVI may be formed to electrically connect the first metal layer M1 to the gate contact GC and the upper active contact UAC. A back-end of line (BEOL) layer including additional layers (e.g., M2, M3, M4, etc.) may be formed on the first metal layer M1.

[0158] Thereafter, the semiconductor substrate 105 may be turned over (ie, reversed) to expose the rear surface of the semiconductor substrate 105. The exposed semiconductor substrate 105 may be selectively removed. Thus, the sacrificial contact pattern PLH may be exposed.

[0159] A lower dielectric layer may be formed on the exposed sacrificial contact pattern PLH. For example, the lower dielectric layer may be formed of a silicon-based dielectric material (eg, silicon oxide, silicon oxynitride, or silicon nitride). In an embodiment, the lower dielectric layer may be formed of the same material as the device isolation layer ST.

[0160] The lower dielectric layer may constitute the substrate 100. The substrate 100 may have a first surface 100a and a second surface 100b. A planarization process may be performed on the second surface 100b of the substrate 100 until the top surface of the sacrificial contact pattern PLH is exposed.

[0161] The sacrificial contact pattern PLH may be replaced by a lower active contact LAC. For example, the sacrificial contact pattern PLH may be selectively removed. An etching process may be further performed on the region from which the sacrificial contact pattern PLH is removed so that the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 are exposed. The lower active contact LAC may be formed to be coupled to the exposed first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. The lower active contact LAC may be formed in a self-aligned manner using the sacrificial contact pattern PLH.

[0162] A lower interlayer dielectric layer 210 may be formed on the second surface 100b of the substrate 100. A back metal layer BSM may be formed in the lower interlayer dielectric layer 210. The back metal layer BSM may include a lower line LMI. A lower via LVI may be formed to electrically connect the back metal layer BSM to the lower active contact LAC. In an embodiment, the lower via LVI may be formed to connect the lower active contact LAC to the lower line LMI. An additional back metal layer may be formed on the back metal layer BSM. In an embodiment of the inventive concept, the additional back metal layer may include a power delivery network.

[0163] In the three-dimensional semiconductor device according to the present inventive concept, the active contact, gate electrode and nanosheet on the logic cell can be formed to extend along the first direction. Therefore, the effective channel width of the nanosheet can be increased to improve the electrical characteristics of the device.

[0164] In a three-dimensional semiconductor device according to the present invention, an active contact portion connected to a source / drain pattern on a double-height cell can be provided. When the active contact portion extends to contact multiple source / drain patterns, the size of the dummy area between ordinary logic cells can be reduced to increase the integration of the device.

[0165] Although some embodiments of the present invention have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are only illustrative and not restrictive in all aspects.

Claims

1. A three-dimensional semiconductor device, comprising: A substrate including a first region and a second region; a first active portion on the first region, wherein the first active portion includes a first lower channel pattern and a first lower source / drain pattern connected to the first lower channel pattern; a second active portion on the first active portion, wherein the second active portion includes a first upper channel pattern and a first upper source / drain pattern connected to the first upper channel pattern; a third active portion on the second region, wherein the third active portion includes a second lower channel pattern and a second lower source / drain pattern connected to the second lower channel pattern; a fourth active portion on the third active portion, wherein the fourth active portion includes a second upper channel pattern and a second upper source / drain pattern connected to the second upper channel pattern; and a gate electrode on the first lower channel pattern and the second lower channel pattern and the first upper channel pattern and the second upper channel pattern, Wherein, a first width of the first lower channel pattern in the first direction is greater than a second width of the second lower channel pattern in the first direction.

2. The device according to claim 1, wherein The first width is 1.5 to 2.5 times the second width.

3. The device according to claim 1, wherein A third width of the first upper channel pattern in the first direction is the same as the first width.

4. The device according to claim 1, wherein A fourth width of the second upper channel pattern in the first direction is the same as the second width.

5. The device according to claim 1, wherein A third width of the first upper channel pattern in the first direction is the same as the first width, A fourth width of the second upper channel pattern in the first direction is the same as the second width, and The third width is greater than the fourth width.

6. The device according to claim 5, wherein The third width is 1.5 to 2.5 times the fourth width.

7. The device according to claim 1, further comprising: a lower active contact electrically connected to the first lower source / drain pattern; as well as A first upper active contact is electrically connected to the first upper source / drain pattern.

8. The device according to claim 7, further comprising: an upper line on the first active contact; as well as The lower line, below the lower active contact, wherein the upper line is electrically connected to the first upper active contact, and Wherein, the lower line is electrically connected to the lower active contact portion.

9. The device according to claim 1, wherein Each of the first and second lower channel patterns and the first and second upper channel patterns includes a plurality of semiconductor patterns that are stacked while being vertically spaced apart from each other, and The gate electrode surrounds the plurality of semiconductor patterns.

10. The device according to claim 1, further comprising: a dummy channel pattern between the first lower channel pattern and the first upper channel pattern, Wherein, the dummy channel pattern is spaced apart from the first lower source / drain pattern and the first upper source / drain pattern.

11. The device according to claim 10, further comprising: A seed layer, on the dummy channel pattern, Wherein, the seed layer is between the dummy channel pattern and the first upper channel pattern.

12. A three-dimensional semiconductor device, comprising: a first active portion on a substrate, wherein the first active portion includes a first lower channel pattern, a second lower channel pattern horizontally spaced apart from the first lower channel pattern, a first lower source / drain pattern connected to the first lower channel pattern, and a second lower source / drain pattern connected to the second lower channel pattern; a second active portion on the first active portion, wherein the second active portion includes a first upper channel pattern, a second upper channel pattern horizontally spaced apart from the first upper channel pattern, a first upper source / drain pattern connected to the first upper channel pattern, and a second upper source / drain pattern connected to the second upper channel pattern; a gate electrode on the first lower channel pattern and the second lower channel pattern and the first upper channel pattern and the second upper channel pattern; a lower active contact electrically connected to the first lower source / drain pattern and the second lower source / drain pattern; and a first upper active contact electrically connected to the first upper source / drain pattern and the second upper source / drain pattern, Wherein, the first active contact portion has a strip shape extending along a first direction, and The width of the first upper active contact in the first direction is greater than the maximum width of each of the first upper source / drain pattern and the second upper source / drain pattern.

13. The device according to claim 12, wherein The lower active contact comprises: a horizontal portion extending along the first direction; and A protruding portion contacts each of the first lower source / drain pattern and the second lower source / drain pattern.

14. The device according to claim 13, wherein A width of the horizontal portion in the first direction is greater than a maximum width of each of the first lower source / drain pattern and the second lower source / drain pattern.

15. The device according to claim 12, wherein: Each of the first and second lower channel patterns and the first and second upper channel patterns includes a plurality of semiconductor patterns that are stacked while being vertically spaced apart from each other, and The gate electrode surrounds the plurality of semiconductor patterns.

16. The device according to claim 12, further comprising: a first dummy channel pattern between the first lower channel pattern and the first upper channel pattern; as well as a second dummy channel pattern between the second lower channel pattern and the second upper channel pattern, wherein the first dummy channel pattern is spaced apart from the first lower source / drain pattern and the first upper source / drain pattern, and Wherein, the second dummy channel pattern is spaced apart from the second lower source / drain pattern and the second upper source / drain pattern.

17. A three-dimensional semiconductor device, comprising: A substrate including a first region, a second region, and a third region; a first single-height unit on the first region, wherein the first single-height unit includes a first active portion and a second active portion stacked on the first active portion; a plurality of second single-height cells on the second region and a dummy region between the plurality of second single-height cells, wherein each of the plurality of second single-height cells includes a third active portion and a fourth active portion stacked on the third active portion; a double height cell on the third region, wherein the double height cell comprises a fifth active portion, a sixth active portion stacked on the fifth active portion, a seventh active portion, and an eighth active portion stacked on the seventh active portion; a plurality of first gate electrodes on the first active portion and the second active portion, wherein each of the plurality of first gate electrodes has a strip shape extending along a first direction; A first upper active contact portion is provided between the plurality of first gate electrodes, wherein the first upper active contact portion has a strip shape extending along the first direction; a plurality of second gate electrodes on the third active portion and the fourth active portion, wherein each of the plurality of second gate electrodes has a strip shape extending along the first direction; a second upper active contact portion between the plurality of second gate electrodes, wherein the second upper active contact portion has a strip shape extending along the first direction; a plurality of third gate electrodes on the fifth active portion and the sixth active portion, wherein each of the plurality of third gate electrodes has a strip shape extending along the first direction; and A third upper active contact portion is provided between the plurality of third gate electrodes, wherein the third upper active contact portion has a strip shape extending along the first direction, Wherein, a first height of the first single-height unit in the first direction is in a range from 1.5 times to 2.5 times a second height of the second single-height unit in the first direction.

18. The device according to claim 17, wherein A width of the second upper active contact in the first direction is smaller than a width of the first upper active contact in the first direction and smaller than a width of the third upper active contact in the first direction.

19. The device according to claim 18, wherein A width of the first upper active contact in the first direction is the same as a width of the third upper active contact in the first direction.

20. The device according to claim 17, wherein Each of the first active portion, the third active portion, and the fifth active portion includes a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern of the corresponding active portion, each of the second active portion, the fourth active portion, and the sixth active portion includes an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern of the corresponding active portion, Each of the lower channel patterns and each of the upper channel patterns includes a plurality of semiconductor patterns that are stacked and vertically spaced apart from adjacent semiconductor patterns, and Each of the first gate electrode, the second gate electrode, and the third gate electrode surrounds a corresponding plurality of semiconductor patterns of one of the lower channel pattern and the upper channel pattern.

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