Driving back plate, epitaxial wafer, preparation method of epitaxial wafer, display module and electronic equipment

Abstract

The invention provides a driving backboard, an epitaxial wafer, a preparation method, a display module and electronic equipment, relates to the technical field of electronics, and is used for improving the efficiency of a light-emitting device in the display module. The driving backboard comprises a substrate, a driving circuit layer, a reflecting layer and a first bonding layer, and the driving circuit layer, the reflecting layer and the first bonding layer are sequentially arranged on the same side of the substrate. The reflecting layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the refractive indexes of the first dielectric layer and the second dielectric layer are different; in different driving backboards, the thickness, the material and the number of layers of the first dielectric layer and the second dielectric layer included in the reflecting layer can be different. And the first bonding layer is connected with the driving circuit layer and is used for realizing bonding of the driving backboard and the epitaxial wafer. When the driving backboard is applied to the display module, the structure of the reflecting layer can be adjusted according to the light-emitting wavelength of the light-emitting device, so that the reflectivity of the reflecting layer to red light, green light and blue light can reach more than 90%, and the efficiency of the light-emitting device is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a driving backplane, an epitaxial wafer and a preparation method, a display module, and an electronic device. Background Art

[0002] Micro light emitting diode (Micro LED) refers to LED with a size less than 100μm. Micro LED is the core light-emitting device of micro displays. Due to its advantages such as fast response, autonomous light emission, high brightness, low power consumption, high resolution and color saturation, Micro LED has become a research hotspot in the current display field.

[0003] At present, display modules including Micro LED are prepared by connecting the driving backplane with the Micro LED epitaxial wafer through bonding technology. However, the Micro LED display modules prepared by the current mainstream bonding process have problems such as low efficiency of Micro LED devices. Summary of the invention

[0004] The embodiments of the present application provide a driving backplane, an epitaxial wafer and a preparation method, a display module, and an electronic device for improving the efficiency of light-emitting devices in a display module.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a driving backplane is provided, comprising a substrate, a driving circuit layer, a reflecting layer and a first bonding layer, wherein the driving circuit layer, the reflecting layer and the first bonding layer are sequentially arranged on the same side of the substrate. The reflecting layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; in different driving backplanes, the thickness, material and number of layers of the first dielectric layer and the second dielectric layer included in the reflecting layer may be different. The first bonding layer is connected to the driving circuit layer through a conductive column, and is used to realize the bonding between the driving backplane and the epitaxial wafer.

[0007] The reflective layer of the driving backplane includes one or more first dielectric layers and one or more second dielectric layers stacked in layers. The number, thickness, and material of the first dielectric layer and the second dielectric layer can be adjusted according to the requirements. When the driving backplane is applied to the display module, the structure of the first dielectric layer and the second dielectric layer can be adjusted according to the light emission wavelength of the light-emitting device in the display module, so that the reflectivity of the reflective layer to red light, green light, and blue light can reach more than 90%, so as to improve the efficiency of the light-emitting device in the display module. In addition, the material of the reflective layer is an inorganic thin film material, which does not need to include heavy metal materials such as silver, and there is no heavy metal pollution problem. It is compatible with the standard production line process of the driving backplane, and the processing technology is simple, which can achieve low-cost mass production.

[0008] In one possible implementation, the material of the first bonding layer includes a transparent conductive material. The material of the first bonding layer in the driver backplane includes a transparent conductive material, which has a high light transmittance and can further improve the reflective light transmittance of the reflective layer. Moreover, the first bonding layer does not include metals such as gold, and there is no metal contamination problem. It is compatible with the standard production line process of the driver backplane, has a simple processing technology, and can achieve low-cost mass production.

[0009] In a possible implementation, there are multiple first dielectric layers and multiple second dielectric layers, and the multiple first dielectric layers and the multiple second dielectric layers are arranged alternately. The structure of the reflective layer can be flexibly deformed to optimize the reflectivity of the reflective layer to visible light of different wavelength bands as much as possible.

[0010] In a possible implementation, the first bonding layer covers the reflective layer. The driving backplane provided in the embodiment of the present application is suitable for scenarios with non-aligned bonding requirements.

[0011] In a possible implementation, the first bonding layer includes a first patterned bonding area and a first dielectric area; the first patterned bonding area is arranged in the first dielectric area and penetrates the first dielectric area along the thickness direction of the first dielectric area; the driving circuit layer includes a back-end metal interconnect pad, and the first patterned bonding area is connected to the back-end metal interconnect pad through a conductive column. The driving backplane provided in the embodiment of the present application is suitable for scenarios where alignment bonding is required.

[0012] In a possible implementation, the materials of the first dielectric layer and the second dielectric layer include silicon oxide, titanium dioxide, tantalum pentoxide or niobium pentoxide, which is a technically mature material selection, and there is no need to develop new dielectric materials.

[0013] In a possible implementation, the material of the first dielectric region includes silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide or niobium pentoxide, which is a technically mature material selection, and there is no need to develop new dielectric materials.

[0014] In a possible implementation, the material of the first patterned bonding region includes indium tin oxide, zinc aluminum oxide or transparent conductive oxide, which is a mature material selection technology, and there is no need to develop new transparent conductive materials.

[0015] According to a second aspect of the embodiment of the present application, an epitaxial wafer is provided, comprising: a substrate, an epitaxial stack and a second bonding layer; the epitaxial stack and the second bonding layer are sequentially arranged on the same side of the substrate. The second bonding layer is used to achieve bonding between the epitaxial wafer and the driving backplane; the material of the second bonding layer includes a transparent conductive material.

[0016] The material of the second bonding layer in the epitaxial wafer includes a transparent conductive material. The light transmittance of the transparent conductive material is higher than that of the metal material, which can further improve the efficiency of the light-emitting device. In addition, the second bonding layer does not include metals such as gold, so there is no metal pollution problem, and low-cost mass production can be achieved. Furthermore, the second bonding layer can be directly reused as an electrode layer, simplifying the film layer structure of the epitaxial wafer and simplifying the preparation process.

[0017] In a possible implementation, the second bonding layer covers the epitaxial stack. The driving backplane provided in the embodiment of the present application is suitable for scenarios with non-aligned bonding requirements.

[0018] In a possible implementation, the second bonding layer includes a second patterned bonding area and a second dielectric area; the second patterned bonding area is arranged in the second dielectric area and penetrates the second dielectric area along the thickness direction of the second dielectric area. The driving backplane provided in the embodiment of the present application is suitable for scenarios where alignment bonding is required.

[0019] In a possible implementation, the material of the second dielectric region includes silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide or niobium pentoxide, which is a technically mature material selection, and there is no need to develop new dielectric materials.

[0020] In a possible implementation, the material of the second patterned bonding region includes indium tin oxide, zinc aluminum oxide or transparent conductive oxide, which is a mature material selection technology, and there is no need to develop new transparent conductive materials.

[0021] In a possible implementation, the epitaxial stack includes a second semiconductor layer, an active layer, and a first semiconductor layer stacked in sequence on one side of the substrate; the first semiconductor layer is an N-type semiconductor layer and the second semiconductor layer is a P-type semiconductor layer. This light-emitting structure has a simple structure and a wide range of applications.

[0022] In a possible implementation, the epitaxial wafer further includes a first electrode layer, and the first electrode layer is disposed between the second bonding layer and the epitaxial stack. In this structure, the material of the first electrode layer and the material of the second bonding layer can be different materials.

[0023] In a third aspect of the embodiments of the present application, a display module is provided, comprising a substrate and a driving circuit layer, a reflective layer, a bonding layer and a plurality of light-emitting devices arranged in sequence on one side of the substrate. The reflective layer comprises a first dielectric layer and a second dielectric layer stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; the bonding layer is connected to the light-emitting device and is connected to the driving circuit layer through a conductive column.

[0024] In the display module provided in the embodiment of the present application, the reflective layer includes one or more first dielectric layers and one or more second dielectric layers stacked in layers, and the number of layers, thickness, and material of the first dielectric layer and the second dielectric layer can be adjusted according to the requirements. The structure of the first dielectric layer and the second dielectric layer can be adjusted according to the light emission wavelength of the light-emitting device in the display module, so that the reflectivity of the reflective layer to red light, green light, and blue light can reach more than 90%, so as to improve the light emission efficiency of the display module. In addition, the material of the reflective layer is an inorganic thin film material, which does not need to include heavy metal materials such as silver, and there is no heavy metal pollution problem. It is compatible with the standard process of the production line, and the processing technology is simple, which can achieve low-cost mass production.

[0025] In one possible implementation, the material of the bonding layer includes a transparent conductive material. The transparent conductive material has a high light transmittance, which can further improve the light extraction efficiency of the display module. Moreover, the bonding layer does not include metals such as gold, so there is no metal contamination problem, it is compatible with the standard process of the production line, the processing technology is simple, and low-cost mass production can be achieved.

[0026] In a possible implementation, the bonding layer includes a patterned bonding area and a dielectric area; the patterned bonding area is arranged in the dielectric area and penetrates the dielectric area along the thickness direction of the dielectric area. The materials of the patterned bonding area and the dielectric area are both transparent materials, which can further improve the efficiency of the light-emitting device.

[0027] In a possible implementation, the sum of the thickness of the bonding layer and the reflective layer ranges from 100 nm to 2000 nm. Based on the characteristics of the bonding layer provided in the present application, the thickness of the bonding layer can be less than 2000 nm, making the subsequent etching process easy to perform.

[0028] In one possible implementation, the light-emitting device includes a first semiconductor layer, an active layer, a second semiconductor layer, and a second electrode, which are sequentially arranged in a direction away from the bonding layer; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

[0029] In a possible implementation, the light emitting device further includes a first electrode, which is disposed between the first semiconductor layer and the bonding layer. In this structure, the first electrode is an independent film layer, and the bonding layer is not reused as the first electrode, which can reduce restrictions on the bonding layer material.

[0030] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising a display module and a processor, wherein the processor is used to control the display module to display an image; the display module comprises the display module of any one of the third aspects.

[0031] In a fifth aspect of the embodiments of the present application, a method for preparing a driving backplane is provided, comprising: forming a driving circuit layer on a substrate; forming a reflecting layer on the side of the driving circuit layer away from the substrate; the reflecting layer comprises a first dielectric layer and a second dielectric layer stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; forming a first bonding layer on the side of the reflecting layer away from the substrate; the first bonding layer is connected to the driving circuit layer through a conductive column. The beneficial effects of the driving backplane obtained by the preparation method provided by the embodiments of the present application are the same as the beneficial effects of the driving backplane provided by the first aspect, and will not be repeated here.

[0032] In a possible implementation, forming a first bonding layer on a side of the reflective layer away from the substrate includes: depositing the first bonding layer covering the reflective layer on a side of the reflective layer away from the substrate, wherein the material of the first bonding layer includes a transparent conductive material.

[0033] In a possible implementation, the first bonding layer includes a first patterned bonding area and a first dielectric area, and the first bonding layer is formed on the side of the reflective layer away from the substrate, including: depositing a first bonding film covering the reflective layer on the side of the reflective layer away from the substrate, the material of the first bonding film includes a transparent conductive material; patterning the first bonding film to form a first patterned bonding area; coupling the first patterned bonding area to the back-end metal interconnection pad of the driving circuit layer; forming a first dielectric area on the side of the reflective layer away from the substrate, the first dielectric area wrapping the side first dielectric area of ​​the first patterned bonding area.

[0034] In a sixth aspect of the embodiment of the present application, a method for preparing an epitaxial wafer is provided, comprising: forming an epitaxial stack on a substrate; forming a second bonding layer on a side of the epitaxial stack away from the substrate; the material of the second bonding layer includes a transparent conductive material. The beneficial effects of the epitaxial wafer obtained by the preparation method provided by the embodiment of the present application are the same as the beneficial effects of the epitaxial wafer provided by the second aspect, and will not be repeated here.

[0035] In a possible implementation, forming a second bonding layer on the side of the epitaxial stack away from the substrate includes: depositing the second bonding layer covering the epitaxial stack on the side of the epitaxial stack away from the substrate. In this structure, the second bonding layer is reused as the first electrode layer, which can simplify the preparation process of the epitaxial wafer.

[0036] In a possible implementation, the second bonding layer includes a second patterned bonding area and a second dielectric area, and the second bonding layer is formed on the side of the epitaxial stack away from the substrate, including: forming a second bonding film on the side of the epitaxial stack away from the substrate, the material of the second bonding film is a transparent conductive material; patterning the second bonding film to form a plurality of second patterned bonding areas; forming a second dielectric area on the side of the first electrode layer away from the substrate, the second dielectric area wrapping the side second dielectric area of ​​the second patterned bonding area. In this structure, part of the second patterned bonding area is reused as the first electrode layer, which can simplify the preparation process of the epitaxial wafer.

[0037] In a possible implementation, before forming the second bonding layer on the side of the epitaxial stack away from the substrate, the preparation method further includes: forming a first electrode layer on the side of the epitaxial stack away from the substrate. In this structure, the epitaxial wafer includes the first electrode layer, which can reduce the restrictions on the material of the second bonding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0039] Figure 2A A schematic diagram of a manufacturing process of a display module according to an embodiment of the present application;

[0040] Figure 2B A schematic diagram of a manufacturing process of a display module according to an embodiment of the present application;

[0041] Figure 3A A schematic diagram of the structure of a driving backplane provided in an embodiment of the present application;

[0042] Figure 3B A schematic diagram of the structure of an epitaxial wafer provided in an embodiment of the present application;

[0043] Figure 3C A schematic diagram of the structure of a bonded wafer provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a process for preparing a driving backplane provided in an embodiment of the present application;

[0045] Figure 5-Figure 9 A schematic diagram of a process for preparing a driving backplane provided in an embodiment of the present application;

[0046] Fig.10 A schematic diagram of a process for preparing an epitaxial wafer provided in an embodiment of the present application;

[0047] Figure 11-13 A schematic diagram of a process for preparing a stretched sheet provided in an embodiment of the present application;

[0048] Fig.14A and Fig. 14B A schematic diagram of the structure of a bonded wafer provided in an embodiment of the present application;

[0049] Fig.15 A schematic diagram of another process for preparing a driving backplane provided in an embodiment of the present application;

[0050] Fig.16 A schematic diagram of another process for preparing an epitaxial wafer provided in an embodiment of the present application;

[0051] Figure 17-Figure 22 Another schematic diagram of the preparation process of a stretched sheet is provided for the embodiment of the present application;

[0052] Fig.23A and Fig. 23B A schematic diagram of the structure of another bonded wafer provided in an embodiment of the present application;

[0053] Fig.24A and Fig. 24B A schematic diagram of the structure of a display module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0055] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0056] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to the change of the orientation of the components in the drawings.

[0057] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0058] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0059] The embodiment of the present application provides an electronic device, which is, for example, a consumer electronic product with a display module, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Consumer electronic products include virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, mixed reality (MR) electronic devices, mobile phones, tablet computers, notebooks, personal digital assistants (PDAs), etc. Home electronic products include smart door locks, rechargeable small household appliances (such as soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted computers, etc. The embodiment of the present application does not impose any special restrictions on the specific forms of the above-mentioned electronic devices.

[0060] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application.

[0061] AR electronic devices are wearable devices that can be worn on the human head for display. Through computer technology, they can superimpose virtual information onto the real world, allowing the real environment and virtual objects to be superimposed on the same screen in real time, achieving mutual complementation of the two types of information, and interacting with visual, auditory and other information. They also display images in front of the user's eyes through helmets, glasses and other devices, enhancing the user's sense of reality.

[0062] Take the electronic device as AR glasses as an example. Figure 1 As shown, the AR glasses include a display module 1, a frame 2 and a lens 3.

[0063] The frame 2 includes a temple 21, and the display module 1 can be arranged on the temple 21, that is, the display module 1 is placed sideways. The frame 2 is also equipped with a lens 3, for example, the frame 2 is fixed to the lens 3. Alternatively, the frame 2 also includes a frame 22, and the lens 3 is installed in the frame 22.

[0064] In some embodiments, an optical waveguide structure is also integrated in the AR glasses, and the optical waveguide structure includes three parts: incident light coupling, waveguide, and outgoing light coupling. For example, the optical waveguide structure is integrated in the lens 3. The optical signal emitted by the display module 1 is coupled into the waveguide part through the incident coupling part, and the light coupled into the waveguide part adjusts the transmission direction of the light through the waveguide part, and enters the human eye through the outgoing light coupling part, thereby realizing the transmission of the optical signal of the display module 1 to the entrance pupil of the human eye.

[0065] The display module 1 included in the AR glasses may be one or more. In the embodiment of the present application, the AR glasses are illustrated by taking the example of including one display module 1 .

[0066] In some embodiments, the AR glasses further include a processor, and the processor is used to control the display module 1 to display images.

[0067] Micro light emitting diodes (Micro LEDs) are widely used as Micro LED light-emitting chips in micro-sized display modules 1 due to their advantages such as fast response, autonomous light emission, high brightness, low power consumption, high resolution and color saturation. How to manufacture display modules 1 on a large scale and at low cost is one of the key factors for the penetration of Micro LED technology. At present, display modules including Micro LEDs are prepared by connecting a driving backplane to an epitaxial wafer through bonding technology.

[0068] In one implementation, bonding layers are respectively made on the driving backplane and the epitaxial wafer, and then a bonding process is performed to connect the driving backplane and the epitaxial wafer, and finally the bonded wafer is processed to form the display module 1 .

[0069] Figure 2A A schematic diagram of a preparation process of a display module according to an embodiment of the present application.

[0070] In some embodiments, Figure 2A As shown, the process of preparing the display module 1 includes: forming a driving backplane 30, the driving backplane 30 includes a substrate 31, a driving circuit layer 32, a reflective layer 34 (the material is a metal with a high reflectivity, such as silver (Ag)), and a first bonding layer 33 covering the surface of the reflective layer 34, and the material of the first bonding layer 33 includes a gold / tin (Au / Sn) alloy. Forming an epitaxial wafer 40, the epitaxial wafer 40 includes a substrate 41, an epitaxial stack 42′, and a second bonding layer 44, and the material of the second bonding layer 44 includes a gold / tin alloy. Bonding the first bonding layer 33 of the driving backplane 30 to the second bonding layer 44 of the epitaxial wafer 40 to form a bonded wafer. Then processing the bonded wafer to form the display module 1 (this step Figure 2A not shown).

[0071] In the above process, the materials of the first bonding layer 33 and the second bonding layer 44 include gold / tin alloy, and the reflectivity of the gold material to the visible light wavelength band is about 40%-90%, and the reflectivity of the red light / green light / blue light wavelength bands is very different, the reflectivity of the blue light wavelength band is about 30%-40%, the reflectivity of the green light wavelength band is about 70%, and the reflectivity of the red light wavelength band is greater than 80%. In order to improve the efficiency of the light-emitting device, a reflective layer 34 needs to be provided to improve the reflectivity, thereby improving the efficiency of the light-emitting device. However, after the reflective layer 34 is provided, the improvement of the reflectivity of the visible light wavelength band by the stack of the reflective layer 34, the first bonding layer 33 and the second bonding layer 44 is not ideal.

[0072] Figure 2B A schematic diagram of a preparation process of a display module according to an embodiment of the present application.

[0073] In some embodiments, Figure 2B As shown, the process of preparing the display module 1 includes: forming a driving backplane 30, the driving backplane 30 includes a substrate 31, a driving circuit layer 32, a reflective layer 34 (the material is a metal with a high reflectivity, such as silver), and a first bonding layer 33, the first bonding layer 33 includes a first patterned bonding area 331 and a first dielectric area 332 wrapping the first patterned bonding area 331, and the material of the first patterned bonding area 331 includes copper (Cu). Forming an epitaxial wafer 40, the epitaxial wafer 40 includes a substrate 41, a light-emitting structure 42, and a second bonding layer 44, the second bonding layer 44 includes a second patterned bonding area 441 and a second dielectric area 442 wrapping the second patterned bonding area 441, and the material of the second patterned bonding area 441 includes copper. The first bonding layer 33 of the driving backplane 30 is bonded to the second bonding layer 44 of the epitaxial wafer 40, and the first patterned bonding area 331 and the second patterned bonding area 441 are aligned and bonded to each other to form a bonded wafer. Then the bonded wafers are processed to form a display module 1 (this step Figure 2B not shown).

[0074] In the above process, the materials of the first patterned bonding area 331 and the second patterned bonding area 441 include copper, and the reflectivity of the copper material to the visible light wavelength band is about 60%-90%, and the reflectivity of the red light / green light / blue light wavelength bands is very different, the reflectivity of the blue light wavelength band is about 60%-70%, the reflectivity of the green light wavelength band is about 60%-70%, and the reflectivity of the red light wavelength band is about 90%. In order to improve the efficiency of the light-emitting device, a reflective layer 34 needs to be set to improve the reflectivity, thereby improving the efficiency of the light-emitting device. However, after the reflective layer 34 is set, the improvement of the reflectivity of the visible light wavelength band by the stack of the reflective layer 34, the first bonding layer 33 and the second bonding layer 44 is not ideal.

[0075] The embodiment of the present application provides a new driving backplane 30 and epitaxial wafer 40 for improving the device efficiency of the display module 1 .

[0076] Figure 3A A schematic diagram of the structure of a driving backplane provided in an embodiment of the present application.

[0077] The embodiment of the present application provides a driving backplane 30, such as Figure 3A As shown, the driving backplane 30 includes a substrate 31 , a driving circuit layer 32 , a reflective layer 34 and a first bonding layer 33 , and the driving circuit layer 32 , the reflective layer 34 and the first bonding layer 33 are sequentially arranged on one side of the substrate 31 .

[0078] In some embodiments, the reflective layer 34 includes a first dielectric layer 341 and a second dielectric layer 342 which are stacked, and the first dielectric layer 341 and the second dielectric layer 342 have different refractive indices.

[0079] For example, the first dielectric layer 341 and the second dielectric layer 342 are made of different materials, so that the refractive indexes of the first dielectric layer 341 and the second dielectric layer 342 are different.

[0080] Optionally, the materials of the first dielectric layer 341 and the second dielectric layer 342 are both transparent dielectric materials. For example, the materials of the first dielectric layer 341 and the second dielectric layer 342 include inorganic materials such as silicon oxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), and niobium pentoxide (Nb2O5). In one possible implementation, the material of the first dielectric layer 341 is SiO2, and the material of the second dielectric layer 342 is TiO2. In another possible implementation, the material of the first dielectric layer 341 is SiO2, and the material of the second dielectric layer 342 is Ta2O5. In yet another implementation, the material of the first dielectric layer 341 is SiO2, and the material of the second dielectric layer 342 is Nb2O5.

[0081] In some embodiments, the reflective layer 34 includes only a first dielectric layer 341 and a second dielectric layer 342 , and the first dielectric layer 341 and the second dielectric layer 342 are stacked along the thickness direction of the driving backplane 30 .

[0082] In other embodiments, Figure 3A As shown, there are multiple first dielectric layers 341 in the reflective layer 34 , and there are multiple second dielectric layers 342 in the reflective layer 34 . The multiple first dielectric layers 341 and the multiple second dielectric layers 342 are alternately arranged along the thickness direction of the driving backplane 30 .

[0083] Alternatively, it can be understood that one first dielectric layer 341 and one second dielectric layer 342 are regarded as a repetition period, and multiple first dielectric layers 341 and multiple second dielectric layers 342 are divided into multiple repetition periods, and multiple repetition periods are stacked along the thickness direction of the driving backplane 30. The thickness of the first dielectric layer 341 in each repetition period can be equal or unequal. The thickness of the second dielectric layer 342 in each repetition period can be equal or unequal.

[0084] For example, the material of the first dielectric layer 341 in each repetition period is the same, and the material of the second dielectric layer 342 in each repetition period is the same.

[0085] In the driving backplane 30 provided in the embodiment of the present application, the reflective layer 34 includes one or more first dielectric layers 341 and one or more second dielectric layers 342 which are stacked, and the number, thickness, and material of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the demand. When the driving backplane 30 is applied to the display module 1, the structure of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the light emission wavelength of the light-emitting device in the display module 1, so that the reflectivity of the reflective layer 34 to red light, green light, and blue light can reach more than 90%, so as to improve the efficiency of the light-emitting device in the display module 1. In addition, the material of the reflective layer 34 is an inorganic thin film material, and there is no need to include heavy metal materials such as silver (Ag), and there is no heavy metal pollution problem. It is compatible with the standard production line process of the driving backplane 30, and the processing technology is simple, and low-cost mass production can be achieved.

[0086] In some embodiments, the first bonding layer 33 is connected to the driving circuit layer 32 through a conductive column. For example, the driving backplane 30 includes a first conductive column 35 that penetrates the reflecting layer 34 along the thickness direction of the reflecting layer 34, and both ends of the first conductive column 35 are connected to the first bonding layer 33 and the driving circuit layer 32 respectively, so as to realize the connection between the first bonding layer 33 and the driving circuit layer 32.

[0087] Illustratively, the material of the first bonding layer 33 includes metal.

[0088] Alternatively, for example, the material of the first bonding layer 33 includes a transparent conductive material.

[0089] For example, the material of the first bonding layer 33 includes indium tin oxide (ITO), aluminum zinc oxide (AZO), transparent conductive oxide (TCO), and the like.

[0090] In the embodiment of the present application, the material of the first bonding layer 33 in the driving backplane 30 includes a transparent conductive material, and the light transmittance of the transparent conductive material is higher than that of the metal material, which can further improve the efficiency of the light-emitting device. Moreover, the first bonding layer 33 does not include metals such as gold (Au), and there is no metal contamination problem. It is compatible with the standard production line process of the driving backplane 30, and the processing technology is simple, which can achieve low-cost mass production.

[0091] Figure 3B A schematic diagram of the structure of an epitaxial wafer provided in an embodiment of the present application.

[0092] The present application embodiment provides an epitaxial wafer 40, such as Figure 3B As shown, the epitaxial wafer 40 includes a substrate 41, an epitaxial stack 42', a first electrode layer 45 and a second bonding layer 44. The epitaxial stack 42', the first electrode layer 45 and the second bonding layer 44 are sequentially arranged on one side of the substrate 41.

[0093] The second bonding layer 44 is connected to the first electrode layer 45 , and the material of the second bonding layer 44 includes a transparent conductive material.

[0094] For example, the material of the second bonding layer 44 includes ITO, AZO, TCO, etc. In some embodiments, the material of the first bonding layer 33 is the same as the material of the second bonding layer 44 .

[0095] In some embodiments, the material of the first electrode layer 45 includes a transparent conductive material. For example, the material of the first electrode layer 45 includes ITO, AZO, TCO, etc. For example, the material of the first electrode layer 45 is the same as the material of the second bonding layer 44 .

[0096] In some embodiments, the first electrode layer 45 and the second bonding layer 44 are an integrally formed structure, and the two are simultaneously prepared using the same process.

[0097] For example, the second bonding layer 44 is reused as the first electrode layer 45. Alternatively, part of the second bonding layer 44 is used as the first electrode layer 45. In this structure, the film structure of the epitaxial wafer 40 is simple, and the preparation process can also be simplified.

[0098] In the embodiment of the present application, the material of the second bonding layer 44 in the epitaxial wafer 40 includes a transparent conductive material, and the light transmittance of the transparent conductive material is higher than that of the metal material, which can further improve the efficiency of the light-emitting device. Moreover, the second bonding layer 44 does not include metals such as gold (Au), and there is no metal pollution problem, which can achieve low-cost mass production.

[0099] Figure 3C A schematic diagram of the structure of a bonded wafer provided in an embodiment of the present application.

[0100] like Figure 3CAs shown, a first bonding layer 33 is prepared on the driving backplane 30 , and a second bonding layer 44 is prepared on the epitaxial wafer 40 . The first bonding layer 33 and the second bonding layer 44 are bonded to form a bonded wafer to achieve connection between the driving backplane 30 and the epitaxial wafer 40 .

[0101] In some embodiments, the sum L3 of the thickness of the first bonding layer 33 and the second bonding layer 44 after bonding and the reflective layer 34 is in the range of 100 nm to 2000 nm. For example, the sum L3 is 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm.

[0102] Based on the structure of the first bonding layer 33, the second bonding layer 44 and the reflective layer 34 provided in the present application, the sum L3 of the thickness of the first bonding layer 33 and the second bonding layer 44 after bonding and the reflective layer 34 can be less than 2000nm, making the subsequent etching process easy to carry out.

[0103] The following is an exemplary description of the method for preparing the driving backplane 30 and the method for preparing the epitaxial wafer 40 provided in the embodiments of the present application.

[0104] Example 1

[0105] Figure 4 A schematic diagram of a process for preparing a driving backplane provided in an embodiment of the present application is shown in FIG. Figure 5-Figure 9 A schematic diagram of a process for preparing a driving backplane provided in an embodiment of the present application.

[0106] The present application provides a method for preparing a driving backplane. Figure 4 As shown, the preparation method comprises:

[0107] S1, such as Figure 5 As shown, a driving circuit layer 32 is formed on a substrate 31 .

[0108] For example, the substrate 31 is a single crystal silicon (Si) substrate, and a driving circuit layer 32 is formed on the substrate 31 using a complementary metal oxide semiconductor (CMOS) process. For example, a transistor and other structures are formed by a front end of line (FEOL) process as the FEOL layer of the driving backplane 30. A wiring layer, a via, and a back-end metal interconnect pad (Pad) and other structures are formed by a back end of line (BEOL) process as the BEOL layer of the driving backplane 30. The back-end metal interconnect pads of the driving circuit layer 32 include a plurality of pads, etc.

[0109] S2, such as Figure 6 As shown, a reflective film 34 ′ is formed on the side of the driving circuit layer 32 away from the substrate 31 .

[0110] The reflective film 34' includes a first dielectric film 341' and a second dielectric film 342' which are stacked. When the reflective film 34' includes multiple layers of the first dielectric film 341' and multiple layers of the second dielectric film 342', the multiple layers of the first dielectric film 341' and the multiple layers of the second dielectric film 342' are alternately arranged.

[0111] For example, the first dielectric film 341' and the second dielectric film 342' in the reflective film 34' have different materials or thicknesses. The multi-layer first dielectric film 341' has the same material but different thicknesses. The multi-layer second dielectric film 342' has the same material but different thicknesses.

[0112] For example, the material of the first dielectric film 341' is SiO2, and the material of the second dielectric film 342' is TiO2. Or for example, the material of the first dielectric film 341' is SiO2, and the material of the second dielectric film 342' is Ta2O5. Or for example, the material of the first dielectric film 341' is SiO2, and the material of the second dielectric film 342' is Nb2O5.

[0113] The embodiment of the present application does not limit the number of layers, thickness of each layer, and material of each layer of the first dielectric film 341 ′ and the second dielectric film 342 ′ in the reflective layer 34 , and can be adjusted in combination with the desired reflectivity of the reflective layer 34 . Figure 6 In the figure, the reflective layer 34 includes a plurality of first dielectric films 341' and a plurality of second dielectric films 342' stacked together as an example.

[0114] S3, such as Figure 7 As shown, via holes are formed in the reflective film 34 ′ to form the reflective layer 34 .

[0115] The via hole penetrates the reflective film 34' and communicates with the back-end metal interconnect pad of the driving circuit layer 32. For example, the reflective film 34' is patterned by exposure, development, etching and other processes to form the reflective layer 34.

[0116] S4, such as Figure 8 As shown, a first conductive column 35 is formed in the via hole in the reflective layer 34 .

[0117] For example, step S4 includes:

[0118] S41 , depositing a metal film on the reflective layer 34 , wherein the metal film fills the via holes to connect with the back-end metal interconnect pads and covers the reflective layer 34 .

[0119] For example, the material of the metal film includes aluminum (Al), tungsten (W), and other metals with low impedance and good hole-filling effect.

[0120] S42, planarize the metal film by etching or chemical mechanical polishing, remove the metal film on the surface of the reflective layer 34, and keep the metal film in the via hole to form a first conductive column 35. The material of the first conductive column 35 includes metals such as aluminum and tungsten.

[0121] S5, such as Fig. 9 As shown, a first bonding layer 33 is formed on a side of the reflective layer 34 away from the substrate 31 .

[0122] For example, step S5 includes: depositing a first bonding layer 33 covering the reflective layer 34 and the first conductive pillar 35 on the side of the reflective layer 34 away from the substrate 31, the first bonding layer 33 is connected to the first conductive pillar 35, and the first bonding layer 33 is connected to the back-end metal interconnect pad of the driving circuit layer 32 through the first conductive pillar 35.

[0123] In some embodiments, the first bonding layer 33 covers the reflective layer 34 and the first conductive pillars 35 , and the material of the first bonding layer 33 is a transparent conductive material.

[0124] At this point, the driving backplane 30 provided in the embodiment of the present application is prepared. The first bonding layer 33 in the driving backplane 30 provided in this example is a structure in which the entire layer is made of conductive material. When the driving backplane 30 is subsequently bonded to the epitaxial wafer 40, a non-alignment process can be used for bonding, which can reduce the process difficulty.

[0125] Fig.10 A schematic diagram of a preparation process of an epitaxial wafer provided in an embodiment of the present application, Figure 11-13 A schematic diagram of a process for preparing a stretched sheet provided in an embodiment of the present application.

[0126] The present application embodiment provides a method for preparing an epitaxial wafer 40, such as Fig.10 As shown, the preparation method comprises:

[0127] S10, such as Fig.11 As shown, an epitaxial stack 42 ′ is formed on a substrate 41 .

[0128] The substrate 41 includes, for example, a sapphire substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a single crystal silicon substrate, a zinc oxide (ZnO) substrate, or the like.

[0129] In some embodiments, step S10 includes:

[0130] S101 , forming a nucleation film 421 ′ on a substrate 41 .

[0131] For example, the nucleation film 421 ′ may be formed by a metal-organic chemical vapor deposition (MOCVD) growth method or a molecular beam epitaxy (MBE) growth method.

[0132] The material of the nucleation film 421 ′ may include, for example, one or more of GaN, aluminum gallium nitride (AlGaN), and aluminum nitride (AlN).

[0133] S102 , forming a buffer film 422 ′ on a side of the nucleation film 421 ′ away from the substrate 41 .

[0134] For example, an AlGaN graded layer with a gradually decreasing Al (aluminum) component may be epitaxially grown using a MOCVD process.

[0135] The buffer film 422 ′ may be a graded buffer layer. The buffer film 422 ′ may be a GaN layer, an AlN / GaN superlattice structure layer, or a combination layer of the aforementioned structures.

[0136] S103 , forming a second semiconductor film 423 ′ on a side of the buffer film 422 ′ away from the substrate 41 .

[0137] For example, the second semiconductor film 423' is formed by using an MOCVD growth method or an MBE growth method.

[0138] S104 , forming an active film 424 ′ on a side of the second semiconductor film 423 ′ away from the substrate 41 .

[0139] The active film 424 ′ is used to emit light of different colors. The material of the active film 424 ′ includes, for example, indium gallium nitride (InGaN). By adjusting the In component in InGaN, light of different colors can be emitted.

[0140] S105 , forming a first semiconductor film 425 ′ on a side of the active film 424 ′ away from the substrate 41 .

[0141] For example, the first semiconductor film 425' is formed by using an MOCVD growth method or an MBE growth method.

[0142] In some embodiments, the second semiconductor film 423 ′ and the first semiconductor film 425 ′ are an N-type semiconductor film and a P-type semiconductor film, respectively.

[0143] For example, the second semiconductor film 423′ may be an N-type semiconductor film. For example, the N-type semiconductor film may be formed by doping in a semiconductor material, such as gallium nitride. In an N-type semiconductor film, free electrons are majority carriers and holes are minority carriers, and the free electrons are mainly used for conducting electricity. The higher the concentration of free electrons, the stronger the conductivity of the N-type semiconductor film.

[0144] The first semiconductor film 425' may be a P-type semiconductor film. For example, the P-type semiconductor film may be formed by doping in a semiconductor material, such as gallium nitride. In a P-type semiconductor film, holes are majority carriers and free electrons are minority carriers, and the conduction is mainly carried out by holes. The higher the concentration of holes, the stronger the conductivity of the P-type semiconductor film.

[0145] In some embodiments, the epitaxial stack 42′ includes a nucleation film 421′, a buffer film 422′, a second semiconductor film 423′, an active film 424′, and a first semiconductor film 425′. The structure of the epitaxial stack 42′ provided in the embodiment of the present application is only a schematic diagram, and film layers can be increased or reduced on the basis of the above structure. For example, the epitaxial stack 42′ only includes the first semiconductor film 425′, the active film 424′, and the second semiconductor film 423′. When the epitaxial wafer is bonded to the driving backplane using a non-aligned process, the first semiconductor film 425′, the active film 424′, and the second semiconductor film 423′ serve as the first semiconductor layer 425, the active layer 424, and the second semiconductor layer 423 of the epitaxial stack 42′.

[0146] S20, such as Fig.12 and Fig.13 As shown, a first electrode layer 45 and a second bonding layer 44 are formed on a side of the epitaxial stack 42 ′ away from the substrate 41 .

[0147] In some embodiments, Fig.12 As shown, step S20 includes:

[0148] S21 . Form a first electrode layer 45 on a side of the epitaxial stack 42 ′ away from the substrate 41 .

[0149] For example, the material of the first electrode layer 45 includes a transparent conductive material. The first electrode layer 45 is disposed on the surface of the first semiconductor film 425' and connected to the first semiconductor film 425'. When the first semiconductor film 425' is a P-type semiconductor layer, the first electrode layer 45 connected to the first semiconductor film 425' is a P-electrode.

[0150] S22 , forming a second bonding layer 44 on a side of the first electrode layer 45 away from the substrate 41 .

[0151] For example, step S22 includes: depositing a second bonding layer 44 covering the first electrode layer 45 on a side of the first electrode layer 45 away from the substrate 41 . In some embodiments, the second bonding layer 44 covers the first electrode layer 45 .

[0152] The second bonding layer 44 is connected to the first electrode layer 45. For example, the second bonding layer 44 is formed on the surface of the first electrode layer 45 and is in contact with and connected to the first electrode layer 45. The material of the second bonding layer 44 includes, for example, a transparent conductive material.

[0153] In this structure, the materials of the first electrode layer 45 and the second bonding layer 44 can be different, which reduces the requirement on material consistency.

[0154] In other embodiments, Fig.13 As shown, step S20 includes:

[0155] A second bonding layer 44 is formed on the side of the epitaxial stack 42' away from the substrate 41, and the second bonding layer 44 is reused as the first electrode layer 45. For example, the material of the second bonding layer 44 includes a transparent conductive material.

[0156] In this structure, the first electrode layer 45 and the second bonding layer 44 can be formed in one process, which can simplify the preparation process of the epitaxial wafer.

[0157] like Fig.12 and Fig.13 As shown, in this example, the second bonding layer 44, the first electrode layer 45 and the epitaxial stack 42' are not patterned.

[0158] At this point, the epitaxial wafer 40 provided in the embodiment of the present application is prepared. The second bonding layer 44 in the epitaxial wafer 40 provided in this example is a structure in which the entire layer is made of conductive material. Fig.14A and Fig. 14B As shown, when the driving back plate 30 is bonded to the epitaxial wafer 40 , a non-alignment process can be used to bond the first bonding layer 33 and the second bonding layer 44 , which can reduce the difficulty of the process.

[0159] Example 2

[0160] Fig.15 A schematic diagram of a process for preparing a driving backplane provided in an embodiment of the present application.

[0161] The present application provides a method for preparing a driving backplane. Figure 4 As shown, the preparation method comprises:

[0162] S1, such as Figure 5 As shown, a driving circuit layer 32 is formed on a substrate 31 .

[0163] S2, such as Figure 6 As shown, a reflective film 34 ′ is formed on the side of the driving circuit layer 32 away from the substrate 31 .

[0164] S3, such as Figure 7 As shown, via holes are formed in the reflective film 34 ′ to form the reflective layer 34 .

[0165] S4, such as Figure 8 As shown, a first conductive column 35 is formed in the via hole in the reflective layer 34 .

[0166] Steps S1-S4 are the same as steps S1-S4 in Example 1, and you can refer to the above related descriptions, which will not be repeated here.

[0167] S5, such as Fig.15 As shown, a first bonding layer 33 is formed on a side of the reflective layer 34 away from the substrate 31 .

[0168] In some embodiments, step S5 includes:

[0169] S51 . Depositing a first bonding film 33 ′ covering the reflective layer 34 and the first conductive pillars 35 on a side of the reflective layer 34 away from the substrate 31 . The material of the first bonding film 33 ′ includes a transparent conductive material.

[0170] S52 , patterning the first bonding film 33 ′ to form a first patterned bonding region 331 .

[0171] The first patterned bonding area 331 is connected to the driving circuit layer 32 through the first conductive pillar 35 , and the structure of the first patterned bonding area 331 corresponds one-to-one to the back-end metal interconnect pad in the driving circuit layer 32 .

[0172] S53 , forming a first dielectric region 332 on a side of the reflective layer 34 away from the substrate 31 .

[0173] The first dielectric region 332 fills the gap area around the first patterned bonding region 331 and wraps the side surface of the first patterned bonding region 331 to achieve electrical insulation.

[0174] For example, step S53 includes:

[0175] S531 , depositing a third dielectric film 332 ′ covering the first patterned bonding region 331 and the reflective layer 34 on a side of the reflective layer 34 away from the substrate 31 .

[0176] S532 , planarizing the third dielectric film 332 ′ by etching or chemical mechanical polishing process, so as to planarize the surface of the third dielectric film 332 ′ and form the first dielectric region 332 .

[0177] like Fig.15 As shown, the driving backplane 30 includes a substrate 31, a driving circuit layer 32, a reflective layer 34 and a first bonding layer 33. The first bonding layer 33 includes a first patterned bonding area 331 and a first dielectric area 332. The first patterned bonding area 331 is arranged in the first dielectric area 332 and penetrates the first dielectric area 332 along the thickness direction of the first dielectric area 332. The first patterned bonding area 331 can be connected to the back-end metal interconnect pad in the driving circuit layer 32 through the first conductive column 35.

[0178] For example, the material of the first dielectric region 332 includes inorganic materials such as silicon dioxide (SiO 2 ) and silicon nitride (SiN).

[0179] At this point, the drive backplane 30 provided in the embodiment of the present application is prepared. The first bonding layer 33 in the drive backplane 30 provided in this example is a patterned structure. When the drive backplane 30 is subsequently bonded to the epitaxial wafer 40, an alignment process can be used for bonding.

[0180] Fig.16 A schematic diagram of the preparation process of an epitaxial wafer provided in an embodiment of the present application. Figure 17-Figure 21 A schematic diagram of a process for preparing a stretched sheet provided in an embodiment of the present application.

[0181] The present application embodiment provides a method for preparing an epitaxial wafer 40, such as Fig.16 As shown, the preparation method comprises:

[0182] S10, such as Fig.17 As shown, an epitaxial stack 42 ′ is formed on a substrate 41 .

[0183] In some embodiments, step S10 includes:

[0184] First, the steps S101 to S105 in Example 1 are performed to form a stack of a nucleation film 421 ′, a buffer film 422 ′, a second semiconductor film 423 ′, an active film 424 ′, and a first semiconductor film 425 ′.

[0185] S106, such as Fig.17 As shown, the second semiconductor film 423 ′, the active film 424 ′ and the first semiconductor film 425 ′ are patterned to form a light emitting structure 42 .

[0186] For example, patterning is performed using processes such as exposure, development, and etching, and the light-emitting structure 42 serves as a MicroLED light-emitting pixel (mesa) unit structure.

[0187] Depending on the structure of the epitaxial stack 42', the film layers for patterning the epitaxial stack 42' are also different. However, regardless of the structure, the first semiconductor film 425', the active film 424' and the second semiconductor film 423' in the epitaxial stack 42' need to be patterned. Fig.17 As shown, after the epitaxial stack 42' is patterned, the light emitting structure 42 formed includes a first semiconductor layer 425, an active layer 424 and a second semiconductor layer 423. The nucleation film 421' and the buffer film 422' in the epitaxial stack 42' may not be patterned. Of course, the nucleation film 421' and the buffer film 422' may also be patterned.

[0188] In some embodiments, after executing step 106 , the light emitting structure 42 may be passivated to eliminate etching damage, surface defects and other problems of the light emitting structure 42 , thereby improving the light emitting efficiency of the light emitting structure 42 .

[0189] S20, such as Fig.18 As shown, a first electrode layer 45 is formed on the side of the epitaxial stack 42 ′ away from the substrate 41 .

[0190] The first electrode layer 45 is located at one side of the first semiconductor layer 425 . The first electrode layer 45 includes a plurality of first electrodes 451 . The first electrodes 451 are connected to the first semiconductor layer 425 in the light emitting structure 42 correspondingly, and serve as driving electrodes of the light emitting structure 42 .

[0191] S21, such as Fig.19 As shown, a planar layer 46 is formed, and the planar layer 46 wraps the side surfaces of the first electrode 451 and the light emitting structure 42 .

[0192] For example, step S21 includes:

[0193] S211 , depositing a planar film, the planar film filling a gap between the first electrode 451 and the light emitting structure 42 .

[0194] S212, planarizing the planar film by etching or chemical mechanical polishing to expose the first electrode 451, so as to form a planar layer 46. The material of the planar layer 46 includes, for example, silicon dioxide (SiO2), silicon nitride (SiN), and the like.

[0195] S22, such as Fig. 20 As shown, a second conductive column 47 is formed.

[0196] For example, step S22 includes:

[0197] S221 , etching is performed on the planar layer 46 by using exposure, development, etching and other processes to form via holes, the positions of which correspond to the positions of the back-end metal interconnect pads in the driving circuit layer 32 .

[0198] S222 , depositing a conductive film to fill the via hole and cover the planarization layer 46 .

[0199] S223 , planarizing the conductive film by etching or chemical mechanical polishing, removing the portion of the conductive film located above the planarization layer 46 , and retaining the portion of the conductive film located in the via hole as the second conductive pillar 47 .

[0200] S30, such as Fig.21 As shown, a second bonding layer 44 is formed on a side of the first electrode layer 45 away from the substrate 41 .

[0201] In some embodiments, the step of forming the second bonding layer 44 is the same as the step of forming the first bonding layer 33 .

[0202] For example, step S30 includes:

[0203] S301 , depositing a second bonding film covering the planar layer 46 , the first electrode layer 45 and the second conductive pillars 47 on a side of the planar layer 46 away from the substrate 41 , wherein the material of the second bonding film includes a transparent conductive material.

[0204] S302 , patterning the second bonding film to form a second patterned bonding region 441 .

[0205] The structure of the second patterned bonding area 441 corresponds to the back-end metal interconnect pad in the driving circuit layer 32 , and the first electrode layer 45 is connected to the second patterned bonding area 441 .

[0206] S303 , forming a second dielectric region 442 on a side of the planar layer 46 away from the substrate 41 .

[0207] The second dielectric region 442 fills the gap area around the second patterned bonding region 441 and wraps the side surface of the second patterned bonding region 441 to achieve electrical insulation.

[0208] For example, step S303 includes:

[0209] S3031 , depositing a fourth dielectric film covering the second patterned bonding region 441 and the planar layer 46 on a side of the planar layer 46 away from the substrate 41 .

[0210] S3032 , planarizing the fourth dielectric film by etching or chemical mechanical polishing to planarize the surface of the fourth dielectric film and form a second dielectric region 442 .

[0211] In some embodiments, the epitaxial wafer 40 includes a substrate 41, an epitaxial stack 42', a first electrode layer 45, and a second bonding layer 44. Fig.21As shown, the epitaxial stack 42 ′ includes a plurality of light emitting structures 42 , and the plurality of light emitting structures 42 are used to emit light of the same color.

[0212] The light emitting structure 42 includes a first semiconductor layer 425, an active layer 424, and a second semiconductor layer 423 which are sequentially stacked in a direction away from the second bonding layer 44. The first electrode layer 45 includes a plurality of first electrodes 451, which are arranged on a side of the first semiconductor layer 425 away from the substrate 41, and the first electrodes 451 are in contact with the first semiconductor layer 425 and connected to the second patterned bonding region 441.

[0213] The second bonding layer 44 includes a second patterned bonding region 441 and a second dielectric region 442 . The second patterned bonding region 441 is disposed in the second dielectric region 442 and penetrates the second dielectric region 442 along a thickness direction of the second dielectric region 442 .

[0214] In other embodiments, Fig. 22 As shown, the epitaxial wafer 40 does not include the first electrode layer 45, and the second patterned bonding region 441 is reused as the first electrode layer 45. After executing step S10, steps S21, S22, and S30 are directly executed.

[0215] The second bonding layer 44 includes a plurality of second patterned bonding regions 441 and a second dielectric region 442. The second patterned bonding regions 441 are disposed in the second dielectric region 442 and penetrate the second dielectric region 442 along the thickness direction of the second dielectric region 442. Among the plurality of second patterned bonding regions 441, the second patterned bonding regions 441 corresponding to the positions of the light emitting structures 42 are reused as the first electrodes 451 for driving the light emitting structures 42 to emit light, and the epitaxial wafer 40 does not include an independent first electrode layer 45.

[0216] At this point, the epitaxial wafer 40 provided in the embodiment of the present application is prepared. The second bonding layer 44 in the epitaxial wafer 40 provided in this example is a patterned structure, such as Fig.23A and Fig. 23B As shown, when the driving back plate 30 is subsequently bonded to the epitaxial wafer 40 , the first bonding layer 33 and the second bonding layer 44 are bonded by an alignment process.

[0217] Example 3

[0218] The driving backplane 30 provided in Example 1 and Example 2 is bonded to the epitaxial wafer 40 to obtain a bonded wafer. After processing the bonded wafer, the display module 1 provided in the embodiment of the present application can be obtained.

[0219] Fig.24A and Fig. 24B A schematic diagram of the structure of a display module provided in an embodiment of the present application.

[0220] The present application embodiment provides a display module 1, such as Fig.24A As shown, the display module 1 includes a substrate 31 and a driving circuit layer 32 , a reflective layer 34 , a bonding layer 50 and a light emitting device 60 which are sequentially arranged on one side of the substrate 31 .

[0221] The driving circuit layer 32 includes, for example, a pixel circuit for driving the light-emitting device 60 and a back-end metal interconnect pad corresponding to the pixel circuit.

[0222] The reflective layer 34 includes a first dielectric layer 341 and a second dielectric layer 342 stacked together, and the first dielectric layer 341 and the second dielectric layer 342 have different refractive indices. The structure of the reflective layer 34 can refer to the above description of the reflective layer 34 in the driving backplane 30, which will not be repeated here.

[0223] The bonding layer 50 is connected to the light emitting device 60 , and is connected to the driving circuit layer 32 via the first conductive pillar 35 , so as to transmit the signal of the driving circuit layer 32 to the light emitting device 60 .

[0224] In the display module 1 provided in the embodiment of the present application, the reflective layer 34 includes one or more first dielectric layers 341 and one or more second dielectric layers 342 which are stacked. The number of layers, thickness, and material of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the requirements. The structure of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the light emission wavelength of the light-emitting device in the display module 1, so that the reflectivity of the reflective layer 34 to red light, green light, and blue light can reach more than 90%, so as to improve the efficiency of the light-emitting device in the display module 1. In addition, the material of the reflective layer 34 is an inorganic thin film material, which does not need to include heavy metal materials such as silver, and there is no heavy metal pollution problem. It is compatible with the standard process of the production line of the driving backplane 30, and the processing technology is simple, which can achieve low-cost mass production.

[0225] In some embodiments, the material of bonding layer 50 includes a transparent conductive material.

[0226] For example, the bonding layer 50 includes a plurality of patterned bonding regions 51 and a dielectric region 52 . The patterned bonding region 51 is disposed in the dielectric region 52 and penetrates the dielectric region 52 along a thickness direction of the dielectric region 52 .

[0227] The bonding layer 50 is obtained by bonding the first bonding layer 33 in the driving backplane 30 and the second bonding layer 44 in the epitaxial wafer 40. The patterned bonding area 51 is obtained by bonding the first patterned bonding area 331 and the second patterned bonding area 441. The patterned bonding area 51 may have a bonding interface or may not have a bonding contact surface. The dielectric area 52 is obtained by bonding the first dielectric area 332 in the driving backplane 30 and the second dielectric area 442 in the epitaxial wafer 40.

[0228] The plurality of light emitting devices 60 are disposed corresponding to the plurality of patterned bonding regions 51 .

[0229] In some embodiments, Fig.24A As shown, the light emitting device 60 includes a first electrode 451 , a first semiconductor layer 425 , an active layer 424 , a second semiconductor layer 423 and a second electrode 48 which are sequentially arranged in a direction away from the bonding layer 50 .

[0230] In other embodiments, Fig. 24B As shown, the light-emitting device 60 includes a first semiconductor layer 425, an active layer 424, a second semiconductor layer 423 and a second electrode 48 arranged in sequence along a direction away from the bonding layer 50, and the patterned bonding area 51 arranged corresponding to the light-emitting structure 42 is reused as the first electrode 451 in the light-emitting device 60.

[0231] The material of the bonding layer 50 includes a transparent conductive material, which has a high light transmittance and can further improve the efficiency of the light-emitting device. Moreover, the bonding layer 50 does not include metals such as gold, so there is no metal contamination problem, and it is compatible with the standard process of the production line, and the processing technology is simple, so low-cost mass production can be achieved.

[0232] In some embodiments, the sum L4 of the thickness of the bonding layer 50 and the reflective layer 34 ranges from 100 nm to 2000 nm. For example, the sum L4 is 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm.

[0233] Based on the characteristics of the bonding layer 50 provided in the present application, the thickness of the bonding layer 50 can be less than 2000 nm, making the subsequent etching process easy to perform.

[0234] In some embodiments, Fig. 24B As shown, the display module 1 also includes a plurality of device pads located on the side of the flat layer 46 away from the substrate 31, one side of the device pads is connected to the driving circuit layer 32 through the second conductive column 47, the patterned bonding area 51, and the first conductive column 35, and the other side of some device pads is connected to the second electrode 48, which is used to transmit the signal of the driving circuit layer 32 to the second electrode 48. The other side of some device pads is used to connect to components such as a circuit board, and is used to receive external signals and transmit them to the driving circuit layer 32.

[0235] In some embodiments, the light emitting devices 60 in the display module 1 are used to emit light of the same color.

[0236] The structures of the first dielectric layer 341 and the second dielectric layer 342 included in the reflective layer 34 in the display module 1 are matched and adjusted according to the light-emitting color of the light-emitting device 60. Therefore, the structure of the reflective layer 34 in the display module 1 for emitting red light, the structure of the reflective layer 34 in the display module 1 for emitting blue light, and the structure of the reflective layer 34 in the display module 1 for emitting green light can be different, so that the reflectivity of the reflective layer 34 in each display module 1 to the light emitted by the light-emitting device 60 included in the display module 1 can reach more than 90%.

[0237] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving backplane, characterized in that: include: substrate; A driving circuit layer, arranged on one side of the substrate; A reflective layer is arranged on a side of the driving circuit away from the substrate; the reflective layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; The first bonding layer is arranged on a side of the reflective layer away from the substrate; the first bonding layer is connected to the driving circuit layer through a conductive column.

2. The driving backplane according to claim 1, characterized in that: The material of the first bonding layer includes a transparent conductive material.

3. The driving backplane according to claim 1 or 2, characterized in that: There are a plurality of the first dielectric layers and a plurality of the second dielectric layers, and the plurality of the first dielectric layers and the plurality of the second dielectric layers are arranged alternately.

4. The driving backplane according to any one of claims 1 to 3, characterized in that: The first bonding layer covers the reflective layer.

5. The driving backplane according to claim 1, characterized in that: The first bonding layer includes a first patterned bonding region and a first dielectric region; The first patterned bonding area is disposed in the first dielectric area and penetrates the first dielectric area along a thickness direction of the first dielectric area; The driving circuit layer includes a back-end metal interconnect pad, and the first patterned bonding area is connected to the back-end metal interconnect pad through the conductive column.

6. The driving backplane according to any one of claims 1 to 5, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the first dielectric region include silicon oxide, titanium dioxide, tantalum pentoxide or niobium pentoxide.

7. The driving backplane according to claim 5, characterized in that: The material of the first patterned bonding region includes indium tin oxide, zinc aluminum oxide or transparent conductive oxide.

8. An epitaxial wafer, characterized in that: include: substrate; An epitaxial stack is arranged on one side of the substrate; A second bonding layer is arranged on a side of the epitaxial stack away from the substrate; The material of the second bonding layer includes a transparent conductive material.

9. The epitaxial wafer according to claim 8, characterized in that: The second bonding layer covers the epitaxial stack.

10. The epitaxial wafer according to claim 8, characterized in that: The second bonding layer includes a second patterned bonding area and a second dielectric area; the second patterned bonding area is arranged in the second dielectric area and penetrates the second dielectric area along a thickness direction of the second dielectric area.

11. The epitaxial wafer according to claim 10, characterized in that: The epitaxial stack includes a second semiconductor layer, an active layer and a first semiconductor layer which are sequentially stacked on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

12. The epitaxial wafer according to any one of claims 8 to 11, characterized in that: The epitaxial wafer further includes a first electrode layer, and the first electrode layer is arranged between the second bonding layer and the epitaxial stack.

13. The epitaxial wafer according to claim 10, characterized in that: The material of the second patterned bonding area includes indium tin oxide, zinc aluminum oxide or transparent conductive oxide; the material of the second dielectric area includes silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide or niobium pentoxide.

14. A display module, characterized in that: include: substrate; A driving circuit layer, a reflective layer, a bonding layer and a plurality of light-emitting devices are sequentially arranged on one side of the substrate; The reflective layer includes a first dielectric layer and a second dielectric layer which are stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; the bonding layer is connected to the light emitting device and is connected to the driving circuit layer through a conductive column.

15. The display module according to claim 14, characterized in that: The material of the bonding layer includes a transparent conductive material.

16. The display module according to claim 14 or 15, characterized in that: The bonding layer includes a plurality of patterned bonding areas and a dielectric area; the plurality of patterned bonding areas are arranged in the dielectric area and penetrate the dielectric area along the thickness direction of the dielectric area; the light emitting device is arranged corresponding to some of the patterned bonding areas among the plurality of patterned bonding areas.

17. The display module according to any one of claims 14 to 16, characterized in that: The sum of the thickness of the bonding layer and the reflective layer ranges from 100 nm to 2000 nm.

18. The display module according to any one of claims 14 to 17, characterized in that: The light emitting device comprises a first semiconductor layer, an active layer, a second semiconductor layer and a second electrode which are sequentially arranged in a direction away from the bonding layer; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

19. An electronic device, characterized in that: It comprises a display module and a processor, wherein the processor is used to control the display module to display an image; the display module comprises the display module described in any one of claims 14-18.

20. A method for preparing a driving backplane, characterized in that: include: forming a driving circuit layer on the substrate; A reflective layer is formed on a side of the driving circuit layer away from the substrate; the reflective layer comprises a first dielectric layer and a second dielectric layer stacked in layers, and the first dielectric layer and the second dielectric layer have different refractive indices; A first bonding layer is formed on a side of the reflective layer away from the substrate; the first bonding layer is connected to the driving circuit layer through a conductive column.

21. The preparation method according to claim 20, characterized in that: Forming a first bonding layer on a side of the reflective layer away from the substrate, comprising: A first bonding layer covering the reflective layer is deposited on a side of the reflective layer away from the substrate, wherein the material of the first bonding layer includes a transparent conductive material.

22. The preparation method according to claim 20, characterized in that: The first bonding layer includes a first patterned bonding area and a first dielectric area, and the first bonding layer is formed on a side of the reflective layer away from the substrate, including: Depositing a first bonding film covering the reflective layer on a side of the reflective layer away from the substrate, wherein the material of the first bonding film includes a transparent conductive material; Patterning the first bonding film to form a first patterned bonding area; the first patterned bonding area is connected to the driving circuit layer; A first dielectric region is formed on a side of the reflective layer away from the substrate, and the first dielectric region wraps a side surface of the first patterned bonding region.

23. A method for preparing an epitaxial wafer, characterized in that: include: forming an epitaxial stack on a substrate; forming a second bonding layer on a side of the epitaxial stack away from the substrate; The material of the second bonding layer includes a transparent conductive material.

24. The preparation method according to claim 23, characterized in that: Forming a second bonding layer on a side of the epitaxial stack away from the substrate, comprising: A second bonding layer covering the epitaxial stack is deposited on a side of the epitaxial stack away from the substrate.

25. The preparation method according to claim 23, characterized in that: The second bonding layer includes a second patterned bonding area and a second dielectric area, and the second bonding layer is formed on a side of the epitaxial stack away from the substrate, including: forming a second bonding film on a side of the epitaxial stack away from the substrate, wherein the material of the second bonding film is a transparent conductive material; patterning the second bonding film to form a plurality of second patterned bonding regions; A second dielectric region is formed on a side of the epitaxial stack away from the substrate, and the second dielectric region wraps around a side surface of the second patterned bonding region.

26. The preparation method according to any one of claims 23 to 25, characterized in that: Before forming a second bonding layer on a side of the epitaxial stack away from the substrate, the preparation method further comprises: A first electrode layer is formed on a side of the epitaxial stack away from the substrate.

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