Array substrate, preparation method of array substrate and display panel

Abstract

The invention provides an array substrate, a preparation method of the array substrate and a display panel. The array substrate comprises a substrate; the capacitor is positioned on one side of the bottom; the at least one oxide thin film transistor is positioned on one side, far away from the substrate, of the capacitor; the orthographic projection of the oxide thin film transistor and the orthographic projection of the capacitor on the substrate are overlapped. An oxide thin film transistor is integrated in a free region of one side, far away from a substrate, of a capacitor in a pixel circuit, so that the effect of the transistor is realized, the space of one side, far away from the substrate, of the capacitor is fully utilized, the capacitor and the oxide thin film transistor are integrated and stacked together, the size of the pixel circuit is reduced, and the pixel circuit is more compact. Therefore, the technical effect of improving the pixel density of the pixel circuit is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a method for preparing the array substrate, and a display panel. Background Art

[0002] Organic Light-Emitting Diode (OLED) has excellent properties such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility, and is therefore widely used in terminal devices.

[0003] In conventional array substrates, the pixel circuit occupies a large layout space, which is not conducive to improving the pixel density (Pixels Per Inch, PPI) of OLED. How to improve the PPI of OLED is a problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the above-mentioned technical problem of how to improve pixel density, the present invention provides an array substrate, a method for preparing the array substrate and a display panel.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, comprising: a substrate; a capacitor, the capacitor being located on one side of the substrate; and at least one oxide thin film transistor, the oxide thin film transistor being located on a side of the capacitor away from the substrate; the oxide thin film transistor and the capacitor having an overlapping orthographic projection on the substrate.

[0006] In combination with the first aspect, the capacitor includes a first electrode plate and a second electrode plate stacked in a direction away from the substrate, and an orthographic projection of the first electrode plate on the substrate overlaps with an orthographic projection of the second electrode plate on the substrate.

[0007] In combination with the first aspect, the oxide thin film transistor includes a first gate, and the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the capacitor on the substrate; preferably, the active layer of the oxide thin film transistor is located on a side of the first gate close to the substrate; preferably, the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the active layer of the oxide thin film transistor on the substrate.

[0008] In combination with the first aspect, the oxide thin film transistor also includes a second gate, which is located on the side of the first gate close to the substrate; preferably, the active layer of the oxide thin film transistor is located between the first gate and the second gate; preferably, the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the active layer of the oxide thin film transistor on the substrate; preferably, the orthographic projection of the first gate on the substrate is located within the orthographic projection of the second gate on the substrate; preferably, the array substrate also includes a first insulating layer, which is located between the oxide thin film transistor and the capacitor; preferably, the array substrate also includes a second insulating layer, which is located between the active layer of the oxide thin film transistor and the second gate, and the second insulating layer and the first insulating layer are made of the same material.

[0009] In combination with the first aspect, the at least one oxide thin film transistor includes a first oxide thin film transistor and a second oxide thin film transistor, the gate of the first oxide thin film transistor and the gate of the second oxide thin film transistor are arranged on the same layer, and the active layer of the first oxide thin film transistor and the active layer of the second oxide thin film transistor are arranged on the same layer.

[0010] In combination with the first aspect, it also includes a plurality of low-temperature polysilicon thin film transistors, the plurality of low-temperature polysilicon thin film transistors include a first low-temperature polysilicon thin film transistor, the first low-temperature polysilicon thin film transistor is located between the substrate and the oxide thin film transistor, and the orthographic projection of the oxide thin film transistor on the substrate overlaps with the orthographic projection of the first low-temperature polysilicon thin film transistor on the substrate; preferably, the capacitor includes a first electrode plate, and the first electrode plate is reused as the gate of the first low-temperature polysilicon thin film transistor; preferably, the active layer of the first low-temperature polysilicon thin film transistor is located on the side of the gate of the first low-temperature polysilicon thin film transistor close to the substrate; preferably, the plurality of low-temperature polysilicon thin film transistors include a second low-temperature polysilicon thin film transistor, and the orthographic projection of the second low-temperature polysilicon thin film transistor on the substrate does not overlap with the orthographic projection of the first low-temperature polysilicon thin film transistor on the substrate; preferably, the gate of the second low-temperature polysilicon thin film transistor and the gate of the first low-temperature polysilicon thin film transistor are arranged on the same layer, and the active layer of the second low-temperature polysilicon thin film transistor and the active layer of the first low-temperature polysilicon thin film transistor are arranged on the same layer.

[0011] In a second aspect, an embodiment of the present application provides a method for preparing an array substrate, comprising: preparing a capacitor and a plurality of low-temperature polycrystalline silicon thin-film transistors on a substrate; preparing a first insulating layer on a side of the capacitor and the plurality of low-temperature polycrystalline silicon thin-film transistors facing away from the substrate; preparing at least one oxide thin-film transistor on a side of the first insulating layer facing away from the substrate; wherein the orthographic projection of the oxide thin-film transistor on the substrate overlaps with the orthographic projection of the capacitor on the substrate.

[0012] In combination with the second aspect, at least one oxide thin film transistor is prepared on the side of the first insulating layer facing away from the substrate, including: preparing an oxide material layer on the side of the first insulating layer facing away from the substrate, and patterning the oxide material layer to obtain an active layer of the oxide thin film transistor; preparing a third insulating layer on the side of the active layer facing away from the substrate; and preparing a first gate on the side of the third insulating layer facing away from the substrate.

[0013] In combination with the second aspect, before preparing the oxide material layer on the side of the first insulating layer facing away from the substrate, it also includes: preparing a second gate on the side of the first insulating layer facing away from the substrate; preparing an oxide material layer on the side of the first insulating layer facing away from the substrate, and graphing the oxide material layer to obtain the active layer of the oxide thin film transistor, which includes: preparing the oxide material layer on the side of the second gate facing away from the substrate, and graphing the oxide material layer to obtain the active layer of the oxide thin film transistor; preferably, the second insulating layer and the first insulating layer are made of the same material.

[0014] In a third aspect, an embodiment of the present application provides a display panel, comprising any array substrate described in the first aspect.

[0015] In the array substrate, the method for preparing the array substrate and the display panel provided by the present application, a substrate is provided; a capacitor, the capacitor is located on one side of the substrate; and at least one oxide thin film transistor, the oxide thin film transistor is located on the side of the capacitor away from the substrate; the oxide thin film transistor overlaps with the positive projection of the capacitor on the substrate. By integrating the oxide thin film transistor in the idle area of ​​the capacitor away from the substrate in the pixel circuit, while realizing the transistor function, the space on the side of the capacitor away from the substrate is fully utilized, so that the capacitor and the oxide thin film transistor are integrated and stacked together, the size of the pixel circuit is reduced, and the pixel density of the pixel circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. In addition, these drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to specific embodiments.

[0017] Figure 1a A schematic diagram of a film layer structure of an array substrate provided by the prior art; Figure 1b A local wiring diagram of an array substrate provided by the prior art; Figure 2 A schematic diagram of a film layer structure of an array substrate provided in Example 1 of the present application; Figure 3a A schematic diagram of a film layer structure of an array substrate provided in Embodiment 2 of the present application; Figure 3b A schematic diagram of a film layer structure of another array substrate provided in Embodiment 2 of the present application; Figure 4a A schematic diagram of a film layer structure of an array substrate provided in Embodiment 3 of the present application; Figure 4b A local wiring diagram of an array substrate provided in Embodiment 3 of the present application; Figure 4c A partial split wiring diagram of an array substrate provided in Embodiment 3 of the present application; Figure 4d A partial split wiring diagram of an array substrate provided in Embodiment 3 of the present application; Figure 4e A schematic diagram of a film layer structure of another array substrate provided in Embodiment 3 of the present application; Figure 4f A local wiring diagram of another array substrate provided in Embodiment 3 of the present application; Figure 4g A partial split wiring diagram of another array substrate provided in Embodiment 3 of the present application; Figure 4h A partial split wiring diagram of another array substrate provided in Embodiment 3 of the present application; Figure 4i A schematic diagram of a film layer structure of another array substrate provided in Embodiment 3 of the present application; Figure 4j A local wiring diagram of another array substrate provided in Embodiment 3 of the present application; Figure 4k A partial split wiring diagram of another array substrate provided in Embodiment 3 of the present application; Figure 4lA partial split wiring diagram of another array substrate provided in Embodiment 3 of the present application; Figure 5 A schematic diagram of a process for preparing an array substrate provided in Embodiment 4 of the present application; Figure 6 A schematic flow chart of a method for preparing an oxide thin film transistor provided in Example 5 of the present application; Figure 7 A schematic flow chart of another method for preparing an oxide thin film transistor provided in Example 5 of the present application; Figure 8 A structural schematic diagram of a display panel provided in Example 6 of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention application clearer, the technical solution in the embodiment of the present invention application will be clearly and completely described below in combination with the embodiment of the present invention application. Obviously, the described embodiment is a part of the embodiment of the present invention application, not all of the embodiments. Based on the embodiment in the present invention application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention application. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] Figure 1a A schematic diagram of a film layer structure of an array substrate provided by the prior art. Figure 1b A local wiring diagram of an array substrate provided in the prior art. Figure 1a According to the diagram provided, a pixel capacitor Cst and a plurality of transistors are arranged on one side of the substrate, wherein a single-gate transistor and a double-gate transistor are arranged on both sides of the pixel capacitor Cst. It can be seen that the pixel capacitor Cst and the single-gate transistor are stacked, and no other devices are arranged on the side of the pixel capacitor Cst away from the substrate, resulting in waste. Figure 1b It can be seen that the capacitor occupies a large area, which makes the OLED layout size large, resulting in low pixel density of the OLED display.

[0020] according to Figure 1b A pixel circuit with an 8T1C structure is provided, wherein a switch transistor and a drive transistor in the pixel circuit generally adopt a low temperature polycrystalline oxide semiconductor (Low Temperature Polysilicon Oxide, LTPO for short). Figure 1b The transistors T3 and T4 in the circuit are both made using the Indium Gallium Zinc Oxide (InGaZnO, IGZO for short) process. Figure 1a, transistor T3 and transistor T4 adopt a dual-gate structure, in which the top gate adopts a top gate oxide GATO, and the bottom gate generally adopts a metal conductive layer M2, while transistor T1 and other transistors are usually made of low-temperature polysilicon semiconductor (Low Temperature PolySi, referred to as LTPS) material process.

[0021] according to Figure 1a According to the diagram provided, the pixel capacitor Cst is composed of two plates, the metal conductive layer M1 and the metal conductive layer M2. At the same time, the upper plate M2 and the bottom gates of the transistors T3 and T4 are made of the same material in the same layer. Because the pixel capacitor Cst is staggered with the transistors T3 and T4, the pixel capacitor Cst is far away from the substrate, so the design size of the pixel circuit becomes larger, resulting in a low pixel density of the OLED display.

[0022] Since the preparation process of general LTPO technology OLED products is fixed, the IGZO structure thin film transistor adopts a dual-gate structure, the bottom gate adopts M2, and the transistor T1 and the capacitor Cst are integrated together. At the same time, the upper plate of the pixel capacitor Cst also adopts M2. Although the transistor T1 and the pixel capacitor Cst occupy a large space, due to the limitation that M2 is used, the transistor T3 and the transistor T4 cannot be stacked with the transistor T1 and the pixel capacitor Cst, resulting in the problem of low pixel density.

[0023] In the case of low pixel density, the conventional method is to reduce the size of the pixel capacitor Cst and the transistor (including IGZO and LTPSTFT), which will sacrifice the performance and reliability of the product; or to compress the line width, line spacing and connection hole size of the routing, but this method requires high engineering capabilities, increases the risk of process defects, and may also affect product performance; or optimize the placement of different components to optimize the connection solution in order to save space, but as the pixel size continues to shrink, the optimization effect is not obvious.

[0024] In order to solve the problem of low pixel density, the present application provides an array substrate, which utilizes the fact that the capacitor and the dual-gate transistor have the same material layer in the same layer, and stacks the dual-gate transistor on the side of the capacitor away from the substrate. By adding a conductive layer between the upper plate of the capacitor and the active layer of the dual-gate transistor to serve as the bottom gate of the dual-gate transistor, the dual-gate transistor is stacked above the capacitor and the transistor (single-gate structure), eliminating the position of the original dual-gate transistor, thereby achieving the purpose of reducing the size of the pixel circuit and realizing the technical effect of improving the pixel density.

[0025] To facilitate understanding of the embodiments of the present application, further explanation will be given below with reference to specific embodiments in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present application.

[0026] Embodiment 1 Figure 2 A schematic diagram of a film layer structure of an array substrate provided in Example 1 of the present application. Figure 2 In the provided diagram, the array substrate 100 includes a substrate 10 and a capacitor 20, the capacitor 20 is located on one side of the substrate 10; and at least one oxide thin film transistor 30, the oxide thin film transistor 30 is located on the side of the capacitor 20 away from the substrate 10; the oxide thin film transistor 30 overlaps with the orthographic projection of the capacitor 20 on the substrate 10. The array substrate 100 saves the space originally occupied by the oxide thin film transistor 30 by stacking at least one oxide thin film transistor 30 on the side of the capacitor away from the substrate, while ensuring the functional stability of the array substrate, and integrates the oxide thin film transistor 30 with the capacitor 20, making full use of the space on the side of the capacitor 20 away from the substrate 10, so as to reduce the size of the array substrate and achieve the technical effect of improving the PPI.

[0027] Preferably, in a possible example scenario, the substrate 10 may be a substrate substrate, and the substrate substrate may include but is not limited to any one of a conductive silicon (Si) substrate substrate, a silicon oxide (SiOx) substrate substrate, an aluminum oxide (Al2O3) substrate substrate (i.e., a sapphire substrate substrate), a silicon carbide (SiC) substrate substrate, and a gallium nitride (GaN) substrate substrate. In addition, the substrate 10 may also be a flexible substrate substrate, for example, a flexible substrate substrate composed of polyimide PI.

[0028] Preferably, in a possible example scenario, the substrate 10 not only represents a layer of substrate material, but may also include a substrate base plate and multiple film layers (the specific stacking is not the focus of this application and is omitted here and is collectively referred to as a substrate).

[0029] Optionally, in a possible example scenario, the capacitor 20 is disposed on one side of the substrate 10, and at the same time, the oxide thin film transistor 30 is stacked with the capacitor 20 to fully utilize the space of the capacitor 20 away from the side of the substrate 10, integrate the oxide thin film transistor 30, release the original space of the oxide thin film transistor 30, and improve the PPI of the pixel circuit.

[0030] Optionally, the oxide thin film transistor 30 mentioned here is a low-temperature polycrystalline oxide semiconductor structure device.

[0031] Optionally, a first insulating layer 40 is disposed on one side of the substrate 10 , and the capacitor 20 is disposed on a side of the first insulating layer 40 away from the substrate 10 , and the capacitor 20 and the substrate 10 are isolated by the first insulating layer 40 .

[0032] Optionally, a second insulating layer 70 is provided on a side of the capacitor 20 away from the substrate 10 , and the oxide thin film transistor 30 is provided on a side of the second insulating layer 70 away from the capacitor 20 , and the capacitor 20 and the oxide thin film transistor 30 are isolated by the second insulating layer 70 .

[0033] The array substrate provided in the present application arranges the oxide thin film transistor on the side of the capacitor away from the substrate, thereby integrating the capacitor and the oxide thin film transistor stack, making full use of the space above the capacitor, and achieving the technical effect of improving the pixel density of the display screen.

[0034] Embodiment 2 Figure 3a This is a schematic diagram of a film layer structure of an array substrate provided in Example 2 of the present application. Figure 3a According to the provided diagram, the structure of the array substrate includes: a substrate 10 , a capacitor 20 and an oxide thin film transistor 30 .

[0035] according to Figure 3a According to the provided diagram, the capacitor 20 includes a first plate 201 and a second plate 202 stacked in a direction away from the substrate 10 , and the orthographic projection of the first plate 201 on the substrate 10 overlaps with the orthographic projection of the second plate 202 on the substrate 10 .

[0036] Optionally, in a possible example scenario, the first electrode plate 201 is formed by the metal conductive layer M1, and the second electrode plate 202 is formed by the metal conductive layer M2.

[0037] Furthermore, the metal conductive layer M1 may be made of molybdenum material, and the metal conductive layer M2 may be made of molybdenum or titanium material.

[0038] Preferably, a fourth insulating layer 90 is included between the first electrode plate 201 and the second electrode plate 202 .

[0039] Preferably, the array substrate 100 further includes a first insulating layer 40 located between the oxide thin film transistor 30 and the capacitor 20 .

[0040] Preferably, the array substrate 100 further includes a fifth insulating layer 110 located between the capacitor 20 and the substrate 10 .

[0041] Preferably, the array substrate 100 further includes an encapsulation layer 120 located on a side of the first gate 301 away from the substrate 10 .

[0042] according to Figure 3a In the provided diagram, the oxide thin film transistor 30 includes a first gate 301 , and the orthographic projection of the first gate 301 on the substrate 10 overlaps with the orthographic projection of the capacitor 20 on the substrate 10 .

[0043] Preferably, in a possible exemplary scenario, the active layer 302 of the oxide thin film transistor is located on a side of the first gate 301 close to the substrate 10 .

[0044] Preferably, in a possible example scenario, an orthographic projection of the first gate 301 on the substrate 10 overlaps with an orthographic projection of the active layer 302 of the oxide thin film transistor on the substrate 10 .

[0045] Preferably, the first gate 301 is made of top gate oxide (GATO), and the active layer 302 of the oxide thin film transistor is indium gallium zinc oxide (IGZO).

[0046] Preferably, the oxide thin film transistor 30 further includes a source-drain electrode layer 50 , and the source-drain electrode layer is located on a side of the first gate 301 away from the substrate 10 .

[0047] Preferably, the array substrate 100 further includes a third insulating layer 80 located between the active layer 302 and the first gate 301 of the oxide thin film transistor.

[0048] Preferably, the array substrate 100 further includes a first insulating layer 40 located between the oxide thin film transistor 30 and the capacitor 20 .

[0049] Optionally, in one embodiment, the source-drain electrode layer 50 includes a source electrode S and a drain electrode D, and the source electrode S, the drain electrode D and the active layer 302 of the oxide thin film transistor are electrically connected. The source electrode S and the drain electrode D are the inlet and outlet of the current, and the current size of the channel between them can be adjusted by controlling the gate voltage. The material of the source electrode S and the drain electrode D can be one or a stacked combination of molybdenum, titanium, aluminum, and copper.

[0050] Preferably, according to Figure 3a In the diagram provided, the active layer 302 and the first gate 301 of the oxide thin film transistor constitute a single-gate oxide thin film transistor T4. The capacitor and the single-gate oxide thin film transistor T4 are stacked, thereby rationally utilizing the space above the capacitor 20, saving the space occupied by the single-gate oxide thin film transistor T4, reducing the size of the pixel circuit, and achieving the effect of improving the pixel PPI.

[0051] according to Figure 3a , the array substrate 100 also includes a plurality of low-temperature poly-silicon thin film transistors 60, the plurality of low-temperature poly-silicon thin film transistors 60 include a first low-temperature poly-silicon thin film transistor T1, the first low-temperature poly-silicon thin film transistor T1 is located between the substrate 10 and the oxide thin film transistor 30, and the orthographic projection of the oxide thin film transistor 30 on the substrate 10 overlaps with the orthographic projection of the first low-temperature poly-silicon thin film transistor T1 on the substrate 10.

[0052] Preferably, in a possible example scenario, the capacitor 20 includes a first electrode plate 201 (ie, the above-mentioned M1 ), and the first electrode plate 201 is reused as a gate of a first low-temperature polysilicon thin film transistor.

[0053] Preferably, in a possible example scenario, the active layer 601 (P—Si ​​active layer) of the first low-temperature polysilicon thin film transistor is located on a side of the gate 201 of the first low-temperature polysilicon thin film transistor close to the substrate 10 .

[0054] Preferably, in a possible example scenario, the plurality of low-temperature polysilicon thin film transistors 60 include a second low-temperature polysilicon thin film transistor T2, and the orthographic projection of the second low-temperature polysilicon thin film transistor T2 on the substrate 10 has no overlap with the orthographic projection of the first low-temperature polysilicon thin film transistor T1 on the substrate 10.

[0055] Preferably, in a possible example scenario, the gate of the second low-temperature polysilicon thin film transistor is arranged in the same layer as the gate of the first low-temperature polysilicon thin film transistor, and the active layer of the second low-temperature polysilicon thin film transistor is arranged in the same layer as the active layer of the first low-temperature polysilicon thin film transistor. This part is not shown in the drawings.

[0056] Preferably, in a possible example scenario, the plurality of low temperature polysilicon thin film transistors 60 are made of low temperature polysilicon semiconductor (Low Temperature Poly Si, LTPS for short) material.

[0057] according to Figure 3a An array substrate is provided, in which a single-gate oxide thin film transistor is arranged on a side of a capacitor away from a substrate, and at the same time, a partial stacking design of the capacitor and the low-temperature polysilicon thin film transistor is retained, so as to make full use of the space on the side of the capacitor away from the substrate and improve the pixel density corresponding to the pixel circuit.

[0058] Figure 3b A schematic diagram of the film layer structure of another array substrate provided in Example 2 of the present application. Figure 3b The array substrate shown is Figure 3a The difference of the array substrate shown is that the oxide thin film transistor 30 further includes a second gate 303 , and the second gate 303 is located on a side of the first gate 301 close to the substrate 10 .

[0059] Preferably, the active layer 302 of the oxide thin film transistor (ie, the P—Si layer in FIG. 1 ) is located between the first gate 301 and the second gate 303 .

[0060] Preferably, the orthographic projection of the second gate 303 on the substrate 10 overlaps with the orthographic projection of the active layer 302 of the oxide thin film transistor on the substrate 10 .

[0061] Preferably, the orthographic projection of the first gate 301 on the substrate 10 is located within the orthographic projection of the second gate 303 on the substrate 10 .

[0062] Preferably, the array substrate 100 further includes a first insulating layer 40 located between the oxide thin film transistor 30 and the capacitor 20 .

[0063] Preferably, the array substrate 100 further includes a second insulating layer 70 located between the active layer 302 and the second gate 303 of the oxide thin film transistor, and the second insulating layer 70 and the first insulating layer 40 are made of the same material.

[0064] Preferably, the second gate 303 is set as a conductive layer, and the material may be molybdenum or titanium, which is the same as the material of the second electrode in the capacitor 20 .

[0065] Preferably, the first gate 301 may be a top gate of the oxide thin film transistor 30, and the second gate 303 may be a bottom gate of the oxide thin film transistor 30. Figure 3b The structure of the double-gate oxide thin film transistor is obtained.

[0066] Preferably, according to Figure 3b In the diagram provided, the active layer 302, the first gate 301 and the second gate 303 of the oxide thin film transistor constitute a double-gate oxide thin film transistor T3. The capacitor and the double-gate oxide thin film transistor T3 are stacked, thereby rationally utilizing the space above the capacitor 20, saving the space occupied by T3, reducing the size of the pixel circuit, and achieving the effect of improving the pixel PPI.

[0067] according to Figure 3b An array substrate is provided, and a dual-gate oxide thin film transistor is arranged on the side of the capacitor away from the substrate. At the same time, a partial stacking design of the capacitor and the low-temperature polysilicon thin film transistor is retained to fully utilize the space on the side of the capacitor away from the substrate, reduce the layout size, and improve the PPI corresponding to the pixel circuit.

[0068] Embodiment 3 Figure 4a A schematic diagram of the film layer structure of an array substrate provided in Example 3 of the present application. Figure 4b For the corresponding Figure 4a Local wiring diagram of the array substrate. Figure 4c and Figure 4d For the corresponding Figure 4b Split diagram of the dotted part. Figure 4a and Figure 4b The array shown is basically the same as Figure 3bThe basic difference of the array shown is that at least one oxide thin film transistor 30 includes a first oxide thin film transistor 31 and a second oxide thin film transistor 32, the gate of the first oxide thin film transistor and the gate of the second oxide thin film transistor are arranged in the same layer, and the active layer of the first oxide thin film transistor and the active layer of the second oxide thin film transistor are arranged in the same layer.

[0069] Preferably, when the first oxide thin film transistor 31 and the second oxide thin film transistor 32 are both oxide thin film transistors with a dual-gate structure, the following can be obtained: Figure 4a In the structure shown, two double-gate oxide thin film transistors are arranged on the side of the capacitor 20 away from the substrate 10, and the structures of the two double-gate oxide thin film transistors are the same.

[0070] Optionally, the orthographic projection of the first oxide thin film transistor 31 on the substrate 10 does not overlap with the projection of the second oxide thin film transistor 32 on the substrate 10. At the same time, the orthographic projection of the first oxide thin film transistor 31 on the substrate partially overlaps with the orthographic projection of the capacitor 20 on the substrate 10, and the projection of the second oxide thin film transistor 32 on the substrate 10 partially overlaps with the orthographic projection of the capacitor 20 on the substrate 10.

[0071] Preferably, in a possible example scenario, combined with Figure 4b In the diagram provided, the plurality of low-temperature polysilicon thin film transistors 60 also include low-temperature polysilicon thin film transistors T5, T6, T7 and T8, which are made of the same material. The specific wiring position is the same as the driving transistor position and structure corresponding to 8T1C in the traditional pixel circuit, which is not the focus of this application and will not be repeated here.

[0072] Figure 4e A schematic diagram of the film layer structure of another array substrate provided in Example 3 of the present application. Figure 4f For the corresponding Figure 4e Local wiring diagram of the array substrate. Figure 4g and Figure 4h For the corresponding Figure 4f Split diagram of the dotted part. Figure 4e and Figure 4f The array shown is basically the same as Figure 3a The basic difference of the array shown is that at least one oxide thin film transistor 30 includes a first oxide thin film transistor 31 and a second oxide thin film transistor 32, the gate of the first oxide thin film transistor and the gate of the second oxide thin film transistor are arranged in the same layer, and the active layer of the first oxide thin film transistor and the active layer of the second oxide thin film transistor are arranged in the same layer.

[0073] Preferably, when the first oxide thin film transistor 31 and the second oxide thin film transistor 32 are both oxide thin film transistors with a single-gate structure, the following can be obtained: Figure 4e In the structure shown, two single-gate oxide thin film transistors are arranged on the side of the capacitor 20 away from the substrate 10, and the structures of the two single-gate oxide thin film transistors are the same.

[0074] Optionally, the orthographic projection of the first oxide thin film transistor 31 on the substrate 10 does not overlap with the projection of the second oxide thin film transistor 32 on the substrate 10. At the same time, the orthographic projection of the first oxide thin film transistor 31 on the substrate partially overlaps with the orthographic projection of the capacitor 20 on the substrate 10, and the projection of the second oxide thin film transistor 32 on the substrate 10 partially overlaps with the orthographic projection of the capacitor 20 on the substrate 10.

[0075] Preferably, in a possible example scenario, combined with Figure 4f In the diagram provided, the plurality of low-temperature polysilicon thin film transistors 60 also include low-temperature polysilicon thin film transistors T5, T6, T7 and T8, which are made of the same material. The specific wiring position is the same as the driving transistor position and structure corresponding to 8T1C in the traditional pixel circuit, which is not the focus of this application and will not be repeated here.

[0076] Figure 4i This is a schematic diagram of the film layer structure of another array substrate provided in Example 3 of the present application. Figure 4j For the corresponding Figure 4i Local wiring diagram of the array substrate. Figure 4k and Figure 4l For the corresponding Figure 4j Split diagram of the dotted part. Figure 4i and Figure 4j The array shown is basically the same as Figure 3a and Figure 3b The basic difference of the array shown is that at least one oxide thin film transistor 30 includes a first oxide thin film transistor 31 and a second oxide thin film transistor 32, the gate of the first oxide thin film transistor and the gate of the second oxide thin film transistor are arranged in the same layer, and the active layer of the first oxide thin film transistor and the active layer of the second oxide thin film transistor are arranged in the same layer.

[0077] Preferably, when the first oxide thin film transistor 31 is an oxide thin film transistor with a single gate structure and the second oxide thin film transistor 32 is an oxide thin film transistor with a double gate structure, the following can be obtained: Figure 4i In the structure shown, a single-gate oxide thin film transistor T4 and a double-gate oxide thin film transistor T3 are arranged on the side of the capacitor 20 away from the substrate 10. The first gate of the first oxide thin film transistor and the first gate of the second oxide thin film transistor are arranged in the same layer.

[0078] Optionally, the orthographic projection of the first oxide thin film transistor 31 on the substrate 10 does not overlap with the projection of the second oxide thin film transistor 32 on the substrate 10. At the same time, the orthographic projection of the first oxide thin film transistor 31 on the substrate partially overlaps with the orthographic projection of the capacitor 20 on the substrate 10, and the projection of the second oxide thin film transistor 32 on the substrate 10 partially overlaps with the orthographic projection of the capacitor 20 on the substrate 10.

[0079] Optionally, three or more oxide thin film transistors may be arranged in the space on the side of the capacitor away from the substrate according to different functional circuits.

[0080] Preferably, in a possible example scenario, combined with Figure 4j In the diagram provided, the plurality of low-temperature polysilicon thin film transistors 60 also include low-temperature polysilicon thin film transistors T5, T6, T7 and T8, which are made of the same material. The specific wiring position is the same as the driving transistor position and structure corresponding to 8T1C in the traditional pixel circuit, which is not the focus of this application and will not be repeated here.

[0081] The array substrate provided by the present application forms a double-gate oxide thin film transistor by arranging a single-gate oxide thin film transistor on the side of the capacitor away from the substrate, and adding a layer of conductor as the second gate of the IGZO transistor on the basis of a conventional OLED process film layer using LTPO technology. The space on the side of the capacitor away from the substrate is fully utilized, the space occupied by the oxide thin film transistor is saved, the wiring size is reduced, and the pixel density is improved.

[0082] Embodiment 4 Figure 5 A schematic diagram of a method for preparing an array substrate provided in Example 4 of the present application. Figure 5 The steps of the method for preparing the array substrate include: S501, preparing a capacitor and a plurality of low-temperature polysilicon thin film transistors on a substrate.

[0083] In this embodiment, the specific implementation of S501 is the same as the conventional preparation process, and will not be described in detail here.

[0084] S502 , preparing a first insulating layer on the side of the capacitor and a plurality of low-temperature polysilicon thin film transistors facing away from the substrate.

[0085] Optionally, in a possible example scenario, the first insulating layer may be obtained by chemical vapor deposition (CVD).

[0086] S503 , preparing at least one oxide thin film transistor on a side of the first insulating layer facing away from the substrate.

[0087] The orthographic projection of the oxide thin film transistor on the substrate overlaps with the orthographic projection of the capacitor on the substrate.

[0088] Furthermore, a gate and an active layer are respectively prepared on a side of the first insulating layer away from the substrate according to the structure of an oxide thin film transistor, wherein the active layer and the gate are isolated from each other by an insulating layer.

[0089] Preferably, a source electrode and a drain electrode are prepared at both ends of the active layer by etching and deposition, and an oxide thin film transistor is obtained on the side of the capacitor away from the substrate.

[0090] Embodiment 5 Figure 6 A schematic flow chart of a method for preparing an oxide thin film transistor provided in Example 5 of the present application. Figure 6 This is introduced based on the previous embodiment. Figure 6 The method for preparing an oxide thin film transistor includes: S601 , preparing an oxide material layer on a side of the first insulating layer facing away from the substrate, and performing patterning on the oxide material layer to obtain an active layer of an oxide thin film transistor.

[0091] In one embodiment, an oxide material layer may be obtained by chemical vapor deposition (CVD), and then the oxide material layer may be patterned to obtain an active layer of an oxide thin film transistor.

[0092] S602 , preparing a third insulating layer on the side of the active layer facing away from the substrate.

[0093] In one embodiment, the third insulating layer 80 may be formed on the side of the active layer facing away from the substrate by chemical vapor deposition (CVD).

[0094] S603 , preparing a first gate on a side of the third insulating layer facing away from the substrate.

[0095] In one embodiment, the first gate may be obtained by physical vapor deposition (PVD), and then the first gate material layer may be patterned to obtain the first gate.

[0096] Preferably, the active layer of the oxide thin film transistor can be deposited by plasma enhanced chemical vapor deposition (PECVD) equipment, and the third insulating layer can be patterned to form a via. Then, a single layer or stacked metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), and copper (Cu) is deposited by physical vapor deposition equipment to obtain a source and drain layer. The source and drain layer is patterned to form a source S and a drain D. Then, a single-gate oxide thin film transistor is prepared.

[0097] Figure 7 A schematic diagram of a process for preparing another oxide thin film transistor provided in Example 5 of the present application. Figure 7 The diagram provided, Figure 7 and Figure 6 The difference is that the method for preparing the oxide thin film transistor also includes: S701, preparing a second gate on a side of the first insulating layer facing away from the substrate.

[0098] Preferably, the process of preparing the second gate is the same as the process of preparing the first gate, which will not be described in detail here.

[0099] S702 , preparing an oxide material layer on the side of the second gate facing away from the substrate, and performing patterning on the oxide material layer to obtain an active layer of the oxide thin film transistor.

[0100] Preferably, the second insulating layer is made of the same material as the first insulating layer.

[0101] Furthermore, step S601 of the preparation process of the active layer of the oxide thin film transistor has been described, and will not be described here one by one.

[0102] Preferably, a patterning process is performed on the second insulating layer to form a via hole, and then a single layer or a stacked layer of metal is deposited using a physical vapor deposition device to obtain the gate M3.

[0103] Embodiment 6 Figure 8 This is a schematic diagram of the structure of a display panel 1000 provided in Embodiment 6 of the present application. Figure 8 1 , the display panel 1000 includes an array substrate 100 .

[0104] The display panel 1000 provided in this embodiment may be as follows Figure 8 The display panel 1000 shown in FIG. 1 includes: Figure 2-4f The structure of the array substrate shown in FIG. 1 can be implemented as follows: Figure 5-7 All steps of the method for preparing the array substrate are implemented Figure 5-7For details on the technical effects of the method for preparing the array substrate shown in FIG. Figure 2-7 For the sake of brevity, the relevant description is not repeated here.

[0105] In addition, in this application, unless otherwise clearly specified and limited, the terms "connected", "connected", "stacked" and the like should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A capacitor, wherein the capacitor is located on one side of the substrate; as well as At least one oxide thin film transistor is located on a side of the capacitor away from the substrate; the oxide thin film transistor and the capacitor have an overlapped orthographic projection on the substrate.

2. The array substrate according to claim 1, characterized in that: The capacitor includes a first electrode plate and a second electrode plate stacked in a direction away from the substrate, and an orthographic projection of the first electrode plate on the substrate overlaps with an orthographic projection of the second electrode plate on the substrate.

3. The array substrate according to claim 1, characterized in that: The oxide thin film transistor comprises a first gate, and an orthographic projection of the first gate on the substrate overlaps with an orthographic projection of the capacitor on the substrate; Preferably, the active layer of the oxide thin film transistor is located on a side of the first gate close to the substrate; Preferably, an orthographic projection of the first gate on the substrate overlaps with an orthographic projection of the active layer of the oxide thin film transistor on the substrate.

4. The array substrate according to claim 3, characterized in that: The oxide thin film transistor further includes a second gate, and the second gate is located on a side of the first gate close to the substrate; Preferably, the active layer of the oxide thin film transistor is located between the first gate and the second gate; Preferably, an orthographic projection of the second gate on the substrate overlaps with an orthographic projection of the active layer of the oxide thin film transistor on the substrate; Preferably, the orthographic projection of the first gate on the substrate is located within the orthographic projection of the second gate on the substrate; Preferably, the array substrate further comprises a first insulating layer located between the oxide thin film transistor and the capacitor; Preferably, the array substrate further comprises a second insulating layer located between the active layer of the oxide thin film transistor and the second gate, and the second insulating layer is made of the same material as the first insulating layer.

5. The array substrate according to claim 1, characterized in that: The at least one oxide thin film transistor includes a first oxide thin film transistor and a second oxide thin film transistor, a gate of the first oxide thin film transistor and a gate of the second oxide thin film transistor are arranged in the same layer, and an active layer of the first oxide thin film transistor and an active layer of the second oxide thin film transistor are arranged in the same layer.

6. The array substrate according to any one of claims 1 to 5, characterized in that: Also included are a plurality of low-temperature polysilicon thin film transistors, wherein the plurality of low-temperature polysilicon thin film transistors include a first low-temperature polysilicon thin film transistor, the first low-temperature polysilicon thin film transistor is located between the substrate and the oxide thin film transistor, and the orthographic projection of the oxide thin film transistor on the substrate overlaps with the orthographic projection of the first low-temperature polysilicon thin film transistor on the substrate; Preferably, the capacitor includes a first electrode plate, and the first electrode plate is multiplexed as a gate of the first low-temperature polysilicon thin-film transistor; Preferably, the active layer of the first low-temperature polysilicon thin film transistor is located on a side of the gate of the first low-temperature polysilicon thin film transistor close to the substrate; Preferably, the plurality of low-temperature polysilicon thin film transistors include a second low-temperature polysilicon thin film transistor, and an orthographic projection of the second low-temperature polysilicon thin film transistor on the substrate and an orthographic projection of the first low-temperature polysilicon thin film transistor on the substrate do not overlap; Preferably, the gate of the second low-temperature polysilicon thin film transistor is arranged in the same layer as the gate of the first low-temperature polysilicon thin film transistor, and the active layer of the second low-temperature polysilicon thin film transistor is arranged in the same layer as the active layer of the first low-temperature polysilicon thin film transistor.

7. A method for preparing an array substrate, characterized in that: include: Fabricating a capacitor and a plurality of low temperature polysilicon thin film transistors on a substrate; Prepare a first insulating layer on the side of the capacitor and the plurality of low-temperature polysilicon thin-film transistors away from the substrate; Prepare at least one oxide thin film transistor on a side of the first insulating layer away from the substrate; The orthographic projection of the oxide thin film transistor on the substrate overlaps with the orthographic projection of the capacitor on the substrate.

8. The method according to claim 7, characterized in that At least one oxide thin film transistor is prepared on a side of the first insulating layer facing away from the substrate, comprising: Preparing an oxide material layer on a side of the first insulating layer away from the substrate, and performing a patterning process on the oxide material layer to obtain an active layer of the oxide thin film transistor; Preparing a third insulating layer on a side of the active layer facing away from the substrate; A first gate is formed on a side of the third insulating layer facing away from the substrate.

9. The method according to claim 8, characterized in that Before preparing the oxide material layer on the side of the first insulating layer facing away from the substrate, the method further comprises: Prepare a second gate on a side of the first insulating layer away from the substrate; Preparing an oxide material layer on a side of the first insulating layer away from the substrate, and patterning the oxide material layer to obtain an active layer of the oxide thin film transistor comprises: Preparing the oxide material layer on the side of the second gate away from the substrate, and performing patterning on the oxide material layer to obtain an active layer of the oxide thin film transistor; Preferably, the second insulating layer and the first insulating layer are made of the same material.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 6.

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