Array substrate, display panel and electronic equipment

Abstract

The invention provides an array substrate, a display panel and electronic equipment, and relates to the technical field of display, the array substrate comprises a first initialization voltage wire, a second initialization voltage wire and a first power supply wire which extend along a first direction; the first initialization voltage wire and the second initialization voltage wire are located on different wire layers; the orthographic projection of one of the first initialization voltage wire and the second initialization voltage wire on the substrate is at least partially overlapped with the orthographic projection of the first power supply wire on the substrate, so that the distance between the wires can be saved, the total metal area can be reduced, and the space utilization rate and the transmittance of the layout can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] In order to overcome the above-mentioned deficiencies in the prior art, the object of the present application is to provide an array substrate, the array substrate comprising a substrate and at least two wiring layers stacked and arranged on one side of the substrate and away from the substrate;

[0005] The array substrate comprises a first initialization voltage wiring, a second initialization voltage wiring and a first power wiring extending along a first direction;

[0006] The first initialization voltage routing and the second initialization voltage routing are located in different routing layers; an orthographic projection of one of the first initialization voltage routing and the second initialization voltage routing on the substrate at least partially overlaps with an orthographic projection of the first power routing on the substrate.

[0007] In a possible implementation, the array substrate further includes a plurality of pixel circuits distributed in an array, the pixel circuits being used to drive the light-emitting device; the pixel circuits include a gate reset transistor and an anode reset transistor; the gate reset transistor is connected to the first initialization voltage wiring, the anode reset transistor is connected to the second initialization voltage wiring, and the cathode of the light-emitting device is connected to the first power wiring;

[0008] The orthographic projection of the second initialization voltage line on the substrate and the orthographic projection of the first power line on the substrate at least partially overlap;

[0009] Preferably, the first initialization voltage wiring and the first power wiring are located in the same wiring layer.

[0010] In a possible implementation, the array substrate has a pixel circuit array area and a border area, the border area surrounds the pixel circuit array area, the pixel circuit array area includes a plurality of pixel circuits distributed in an array, the first power supply line is located in the border area, and the first initialization voltage line and the second initialization voltage line extend from the border area to the pixel circuit array area;

[0011] Preferably, the frame area includes a first sub-frame area and a second sub-frame area located at two opposite sides of the pixel circuit array area, and the first power supply line is located in the first sub-frame area and / or the second sub-frame area;

[0012] Preferably, the second initialization voltage wiring is connected to the first power wiring, and the connection between the second initialization voltage wiring and the first power wiring is located in the first sub-frame area and the second sub-frame area.

[0013] In a possible implementation, the array substrate further includes a third initialization voltage routing and a fourth initialization voltage routing extending along a second direction, the third initialization voltage routing and the fourth initialization voltage routing are located in the same routing layer, and the third initialization voltage routing and the fourth initialization voltage routing are located in different routing layers from the first initialization voltage routing and the second initialization voltage routing; the second direction is perpendicular to the first direction;

[0014] The third initialization voltage routing line is connected to the first initialization voltage routing line through a first via hole, and the fourth initialization voltage routing line is connected to the second initialization voltage routing line through a second via hole.

[0015] Another object of the present application is to provide an array substrate, the array substrate comprising a first initialization voltage trace and a first power trace extending along a first direction;

[0016] The array substrate also includes a plurality of pixel circuits distributed in an array, and the pixel circuits are used to drive the light-emitting device; the pixel circuits include a gate reset transistor and an anode reset transistor; the gate reset transistor is connected to the first initialization voltage wiring, the anode reset transistor is connected to the first power wiring, and the cathode of the light-emitting device is connected to the first power wiring.

[0017] In a possible implementation, the array substrate includes a substrate and at least two wiring layers located on one side of the substrate and stacked in a direction away from the substrate;

[0018] The first initialization voltage wiring and the first power wiring are located in the same wiring layer.

[0019] In a possible implementation, the at least two routing layers include a first routing layer and a second routing layer located on a side of the first routing layer away from the substrate, and the first power routing line is located in the second routing layer;

[0020] Preferably, the first initialization voltage wiring is located in the second wiring layer;

[0021] Preferably, the first wiring layer is a single-layer metal structure, and the second wiring layer includes a first sublayer, a second sublayer and a third sublayer stacked in a direction away from the substrate;

[0022] Preferably, the material of the first wiring layer includes molybdenum; and / or the material of the first sub-layer and the third sub-layer includes titanium, and the material of the second sub-layer includes aluminum.

[0023] In one possible implementation, the pixel circuit also includes a driving transistor, the gate reset transistor is connected between the gate of the driving transistor and the first initialization voltage line, and the anode reset transistor is connected between the anode of the light-emitting device and the second initialization voltage line or the first power supply line.

[0024] Another object of the present application is to provide a display panel, which includes the above-mentioned array substrate provided in the present application.

[0025] Another object of the present application is to provide an electronic device, which includes the above-mentioned display panel provided in the present application.

[0026] Compared with the prior art, this application has the following beneficial effects:

[0027] The embodiments of the present application provide an array substrate, a display panel and an electronic device. By setting the orthographic projection of one of the first initialization voltage line and the second initialization voltage line on the substrate to at least partially overlap with the orthographic projection of the first power line on the substrate, the line width of an initialization voltage line can be reduced, thereby saving the line spacing. At the same time, the total metal area can also be reduced, and the layout space utilization and transmittance can be improved.

[0028] In addition, by arranging the first power supply line and the second initialization signal line on the same line, the line width can be reduced, the line spacing can be saved, the total metal area can be reduced, the layout space utilization and transmittance can be improved, the parasitic capacitance can be reduced, and the risk of metal short circuit between process layers can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 is a schematic diagram of the structure of an array substrate in the prior art;

[0031] Figure 2a One of the structural schematic diagrams of the array substrate provided in the embodiment of the present application;

[0032] Figure 2b A second structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0033] Figure 3a Provided in the embodiments of this application Figure 2a Schematic diagram of the cross section at the AA position;

[0034] Figure 3b Provided in the embodiments of this application Figure 2b Schematic diagram of the cross section at the AA position;

[0035] Figure 4 One of the schematic diagrams of a pixel circuit provided in an embodiment of the present application;

[0036] Figure 5 is a cross-sectional schematic diagram of an array substrate in the prior art;

[0037] Figure 6 A cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application;

[0038] Figure 7 The third structural schematic diagram of the array substrate provided in the embodiment of the present application;

[0039] Figure 8 A schematic diagram of the distribution of initialization signal routing provided in an embodiment of the present application;

[0040] Fig. 9 A fourth structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0041] Fig.10 This is a second schematic diagram of a pixel circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0045] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0046] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0047] The inventor has found that, please refer to Figure 1 In some display panels, the first initialization signal routing 210' of the reset gate (such as the routing for transmitting the first initialization voltage Vref1) and the second initialization signal routing 220' of the reset anode (such as the routing for transmitting the second initialization voltage Vref2) are located in the same routing layer, and the first initialization signal routing 210' and the second initialization signal routing 220' and the first power routing 310' are located in different routing layers. In order to improve the display uniformity of low grayscale images, the first initialization signal routing 210' and the second initialization signal routing 220' are usually set separately, which leads to tight layout space and reduced transmittance.

[0048] In view of this, this embodiment provides a solution that can solve the above-mentioned problem, and the solution provided by this embodiment is described in detail below.

[0049] Please refer to Figure 2a and Figure 2b , Figure 2a and Figure 2b The schematic structural diagram of the array substrate provided by the present embodiment is illustrated as follows: The array substrate may include a substrate and at least two wiring layers located on one side of the substrate and stacked in a direction away from the substrate.

[0050] The array substrate may include a first initialization voltage trace 210 , a second initialization voltage trace 220 , and a first power trace 310 extending along a first direction D1 .

[0051] The first initialization voltage trace 210 may be used to transmit a first initialization voltage Vref1 , the second initialization voltage trace 220 may be used to transmit a second initialization voltage Vref2 , and the first power trace 310 may be used to transmit a first power voltage VSS.

[0052] See also Figure 3a and Figure 3b , Figure 3a for Figure 2a Schematic diagram of the cross section at the AA position. Figure 3b for Figure 2b The array substrate may include a substrate and at least two wiring layers stacked and arranged on one side of the substrate and away from the substrate. Optionally, an insulating layer may be arranged between two adjacent wiring layers.

[0053] The first initialization voltage trace 210 and the second initialization voltage trace 220 are located in different trace layers. The orthographic projection of one of the first initialization voltage trace 210 and the second initialization voltage trace 220 on the substrate at least partially overlaps with the orthographic projection of the first power trace 310 on the substrate.

[0054] In this embodiment, one of the first initialization voltage routing 210 and the second initialization voltage routing 220 is located in a different routing layer from the first power routing 310, and the orthographic projection of one of the first initialization voltage routing 210 and the second initialization voltage routing 220 on the substrate may partially overlap or completely overlap with the orthographic projection of the first power routing 310 on the substrate, and the other of the first initialization voltage routing 210 and the second initialization voltage routing 220 may be located in the same routing layer as the first power routing 310.

[0055] For example, the at least two routing layers may include a first routing layer 200 and a second routing layer 300 located on a side of the first routing layer 200 away from the substrate. Figure 3aAs shown, the second initialization voltage wiring 220 may be located in the first wiring layer 200, and the first initialization voltage wiring 210 and the first power wiring 310 may be located in the second wiring layer 300. Alternatively, as Figure 3b As shown, the first initialization voltage wiring 210 may be located in the first wiring layer 200 , and the second initialization voltage wiring 220 and the first power wiring 310 may be located in the second wiring layer 300 .

[0056] Please refer to Figure 4 The array substrate may further include a plurality of pixel circuits 700 distributed in an array, and the pixel circuits 700 may be used to drive the light emitting device EL. The pixel circuit 700 may include a gate reset transistor M4 and an anode reset transistor M7; the gate reset transistor M4 is connected to the first initialization voltage wiring 210, the anode reset transistor M7 is connected to the second initialization voltage wiring 220, and the cathode of the light emitting device EL is connected to the first power wiring 310.

[0057] In some possible implementations, such as Figure 4 As shown, the pixel circuit 700 provided in this embodiment can adopt the circuit form of 7T1C. Specifically, the pixel circuit 700 can also include a driving transistor M1, a storage capacitor Cst, a first light emission control transistor M5, a second light emission control transistor M6, a compensation transistor M3 and a data writing transistor M2. The array substrate can also include a second power supply line 420 (a line for transmitting a second power supply voltage VDD) and a data signal line 410 (a line for transmitting a data signal Data).

[0058] The gate reset transistor M4 is connected between the gate of the driving transistor M1 and the first initialization voltage wiring 210, and the anode reset transistor M7 is connected between the anode of the light emitting device EL and the second initialization voltage wiring 220. The driving transistor M1 is connected between the second power wiring 420 and the anode of the light emitting device EL, the first end of the storage capacitor Cst is connected to the second power wiring 420, the second end of the storage capacitor Cst is connected to the gate of the driving transistor M1, the second light emitting control transistor M6 is connected between the first electrode of the driving transistor M1 and the anode of the light emitting device EL, the first light emitting control transistor M5 is connected between the second power wiring 420 and the second electrode of the driving transistor M1, and the compensation transistor M3 is connected between the first electrode of the driving transistor M1 and the gate of the driving transistor M1, wherein the first electrode of the driving transistor M1 is one of the source and the drain, and the second electrode of the driving transistor M1 is the other of the source and the drain. The data writing transistor M2 is connected between the data signal wiring 410 and the second electrode of the driving transistor M1.

[0059] In this embodiment, the pixel circuit 700 may include a plurality of pixel circuit rows and a plurality of pixel unit columns. The plurality of pixel circuit rows may be arranged along the second direction D2 , and the plurality of pixel circuit columns may be arranged along the first direction D1 .

[0060] Based on the above design, in the array substrate provided in this embodiment, by setting the orthographic projection of one of the first initialization voltage line 210 and the second initialization voltage line 220 on the substrate to at least partially overlap with the orthographic projection of the first power line 310 on the substrate, the line width of an initialization voltage line can be reduced, thereby saving the line spacing. At the same time, the total metal area can also be reduced, thereby improving the layout space utilization and transmittance.

[0061] Please refer to Figure 5 In the prior art, the first initialization voltage wiring 210 needs to be punched to the second wiring layer 300, and then punched from the second wiring layer 300 to the active layer 500 to achieve the function of resetting the gate.

[0062] In a possible implementation, an orthographic projection of the second initialization voltage trace 220 on the substrate and an orthographic projection of the first power trace 310 on the substrate at least partially overlap.

[0063] Preferably, please refer to Figure 6 , the first initialization voltage wiring 210 and the first power wiring 310 are located in the same wiring layer.

[0064] In this embodiment, the first initialization voltage routing 210 and the first power routing 310 can be located in the same routing layer, the second initialization voltage routing 220 and the first power routing 310 can be located in different routing layers, the orthographic projection of the second initialization voltage routing 220 on the substrate and the orthographic projection of the first power routing 310 on the substrate can partially overlap, and the orthographic projection of the second initialization voltage routing 220 on the substrate and the orthographic projection of the first power routing 310 on the substrate can also completely overlap.

[0065] In the above design, by setting the first initialization voltage routing 210 and the first power routing 310 to the same routing layer, the first initialization voltage routing 210 can be directly punched to the active layer 500 to realize the function of resetting the gate. In this way, the number of punchings can be saved, the voltage drop of the routing can be effectively reduced, and power consumption can be saved.

[0066] Please refer again Figure 2a and Figure 2b The array substrate may further include a first initialization voltage trace 210 extending along a second direction D2, the first direction D1 is perpendicular to the second direction D2, and the first initialization voltage trace 210 extending along the second direction D2 and the first power trace 310 may be located in the same trace layer.

[0067] In one possible implementation, see Figure 7 The array substrate has a pixel circuit array area 620 and a border area 610. The border area 610 can be arranged around the pixel circuit array area 620. The pixel circuit array area 620 can include a plurality of pixel circuits 700 distributed in an array. The first power supply line 310 can be located in the border area 610. The first initialization voltage line 210 and the second initialization voltage line 220 can both extend from the border area 610 to the pixel circuit array area 620.

[0068] In the present embodiment, the border area 610 may include a first sub-border area 611 and a second sub-border area 612 located on opposite sides of the pixel circuit array area 620, and may also include a third sub-border area 613 and a fourth sub-border area 614 located between the first sub-border area 611 and the second sub-border area 612, and the third sub-border area 613 and the fourth sub-border area 614 are also located on opposite sides of the pixel circuit array area 620, and the first power supply line 310 may be located in the first sub-border area 611 and / or the second sub-border area 612. The second initialization voltage line 220 is connected to the first power supply line 310, and the connection between the second initialization voltage line 220 and the first power supply line 310 may be located in the first sub-border area 611 and the second sub-border area 612.

[0069] In one possible implementation, see Figure 8 The array substrate may further include a third initialization voltage trace 401 and a fourth initialization voltage trace 402 extending along the second direction D2. The third initialization voltage trace 401 and the fourth initialization voltage trace 402 may be located in the same trace layer, and the third initialization voltage trace 401 and the fourth initialization voltage trace 402 and the first initialization voltage trace 210 and the second initialization voltage trace 220 may be located in different trace layers. The third initialization voltage trace 401 and the first initialization voltage trace 210 may be connected through a first via hole, and the fourth initialization voltage trace 402 and the second initialization voltage trace 220 may be connected through a second via hole.

[0070] In this embodiment, the array substrate may include a first routing layer 200, a second routing layer 300 and a third routing layer 400 which are stacked, the third initialization voltage routing 401 and the fourth initialization voltage routing 402 may be located in the third routing layer 400, the first initialization voltage routing 210 may be located in the second routing layer 300, and the second initialization voltage routing 220 may be located in the first routing layer 200.

[0071] In addition, the extension direction of the third initialization voltage line 401 and the fourth initialization voltage line 402 is perpendicular to the extension direction of the first initialization voltage line 210 and the second initialization voltage line 220 .

[0072] In the above design, the first initialization voltage line 210, the second initialization voltage line 220, the third initialization voltage line 401 and the fourth initialization voltage line 402 are designed in a mesh shape in the first direction D1 and the second direction D2, which can improve the voltage uniformity of the first initialization voltage line 210, the second initialization voltage line 220, the third initialization voltage line 401 and the fourth initialization voltage line 402.

[0073] The present application also provides another array substrate. Fig. 9 , the array substrate may include a first initialization voltage trace 210 and a first power trace 310 extending along a first direction D1.

[0074] Please refer to Fig.10 The array substrate may further include a plurality of pixel circuits 700 distributed in an array, and the pixel circuits 700 are used to drive the light emitting device EL. The pixel circuit 700 may include a gate reset transistor M4 and an anode reset transistor M7; the gate reset transistor M4 is connected to the first initialization voltage wiring 210, the anode reset transistor M7 is connected to the first power wiring 310, and the cathode of the light emitting device EL is connected to the first power wiring 310.

[0075] In this embodiment, the pixel circuit 700 may include a plurality of pixel circuit rows and a plurality of pixel unit columns, the plurality of pixel circuit rows may be arranged along the second direction D2, and the plurality of pixel circuit columns may be arranged along the first direction D1. The first power supply line 310 may be connected to the anode reset transistor M7 as a line for transmitting the second initialization voltage Vref2, and the anode reset transistor M7 may be connected between the anode of the light emitting device EL and the first power supply line 310.

[0076] Based on the above design, in the array substrate provided in this embodiment, by arranging the first power line 310 (VSS) and the second initialization signal line on the same line, it is possible to reduce the line width, save the line spacing, save the number of punching holes, reduce the total metal area, improve the layout space utilization and transmittance, reduce parasitic capacitance, and reduce the risk of metal short circuit between process layers.

[0077] In a possible implementation, the array substrate may include a substrate and at least two wiring layers located on one side of the substrate and stacked in a direction away from the substrate. Optionally, an insulating layer may be further disposed between two adjacent wiring layers.

[0078] The first initialization voltage wiring 210 and the first power wiring 310 may be located in the same wiring layer.

[0079] Please refer again Fig. 9The array substrate may further include a first initialization voltage trace 210 extending along a second direction D2, the first direction D1 is perpendicular to the second direction D2, and the first initialization voltage trace 210 extending along the second direction D2 and the first power trace 310 are located in the same trace layer.

[0080] In a possible implementation, the at least two routing layers may include a first routing layer 200 and a second routing layer 300 located on a side of the first routing layer 200 away from the substrate, and the first initialization voltage routing 210 and the first power routing 310 may be located in the second routing layer 300 .

[0081] The first routing layer 200 may be a single-layer metal structure, and the second routing layer 300 may include a first sublayer, a second sublayer, and a third sublayer stacked in a direction away from the substrate.

[0082] Specifically, the material of the first wiring layer 200 may include molybdenum. The materials of the first sub-layer and the third sub-layer may include titanium, and the material of the second sub-layer may include aluminum.

[0083] In one possible implementation, please refer again to Fig.10 The pixel circuit 700 may further include a driving transistor M1, a gate reset transistor M4 connected between the gate of the driving transistor M1 and the first initialization voltage wiring 210, and an anode reset transistor M7 connected between the anode of the light emitting device EL and the first power wiring 310.

[0084] In one possible implementation, please refer again to Fig.10 The pixel circuit 700 may further include a storage capacitor Cst, a first light emission control transistor M5, a second light emission control transistor M6 and a compensation transistor M3. The array substrate may further include a second power supply line 420 extending along a second direction D2, wherein the first direction D1 is perpendicular to the second direction D2. The driving transistor M1 is connected between the second power supply line 420 and the anode of the light emitting device EL, the first end of the storage capacitor Cst is connected to the second power supply line 420, the second end of the storage capacitor Cst is connected to the gate of the driving transistor M1, the second light emission control transistor M6 is connected between the first electrode of the driving transistor M1 and the anode of the light emitting device EL, the first light emission control transistor M5 is connected between the second power supply line 420 and the second electrode of the driving transistor M1, and the compensation transistor M3 is connected between the first electrode of the driving transistor M1 and the gate of the driving transistor M1, wherein the first electrode of the driving transistor M1 is one of the source and the drain, and the second electrode of the driving transistor M1 is the other of the source and the drain.

[0085] Specifically, the first electrode of the driving transistor M1 may be a drain, and the second electrode of the driving transistor M1 may be a source.

[0086] In one possible implementation, please refer again to Fig.10 The pixel circuit 700 may further include a data writing transistor M2, and the array substrate may further include a data signal wiring 410 extending along the second direction D2, and the data writing transistor M2 is connected between the data signal wiring 410 and the second electrode of the driving transistor M1.

[0087] In addition, in this embodiment, in addition to the first initialization voltage line 210, the second initialization voltage line 220, the first power line 310, the data signal line 410 and the second power line 420, the array substrate may also include a scan signal line and a light-emitting control signal line 130, which are not described one by one in this embodiment. In addition, the scan signal line may also include multiple lines that are independent of each other, for example, the scan signal line may include a line 110 for transmitting the first scan signal S1, a line 120 for transmitting the second scan signal S2 and a line for transmitting the third scan signal S3.

[0088] The light-emitting control signal wiring 130 can be used to transmit the light-emitting control signal EM, the scanning signal wiring can be used to transmit the scanning signal Scan for the pixel circuit 700, the gate reset transistor M4 is connected to the wiring for transmitting the first scanning signal S1, the data write transistor M2 is connected to the wiring for transmitting the second scanning signal S2, and the anode reset transistor M7 is connected to the wiring for transmitting the third scanning signal S3. The gate reset transistor M4 can be used to receive the first scanning signal S1, the data write transistor M2 can be used to receive the second scanning signal S2, and the anode reset transistor M7 can be used to receive the third scanning signal S3.

[0089] An embodiment of the present application further provides a display panel, which may include the array substrate provided in this embodiment. The display panel may further include a light-emitting functional film layer or a light-emitting device located on one side of the array substrate.

[0090] An embodiment of the present application further provides an electronic device, which may include the above-mentioned display panel provided by this embodiment.

[0091] In summary, the embodiments of the present application provide an array substrate, a display panel and an electronic device. By setting the orthographic projection of a first initialization voltage line and one of the second initialization voltage lines on the substrate to at least partially overlap with the orthographic projection of the first power line on the substrate, the line width of an initialization voltage line can be shortened, thereby saving the line spacing. At the same time, the total metal area can also be reduced, thereby improving the layout space utilization and transmittance.

[0092] In addition, by arranging the first power supply line and the second initialization signal line on the same line, the line width can be reduced, the line spacing can be saved, the total metal area can be reduced, the layout space utilization and transmittance can be improved, the parasitic capacitance can be reduced, and the risk of metal short circuit between process layers can be reduced.

[0093] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a substrate and at least two wiring layers which are located on one side of the substrate and are stacked in a direction away from the substrate; The array substrate comprises a first initialization voltage wiring, a second initialization voltage wiring and a first power wiring extending along a first direction; The first initialization voltage routing and the second initialization voltage routing are located in different routing layers; an orthographic projection of one of the first initialization voltage routing and the second initialization voltage routing on the substrate at least partially overlaps with an orthographic projection of the first power routing on the substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes a plurality of pixel circuits distributed in an array, the pixel circuits being used to drive the light-emitting device; the pixel circuits include a gate reset transistor and an anode reset transistor; the gate reset transistor is connected to the first initialization voltage wiring, the anode reset transistor is connected to the second initialization voltage wiring, and the cathode of the light-emitting device is connected to the first power wiring; The orthographic projection of the second initialization voltage line on the substrate and the orthographic projection of the first power line on the substrate at least partially overlap; Preferably, the first initialization voltage wiring and the first power wiring are located in the same wiring layer.

3. The array substrate according to claim 1, characterized in that: The array substrate comprises a pixel circuit array area and a frame area, wherein the frame area surrounds the pixel circuit array area, the pixel circuit array area comprises a plurality of pixel circuits distributed in an array, the first power supply line is located in the frame area, and the first initialization voltage line and the second initialization voltage line extend from the frame area to the pixel circuit array area; Preferably, the frame area includes a first sub-frame area and a second sub-frame area located at two opposite sides of the pixel circuit array area, and the first power supply line is located in the first sub-frame area and / or the second sub-frame area; Preferably, the second initialization voltage wiring is connected to the first power wiring, and the connection between the second initialization voltage wiring and the first power wiring is located in the first sub-frame area and the second sub-frame area.

4. The array substrate according to claim 3, characterized in that: The array substrate further includes a third initialization voltage routing line and a fourth initialization voltage routing line extending along a second direction, the third initialization voltage routing line and the fourth initialization voltage routing line are located in the same routing layer, and the third initialization voltage routing line and the fourth initialization voltage routing line are located in different routing layers from the first initialization voltage routing line and the second initialization voltage routing line; the second direction is perpendicular to the first direction; The third initialization voltage routing line is connected to the first initialization voltage routing line through a first via hole, and the fourth initialization voltage routing line is connected to the second initialization voltage routing line through a second via hole.

5. An array substrate, characterized in that: The array substrate comprises a first initialization voltage wiring and a first power wiring extending along a first direction; The array substrate also includes a plurality of pixel circuits distributed in an array, and the pixel circuits are used to drive the light-emitting device; the pixel circuits include a gate reset transistor and an anode reset transistor; the gate reset transistor is connected to the first initialization voltage wiring, the anode reset transistor is connected to the first power wiring, and the cathode of the light-emitting device is connected to the first power wiring.

6. The array substrate according to claim 5, characterized in that: The array substrate comprises a substrate and at least two wiring layers which are located on one side of the substrate and are stacked in a direction away from the substrate; The first initialization voltage wiring and the first power wiring are located in the same wiring layer.

7. The array substrate according to claim 1 or 5, characterized in that: The at least two routing layers include a first routing layer and a second routing layer located on a side of the first routing layer away from the substrate, and the first power routing is located in the second routing layer; Preferably, the first initialization voltage wiring is located in the second wiring layer; Preferably, the first wiring layer is a single-layer metal structure, and the second wiring layer includes a first sublayer, a second sublayer and a third sublayer stacked in a direction away from the substrate; Preferably, the material of the first wiring layer includes molybdenum; and / or the material of the first sub-layer and the third sub-layer includes titanium, and the material of the second sub-layer includes aluminum.

8. The array substrate according to claim 1 or 5, characterized in that: The pixel circuit also includes a driving transistor, the gate reset transistor is connected between the gate of the driving transistor and the first initialization voltage line, and the anode reset transistor is connected between the anode of the light emitting device and the second initialization voltage line or the first power line.

9. A display panel, characterized in that: The invention comprises the array substrate as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the display panel as claimed in claim 9.

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