Full-color Micro LED display device and preparation method thereof

Abstract

The invention discloses a full-color Micro LED display device and a preparation method thereof, the device comprises a plurality of groups of display units, each display unit comprises a first N-GaN layer, a blue light LED light-emitting layer, a first P-GaN layer, a first heavily doped PN junction layer, a second N-GaN layer, a green light LED light-emitting layer, a second P-GaN layer, a second heavily doped PN junction layer, a third N-GaN layer, a red light LED light-emitting layer, a third P-GaN layer and a third heavily doped PN junction layer, a fourth N-GaN layer and a metal reflection layer; the passivation layer covers the side walls of the first N-GaN layer, the blue light LED light-emitting layer, the first P-GaN layer, the first heavily-doped PN junction layer, the second N-GaN layer, the green light LED light-emitting layer, the second P-GaN layer, the second heavily-doped PN junction layer, the third N-GaN layer, the red light LED light-emitting layer, the third P-GaN layer, the third heavily-doped PN junction layer, the fourth N-GaN layer and the metal reflecting layer; the upper surfaces of the first electrode, the second electrode, the third electrode and the fourth electrode are flush in height; and the CMOS driver covers the upper surface of the bonding layer and is electrically connected with the first electrode, the second electrode, the third electrode and the fourth electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a full-color Micro LED display device and a preparation method thereof. Background Art

[0002] Gallium nitride is a semiconductor material with excellent electrical properties and thermal stability, and is very suitable for manufacturing high-brightness, high-efficiency Micro LEDs. Gallium nitride Micro LEDs have high luminous efficiency, which can significantly reduce energy consumption while providing high enough brightness to meet the needs of full-color display. Gallium nitride Micro LEDs have high stability and can run stably for a long time without prone to failure, which is especially important for full-color display devices that need to run for a long time.

[0003] In order to realize full-color Micro LED display in the prior art, it is often necessary to make devices from three wafers with different luminous colors, and then realize three-color integration by bonding wafers with different luminous wavelengths. This method is complex, costly, low-yield, and has a long production cycle. Alternatively, a full-color display can be realized by changing the luminous wavelength through a piece of epitaxial wafer by changing the magnitude of the current. This method has a limited range of wavelength variation, covering only the range from green to red, or from cyan to red, and the displayed color gamut is insufficient. Summary of the invention

[0004] Purpose of the invention: In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a full-color Micro LED display device. Another purpose of the present invention is to provide a method for preparing a full-color Micro LED display device.

[0005] In order to solve the above technical problems, the present invention provides a full-color Micro LED display device, including a plurality of display units, wherein the display units include:

[0006] A first N-GaN layer, wherein a side edge of the first N-GaN layer has a first step;

[0007] A blue LED light-emitting layer covering the upper surface of the non-step region of the first N-GaN layer;

[0008] A first P-GaN layer covering the upper surface of the blue LED light emitting layer;

[0009] a first heavily doped PN junction layer, covering an upper surface of the first P-GaN layer;

[0010] a second N-GaN layer, covering an upper surface of the first heavily doped PN junction layer, wherein a side edge of the second N-GaN layer has a second step;

[0011] A green LED light-emitting layer covering the upper surface of the second N-GaN layer in the non-step region;

[0012] A second P-GaN layer covering the upper surface of the green LED light-emitting layer;

[0013] a second heavily doped PN junction layer, covering an upper surface of the second P-GaN layer;

[0014] a third N-GaN layer, covering an upper surface of the second heavily doped PN junction layer, wherein a side edge of the third N-GaN layer has a third step;

[0015] A red LED light-emitting layer covering the upper surface of the non-step region of the third N-GaN layer;

[0016] A third P-GaN layer, covering the upper surface of the red LED light-emitting layer;

[0017] a third heavily doped PN junction layer, covering an upper surface of the third P-GaN layer;

[0018] a fourth N-GaN layer, covering an upper surface of the third heavily doped PN junction layer;

[0019] a metal reflective layer, covering an upper surface of the fourth N-GaN layer;

[0020] A passivation layer covering the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red LED light-emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer, and the sidewalls of the metal reflective layer;

[0021] A first electrode, located on the first step and extending back toward the first N-GaN layer;

[0022] a second electrode, located on the second step and extending back toward the first N-GaN layer;

[0023] a third electrode, located on the metal reflective layer and extending back toward the first N-GaN layer;

[0024] a fourth electrode, located on the third step and extending back toward the first N-GaN layer;

[0025] The upper surfaces of the first electrode, the second electrode, the third electrode and the fourth electrode are flush with each other;

[0026] A bonding layer, filling the gaps between the first electrode, the second electrode, the third electrode, the fourth electrode, and the passivation layer and covering the first electrode, the second electrode, the third electrode, the fourth electrode, and the passivation layer;

[0027] A CMOS driver covers the upper surface of the bonding layer and is electrically connected to the first electrode, the second electrode, the third electrode, and the fourth electrode.

[0028] Preferably, the bonding layer includes a first bonding layer and a second bonding layer stacked from bottom to top; the parts of the first electrode, the second electrode, the third electrode, and the fourth electrode located in the second bonding layer are respectively the first contact electrode, the second contact electrode, the third contact electrode, and the fourth contact electrode.

[0029] Preferably, the first heavily doped PN junction layer comprises a first P+-InGaN layer and a first N+-InGaN layer stacked from bottom to top, the first P+-InGaN layer has an In content of 0-10%, a dopant is Mg, and a doping concentration of >5E19cm -3 The first N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration of >2E19cm -3 .

[0030] Preferably, the second heavily doped PN junction layer comprises a second P+-InGaN layer and a second N+-InGaN layer stacked from bottom to top, the second P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration of >5E19cm -3 The second N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration of >2E19cm -3 .

[0031] Preferably, the third heavily doped PN junction layer comprises a third P+-InGaN layer and a third N+-InGaN layer stacked from bottom to top, the In content of the third P+-InGaN layer is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm -3 The third N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration of >2E19cm -3 .

[0032] Preferably, the thickness of the first P+-InGaN layer is 5-20 nm, the thickness of the first N+-InGaN layer is 5-20 nm, and the thickness ratio of the first P+-InGaN layer to the first N+-InGaN layer is 1:1.

[0033] Preferably, the thickness of the second P+-InGaN layer is 5-20 nm, the thickness of the second N+-InGaN layer is 5-20 nm, and the thickness ratio of the second N+-InGaN layer is 1:1.

[0034] Preferably, the thickness of the third P+-InGaN layer is 5-20 nm, the thickness of the third N+-InGaN layer is 5-20 nm, and the thickness ratio of the third P+-InGaN layer to the third N+-InGaN layer is 1:1.

[0035] Based on the same inventive concept, the present invention also provides a method for preparing a full-color Micro LED display device, comprising:

[0036] Forming a first component comprises the following steps:

[0037] Step 11, providing a silicon substrate, and epitaxially growing a nucleation layer, a buffer layer, a first N-GaN layer, a blue LED light-emitting layer, a first P-GaN layer, a first heavily doped PN junction layer, a second N-GaN layer, a green LED light-emitting layer, a second P-GaN layer, a second heavily doped PN junction layer, a third N-GaN layer, a red LED light-emitting layer, a third P-GaN layer, a third heavily doped PN junction layer, and a fourth N-GaN layer in sequence on the surface of the silicon substrate;

[0038] Step 12, etching for the first time, etching a portion of each layer on the first N-GaN layer and a portion of the first N-GaN layer along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer;

[0039] Step 13, etching for the second time, etching a portion of each layer on the second N-GaN layer and a portion of the second N-GaN layer along the thickness direction of the first component, and forming a second step on the side of the second N-GaN layer;

[0040] Step 14, etching for the third time, etching a portion of each layer on the third N-GaN layer and a portion of the third N-GaN layer along the thickness direction of the first component, and forming a third step on the side of the third N-GaN layer;

[0041] Step 15, forming a metal reflective layer on the upper surface of the fourth N-GaN layer;

[0042] Step 16, forming a passivation layer, the passivation layer covers the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red LED light-emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer, and the sidewalls of the metal reflective layer;

[0043] Step 17, respectively disposing a first sub-electrode, a second sub-electrode, a third sub-electrode, and a fourth sub-electrode on the first step, the second step, the metal reflective layer, and the third step;

[0044] Step 18, forming a first bonding layer, wherein the first bonding layer fills the gaps between the first sub-electrode, the second sub-electrode, the third sub-electrode, the fourth sub-electrode, and the passivation layer, and covers the metal reflective layer;

[0045] Step 19, planarizing the first bonding layer;

[0046] Forming the second component comprises the following steps:

[0047] Step 21, providing a CMOS driver, and forming a second bonding layer above the CMOS driver;

[0048] Step 22, etching the second bonding layer along the thickness direction of the second bonding layer to form four through holes penetrating the second bonding layer;

[0049] Step 23, placing a first contact electrode, a second contact electrode, a third contact electrode, and a fourth contact electrode in the through hole respectively;

[0050] Bonding the first component and the second component comprises the following steps:

[0051] Step 31, horizontally transposing the second component, aligning and bonding the first sub-electrode with the first contact electrode, the second sub-electrode with the second contact electrode, the third sub-electrode with the third contact electrode, and the fourth sub-electrode with the fourth contact electrode, and forming a first electrode, a second electrode, a third electrode, and a fourth electrode respectively;

[0052] Step 32, removing the silicon substrate, the nucleation layer, and the buffer layer to obtain the full-color Micro LED display device.

[0053] Preferably, after step 14, the first component is further activated by P-type Mg doping, with a doping concentration of >5E18cm -3 .

[0054] Working principle: In the preparation process of full-color Micro LED display devices, three groups of P+-InGaN / N+-InGaN heavily doped PN junction materials are cleverly introduced to lay a solid foundation for building high-performance electrode structures. The special feature of these PN junctions is their high doping concentration, which directly leads to a significant reduction in the width of the junction area. Under normal circumstances, the junction width of the PN junction is the key factor determining the probability of electron tunneling. The larger the width, the higher the energy required for electron tunneling, and the greater the difficulty. However, in the heavily doped PN junction, due to the increase in doping concentration, the junction width is greatly compressed, allowing electrons to easily pass through this narrow area through the tunneling effect. The quantum tunneling effect is a quantum mechanical phenomenon that allows electrons to cross the potential barrier with a certain probability when the energy is insufficient to overcome the potential barrier. In the heavily doped PN junction, this effect is fully utilized, and electrons can easily achieve reverse conduction, thereby greatly enhancing the conductivity of the electrode. More importantly, this feature brings unprecedented flexibility to electrode production. Since electrons can easily pass through the junction area, the requirements for the etching depth of the material when making electrodes are no longer so stringent. This means that even if there is a certain deviation in the etching depth, it will not have a significant impact on the conductive properties of the electrode, thereby reducing the difficulty and cost of the manufacturing process.

[0055] Beneficial effects: Compared with the prior art, the present invention has the following significant features:

[0056] 1. Three luminous wavelengths are integrated in one epitaxial wafer, and it can be grown once by epitaxial growth, without having to be put into the epitaxial machine (MOCVD / MBE) for re-growth many times. There is no need to bond and integrate three wafers with different luminous wavelengths (RGB) to realize multiple luminous materials, and the device manufacturing process is greatly simplified.

[0057] 2. In the process of electrode manufacturing, there is no need to precisely control the etching depth of the material, the device manufacturing process is highly simplified, and the yield of device manufacturing is improved. By adding a heavily doped PN junction layer, the heavily doped PN junction has a smaller junction width due to the higher doping, and electrons can tunnel through this heavily doped PN junction to form a reverse conduction current. Therefore, each electrode can be placed on the thicker N-type material layer after the heavily doped PN junction through material etching. Since the N-type material layer has a thick thickness, the control of the material etching depth does not need to be very strict.

[0058] 3. The three light-emitting wavelength devices in a wafer can be controlled separately, the light-emitting wavelength can be controlled more accurately, the color adjustment range is wider, and a larger color gamut can be achieved. In addition, the shape of each electrode is relatively vertical, and the process steps are simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In the accompanying drawings, each identical or nearly identical component shown in different drawings is represented by a similar reference numeral. For clarity, not every component in every drawing will be labeled. The drawings are not necessarily drawn to scale, but instead emphasis is placed on illustrating various aspects of the techniques and devices described herein.

[0060] Figure 1 The schematic diagram of the structure of the product obtained in step 11 of the present invention is shown;

[0061] Figure 2 The schematic diagram of the structure of the product obtained in step 14 of the present invention is shown;

[0062] Figure 3 The schematic diagram of the structure of the product obtained in step 15 of the present invention is shown;

[0063] Figure 4 The schematic diagram of the structure of the product obtained in step 16 of the present invention is shown;

[0064] Figure 5 The schematic diagram of the structure of the product obtained in step 17 of the present invention is shown;

[0065] Figure 6 A top view of the product obtained in step 17 of the present invention is shown;

[0066] Figure 7 The schematic diagram of the structure of the product obtained in step 18 of the present invention is shown;

[0067] Figure 8-9 The schematic diagram of the structure of the product obtained in step 21 of the present invention is shown;

[0068] Fig.10 The schematic diagram of the structure of the product obtained in step 22 of the present invention is shown;

[0069] Fig.11 The schematic diagram of the structure of the product obtained in step 23 of the present invention is shown;

[0070] Fig.12 The schematic diagram of the structure of the product obtained in step 32 of the present invention is shown.

[0071] The reference numerals are described as follows:

[0072] 10-substrate, 20-nucleation layer, 30-buffer layer, 40-first N-GaN layer, 50-blue LED light-emitting layer, 60-first P-GaN layer, 70-first heavily doped PN junction layer, 71-first P+-InGaN layer, 72-first N+-InGaN layer, 80-second N-GaN layer, 90-green LED light-emitting layer, 100-second P-GaN layer, 110-second heavily doped PN junction layer, 111-second P+-InGaN layer, 112-second N+-InGaN layer, 120-third N-GaN layer, 130-red LED light-emitting layer, 140 -third P-GaN layer, 150-third heavily-doped PN junction layer, 151-third P+-InGaN layer, 152-third N+-InGaN layer, 160-fourth N-GaN layer, 170-metal reflective layer, 180-passivation layer, 191-first sub-electrode, 192-second sub-electrode, 193-third sub-electrode, 194-fourth sub-electrode, 201-first bonding layer, 202-second bonding layer, 210-CMOS driver, 220-through hole, 231-first contact electrode, 232-second contact electrode, 233-third contact electrode, 234-fourth contact electrode. DETAILED DESCRIPTION

[0073] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided to make the present invention more comprehensive and complete and to fully convey the concepts of example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated description will be omitted.

[0074] The words expressing positions and directions described in the present invention are all explained with reference to the accompanying drawings as examples, but they can be changed as needed, and all such changes are included in the protection scope of the present invention.

[0075] The present invention provides a method for preparing a full-color Micro LED display device, comprising preparing a first component, preparing a second component, and bonding the first component and the second component.

[0076] Specifically, the preparation of the first component, the preparation of the epitaxial structure, can be completed by using MOCVD epitaxial growth equipment, and the steps are as follows:

[0077] Step 11, providing a silicon substrate 10, and epitaxially growing a nucleation layer 20, a buffer layer 30, a first N-GaN layer 40, a blue LED light-emitting layer 50, a first P-GaN layer 60, a first heavily doped PN junction layer 70, a second N-GaN layer 80, a green LED light-emitting layer 90, a second P-GaN layer 100, a second heavily doped PN junction layer 110, a third N-GaN layer 120, a red LED light-emitting layer 130, a third P-GaN layer 140, a third heavily doped PN junction layer 150, and a fourth N-GaN layer 160 in sequence on the surface of the silicon substrate 10, such as Figure 1 shown.

[0078] Specifically, under the conditions of 950-1150° C. and 50-100 torr, a 200 nm AlN nucleation layer 20 is grown on the substrate 10 .

[0079] Under the conditions of temperature of 980-1180° C. and pressure of 50-100 torr, an AlGaN buffer layer 30 with a thickness of 0.2-1 μm is grown on the nucleation layer 20 .

[0080] A first N-GaN layer 40 with a thickness of 0.5-2.0 μm is grown on the buffer layer 30 at a temperature of 1100-1200° C. and a pressure of 200-300 torr.

[0081] Under the conditions of temperature of 760-800° C. and pressure of 400-500 torr, a blue LED light emitting layer 50 with a thickness of 90-150 nm is grown on the first N-GaN layer 40 , and the blue LED light emitting layer 50 is a multi-quantum well structure.

[0082] Under the conditions of temperature of 900-1000° C. and pressure of 200-300 torr, a first P-GaN layer 60 with a thickness of 50-100 nm is grown on the blue LED light emitting layer 50 .

[0083] A first heavily doped PN junction layer 70 is grown on the first P-GaN layer 60, and the first heavily doped PN junction layer 70 includes a first P+-InGaN layer 71 and a first N+-InGaN layer 72 stacked from bottom to top, wherein the In content is 0-10%. When the In content is 0, the first heavily doped PN junction layer 70 includes a first P+-GaN layer 71 and a first N+-GaN layer 72 stacked from bottom to top.

[0084] Under the conditions of 850-950°C temperature and 400-500 torr pressure, a 5-20 nm first P+-InGaN layer 71 is grown on the first P-GaN layer 60, the In content is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm -3 , the preferred value is 1E20cm -3 .

[0085] Under the conditions of 850-950°C temperature and 400-500 torr pressure, a 5-20 nm first N+-InGaN layer 72 is grown on the first P+-InGaN layer 71, the In content is 0-10%, the dopant is Si, and the doping concentration is > 2E19 cm -3 , the preferred value is 3E19cm -3 , a thickness ratio of the first P+-InGaN layer 71 and the first N+-InGaN layer 72 is 1:1.

[0086] Under the conditions of temperature of 1000-1200° C. and pressure of 200-300 torr, a second N-GaN layer 80 with a thickness of 0.5-2.0 μm is grown on the first N + -InGaN layer 72 .

[0087] Under the conditions of 742-782° C. temperature and 400-500 torr pressure, a green LED light emitting layer 90 with a thickness of 90-150 nm is grown on the second N-GaN layer 80 . The green LED light emitting layer 90 is a multi-quantum well structure.

[0088] Under the conditions of temperature of 900-1000° C. and pressure of 200-300 torr, a second P-GaN layer 100 with a thickness of 50-100 nm is grown on the green LED light emitting layer 90 .

[0089] A second heavily doped PN junction layer 110 is grown on the second P-GaN layer 100, and the second heavily doped PN junction layer 110 includes a second P+-InGaN layer 111 and a second N+-InGaN layer 112 stacked from bottom to top, wherein the In content is 0-10%. When the In content is 0, the second heavily doped PN junction layer 110 includes a second P+-GaN layer 111 and a second N+-GaN layer 112 stacked from bottom to top.

[0090] Under the conditions of 850-950°C temperature and 400-500 torr pressure, a 5-20nm second P+-InGaN layer 111 is grown on the second P-GaN layer 100, the In content is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm -3 , the preferred value is 1E20cm -3 .

[0091] Under the conditions of 850-950°C temperature and 400-500 torr pressure, a 5-20 nm second N+-InGaN layer 112 is grown on the second P+-InGaN layer 111, the In content is 0-10%, the dopant is Si, and the doping concentration is >2E19 cm -3 , the preferred value is 3E19cm -3, a thickness ratio of the second P+-InGaN layer to the second N+-InGaN layer is 1:1.

[0092] A third N-GaN layer 120 with a thickness of 0.5-2.0 μm is grown on the second N + -InGaN layer 112 at a temperature of 1000-1200° C. and a pressure of 200-300 torr.

[0093] Under the conditions of 702-742° C. temperature and 400-500 torr pressure, a 90-150 nm red LED light emitting layer 130 is grown on the third N-GaN layer 120 , and the red LED light emitting layer 130 is a multi-quantum well structure.

[0094] Under the conditions of temperature of 900-1000° C. and pressure of 200-300 torr, a third P-GaN layer 140 with a thickness of 50-100 nm is grown on the red LED light emitting layer 130 .

[0095] A third heavily doped PN junction layer 150 is grown on the third P-GaN layer 140, and the third heavily doped PN junction layer 150 includes a third P+-InGaN layer 151 and a third N+-InGaN layer 152 stacked from bottom to top, wherein the In content is 0-10%. When the In content is 0, the third heavily doped PN junction layer 150 includes a third P+-GaN layer 151 and a third N+-GaN layer 152 stacked from bottom to top.

[0096] Under the conditions of 850-950°C temperature and 400-500 torr pressure, a third P+-InGaN layer 151 of 5-20 nm is grown on the third P-GaN layer 140, the In content is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm -3 , the preferred value is 1E20cm -3 .

[0097] Under the conditions of 850-950°C temperature and 400-500 torr pressure, a third N+-InGaN layer 152 with a thickness of 5-20 nm is grown on the third P+-InGaN layer 151, wherein the In content is 0-10%, the dopant is Si, and the doping concentration is >2E19 cm -3 , the preferred value is 3E19cm -3 , a thickness ratio of the third P+-InGaN layer to the third N+-InGaN layer is 1:1.

[0098] The first heavily doped PN junction layer 70 , the second heavily doped PN junction layer 110 , and the third heavily doped PN junction layer 150 are made of InGaN material to reduce the forward voltage.

[0099] A fourth N-GaN layer 160 with a thickness of 0.5-2.0 μm is grown on the third N + -InGaN layer 152 at a temperature of 1000-1200° C. and a pressure of 200-300 torr.

[0100] The epitaxial wafer integrates three light-emitting wavelengths and is formed by one-time epitaxial growth. There is no need to put it into the MOCVD machine for re-growth multiple times. There is no need to bond and integrate three wafers with different light-emitting wavelengths (RGB colors). The related light-emitting materials and device manufacturing processes are greatly simplified.

[0101] Step 12 , etching for the first time, etching a portion of each layer on the first N-GaN layer 40 and a portion of the first N-GaN layer 40 along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer 40 .

[0102] A photoresist is coated on the product obtained in step 11, and a mask is used for exposure and development to form a pattern to be etched, and an ion etching technique is used to etch the epitaxial layer according to the photolithography pattern to remove unnecessary parts, and the first N-GaN layer 40 is etched to form a first step on the side of the first N-GaN layer 40. The thickness of the etched first N-GaN layer 40 is less than the thickness of the first N-GaN layer 40.

[0103] Step 13, etching for the second time, etching a portion of each layer on the second N-GaN layer 80 and a portion of the second N-GaN layer 80 along the thickness direction of the first component, and forming a second step on the side of the second N-GaN layer 80.

[0104] A photoresist is coated on the product obtained in step 12, and a mask is used for exposure and development to form a pattern to be etched, and an ion etching technique is used to etch the epitaxial layer according to the photolithography pattern to remove unnecessary parts, and the second N-GaN layer 80 is etched to form a second step on the side of the second N-GaN layer 80. The etched thickness of the second N-GaN layer 80 is less than the thickness of the second N-GaN layer 80.

[0105] Step 14 , etching for the third time, etching a portion of each layer on the third N-GaN layer 120 and a portion of the third N-GaN layer 120 along the thickness direction of the first component, and forming a third step on the side of the third N-GaN layer 120 .

[0106] A photoresist is coated on the product obtained in step 13, and a mask is used for exposure and development to form a pattern to be etched, and an ion etching technique is used to etch the epitaxial layer according to the photolithography pattern to remove unnecessary parts, and the etching is performed to the third N-GaN layer 120, and a third step is formed on the side of the third N-GaN layer 120. The etched thickness of the third N-GaN layer 120 is less than the thickness of the third N-GaN layer 120.

[0107] After three etchings, Figure 2 The order of step 12 to step 14 can be changed.

[0108] After etching to form the sidewall, the N 2 P-type activation is carried out in the atmosphere. The formation of the sidewall is conducive to the diffusion of H atoms from the sidewall, thereby activating Mg doping, and the doping concentration is > 5E18cm -3 .

[0109] Step 15: forming a metal reflective layer 170 on the upper surface of the fourth N-GaN layer 160 .

[0110] A photoresist is coated on the resultant of step 14 , and exposure and development are performed using a mask to expose the fourth N—GaN layer 160 .

[0111] A 100 nm thick metal reflective layer 170 is formed on the surface of the fourth N-GaN layer 160 using a vacuum electron beam evaporation device. Figure 3 shown.

[0112] The metal reflective layer 170 may be made of silver (Ag), aluminum (Al), or gold (Au). These materials have high reflectivity and can form good adhesion with the fourth N-GaN layer 160 .

[0113] Step 16, forming a passivation layer 180, the passivation layer 180 covers the side walls of the first N-GaN layer 40, the blue LED light-emitting layer 50, the first P-GaN layer 60, the first heavily doped PN junction layer 70, the second N-GaN layer 80, the green LED light-emitting layer 90, the second P-GaN layer 100, the second heavily doped PN junction layer 110, the third N-GaN layer 120, the red LED light-emitting layer 130, the third P-GaN layer 140, the third heavily doped PN junction layer 150, the fourth N-GaN layer 160, and the metal reflective layer 170.

[0114] The passivation layer 180 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Taking the CVD method as an example, an aluminum source (TMAl), nitrogen (N 2 ) and ammonia (NH 3) as the reaction gas, the deposition temperature is 900-1000°C, the aluminum source gas flow rate is 100-150sccm, and the nitrogen (N 2 ) Gas flow rate 15000-25000sccm, ammonia (NH 3 ) Gas flow rate 250-350sccm, reaction time 4-6min, etc. to obtain a uniform and dense passivation layer 180 of 5-50nm.

[0115] After forming the AlN passivation layer 180, photolithography and etching processes are required to form the required patterns and windows, such as Figure 4 shown.

[0116] The main function of the passivation layer 180 is to protect the Micro LED device from damage from the external environment, such as oxidation, moisture, dust, etc., while improving the light extraction efficiency and performance of the Micro LED.

[0117] Step 17: Dispose a first sub-electrode 191 , a second sub-electrode 192 , a third sub-electrode 193 , and a fourth sub-electrode 194 on the first step, the second step, the metal reflective layer 170 , and the third step, respectively.

[0118] The first sub-electrode 191 is perpendicular to the first step and is the cathode of the blue LED. The second sub-electrode 192 is perpendicular to the second step and is the anode of the blue LED and the cathode of the green LED. The third sub-electrode 193 is perpendicular to the metal reflective layer 170 and is the anode of the red LED. The fourth sub-electrode 194 is perpendicular to the third step and is the cathode of the red LED and the anode of the green LED. Figure 5 The electrode material can be gold (Au), platinum (Pt), titanium (Ti) and other metals.

[0119] like Figure 6 As shown, in the top view of the product obtained in step 17, the first N-GaN layer 40 can be seen around the first sub-electrode 191, the second N-GaN layer 80 can be seen around the second sub-electrode 192, the third N-GaN layer 120 can be seen around the fourth sub-electrode 194, and the other areas are the upper surface of the reflective metal layer 170 as is the area around the third sub-electrode 193.

[0120] Step 18: forming a first bonding layer 201 , which fills the gaps between the first sub-electrode 191 , the second sub-electrode 192 , the third sub-electrode 193 , the fourth sub-electrode 194 , and the passivation layer 180 , and covers the metal reflective layer 170 .

[0121] The plasma enhanced chemical vapor deposition (PECVD) process deposits SiO 2The first bonding layer 201 is deposited at a deposition temperature of 300-500° C., and is deposited in the gaps between the first sub-electrode 191, the second sub-electrode 192, the third sub-electrode 193, the fourth sub-electrode 194, and the passivation layer 180, and covers the metal reflective layer 170, such as Figure 7 shown.

[0122] Step 19: planarize the first bonding layer 201 .

[0123] Chemical mechanical polishing (CMP) or other planarization techniques are used to improve the surface quality of the first bonding layer 201 .

[0124] Specifically, preparing the second component to form a CMOS driving circuit includes the following steps:

[0125] Step 21 , providing a CMOS driver 210 , and forming a second bonding layer 202 above the CMOS driver 210 .

[0126] The second bonding layer 202 is deposited by PECVD process at a deposition temperature of 300-500°C to form a 0.1-1 μm SiO 2 The second bonding layer 202, such as Figure 8-9 shown.

[0127] Step 22: etching the second bonding layer 202 along the thickness direction of the second bonding layer 202 to form four through holes 220 penetrating the second bonding layer.

[0128] A photoresist is coated on the upper surface of the second bonding layer 202, and a mask is used for exposure and development to form a pattern to be etched. The second bonding layer 202 is etched according to the photolithography pattern using ion etching technology to form four through holes 220 penetrating the second bonding layer 202, such as Fig.10 shown.

[0129] Step 23, placing a first contact electrode 231, a second contact electrode 232, a third contact electrode 233, and a fourth contact electrode 234 in the through hole 220, respectively. Fig.11 shown.

[0130] Specifically, bonding the first component and the second component comprises the following steps:

[0131] Step 31, horizontally transpose the second component, align and bond the first sub-electrode 191 with the first contact electrode 231, the second sub-electrode 192 with the second contact electrode 232, the third sub-electrode 193 with the third contact electrode 233, and the fourth sub-electrode 194 with the fourth contact electrode 234, and form a first electrode, a second electrode, a third electrode, and a fourth electrode, respectively.

[0132] Using an alignment device such as a microscope, a laser alignment system, etc., the first sub-electrode 191 on the first bonding layer 201 and the second bonding layer 202 is aligned with the first contact electrode 231, the second sub-electrode 192 is aligned with the second contact electrode 232, the third sub-electrode 193 is aligned with the third contact electrode 233, and the fourth sub-electrode 194 is aligned with the fourth contact electrode 234. The first component is bonded to the second component at a temperature below 350°C.

[0133] Step 32, removing the silicon substrate 10, the nucleation layer 20, and the buffer layer 30 to obtain the full-color Micro LED display device.

[0134] The silicon substrate 10 is removed by using chemical solution or physical method, such as laser stripping, mechanical stripping, etc. When the silicon substrate 10 is removed, the nucleation layer 20 and the buffer layer 30 are also removed together to obtain a full-color Micro LED display device, such as Fig.12 shown.

[0135] Devices with three light-emitting wavelengths, blue, green and red, can be controlled separately, which can achieve a display of a larger color gamut. The light of the three color wavelengths goes out from the first N-GaN layer 40, the red light is not absorbed by the green and blue light-emitting layers, and the green light is not absorbed by the blue light-emitting layer, so a higher light extraction efficiency can be achieved.

[0136] Example 1

[0137] A method for preparing a full-color Micro LED display device comprises the following steps:

[0138] Preparation of the first component, the preparation of the epitaxial structure, can be completed by using MOCVD epitaxial growth equipment, the steps are as follows:

[0139] Step 11, providing a silicon substrate 10, and epitaxially growing a nucleation layer 20, a buffer layer 30, a first N-GaN layer 40, a blue LED light-emitting layer 50, a first P-GaN layer 60, a first heavily doped PN junction layer 70, a second N-GaN layer 80, a green LED light-emitting layer 90, a second P-GaN layer 100, a second heavily doped PN junction layer 110, a third N-GaN layer 120, a red LED light-emitting layer 130, a third P-GaN layer 140, a third heavily doped PN junction layer 150, and a fourth N-GaN layer 160 in sequence on the surface of the silicon substrate 10, such as Figure 1 shown.

[0140] Specifically, under the conditions of a temperature of 1100° C. and a pressure of 50 torr, an AlN nucleation layer 20 with a thickness of 200 nm is grown on the substrate 10 .

[0141] Under the conditions of a temperature of 1180° C. and a pressure of 75 torr, an AlGaN buffer layer 30 with a thickness of 1 μm is grown on the nucleation layer 20 .

[0142] Under the conditions of a temperature of 1150° C. and a pressure of 200 torr, a first N—GaN layer 40 with a thickness of 0.5 μm is grown on the buffer layer 30 .

[0143] Under the conditions of 780° C. temperature and 400 torr pressure, a 90 nm blue LED multi-quantum well light emitting layer 50 is grown on the first N-GaN layer 40 .

[0144] Under the conditions of 950° C. and 200 torr, a first P-GaN layer 60 with a thickness of 50 nm is grown on the blue LED light emitting layer 50 .

[0145] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm first P+-InGaN layer 71 is grown on the first P-GaN layer 60, with an In content of 4%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0146] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm first N+-InGaN layer 72 is grown on the first P+-InGaN layer 71, with an In content of 4%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0147] Under the conditions of a temperature of 1150° C. and a pressure of 200 torr, a second N—GaN layer 80 with a thickness of 0.5 μm is grown on the first N + -InGaN layer 72 .

[0148] Under the conditions of 762° C. temperature and 400 torr pressure, a 90 nm green LED light emitting layer 90 is grown on the second N-GaN layer 80 .

[0149] Under the conditions of temperature of 950° C. and pressure of 200 torr, a second P-GaN layer 100 with a thickness of 50 nm is grown on the green LED light emitting layer 90 .

[0150] Under the conditions of 900°C temperature and 400 torr pressure, a 10nm second P+-InGaN layer 111 is grown on the second P-GaN layer 100, the In content is 4%, the dopant is Mg, and the doping concentration is 1E20cm -3 .

[0151] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm second N+-InGaN layer 112 is grown on the second P+-InGaN layer 111, with an In content of 4%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0152] Under the conditions of a temperature of 1150° C. and a pressure of 200 torr, a third N—GaN layer 120 with a thickness of 0.5 μm is grown on the second N + -InGaN layer 112 .

[0153] Under the conditions of a temperature of 722° C. and a pressure of 400 torr, a 90 nm thick red LED light emitting layer 130 is grown on the third N-GaN layer 120 .

[0154] Under the conditions of temperature of 950°C and pressure of 200 torr, a third P-GaN layer 140 with a thickness of 50 nm is grown on the red LED light emitting layer 130 .

[0155] Under the conditions of 900°C temperature and 400 torr pressure, a 10nm third P+-InGaN layer 151 is grown on the third P-GaN layer 140, with an In content of 4%, a dopant of Mg, and a doping concentration of 1E20cm -3 .

[0156] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm third N+-InGaN layer 152 is grown on the third P+-InGaN layer 151, the In content is 4%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0157] The first heavily doped PN junction layer 70 , the second heavily doped PN junction layer 110 , and the third heavily doped PN junction layer 150 are made of InGaN material to reduce the forward voltage.

[0158] Under the conditions of a temperature of 1150° C. and a pressure of 200 torr, a fourth N—GaN layer 160 with a thickness of 0.5 μm is grown on the third N + -InGaN layer 152 .

[0159] Step 12 , etching for the first time, etching a portion of each layer on the first N-GaN layer 40 and a portion of the first N-GaN layer 40 along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer 40 .

[0160] A photoresist is coated on the product obtained in step 11, and a mask is used for exposure and development to form a pattern to be etched, and an ion etching technique is used to etch the epitaxial layer according to the photolithography pattern to remove unnecessary parts, and the first N-GaN layer 40 is etched to form a first step on the side of the first N-GaN layer 40. The thickness of the etched first N-GaN layer 40 is less than the thickness of the first N-GaN layer 40.

[0161] Step 13, etching for the second time, etching a portion of each layer on the second N-GaN layer 80 and a portion of the second N-GaN layer 80 along the thickness direction of the first component, and forming a second step on the side of the second N-GaN layer 80.

[0162] A photoresist is coated on the product obtained in step 12, and a mask is used for exposure and development to form a pattern to be etched, and an ion etching technique is used to etch the epitaxial layer according to the photolithography pattern to remove unnecessary parts, and the second N-GaN layer 80 is etched to form a second step on the side of the second N-GaN layer 80. The etched thickness of the second N-GaN layer 80 is less than the thickness of the second N-GaN layer 80.

[0163] Step 14 , etching for the third time, etching a portion of each layer on the third N-GaN layer 120 and a portion of the third N-GaN layer 120 along the thickness direction of the first component, and forming a third step on the side of the third N-GaN layer 120 .

[0164] A photoresist is coated on the product obtained in step 13, and a mask is used for exposure and development to form a pattern to be etched, and an ion etching technique is used to etch the epitaxial layer according to the photolithography pattern to remove unnecessary parts, and the etching is performed to the third N-GaN layer 120, and a third step is formed on the side of the third N-GaN layer 120. The etched thickness of the third N-GaN layer 120 is less than the thickness of the third N-GaN layer 120.

[0165] After three etchings, Figure 2 shown.

[0166] After etching to form the sidewall, the 2 P-type activation is carried out in the atmosphere. The formation of the sidewall is conducive to the diffusion of H atoms from the sidewall, thereby activating Mg doping, and the doping concentration is > 5E18cm -3 .

[0167] Step 15: forming a metal reflective layer 170 on the upper surface of the fourth N-GaN layer 160 .

[0168] A photoresist is coated on the resultant of step 14 , and exposure and development are performed using a mask to expose the fourth N—GaN layer 160 .

[0169] A 100 nm thick metal reflective layer 170 is formed on the surface of the fourth N-GaN layer 160 using a vacuum electron beam evaporation device. Figure 3 shown.

[0170] The metal reflective layer 170 is made of aluminum (Al), which has high reflectivity and can form good adhesion with the fourth N-GaN layer 160 .

[0171] Step 16, forming a passivation layer 180, the passivation layer 180 covers the side walls of the first N-GaN layer 40, the blue LED light-emitting layer 50, the first P-GaN layer 60, the first heavily doped PN junction layer 70, the second N-GaN layer 80, the green LED light-emitting layer 90, the second P-GaN layer 100, the second heavily doped PN junction layer 110, the third N-GaN layer 120, the red LED light-emitting layer 130, the third P-GaN layer 140, the third heavily doped PN junction layer 150, the fourth N-GaN layer 160, and the metal reflective layer 170.

[0172] The CVD method uses an aluminum source (TMAl), nitrogen (N 2 ) and ammonia (NH 3 ) as the reaction gas, the deposition temperature is 950°C, the aluminum source gas flow rate is 120 sccm, and the nitrogen (N 2 ) gas flow rate 20000sccm, ammonia (NH 3 ) gas flow rate of 300 sccm, reaction time of 5 min, etc. to obtain a uniform and dense passivation layer 180 of 50 nm.

[0173] After forming the AlN passivation layer 180, photolithography and etching processes are required to form the required patterns and windows, such as Figure 4 shown.

[0174] Step 17: Dispose a first sub-electrode 191 , a second sub-electrode 192 , a third sub-electrode 193 , and a fourth sub-electrode 194 on the first step, the second step, the metal reflective layer 170 , and the third step, respectively.

[0175] The first sub-electrode 191 is perpendicular to the first step and is the cathode of the blue LED. The second sub-electrode 192 is perpendicular to the second step and is the anode of the blue LED and the cathode of the green LED. The third sub-electrode 193 is perpendicular to the metal reflective layer 170 and is the anode of the red LED. The fourth sub-electrode 194 is perpendicular to the third step and is the cathode of the red LED and the anode of the green LED. Figure 5 As shown, the electrode material is titanium (Ti).

[0176] like Figure 6As shown, in the top view of the product obtained in step 17, the first N-GaN layer 40 can be seen around the first sub-electrode 191, the second N-GaN layer 80 can be seen around the second sub-electrode 192, the third N-GaN layer 120 can be seen around the fourth sub-electrode 194, and the other areas are the upper surface of the reflective metal layer 170 as is the area around the third sub-electrode 193.

[0177] Step 18: forming a first bonding layer 201 , which fills the gaps between the first sub-electrode 191 , the second sub-electrode 192 , the third sub-electrode 193 , the fourth sub-electrode 194 , and the passivation layer 180 , and covers the metal reflective layer 170 .

[0178] The plasma enhanced chemical vapor deposition (PECVD) process deposits SiO 2 The first bonding layer 201 is deposited at a deposition temperature of 350° C. and is deposited in the gaps between the first sub-electrode 191 , the second sub-electrode 192 , the third sub-electrode 193 , the fourth sub-electrode 194 , and the passivation layer 180 , and covers the metal reflective layer 170 . Figure 7 shown.

[0179] Step 19: planarize the first bonding layer.

[0180] The surface quality of the first bonding layer 201 is improved by using a chemical mechanical polishing (CMP) planarization technique.

[0181] The second component is prepared to form a CMOS driving circuit, comprising the following steps:

[0182] Step 21 , providing a CMOS driver 210 , and forming a second bonding layer 202 above the CMOS driver 210 .

[0183] like Figure 8-9 As shown, the second bonding layer 202 is deposited by PECVD process at a deposition temperature of 350° C. to form a second bonding layer 202 of 0.5 μm.

[0184] Step 22: etching the second bonding layer 202 along the thickness direction of the second bonding layer 202 to form four through holes 220 penetrating the second bonding layer.

[0185] A photoresist is coated on the upper surface of the second bonding layer 202, and a mask is used for exposure and development to form a pattern to be etched. The second bonding layer 202 is etched according to the photolithography pattern using ion etching technology to form four through holes 220 penetrating the second bonding layer 202, such as Fig.10 shown.

[0186] Step 23, placing a first contact electrode 231, a second contact electrode 232, a third contact electrode 233, and a fourth contact electrode 234 in the through hole 220, respectively. Fig.11 shown.

[0187] Bonding the first component and the second component comprises the following steps:

[0188] Step 31, horizontally transpose the second component, align and bond the first sub-electrode 191 with the first contact electrode 231, the second sub-electrode 192 with the second contact electrode 232, the third sub-electrode 193 with the third contact electrode 233, and the fourth sub-electrode 194 with the fourth contact electrode 234, and form a first electrode, a second electrode, a third electrode, and a fourth electrode, respectively.

[0189] Using a microscope, align the first sub-electrode 191 on the first bonding layer 201 and the second bonding layer 202 with the first contact electrode 231, the second sub-electrode 192 with the second contact electrode 232, the third sub-electrode 193 with the third contact electrode 233, and the fourth sub-electrode 194 with the fourth contact electrode 234. Low-temperature bonding is performed on the first component and the second component at a temperature below 350°C.

[0190] Step 32, removing the silicon substrate 10, the nucleation layer 20, and the buffer layer 30 to obtain the full-color Micro LED display device.

[0191] The silicon substrate 10 is removed by using a chemical solution. When the silicon substrate 10 is removed, the nucleation layer 20 and the buffer layer 30 are also removed to obtain a full-color Micro LED display device, such as Fig.12 shown.

[0192] Example 2

[0193] The other steps of this embodiment are the same as those of the embodiment 1, except that the first heavily doped PN junction layer 70 is grown at a temperature of 900°C and a pressure of 400 torr, a 10 nm first P+-GaN layer 71 is grown on the first P-GaN layer 60, the In content is 0%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0194] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm first N+-GaN layer 72 is grown on the first P+-GaN layer 71, the In content is 0%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0195] The second heavily doped PN junction layer 110 is grown at 900°C and 400 torr. A 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100. The In content is 0%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0196] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm second N+-GaN layer 112 is grown on the second P+-GaN layer 111, the In content is 0%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0197] The third heavily doped PN junction layer 150 is grown at 900°C and 400 torr. A 10 nm third P+-GaN layer 151 is grown on the third P-GaN layer 140. The In content is 0%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0198] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm third N+-GaN layer 152 is grown on the third P+-GaN layer 151, the In content is 0%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0199] Example 3

[0200] The other steps of this embodiment are the same as those of the embodiment 1, except that the first heavily doped PN junction layer 70 is grown at a temperature of 900°C and a pressure of 400 torr, and a 10 nm first P+-InGaN layer 71 is grown on the first P-GaN layer 60, the In content is 10%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0201] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm first N+-InGaN layer 72 is grown on the first P+-InGaN layer 71, with an In content of 10%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0202] The second heavily doped PN junction layer 110 is grown at 900°C and 400 torr. A 10 nm thick second P+-InGaN layer 111 is grown on the second P-GaN layer 100. The In content is 10%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0203] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm second N+-InGaN layer 112 is grown on the second P+-InGaN layer 111, the In content is 10%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0204] The third heavily doped PN junction layer 150 is grown at 900°C and 400 torr. A 10 nm third P+-InGaN layer 151 is grown on the third P-GaN layer 140. The In content is 10%, the P dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0205] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm third N+-InGaN layer 152 is grown on the third P+-InGaN layer 151, the In content is 10%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0206] Comparative Example 1

[0207] The other steps of this comparative example are the same as those of Example 1, except that the first heavily doped PN junction layer 70 is grown at a temperature of 900°C and a pressure of 400 torr, and a 10 nm first P+-InGaN layer 71 is grown on the first P-GaN layer 60, the In content is 15%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0208] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm first N+-InGaN layer 72 is grown on the first P+-InGaN layer 71, with an In content of 15%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0209] The second heavily doped PN junction layer 110 is grown at 900°C and 400 torr. A 10 nm thick second P+-InGaN layer 111 is grown on the second P-GaN layer 100. The In content is 15%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0210] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm second N+-InGaN layer 112 is grown on the second P+-InGaN layer 111, with an In content of 15%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0211] The third heavily doped PN junction layer 150 is grown at 900°C and 400 torr. A 10 nm thick third P+-InGaN layer 151 is grown on the third P-GaN layer 140. The In content is 15%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0212] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm third N+-InGaN layer 152 is grown on the third P+-InGaN layer 151, the In content is 15%, the dopant is Si, and the doping concentration is 3E19 cm -3 .

[0213] Comparative Example 2

[0214] The other steps of this comparative example are the same as those of Example 1, except that the first heavily doped PN junction layer 70 is grown at a temperature of 900°C and a pressure of 400 torr, and a 10 nm first P+-InGaN layer 71 is grown on the first P-GaN layer 60, the In content is 20%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0215] Under the conditions of 900°C temperature and 400 torr pressure, a 10 nm first N+-InGaN layer 72 is grown on the first P+-InGaN layer 71, with an In content of 20%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0216] The second heavily doped PN junction layer 110 is grown at 900°C and 400 torr. A 10 nm thick second P+-InGaN layer 111 is grown on the second P-GaN layer 100. The In content is 20%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0217] Under the conditions of 900°C and 400 torr, a 10 nm second N+-InGaN layer 112 is grown on the second P+-InGaN layer 111, with an In content of 20%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0218] The third heavily doped PN junction layer 150 is grown at 900°C and 400 torr. A 10 nm third P+-InGaN layer 151 is grown on the third P-GaN layer 140. The In content is 20%, the dopant is Mg, and the doping concentration is 1E20 cm -3 .

[0219] Under the conditions of 900°C and 400 torr, a 10 nm third N+-InGaN layer 152 is grown on the third P+-InGaN layer 151, with an In content of 20%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0220] The display unit operating voltage test and luminous efficiency test of the full-color Micro LED display devices of Examples 1-3 and Comparative Examples 1-2 are respectively carried out, and the results are shown in Table 1:

[0221] Table 1

[0222]

[0223] It can be seen from the data in Table 1 that: 1. When the In element content of the P+-InGaN layer is 0-4% and the In element content of the N+-InGaN layer is 0-4%, when the In element content is low, the band structure of the P+-InGaN layer and the N+-InGaN layer is relatively stable, and the voltage of the full-color Micro LED display unit is slightly reduced. The increase in the In element content will improve the luminous efficiency of the display unit to a certain extent. The luminous efficiency of the display unit is highest when the In content in the heavily doped PN junction is around 4%. 2. With the increase of the In element content (4-10%), the band structure of the P+-InGaN layer and the N+-InGaN layer begins to change significantly. The introduction of In reduces the bandgap width of the display unit, and the increase in the ionization ratio of the Mg dopant and the Si dopant reduces the voltage of the display unit, and the luminous efficiency is slightly lower than that of Example 1. 3. When the In element content is too high (above 15%), the P+-InGaN layer and the N+-InGaN layer will absorb the light emitted by the display unit, reducing the luminous efficiency, with the blue and green light decreasing more significantly.

[0224] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, substitute and modify the above embodiments within the scope of the invention without departing from the principles and purpose of the present invention. All such changes should fall within the scope of protection of the claims of the present invention.

Claims

1. A full-color Micro LED display device, characterized in that: It comprises several groups of display units, wherein the display units include: A first N-GaN layer, wherein a side edge of the first N-GaN layer has a first step; A blue LED light-emitting layer covering the upper surface of the non-step region of the first N-GaN layer; A first P-GaN layer covering the upper surface of the blue LED light emitting layer; a first heavily doped PN junction layer, covering an upper surface of the first P-GaN layer; a second N-GaN layer, covering an upper surface of the first heavily doped PN junction layer, wherein a side edge of the second N-GaN layer has a second step; A green LED light-emitting layer covering the upper surface of the second N-GaN layer in the non-step region; A second P-GaN layer covering the upper surface of the green LED light-emitting layer; a second heavily doped PN junction layer, covering an upper surface of the second P-GaN layer; a third N-GaN layer, covering an upper surface of the second heavily doped PN junction layer, wherein a side edge of the third N-GaN layer has a third step; A red LED light-emitting layer covering the upper surface of the non-step region of the third N-GaN layer; A third P-GaN layer, covering the upper surface of the red LED light-emitting layer; a third heavily doped PN junction layer, covering an upper surface of the third P-GaN layer; a fourth N-GaN layer, covering an upper surface of the third heavily doped PN junction layer; a metal reflective layer, covering an upper surface of the fourth N-GaN layer; A passivation layer covering the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red LED light-emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer, and the sidewalls of the metal reflective layer; A first electrode, located on the first step and extending back toward the first N-GaN layer; a second electrode, located on the second step and extending back toward the first N-GaN layer; a third electrode, located on the metal reflective layer and extending back toward the first N-GaN layer; a fourth electrode, located on the third step and extending back toward the first N-GaN layer; The upper surfaces of the first electrode, the second electrode, the third electrode and the fourth electrode are flush with each other; A bonding layer, filling the gaps between the first electrode, the second electrode, the third electrode, the fourth electrode, and the passivation layer and covering the first electrode, the second electrode, the third electrode, the fourth electrode, and the passivation layer; A CMOS driver covers the upper surface of the bonding layer and is electrically connected to the first electrode, the second electrode, the third electrode, and the fourth electrode.

2. The full-color Micro LED display device according to claim 1, characterized in that: The bonding layer includes a first bonding layer and a second bonding layer stacked from bottom to top; The parts of the first electrode, the second electrode, the third electrode and the fourth electrode located in the second bonding layer are respectively the first contact electrode, the second contact electrode, the third contact electrode and the fourth contact electrode.

3. The full-color Micro LED display device according to claim 1, characterized in that: The first heavily doped PN junction layer includes a first P+-InGaN layer and a first N+-InGaN layer stacked from bottom to top, the first P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration of >5E19cm -3 The first N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration of >2E19cm -3 .

4. The full-color Micro LED display device according to claim 1, characterized in that: The second heavily doped PN junction layer comprises a second P+-InGaN layer and a second N+-InGaN layer stacked from bottom to top, the second P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration of >5E19cm -3 The second N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration of >2E19cm -3 .

5. The full-color Micro LED display device according to claim 1, characterized in that: The third heavily doped PN junction layer includes a third P+-InGaN layer and a third N+-InGaN layer stacked from bottom to top, the third P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration of >5E19cm -3 The third N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration of >2E19cm -3 .

6. The full-color Micro LED display device according to claim 3, characterized in that: The thickness of the first P+-InGaN layer is 5-20 nm, the thickness of the first N+-InGaN layer is 5-20 nm, and the thickness ratio of the first P+-InGaN layer to the first N+-InGaN layer is 1:

1.

7. The full-color Micro LED display device according to claim 4, characterized in that: The thickness of the second P+-InGaN layer is 5-20 nm, the thickness of the second N+-InGaN layer is 5-20 nm, and the thickness ratio of the second P+-InGaN layer to the second N+-InGaN layer is 1:

1.

8. The full-color Micro LED display device according to claim 5, characterized in that: The thickness of the third P+-InGaN layer is 5-20 nm, the thickness of the third N+-InGaN layer is 5-20 nm, and the thickness ratio of the third P+-InGaN layer to the third N+-InGaN layer is 1:

1.

9. The method for preparing a full-color Micro LED display device according to claim 1, characterized in that: The following steps are involved: Forming a first component comprises the following steps: Step 11, providing a silicon substrate, and epitaxially growing a nucleation layer, a buffer layer, a first N-GaN layer, a blue LED light-emitting layer, a first P-GaN layer, a first heavily doped PN junction layer, a second N-GaN layer, a green LED light-emitting layer, a second P-GaN layer, a second heavily doped PN junction layer, a third N-GaN layer, a red LED light-emitting layer, a third P-GaN layer, a third heavily doped PN junction layer, and a fourth N-GaN layer in sequence on the surface of the silicon substrate; Step 12, etching for the first time, etching a portion of each layer on the first N-GaN layer and a portion of the first N-GaN layer along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer; Step 13, etching for the second time, etching a portion of each layer on the second N-GaN layer and a portion of the second N-GaN layer along the thickness direction of the first component, and forming a second step on the side of the second N-GaN layer; Step 14, etching for the third time, etching a portion of each layer on the third N-GaN layer and a portion of the third N-GaN layer along the thickness direction of the first component, and forming a third step on the side of the third N-GaN layer; Step 15, forming a metal reflective layer on the upper surface of the fourth N-GaN layer; Step 16, forming a passivation layer, the passivation layer covers the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red LED light-emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer, and the sidewalls of the metal reflective layer; Step 17, respectively disposing a first sub-electrode, a second sub-electrode, a third sub-electrode, and a fourth sub-electrode on the first step, the second step, the metal reflective layer, and the third step; Step 18, forming a first bonding layer, wherein the first bonding layer fills the gaps between the first sub-electrode, the second sub-electrode, the third sub-electrode, the fourth sub-electrode, and the passivation layer, and covers the metal reflective layer; Step 19, planarizing the first bonding layer; Forming the second component comprises the following steps: Step 21, providing a CMOS driver, and forming a second bonding layer above the CMOS driver; Step 22, etching the second bonding layer along the thickness direction of the second bonding layer to form four through holes penetrating the second bonding layer; Step 23, placing a first contact electrode, a second contact electrode, a third contact electrode, and a fourth contact electrode in the through hole respectively; Bonding the first component and the second component comprises the following steps: Step 31, horizontally transposing the second component, aligning and bonding the first sub-electrode with the first contact electrode, the second sub-electrode with the second contact electrode, the third sub-electrode with the third contact electrode, and the fourth sub-electrode with the fourth contact electrode, and forming a first electrode, a second electrode, a third electrode, and a fourth electrode respectively; Step 32, removing the silicon substrate, the nucleation layer, and the buffer layer to obtain the full-color Micro LED display device.

10. The method for preparing a full-color Micro LED display device according to claim 9, characterized in that: After step 14, the first component is further activated by P-type Mg doping, with a doping concentration of >5E18cm -3 .

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