Light-emitting substrate and display device

Abstract

The embodiment of the invention discloses a light-emitting substrate and a display device. In one specific implementation mode, the light-emitting substrate comprises a light-emitting area and a frame area surrounding the light-emitting area; wherein the frame area comprises a first substrate; the first passivation layer is arranged on the first substrate; the ground wire layer is arranged on the first passivation layer and surrounds the light emitting area; the second passivation layer covers the ground wire layer, at least one first via hole exposing the ground wire layer is formed in the second passivation layer, and the ground wire layer is electrically connected with an external grounding end through a lead wire arranged at the first via hole. According to the embodiment, when the static electricity is generated, the static electricity can be released to the external grounding end outside the light-emitting substrate through the ground wire layer, the first via hole and the lead, then the capacity of the light-emitting substrate for preventing the static electricity from being released is improved, a driving chip and a light-emitting diode in the light-emitting substrate can be effectively prevented from being broken down by the static electricity, and ESD protection of the light-emitting substrate is enhanced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and more specifically, to a light-emitting substrate and a display device. Background Art

[0002] The inventors have discovered that the light-emitting substrate of the backlight source of a liquid crystal display module, such as a sub-millimeter light emitting diode (MiniLight Emitting Diode, Mini LED) light-emitting substrate, has the problem that the driver chip (IC) array and the sub-millimeter light emitting diode are easily broken down by electrostatic discharge (Electro-Static Discharge, ESD). Summary of the invention

[0003] The purpose of the present disclosure is to provide a light-emitting substrate and a display device to solve at least one of the problems existing in the prior art.

[0004] In order to achieve the above objectives, the present invention adopts the following technical solutions:

[0005] A first aspect of the present disclosure provides a light-emitting substrate, comprising a light-emitting area and a frame area surrounding the light-emitting area; wherein the frame area comprises a first substrate; a first passivation layer arranged on the first substrate; a ground layer arranged on the first passivation layer, the ground layer surrounding the light-emitting area; a second passivation layer covering the ground layer, the second passivation layer having at least one first via hole exposing the ground layer, the ground layer being electrically connected to an external ground terminal through a lead wire arranged at the first via hole.

[0006] Optionally, an anti-breakdown diode is provided on the lead, the ground layer is electrically connected to the positive electrode of the anti-breakdown diode, and the negative electrode of the anti-breakdown diode is electrically connected to the external ground terminal.

[0007] Optionally, the second passivation layer is provided with a plurality of first via holes exposing the ground layer.

[0008] Optionally, the plurality of first via holes are evenly distributed in the border area.

[0009] Optionally, the ground layer includes a first ground layer and a second ground layer, the first ground layer is arranged on the first passivation layer, the border area also includes a third passivation layer covering the first ground layer, the third passivation layer has a first opening exposing the first ground layer, the first opening surrounds the light-emitting area, the second ground layer is electrically connected to the first ground layer through the first opening, and the second ground layer is electrically connected to the external ground terminal through a lead arranged at the first via hole.

[0010] Optionally, the light-emitting area includes a fourth passivation layer arranged on the first substrate and a light-emitting signal wiring layer arranged on the fourth passivation layer, the first passivation layer and the fourth passivation layer are arranged on the same layer, and the ground layer and the light-emitting signal wiring layer are arranged on the same layer.

[0011] Optionally, the light-emitting area further includes a fifth passivation layer covering the light-emitting signal wiring layer, and the second passivation layer is arranged on the same layer as the fifth passivation layer.

[0012] Optionally, the light-emitting signal routing layer includes a first light-emitting signal routing layer and a second light-emitting signal routing layer, the first light-emitting signal routing layer is arranged on the fourth passivation layer, the light-emitting area also includes a sixth passivation layer covering the first light-emitting signal routing layer, the sixth passivation layer is provided with a second via hole exposing the first light-emitting signal routing layer, the second light-emitting signal routing layer is electrically connected to the first light-emitting signal routing layer through the second via hole, the first ground layer is arranged on the same layer as the first light-emitting signal routing layer, the second ground layer is arranged on the same layer as the second light-emitting signal routing layer, and the third passivation layer is arranged on the same layer as the sixth passivation layer.

[0013] Optionally, the border area further includes a bonding area, and the ground layer is located on a side of the bonding area away from the light-emitting area.

[0014] A second aspect of the present disclosure provides a display device, including a backlight source and a liquid crystal display panel, wherein the backlight source includes the light-emitting substrate described in the first aspect of the present disclosure.

[0015] The beneficial effects of the present disclosure are as follows:

[0016] The technical solution disclosed in the present invention, by setting a ground layer surrounding the light-emitting area in the frame area of ​​the light-emitting substrate and exposing the ground layer through at least one first via in the second passivation layer, so that the ground layer is electrically connected to the external ground terminal through the lead set at the first via hole, can release the static electricity through the ground layer, the first via hole and the lead to the external ground terminal outside the light-emitting substrate when static electricity is generated, thereby improving the ability of the light-emitting substrate to prevent static electricity release, effectively preventing the driving chip and the light-emitting diode in the light-emitting substrate from being broken down by static electricity, and enhancing the ESD protection of the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specific implementation methods of the present disclosure are further described in detail below with reference to the accompanying drawings.

[0018] Figure 1 A schematic structural diagram of a light-emitting substrate provided in one embodiment of the present disclosure is shown.

[0019] Figure 2 A schematic structural diagram of a light-emitting substrate provided in another embodiment of the present disclosure is shown.

[0020] Figure 3 A schematic structural diagram of a light-emitting substrate provided in yet another embodiment of the present disclosure is shown.

[0021] Figure 4 A schematic structural diagram of a light-emitting substrate provided in yet another embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic structural diagram of a light-emitting area of ​​a light-emitting substrate provided in one embodiment of the present disclosure is shown.

[0023] Figure 6 A schematic top view of a light-emitting substrate provided in one embodiment of the present disclosure is shown.

[0024] Figure 7 A schematic top view of a light-emitting substrate provided in another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] The terms “on”, “formed on” and “disposed on” in the present disclosure may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0026] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another. Thus, for example, the first part, first member, first element, first region, first layer and / or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and / or second part without departing from the teachings of the present disclosure.

[0027] In the present disclosure, unless otherwise specified, the term "same-layer arrangement" used refers to two layers, parts, components, elements or parts that can be formed by the same preparation process (such as a patterning process, etc.), and the two layers, parts, components, elements or parts are generally formed of the same material. For example, two or more functional layers are arranged in the same layer, which means that these functional layers arranged in the same layer can be formed using the same material layer and the same preparation process, thereby simplifying the preparation process of the display substrate.

[0028] In the present disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0029] In the backlight design of the LCD display module, a large number of driver chips are connected to the glass substrate through thin film diffusion technology. In the light board part of the LCD display module, the driver chip array is often damaged by static electricity or high current, causing the light-emitting diodes to fail to work, so electrostatic protection is particularly important.

[0030] At present, Mini LED has been put into use in the market. The display principle of Mini LED is that the backlight source uses Mini LED design, which is matched with a conventional LCD display module to produce better optical effects. The backlight source is controlled by partitioning to improve the color gamut and significantly improve the contrast.

[0031] The inventors have discovered that the light-emitting substrate of the backlight source of the liquid crystal display module, such as the sub-millimeter light-emitting diode light-emitting substrate, has the problem that the driving chip array and the sub-millimeter light-emitting diodes are easily broken down by static electricity.

[0032] In view of this, an embodiment of the present disclosure provides a light-emitting substrate, comprising a light-emitting area and a border area surrounding the light-emitting area; wherein the border area comprises a first substrate; a first passivation layer arranged on the first substrate; a ground layer arranged on the first passivation layer, the ground layer surrounding the light-emitting area; a second passivation layer covering the ground layer, the second passivation layer having at least one first via hole exposing the ground layer, the ground layer being electrically connected to an external ground terminal through a lead arranged at the first via hole.

[0033] In a specific example, Figure 1 As shown, the light-emitting substrate includes a light-emitting area 20 and a frame area 10 surrounding the light-emitting area 20; wherein the frame area 10 includes a first substrate 101; a first passivation layer 102 arranged on the first substrate 101; a ground layer 103 arranged on the first passivation layer 102, and the ground layer 103 surrounds the light-emitting area 20; a second passivation layer 104 covering the ground layer 103, and the second passivation layer 104 is provided with at least one first via hole 105 exposing the ground layer 103, and the ground layer 103 is electrically connected to an external ground terminal through a lead 106 arranged at the first via hole 105.

[0034] Further, such as Figure 1As shown, the border region 10 further includes a first buffer layer 1010 disposed on a side of the first passivation layer 102 and a portion of the ground layer 103 away from the first substrate 101, the first buffer layer 1010 having an opening exposing a portion of the ground layer 103; a first flat layer 1011 disposed on a side of the first buffer layer 1010 away from the first substrate 101, the first flat layer 1011 having an opening exposing a portion of the ground layer 103; and a second buffer layer 1012 disposed on a side of the first flat layer 1011 away from the first substrate 101. The second buffer layer 1012 has an opening exposing a portion of the ground layer 103; a second flat layer 1013 is arranged on the side of the second buffer layer 1012 away from the first substrate 101, and the second flat layer 1013 has an opening exposing a portion of the ground layer 103; a third passivation layer 1014 is arranged on the side of the second flat layer 1013 away from the first substrate 101, and the third passivation layer 1014 has an opening exposing a portion of the ground layer 103; the first substrate 101 is a glass substrate; the material of the ground layer 103 includes copper.

[0035] The buffer layer of this embodiment is used to protect the glass substrate. As a stress-bearing layer, the buffer layer is beneficial to reducing the stress of the copper layer above on the glass substrate and increasing the adhesion of the flat layer. The flat layer and the passivation layer are used to protect the copper layer and increase the insulation rating.

[0036] Further, such as Figure 1 As shown, the side of the second passivation layer 104 away from the first substrate 101 also needs to avoid the first via 105 when spraying reflective white oil, thereby facilitating electrical connection between the ground layer 103 and the external ground terminal outside the light-emitting substrate.

[0037] Further, such as Figure 1 As shown, when a light-emitting substrate is prepared on a first substrate 101 by a graphic process, a ground layer 103, i.e., a metal ring trace (GND-R), is made above the first passivation layer 102, and is covered with a first buffer layer 1010, etc., leaving a first via 105 connected to the external ground terminal of the light-emitting substrate, for example, electrically connected to the backplane outside the light-emitting substrate through a lead, conductive glue or conductive tape, so that static electricity can be discharged to the backplane through the ground layer to protect the light-emitting diode and driver chip inside the light-emitting substrate.

[0038] In another specific example, Figure 2As shown, the light-emitting substrate includes a light-emitting area 40 and a frame area 30 surrounding the light-emitting area 40; wherein the frame area 30 includes a first substrate 301; a first passivation layer 302 arranged on the first substrate 301; a ground layer 303 arranged on the first passivation layer 302, and the ground layer 303 surrounds the light-emitting area 40; a second passivation layer 304 covering the ground layer 303, and the second passivation layer 304 is provided with at least one first via hole 305 exposing the ground layer 303, and the ground layer 303 is electrically connected to the external ground terminal through a lead 306 arranged at the first via hole 305.

[0039] Further, such as Figure 2 As shown, the border region 30 further includes a first buffer layer 3010 disposed on a side of the first passivation layer 302 and a portion of the ground layer 303 away from the first substrate 301, and the first buffer layer 3010 covers a side of the ground layer 303 close to the light-emitting region 40; a first flat layer 3011 disposed on a side of the first buffer layer 3010 away from the first substrate 301, and the first flat layer 3011 covers a side of the ground layer 303 close to the light-emitting region 40; and a second buffer layer 3012 disposed on a side of the first flat layer 3011 away from the first substrate 301. A second buffer layer 3012 covers a side of the ground layer 303 close to the light-emitting area 40; a second flat layer 3013 is arranged on a side of the second buffer layer 3012 away from the first substrate 301, and the second flat layer 3013 covers a side of the ground layer 303 close to the light-emitting area 40; a third passivation layer 3014 is arranged on a side of the second flat layer 3013 away from the first substrate 301, and the third passivation layer 3014 covers a side of the ground layer 303 close to the light-emitting area 40; the first substrate 301 is a glass substrate; the material of the ground layer 303 includes copper.

[0040] The buffer layer of this embodiment is used to protect the glass substrate. As a stress-bearing layer, the buffer layer is beneficial to reducing the stress of the copper layer above on the glass substrate and increasing the adhesion of the flat layer. The flat layer and the passivation layer are used to protect the copper layer and increase the insulation rating.

[0041] Further, such as Figure 2 As shown, the side of the second passivation layer 304 away from the first substrate 301 also needs to avoid the first via 305 when spraying reflective white oil, which is conducive to the electrical connection between the ground layer 303 and the external ground terminal outside the light-emitting substrate.

[0042] Further, such as Figure 2 As shown, in this embodiment, the side wall of the ground layer 303 away from the light-emitting area 40 is made into a metal layer step to expose the metal layer. Figure 2 In the specific example shown, the outer frame of the light-emitting substrate is relative to Figure 1In the specific example shown, the outer frame of the light-emitting substrate is retracted, which is beneficial to reducing the frame size of the light-emitting substrate and realizing a narrow frame design; a part of the second passivation layer 304 is arranged on the side of the metal layer step away from the first substrate 301, thereby Figure 2 In the specific example shown, the light emitting substrate is relative to Figure 1 In the specific example shown, the first buffer layer 3010 , the first planar layer 3011 , the second buffer layer 3012 and the second planar layer 3013 are omitted on the side of the ground layer 303 away from the light emitting area 40 of the light emitting substrate, which can simplify the process flow.

[0043] Further, such as Figure 2 As shown, when a light-emitting substrate is prepared on a first substrate 301 by a graphic process, a ground layer 303, i.e., a metal ring routing (GND-R), is made on top of the first passivation layer 302, and a first buffer layer 3010 layer is used to cover the side of the ground layer 303 close to the light-emitting area 40, so that a metal layer step is made on the side wall of the ground layer 303 away from the light-emitting area 40 to be exposed, and a first via 305 is left to connect the ground layer 303 to the outside of the light-emitting substrate, for example, by electrically connecting the backplane outside the light-emitting substrate through a lead, conductive glue or conductive tape, so that static electricity can be discharged to the backplane through the ground layer 303 to be released, thereby protecting the light-emitting diode and driving chip inside the light-emitting substrate.

[0044] In this embodiment, a ground layer surrounding the light-emitting area is arranged in the frame area of ​​the light-emitting substrate, and at least one first via hole in the second passivation layer is exposed to the ground layer, so that the ground layer is electrically connected to the external ground terminal through the lead wire arranged at the first via hole. When static electricity is generated, the static electricity can be released to the external ground terminal outside the light-emitting substrate through the ground layer, the first via hole and the lead wire, thereby improving the ability of the light-emitting substrate to prevent static electricity release, effectively preventing the driving chip and the light-emitting diode in the light-emitting substrate from being broken down by static electricity, and enhancing the ESD protection of the light-emitting substrate.

[0045] In a possible implementation, an anti-breakdown diode is provided on the lead, the ground layer is electrically connected to the positive electrode of the anti-breakdown diode, and the negative electrode of the anti-breakdown diode is electrically connected to the external ground terminal.

[0046] In a specific example, Figure 3 As shown, an anti-breakdown diode 107 is provided on the lead 106, the ground layer 103 is electrically connected to the positive electrode of the anti-breakdown diode 107, and the negative electrode of the anti-breakdown diode 107 is electrically connected to the external ground terminal.

[0047] Further, such as Figure 3 As shown, the cathode of the anti-breakdown diode 107 is electrically connected to the back panel 108 of the display device.

[0048] In another specific example, Figure 4 As shown, an anti-breakdown diode 307 is provided on the lead 306, the ground layer 303 is electrically connected to the positive electrode of the anti-breakdown diode 307, and the negative electrode of the anti-breakdown diode 307 is electrically connected to the external ground terminal.

[0049] Further, such as Figure 4 As shown, the cathode of the anti-breakdown diode 307 is electrically connected to the back panel 308 of the display device.

[0050] This embodiment arranges an anti-breakdown diode on the lead wire, which can not only release the static electricity inside the light-emitting substrate to the backplane outside the light-emitting substrate, but also use the anti-breakdown diode to prevent the static electricity outside the light-emitting substrate from being released into the inside of the light-emitting substrate, thereby effectively improving the anti-static release capability of the light-emitting substrate during the process, transportation and use.

[0051] In a possible implementation manner, the second passivation layer is provided with a plurality of first via holes exposing the ground layer.

[0052] In a specific example, the second passivation layer is provided with N first via holes exposing the ground layer, where N is an integer greater than 1.

[0053] Furthermore, the ground layer is electrically connected to the external ground terminal through N leads corresponding to each other at the N first via holes.

[0054] In this embodiment, by opening a plurality of first via holes exposing the ground layer in the second passivation layer, the ability to prevent electrostatic discharge is improved compared to opening a single first via hole exposing the ground layer in the second passivation layer, and electrostatic discharge prevention can be achieved more quickly.

[0055] Furthermore, the ground layer is electrically connected to the back panel of the display device by arranging N corresponding anti-breakdown diodes on N leads at N first vias, for example, the ground layer is electrically connected to the positive electrode of the anti-breakdown diode, and the negative electrode of the anti-breakdown diode is electrically connected to the back panel.

[0056] In this embodiment, a ground layer is arranged inside the light-emitting substrate, and a plurality of first via holes exposing the ground layer are opened in the second passivation layer. The plurality of first via holes of the ground layer are respectively connected to a plurality of anti-breakdown diodes and the backplane. Compared with opening a first via hole exposing the ground layer in the second passivation layer, the ability to prevent electrostatic discharge can be improved and the prevention of electrostatic discharge can be achieved more quickly. Moreover, by utilizing the unidirectional conductivity of the anti-breakdown diode, the external static electricity can be effectively protected from passing through the backplane to the light-emitting substrate, thereby further improving the anti-static ability of the light-emitting substrate.

[0057] In a possible implementation manner, the plurality of first via holes are evenly distributed in the frame area.

[0058] In a specific example, Figure 6 As shown, the display device includes a back panel 810, a light-emitting substrate 820 arranged on the back panel 810, the light-emitting substrate 820 includes a light-emitting area 8210 and a border area 8220, for example, the area within the dotted frame 8200 is the light-emitting area 8210, and the area outside the dotted frame 8200 is the border area 8220, the light-emitting area 8210 includes a plurality of light-emitting partitions 8211, one light-emitting partition 8211 includes a plurality of driving chips 8212, and one driving chip 8212 drives a plurality of lamp beads, i.e., light-emitting diodes.

[0059] Further, such as Figure 6 As shown, the border area 8220 includes a ground layer 8221 surrounding the light-emitting area 8210 , and the border area 8220 also includes a bonding area 8222 .

[0060] Further, such as Figure 6 As shown, the display device also includes a flexible printed circuit board (FPC) 830 and a driving printed circuit board (PCB) 840. The driving signal on the driving printed circuit board 840 enters the bonding area 8222 through the flexible printed circuit board 830, and is then transmitted from the bonding area 8222 to the driving chip 8212. The driving chip 8212 drives the light-emitting diode to emit light.

[0061] Further, such as Figure 6 As shown, four first via holes 8223 are evenly distributed in the border area 8220 , and the ground layer 8221 is electrically connected to the back plate 810 through four anti-breakdown diodes 8224 at the four first via holes 8223 .

[0062] In this embodiment, a ground layer is added to the light-emitting substrate of the existing patterning process through etching technology, and the first via holes are evenly distributed in the border area. For example, through holes are made at the four corners of the light-emitting substrate, and the through holes are connected to the external ground through anti-breakdown diodes, so that the static electricity in the light-emitting substrate is released to the outside, and the static electricity instantly excited by the outside is dispersed through the ground layer, and the static electricity in a corner is released to the four corners, thereby improving the passing value of the electrostatic reliability test, improving the overall electrostatic resistance of the light-emitting substrate, and facilitating passing the customer's electrostatic test.

[0063] In another specific example, Figure 7 As shown, the display device includes a back panel 910, a light-emitting substrate 920 arranged on the back panel 910, the light-emitting substrate 920 includes a light-emitting area 9210 and a border area 9220, for example, the area within the dotted frame 9200 is the light-emitting area 9210, and the area outside the dotted frame 9200 is the border area 9220, the light-emitting area 9210 includes a plurality of light-emitting partitions 9211, one light-emitting partition 9211 includes a plurality of driving chips 9212, and one driving chip 9212 drives a plurality of light-emitting diodes.

[0064] Further, such as Figure 7 As shown, the border area 9220 includes a ground layer 9221 surrounding the light-emitting area 9210 , and the border area 9220 also includes a bonding area 9222 .

[0065] Further, such as Figure 7 As shown, the display device also includes a flexible circuit board 930 and a driving circuit board 940. The driving signal on the driving circuit board 940 enters the bonding area 9222 through the flexible circuit board 930, and is then transmitted from the bonding area 9222 to the driving chip 9212. The driving chip 9212 drives the light-emitting diode to emit light.

[0066] Further, such as Figure 7 As shown, four first via holes 9223 are evenly distributed in the border area 9220 , and the ground layer 9221 is electrically connected to the back plate 910 through four anti-breakdown diodes 9224 at the four first via holes 9223 .

[0067] In this embodiment, the first via holes are evenly distributed in the frame area. For example, through holes are made at the four corners of the light-emitting substrate. When external static electricity accidentally enters the light-emitting substrate from a corner, it can be dispersed to the four corners through the ground layer for static electricity release to the external ground, thereby improving the pass value of the electrostatic reliability test, improving the overall electrostatic impact resistance of the light-emitting substrate, and facilitating passing the customer's electrostatic test; moreover, this embodiment shrinks the frame area, effectively reducing the size of the frame of the light-emitting substrate; at the same time, this embodiment also improves the applicability of the light-emitting substrate, and can make the light-emitting substrate suitable for other special-shaped structures.

[0068] In a possible implementation, the ground layer includes a first ground layer and a second ground layer, the first ground layer is arranged on the first passivation layer, the border area also includes a third passivation layer covering the first ground layer, the third passivation layer has a first opening exposing the first ground layer, the first opening surrounds the light-emitting area, the second ground layer is electrically connected to the first ground layer through the first opening, and the second ground layer is electrically connected to the external ground terminal through a lead arranged at the first via hole.

[0069] In a specific example, Figure 1 As shown, the ground layer 103 includes a first ground layer 1031 and a second ground layer 1032, the first ground layer 1031 is arranged on the first passivation layer 102, the border area 10 also includes a third passivation layer 1014 covering the first ground layer 1031, the third passivation layer 1014 has a first opening 1015 exposing the first ground layer 1031, the first opening 1015 surrounds the light-emitting area 20, the second ground layer 1032 is electrically connected to the first ground layer 1031 through the first opening 1015, and the second ground layer 1032 is electrically connected to the external ground terminal through the lead 106 arranged at the first via 105.

[0070] In another specific example, Figure 3 As shown, the ground layer 103 includes a first ground layer 1031 and a second ground layer 1032, the first ground layer 1031 is arranged on the first passivation layer 102, the frame area 10 also includes a third passivation layer 1014 covering the first ground layer 1031, the third passivation layer 1014 is provided with a first opening 1015 exposing the first ground layer 1031, the first opening 1015 surrounds the light-emitting area 20, the second ground layer 1032 is electrically connected to the first ground layer 1031 through the first opening 1015, the second ground layer 1032 is electrically connected to the positive electrode of the anti-breakdown diode 107 through the lead 106 arranged at the first via hole 105, and the negative electrode of the anti-breakdown diode 107 is electrically connected to the back panel 308 of the display device.

[0071] This embodiment is based on the existing Mini LED glass substrate design, which is relatively mature and the etching process is relatively complete. Based on the existing Mini LED glass substrate design, an etching process is used on the glass substrate to produce a ground layer for preventing static electricity in the border area outside the light board, and then holes are punched through the film layer design to prevent static electricity from entering the Mini LED driver chip array. This embodiment can more conveniently change the etching process pattern, and thus can more conveniently improve the anti-static capability by changing the pattern.

[0072] In a possible implementation, the light-emitting area includes a fourth passivation layer arranged on the first substrate and a light-emitting signal routing layer arranged on the fourth passivation layer, the first passivation layer and the fourth passivation layer are arranged on the same layer, and the ground layer and the light-emitting signal routing layer are arranged on the same layer.

[0073] In a specific example, Figure 1 As shown, the light-emitting area 20 includes a fourth passivation layer 202 arranged on the first substrate 101, and the first passivation layer 102 and the fourth passivation layer 202 are arranged on the same layer; a light-emitting signal wiring layer 203 is arranged on the fourth passivation layer 202, and the ground layer 103 and the light-emitting signal wiring layer 203 are arranged on the same layer.

[0074] In another specific example, Figure 2 As shown, the light-emitting area 40 includes a fourth passivation layer 402 arranged on the first substrate 101, and the first passivation layer 302 and the fourth passivation layer 402 are arranged on the same layer; a light-emitting signal wiring layer 403 is arranged on the fourth passivation layer 402, and the ground layer 303 and the light-emitting signal wiring layer 403 are arranged on the same layer.

[0075] This embodiment can simplify the process flow and improve production efficiency by arranging the first passivation layer and the fourth passivation layer on the same layer and the ground layer and the light emitting signal wiring layer on the same layer.

[0076] In a possible implementation, the light-emitting area further includes a fifth passivation layer covering the light-emitting signal wiring layer, and the second passivation layer is disposed on the same layer as the fifth passivation layer.

[0077] In a specific example, Figure 1 As shown, the light-emitting area 20 also includes a fifth passivation layer 204 covering the light-emitting signal wiring layer 203. The fifth passivation layer 204 has a plurality of vias 205 exposing the light-emitting signal wiring layer 203. The vias 205 are used to connect the positive and negative electrodes of the driving chip and the light-emitting diode. The second passivation layer 104 is arranged on the same layer as the fifth passivation layer 204.

[0078] In another specific example, Figure 2 As shown, the light-emitting area 40 also includes a fifth passivation layer 404 covering the light-emitting signal wiring layer 403. The fifth passivation layer 404 has a plurality of vias 405 exposing the light-emitting signal wiring layer 403. The vias 405 are used to connect the positive and negative electrodes of the driving chip and the light-emitting diode. The second passivation layer 304 is arranged on the same layer as the fifth passivation layer 404.

[0079] In this embodiment, the second passivation layer and the fifth passivation layer are arranged on the same layer, so that the process flow can be further simplified and the production efficiency can be improved.

[0080] In a possible implementation, the light-emitting signal routing layer includes a first light-emitting signal routing layer and a second light-emitting signal routing layer, the first light-emitting signal routing layer is arranged on the fourth passivation layer, the light-emitting area also includes a sixth passivation layer covering the first light-emitting signal routing layer, the sixth passivation layer is provided with a second via hole exposing the first light-emitting signal routing layer, the second light-emitting signal routing layer is electrically connected to the first light-emitting signal routing layer through the second via hole, the first ground layer and the first light-emitting signal routing layer are arranged on the same layer, the second ground layer and the second light-emitting signal routing layer are arranged on the same layer, and the third passivation layer and the sixth passivation layer are arranged on the same layer.

[0081] In a specific example, Figure 1As shown, the light-emitting signal routing layer 203 includes a first light-emitting signal routing layer 2031 and a second light-emitting signal routing layer 2032. The first light-emitting signal routing layer 2031 is arranged on the fourth passivation layer 202. The light-emitting area 20 also includes a sixth passivation layer 2014 covering the first light-emitting signal routing layer 2031. The sixth passivation layer 2014 is provided with a second via hole 2015 exposing the first light-emitting signal routing layer 2031. The second light-emitting signal routing layer 2032 is electrically connected to the first light-emitting signal routing layer 2031 through the second via hole 2015. The first ground layer 1031 is arranged on the same layer as the first light-emitting signal routing layer 2031, the second ground layer 1032 is arranged on the same layer as the second light-emitting signal routing layer 2032, and the third passivation layer 1014 is arranged on the same layer as the sixth passivation layer 2014.

[0082] Further, such as Figure 1 As shown, the light-emitting area 20 further includes a third buffer layer 2010 disposed on a side of the fourth passivation layer 202 and the light-emitting signal wiring layer 203 away from the first substrate 101, and the third buffer layer 2010 has a via hole exposing a portion of the light-emitting signal wiring layer 203; a third flat layer 2011 disposed on a side of the third buffer layer 2010 away from the first substrate 101, and the third flat layer 2011 has a via hole exposing a portion of the light-emitting signal wiring layer 203; and a third flat layer 2011 disposed on a side of the third buffer layer 2010 away from the first substrate 101. A fourth buffer layer 2012 is arranged on one side, and the fourth buffer layer 2012 has a via hole exposing a portion of the light-emitting signal wiring layer 203; a fourth flat layer 2013 is arranged on the side of the fourth buffer layer 2012 away from the first substrate 101, and the fourth flat layer 2013 has a via hole exposing a portion of the light-emitting signal wiring layer 203; a sixth passivation layer 2014 is arranged on the side of the fourth flat layer 2013 away from the first substrate 101, and the sixth passivation layer 2014 has a via hole exposing a portion of the light-emitting signal wiring layer 203.

[0083] This embodiment can further simplify the preparation process and improve production efficiency by setting the first ground layer and the first light-emitting signal routing layer on the same layer, the third passivation layer and the sixth passivation layer on the same layer, and the second ground layer and the second light-emitting signal routing layer on the same layer.

[0084] Further, such as Figure 1 As shown, the first buffer layer 1010 and the third buffer layer 2010 are arranged in the same layer; the first flat layer 1011 and the third flat layer 2011 are arranged in the same layer; the second buffer layer 1012 and the fourth buffer layer 2012 are arranged in the same layer; and the second flat layer 1013 and the fourth flat layer 2013 are arranged in the same layer.

[0085] This embodiment can further simplify the preparation process and improve production efficiency by arranging the buffer layer of the light-emitting area and the buffer layer of the border area on the same layer, and arranging the flat layer of the light-emitting area and the flat layer of the border area on the same layer.

[0086] In another specific example, Figure 2 As shown, the light-emitting signal routing layer 403 includes a first light-emitting signal routing layer 4031 and a second light-emitting signal routing layer 4032. The first light-emitting signal routing layer 4031 is arranged on the fourth passivation layer 402. The light-emitting area 40 also includes a sixth passivation layer 4014 covering the first light-emitting signal routing layer 4031. The sixth passivation layer 4014 is provided with a second via hole 4015 exposing the first light-emitting signal routing layer 4031. The second light-emitting signal routing layer 4032 is electrically connected to the first light-emitting signal routing layer 4031 through the second via hole 4015. The ground layer 303 is arranged on the same layer as the first light-emitting signal routing layer 4031, and the third passivation layer 3014 is arranged on the same layer as the sixth passivation layer 4014.

[0087] Further, such as Figure 2 As shown, the light-emitting area 40 further includes a third buffer layer 4010 disposed on a side of the fourth passivation layer 402 and a portion of the light-emitting signal wiring layer 403 away from the first substrate 301, and the third buffer layer 4010 has a via hole exposing a portion of the light-emitting signal wiring layer 403; a third flat layer 4011 disposed on a side of the third buffer layer 4010 away from the first substrate 301, and the third flat layer 4011 has a via hole exposing a portion of the light-emitting signal wiring layer 403; and a third flat layer 4011 disposed on a side of the third buffer layer 4010 away from the first substrate 301. 1, the fourth buffer layer 4012 having a via hole exposing a portion of the light-emitting signal wiring layer 403; a fourth flat layer 4013 arranged on a side of the fourth buffer layer 4012 away from the first substrate 301, the fourth flat layer 4013 having a via hole exposing a portion of the light-emitting signal wiring layer 403; a third passivation layer 4014 arranged on a side of the fourth flat layer 4013 away from the first substrate 301, the third passivation layer 4014 having a via hole exposing a portion of the light-emitting signal wiring layer 403.

[0088] In this embodiment, the first ground layer and the first light-emitting signal wiring layer are arranged on the same layer, and the third passivation layer and the sixth passivation layer are arranged on the same layer, so as to further simplify the preparation process and improve the production efficiency.

[0089] Further, such as Figure 2 As shown, the first buffer layer 3010 and the third buffer layer 4010 are arranged in the same layer; the first flat layer 3011 and the third flat layer 4011 are arranged in the same layer; the second buffer layer 3012 and the fourth buffer layer 4012 are arranged in the same layer; and the second flat layer 3013 and the fourth flat layer 4013 are arranged in the same layer.

[0090] This embodiment can further simplify the preparation process and improve production efficiency by arranging the buffer layer of the light-emitting area and the buffer layer of the border area on the same layer, and arranging the flat layer of the light-emitting area and the flat layer of the border area on the same layer.

[0091] In a specific example, Figure 5 As shown, the light emitting area 50 includes a fourth passivation layer 502 disposed on a first substrate 501 , and a light emitting signal wiring layer 503 and a light emitting signal wiring layer 506 disposed on the fourth passivation layer 502 .

[0092] Further, such as Figure 5 As shown, the light-emitting area 50 further includes a fifth passivation layer 504 covering the light-emitting signal wiring layer 503 and the light-emitting signal wiring layer 506 , and the fifth passivation layer 504 is provided with a plurality of via holes 505 exposing the light-emitting signal wiring layer 503 and the light-emitting signal wiring layer 506 .

[0093] Further, such as Figure 5 As shown, the light-emitting signal routing layer 503 includes a first light-emitting signal routing layer 5031 and a second light-emitting signal routing layer 5032. The first light-emitting signal routing layer 5031 is arranged on the fourth passivation layer 502. The light-emitting area 50 also includes a sixth passivation layer 5014 covering the first light-emitting signal routing layer 5031. The sixth passivation layer 5014 is provided with a second via hole 5015 exposing the first light-emitting signal routing layer 5031. The second light-emitting signal routing layer 5032 is electrically connected to the first light-emitting signal routing layer 5031 through the second via hole 5015. The second light-emitting signal routing layer 5032 is electrically connected to the positive electrode 701 of the driving chip 70, and the second light-emitting signal routing layer 5032 is electrically connected to the positive electrode 601 of the light-emitting diode 60.

[0094] Further, such as Figure 5 As shown, the light-emitting signal routing layer 506 includes a first light-emitting signal routing layer 5061 and a second light-emitting signal routing layer 5062. The first light-emitting signal routing layer 5061 is arranged on the fourth passivation layer 502. The light-emitting area 50 also includes a sixth passivation layer 5014 covering the first light-emitting signal routing layer 5061. The sixth passivation layer 5014 is provided with a second via hole 5015 exposing the first light-emitting signal routing layer 5061. The second light-emitting signal routing layer 5062 is electrically connected to the first light-emitting signal routing layer 5061 through the second via hole 5015. The second light-emitting signal routing layer 5062 is electrically connected to the cathode 702 of the driving chip 70, and the second light-emitting signal routing layer 5062 is electrically connected to the cathode 602 of the light-emitting diode 60.

[0095] Further, such as Figure 5As shown, the light-emitting area 50 also includes a third buffer layer 5010 arranged on the side where the fourth passivation layer 502, the light-emitting signal routing layer 503 and the light-emitting signal routing layer 506 are away from the first substrate 501, and the third buffer layer 5010 has a via hole exposing part of the light-emitting signal routing layer 503 and part of the light-emitting signal routing layer 506; a third flat layer 5011 arranged on the side where the third buffer layer 5010 is away from the first substrate 501, and the third flat layer 5011 has a via hole exposing part of the light-emitting signal routing layer 503 and part of the light-emitting signal routing layer 506; and a third flat layer 5011 arranged on the side where the third buffer layer 5010 is away from the first substrate 501. A fourth buffer layer 5012 is arranged on the side of the fourth buffer layer 5012, and the fourth buffer layer 5012 has vias exposing part of the light-emitting signal routing layer 503 and part of the light-emitting signal routing layer 506; a fourth flat layer 5013 is arranged on the side of the fourth buffer layer 5012 away from the first substrate 501, and the fourth flat layer 5013 has vias exposing part of the light-emitting signal routing layer 503 and part of the light-emitting signal routing layer 506; a sixth passivation layer 5014 is arranged on the side of the fourth flat layer 5013 away from the first substrate 501, and the sixth passivation layer 5014 has vias exposing part of the light-emitting signal routing layer 503 and part of the light-emitting signal routing layer 506.

[0096] In this embodiment, the film layer of the light-emitting area and the film layer of the frame area are arranged on the same layer, so as to further simplify the process flow of the light-emitting substrate and improve the production efficiency of the light-emitting substrate.

[0097] In a possible implementation, the border area further includes a bonding area, and the ground layer is located on a side of the bonding area away from the light-emitting area.

[0098] In a specific example, Figure 6 As shown, the border area 8220 also includes a bonding area 8222 , and the ground layer 8221 is located on a side of the bonding area 8222 away from the light-emitting area 8210 .

[0099] In another specific example, Figure 7 As shown, the border area 9220 also includes a bonding area 9222 , and the ground layer 9221 is located on a side of the bonding area 9222 away from the light-emitting area 9210 .

[0100] In this embodiment, the ground layer is arranged on the side of the bonding area away from the light-emitting area, that is, the ground layer is located on the periphery of the bonding area. The driving signal of the driving circuit board enters the bonding area through the flexible circuit board, and is then transmitted to the driving chip of the light-emitting diode to drive the light-emitting diode to emit light. There is no interference between the driving signal routing and the peripheral ground layer routing, and there is no need to avoid them, which effectively improves the signal quality.

[0101] Another embodiment of the present disclosure provides a display device, including a backlight source and a liquid crystal display panel, wherein the backlight source includes the light-emitting substrate provided by an embodiment of the present disclosure.

[0102] In a specific example, the display device may be a mobile phone, or a computer, a television, a smart wearable device, etc., and this embodiment does not specifically limit this.

[0103] In this embodiment, a ground layer surrounding the light-emitting area is arranged in the frame area of ​​the light-emitting substrate, and at least one first via hole in the second passivation layer is exposed to the ground layer, so that the ground layer is electrically connected to the external ground terminal through the lead wire arranged at the first via hole. When static electricity is generated, the static electricity can be released to the external ground terminal outside the light-emitting substrate through the ground layer, the first via hole and the lead wire, thereby improving the ability of the light-emitting substrate to prevent static electricity release, effectively preventing the driving chip and the light-emitting diode in the light-emitting substrate from being broken down by static electricity, and enhancing the ESD protection of the light-emitting substrate.

[0104] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in this field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A light-emitting substrate, characterized in that: The invention comprises a light-emitting area and a frame area surrounding the light-emitting area; wherein the frame area comprises: a first substrate; a first passivation layer disposed on the first substrate; A ground layer is provided on the first passivation layer, and the ground layer surrounds the light emitting area; A second passivation layer covers the ground layer, the second passivation layer is provided with at least one first via hole exposing the ground layer, and the ground layer is electrically connected to an external ground terminal through a lead wire arranged at the first via hole.

2. The light-emitting substrate according to claim 1, characterized in that: An anti-breakdown diode is arranged on the lead wire, the ground wire layer is electrically connected to the positive electrode of the anti-breakdown diode, and the negative electrode of the anti-breakdown diode is electrically connected to the external ground terminal.

3. The light-emitting substrate according to claim 1, characterized in that: The second passivation layer is provided with a plurality of first via holes exposing the ground layer.

4. The light-emitting substrate according to claim 3, characterized in that: The plurality of first via holes are evenly distributed in the frame area.

5. The light-emitting substrate according to claim 1 or 2, characterized in that: The ground layer includes a first ground layer and a second ground layer, the first ground layer is arranged on the first passivation layer, the border area also includes a third passivation layer covering the first ground layer, the third passivation layer has a first opening exposing the first ground layer, the first opening surrounds the light-emitting area, the second ground layer is electrically connected to the first ground layer through the first opening, and the second ground layer is electrically connected to the external ground terminal through a lead arranged at the first via hole.

6. The light-emitting substrate according to claim 5, characterized in that: The light-emitting area includes a fourth passivation layer arranged on the first substrate and a light-emitting signal wiring layer arranged on the fourth passivation layer. The first passivation layer and the fourth passivation layer are arranged on the same layer, and the ground layer and the light-emitting signal wiring layer are arranged on the same layer.

7. The light-emitting substrate according to claim 6, characterized in that: The light-emitting area further includes a fifth passivation layer covering the light-emitting signal wiring layer, and the second passivation layer is disposed on the same layer as the fifth passivation layer.

8. The light-emitting substrate according to claim 7, characterized in that: The light-emitting signal routing layer includes a first light-emitting signal routing layer and a second light-emitting signal routing layer, the first light-emitting signal routing layer is arranged on the fourth passivation layer, the light-emitting area also includes a sixth passivation layer covering the first light-emitting signal routing layer, the sixth passivation layer is provided with a second via hole exposing the first light-emitting signal routing layer, the second light-emitting signal routing layer is electrically connected to the first light-emitting signal routing layer through the second via hole, the first ground layer and the first light-emitting signal routing layer are arranged on the same layer, the second ground layer and the second light-emitting signal routing layer are arranged on the same layer, and the third passivation layer and the sixth passivation layer are arranged on the same layer.

9. The light-emitting substrate according to claim 1, characterized in that: The border area also includes a bonding area, and the ground layer is located on a side of the bonding area away from the light-emitting area.

10. A display device, characterized in that: It comprises a backlight source and a liquid crystal display panel, wherein the backlight source comprises the light-emitting substrate as described in any one of claims 1 to 9.

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