Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate; the first conductive layer is positioned on one side of the substrate; a second conductive layer between the first conductive layer and the substrate; the first capacitor comprises a first polar plate, and the first polar plate is located on the second conductive layer; the second capacitor comprises a second pole plate, the second pole plate is located on the second conducting layer, the first capacitor and the second capacitor comprise a common pole plate, the common pole plate is located on the first conducting layer, and the at least one transistor is located between the first conducting layer and the substrate. The orthographic projection of the at least one transistor on the substrate is at least partially located in the orthographic projection of the common polar plate on the substrate. The common polar plate is shared by the plurality of capacitors, and when the space occupied by the transistor is fixed, compared with the prior art, the area of the first capacitor and the area of the second capacitor are increased, the high-resolution requirement is met, the pixel arrangement density is further improved, and the resolution of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] As a carrier of information display and a window for human-computer interaction in the digital age, display screens are becoming an important port for people to receive visual information, and are constantly affecting people's lives and the development of the economy and society. In addition, with the advancement of display technology and the continuous improvement of people's demand for information interaction, commercial display products are being integrated into life at an unprecedented speed, and the functions of commercial display products are also constantly improving. For example, display solutions such as virtual reality (VR) and augmented reality (AR) bring users a new visual experience. Organic light emitting diode (OLED) display devices are widely used due to their light weight, self-luminescence, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption and fast response speed.

[0003] However, existing OLED display devices have the defect of low resolution and cannot meet the application requirements of display solutions such as AR / VR. Summary of the invention

[0004] In view of this, the embodiments of the present application are directed to providing an array substrate and a method for manufacturing the same, and a display panel, so as to solve the problem of low resolution of the display device.

[0005] In a first aspect, the present application provides an array substrate, comprising: a substrate; a first conductive layer, located on one side of the substrate; a second conductive layer, located between the first conductive layer and the substrate; a first capacitor, the first capacitor comprising a first electrode plate, the first electrode plate being located in the second conductive layer; a second capacitor, the second capacitor comprising a second electrode plate, the second electrode plate being located in the second conductive layer, the first capacitor and the second capacitor comprising a common electrode plate, the common electrode plate being located in the first conductive layer, the first electrode plate and the second electrode plate being spaced apart, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate are both at least partially located within the orthographic projection of the common electrode plate on the substrate; and at least one transistor, located between the first conductive layer and the substrate, the orthographic projection of the at least one transistor on the substrate being at least partially located within the orthographic projection of the common electrode plate on the substrate.

[0006] In one embodiment, the array substrate further includes: an active layer, located between the second conductive layer and the substrate; a fourth conductive layer, located between the active layer and the second conductive layer; at least one transistor includes a first transistor, the first transistor includes a first channel and a first gate, the first channel is located in the active layer, the first gate is located in the fourth conductive layer, the orthographic projection of the first gate on the active layer covers the first channel, and the first gate is electrically connected to the first electrode plate of the first capacitor; preferably, the orthographic projection of the first gate on the substrate is at least partially located within the orthographic projection of the first electrode plate on the substrate.

[0007] In one embodiment, the array substrate also includes: a third conductive layer, the third conductive layer is located between the fourth conductive layer and the second conductive layer; a first connecting portion, located in the third conductive layer, and the first gate is electrically connected to the first electrode plate through the first connecting portion; preferably, a second insulating layer is provided between the second conductive layer and the third conductive layer, and a first insulating layer is provided between the third conductive layer and the fourth conductive layer, the first electrode plate passes through the second insulating layer and is connected to the first connecting portion, and the first connecting portion passes through the first insulating layer and is connected to the first gate; preferably, the first transistor is a driving transistor.

[0008] In one embodiment, the array substrate also includes an anode, which is located on the side of the first conductive layer facing away from the substrate, the first electrode of the first transistor is located in the third conductive layer, the second electrode plate passes through the second insulating layer and is connected to the first electrode of the first transistor, and the first electrode of the first transistor is electrically connected to the first end of the first channel; preferably, the second electrode plate is connected to the first power supply signal; preferably, the second electrode of the first transistor is located in the third conductive layer, the second electrode of the first transistor is electrically connected to the second end of the first channel, and the second electrode of the first transistor is connected to the anode.

[0009] In one embodiment, a gate insulating layer is provided between the fourth conductive layer and the active layer, the first electrode of the first transistor passes through the first insulating layer and the gate insulating layer and is electrically connected to the first end of the first channel, and the second electrode of the first transistor passes through the first insulating layer and the gate insulating layer and is electrically connected to the second end of the first channel; preferably, the array substrate also includes a second connecting portion, which is located in the first conductive layer, the second connecting portion is connected to the anode, a third insulating layer is provided between the first conductive layer and the second conductive layer, and the second connecting portion passes through the third insulating layer and the second insulating layer and is connected to the second electrode of the first transistor.

[0010] In one embodiment, at least one transistor also includes a second transistor, the second transistor includes a second channel and a second gate, the second channel is located in the active layer, the second gate is located in the fourth conductive layer, and the orthographic projection of the second gate on the active layer covers the second channel; preferably, the orthographic projection of the second gate on the substrate is at least partially located within the orthographic projection of the second electrode plate on the substrate; preferably, the orthographic projection of the second channel on the substrate is at least partially located within the orthographic projection of the common electrode plate on the substrate; preferably, the array substrate also includes a second scanning signal line, and the second gate is located on the second scanning signal line; preferably, the second transistor is a data write transistor.

[0011] In one embodiment, the first electrode of the second transistor is located in the third conductive layer, and the first electrode of the second transistor passes through the first insulating layer and the gate insulating layer to be electrically connected to the first end of the second channel; preferably, the first electrode of the second transistor is connected to the data voltage signal; preferably, the second electrode of the second transistor is located in the third conductive layer, and the second electrode of the second transistor passes through the first insulating layer and the gate insulating layer to be electrically connected to the second end of the second channel; preferably, the common electrode passes through the third insulating layer and the second insulating layer to be electrically connected to the second electrode of the second transistor.

[0012] In one embodiment, at least one transistor further includes a third transistor, the third transistor includes a third channel and a third gate, the third channel is located in the active layer, the third gate is located in the fourth conductive layer, the orthographic projection of the third gate on the active layer covers the third channel, and the second end of the third channel is electrically connected to the second end of the first channel through the active layer; preferably, the orthographic projection of the third channel on the substrate is at least partially located within the orthographic projection of the common electrode on the substrate; preferably, the first end of the third channel is electrically connected to the first electrode plate; preferably, the first electrode of the third transistor is located in the third conductive layer, the first electrode plate passes through the second insulating layer and is electrically connected to the first electrode of the third transistor, and the first electrode of the third transistor passes through the first insulating layer and the gate insulating layer and is electrically connected to the first end of the third channel; preferably, the array substrate further includes a first scanning signal line, and the third gate is located on the first scanning signal line; preferably, the third transistor is a threshold compensation transistor.

[0013] The second aspect of the present application provides a method for preparing an array substrate, comprising: preparing at least one transistor on a substrate; preparing a second conductive layer on a side of the at least one transistor facing away from the substrate, and preparing a first electrode plate and a second electrode plate spaced apart on the second conductive layer; preparing a first conductive layer on a side of the second conductive layer facing away from the substrate, and preparing a common electrode plate on the first conductive layer; wherein the first electrode plate and the common electrode plate constitute a first capacitor, the second electrode plate and the common electrode plate constitute a second capacitor, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate are both at least partially located within the orthographic projection of the common electrode plate on the substrate, and the orthographic projection of the transistor on the substrate is at least partially located within the orthographic projection of the common electrode plate on the substrate.

[0014] A third aspect of the present application provides a display panel, comprising: an array substrate as mentioned in the above embodiment.

[0015] The technical solution provided by the present application is to set a common plate to be shared by the first capacitor and the second capacitor, and to set the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate to be at least partially located within the orthographic projection of the common plate on the substrate, thereby increasing the capacitor area; and to set the orthographic projection of the transistor on the substrate to be at least partially located within the orthographic projection of the common plate on the substrate, thereby realizing the stacking arrangement of capacitors and transistors. In this way, when the space occupied by the transistor is certain, compared with the prior art, the area of ​​the first capacitor and the second capacitor is increased to meet the high-resolution requirements, so that the pixel size meets the high-resolution requirements, further improves the pixel arrangement density, is conducive to improving the resolution of the display panel, and is conducive to the application of display devices in the AR / VR field. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 1 is a schematic diagram of the structure of an array substrate provided in one embodiment of the present application.

[0017] Figure 2 FIG. 1 is a schematic diagram of the structure of a pixel circuit provided in one embodiment of the present application.

[0018] Figure 3 Shown is a schematic structural diagram of an array substrate provided in another embodiment of the present application.

[0019] Figure 4 FIG. 1 is a schematic diagram of the structure of a pixel circuit provided in one embodiment of the present application.

[0020] Figure 5 Shown is a schematic structural diagram of a pixel circuit provided in another embodiment of the present application.

[0021] Figure 6 Shown is a schematic layout of a pixel circuit provided in one embodiment of the present application.

[0022] Figure 7 Shown is a schematic layout of an array substrate provided in another embodiment of the present application.

[0023] Figure 8 FIG. 1 is a schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application.

[0024] Fig. 9 The figure is a schematic diagram of the preparation process of an array substrate provided in one embodiment of the present application.

[0025] Fig.10 Shown is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] Figure 1 FIG. 1 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application. Figure 1 The array substrate includes: a substrate 100; a first conductive layer M1, located on one side of the substrate 100; a second conductive layer M2, located between the first conductive layer M1 and the substrate 100; a first capacitor C1, the first capacitor C1 includes a first electrode 101, the first electrode 101 is located on the second conductive layer M2; a second capacitor C2, the second capacitor C2 includes a second electrode 201, the second electrode 201 is located on the second conductive layer M2, the first capacitor C1 and the second capacitor C2 include a common electrode 301, the common electrode 301 1 is located in the first conductive layer M1, the first electrode plate 101 and the second electrode plate 201 are arranged at intervals, the orthographic projection of the first electrode plate 101 on the substrate 100 and the orthographic projection of the second electrode plate 201 on the substrate 100 are both at least partially located in the orthographic projection of the common electrode plate 301 on the substrate 100; and at least one transistor 102 is located between the first conductive layer M1 and the substrate 100, and the orthographic projection of the at least one transistor 102 on the substrate 100 is at least partially located in the orthographic projection of the common electrode plate 301 on the substrate 100.

[0028] Specifically, a first conductive layer M1 is provided on one side of the substrate 100, and a common plate 301 is provided on the first conductive layer M1, serving as one side plate of the first capacitor C1 and the second capacitor C2. A second conductive layer M2 is provided between the first conductive layer M1 and the substrate 100, and a first plate 101 is provided on the second conductive layer M2, serving as the other side plate of the first capacitor C1. A second plate 201 is also provided on the second conductive layer M2, serving as the other side plate of the second capacitor C2. The first plate 101 and the second plate 201 are spaced apart to avoid a short circuit between the first capacitor C1 and the second capacitor C2. At least one transistor 102 is provided between the second conductive layer M2 and the substrate 100, and is electrically connected to the capacitor to form a pixel circuit. By controlling the pixel circuit, the display state of each pixel of the display panel can be controlled.

[0029] The orthographic projection of the first electrode plate 101 on the substrate 100 and the orthographic projection of the second electrode plate 201 on the substrate 100 are both at least partially located within the orthographic projection of the common electrode plate 301 on the substrate 100, that is, in the direction away from the substrate 100, the common electrode plate 301 at least partially covers the first electrode plate 101 and the second electrode plate 201. The orthographic projection of the transistor 102 on the substrate 100 is set to be at least partially located within the orthographic projection of the common electrode plate 301 on the substrate 100, that is, in the direction away from the substrate 100, the common electrode plate 301 at least partially covers the transistor 102. The transistor 102 and the capacitor are arranged in a stacked manner in a direction perpendicular to the substrate 100, and the area occupied by the capacitor covers the area occupied by the transistor 102. When the space occupied by the transistor 102 is constant, compared with the prior art, the area of ​​the first capacitor C1 and the second capacitor C2 is increased, so that the size of the pixel meets the high resolution requirement.

[0030] The types of the substrate 100 include, but are not limited to, a glass substrate or a polymer substrate.

[0031] The technical solution provided in this embodiment is to set the common plate 301 to be shared by the first capacitor C1 and the second capacitor C2, and to set the orthographic projection of the first plate 101 of the first capacitor C1 on the substrate 100 and the orthographic projection of the second plate 201 of the second capacitor C2 on the substrate 100 to be at least partially located within the orthographic projection of the common plate 301 on the substrate 100, thereby increasing the capacitor area; and to set the orthographic projection of the transistor 102 on the substrate 100 to be at least partially located within the orthographic projection of the common plate 301 on the substrate 100, thereby realizing the stacking arrangement of the capacitor and the transistor 102. In this way, when the space occupied by the transistor 102 is certain, compared with the prior art, the area of ​​the first capacitor C1 and the second capacitor C2 is increased to meet the high-resolution requirements, thereby making the pixel size meet the high-resolution requirements, further improving the pixel arrangement density, and being conducive to improving the resolution of the display panel, and being conducive to the application of the display device in the AR / VR field.

[0032] Figure 2 FIG. 1 is a schematic diagram of the structure of an array substrate provided by another embodiment of the present application. Figure 2 The array substrate also includes: an active layer PSI, located between the second conductive layer M2 and the substrate 100; a fourth conductive layer M4, located between the active layer PSI and the second conductive layer M2; at least one transistor 102 includes a first transistor T1, the first transistor T1 includes a first channel PSI1 and a first gate G1, the first channel PSI1 is located in the active layer PSI, the first gate G1 is located in the fourth conductive layer M4, the orthographic projection of the first gate G1 on the active layer PSI covers the first channel PSI1, and the first gate G1 is electrically connected to the first electrode 101 of the first capacitor C1; preferably, the orthographic projection of the first gate G1 on the substrate 100 is at least partially located within the orthographic projection of the first electrode 101 on the substrate 100.

[0033] Specifically, an active layer PSI is provided between the second conductive layer M2 and the substrate 100, and a first channel PSI1 of a first transistor T1 is provided on the active layer PSI. A fourth conductive layer M4 is provided between the active layer PSI and the second conductive layer M2, and a first gate G1 of the first transistor T1 is provided on the fourth conductive layer M4. The first gate G1 covers the first channel PSI1 in the orthographic projection of the active layer PSI, and the first gate G1 controls the flow of charge in the first channel PSI1 through an electric field. When a voltage is applied to the first gate G1, the first channel PSI1 allows current to flow between the source and the drain of the first transistor T1. The first gate G1 is electrically connected to the first electrode plate 101 of the first capacitor C1, so that the first transistor T1 is electrically connected to the first capacitor C1, and the first terminal voltage of the first capacitor C1 controls the on-off state of the first transistor T1. The orthographic projection of the first gate G1 on the substrate 100 is at least partially located within the orthographic projection of the first electrode plate 101 on the substrate 100, which is beneficial in that it is conducive to further improving the resolution of the display device.

[0034] In one embodiment, see Figure 2 The array substrate also includes: a third conductive layer M3, the third conductive layer M3 is located between the fourth conductive layer M4 and the second conductive layer M2; a first connecting portion 110, located in the third conductive layer M3, and the first gate G1 is electrically connected to the first electrode 101 through the first connecting portion 110; preferably, a second insulating layer ILD2 is provided between the second conductive layer M2 and the third conductive layer M3, a first insulating layer ILD1 is provided between the third conductive layer M3 and the fourth conductive layer M4, the first electrode 101 penetrates the second insulating layer ILD2 and is connected to the first connecting portion 110, and the first connecting portion 110 penetrates the first insulating layer ILD1 and is connected to the first gate G1; preferably, the first transistor T1 is a driving transistor.

[0035] Specifically, the third conductive layer M3 is arranged between the fourth conductive layer M4 and the second conductive layer M2, and a first connecting portion 110 is arranged thereon. A first insulating layer ILD1 is arranged to isolate the third conductive layer M3 and the fourth conductive layer M4 to prevent short circuit. A via hole is arranged on the first insulating layer ILD1, so that the first connecting portion 110 passes through the first insulating layer ILD1 and is connected to the first gate G1 through the via hole. A second insulating layer ILD2 is arranged to isolate the second conductive layer M2 and the third conductive layer M3, and a via hole is arranged on the second insulating layer ILD2. The first electrode 101 passes through the second insulating layer ILD2 and is connected to the first connecting portion 110 through the via hole. Then the first gate G1 forms an electrical connection path with the first electrode 101. The first transistor T1 can play a driving role in the pixel circuit. Such an arrangement has the advantage that after the first capacitor C1 and the first transistor T1 are stacked, the connection structure between the first gate G1 and the first electrode 101 is optimized through the arrangement of multiple insulating layers, which is conducive to further improving the pixel arrangement density and the resolution of the display panel.

[0036] Illustratively, the material of each of the above-mentioned conductive layers may include metals or alloys such as molybdenum, tungsten, and titanium.

[0037] Figure 3 FIG. 1 is a schematic diagram of the structure of an array substrate provided in another embodiment of the present application. Figure 3 The array substrate also includes an anode Anode1, which is located on the side of the first conductive layer M1 away from the substrate 100, the first electrode 11 of the first transistor T1 is located in the third conductive layer M3, the second electrode plate 201 penetrates the second insulating layer ILD2 and is connected to the first electrode 11 of the first transistor T1, and the first electrode 11 of the first transistor T1 is electrically connected to the first end of the first channel PSI1; preferably, the second electrode plate 201 is connected to the first power signal VDD; preferably, the second electrode 12 of the first transistor T1 is located in the third conductive layer M3, the second electrode 12 of the first transistor T1 is electrically connected to the second end of the first channel PSI1, and the second electrode 12 of the first transistor T1 is connected to the anode Anode1.

[0038] Specifically, the array substrate includes a light-emitting device, and the light-emitting device includes an anode Anode1. The anode Anode1 is arranged on the side of the first conductive layer M1 away from the substrate 100. The first electrode 11 and the second electrode 12 of the first transistor T1 are arranged on the third conductive layer M3, and the first electrode 11 is electrically connected to the first end of the first channel PSI1, and the second electrode 12 is electrically connected to the second end of the first channel PSI1, and the second electrode 12 is connected to the anode Anode1. One end of the second electrode plate 201 is connected to the first power signal VDD, and the first power signal VDD supplies power to the pixel circuit. The second end of the second electrode plate 201 penetrates the second insulating layer ILD2 and is connected to the first electrode 11 of the first transistor T1, completing the electrical connection between the first transistor T1 and the second capacitor C2, and the voltage of the second electrode plate 201 is input to the first electrode 11 of the first transistor T1. The advantage of such a configuration is that after the second capacitor C2 and the first transistor T1 are stacked, the connection structure between the first electrode 11 and the second electrode 12 of the first transistor T1 and the second electrode plate 201 and the anode Anode 1 is optimized through the configuration of multiple insulating layers, which is beneficial to further improve the pixel arrangement density and improve the resolution of the display panel.

[0039] In one embodiment, see Figure 3 A gate insulating layer GI is provided between the fourth conductive layer M4 and the active layer PSI, a first electrode 11 of the first transistor T1 penetrates the first insulating layer ILD1 and the gate insulating layer GI and is electrically connected to the first end of the first channel PSI1, a second electrode 12 of the first transistor T1 penetrates the first insulating layer ILD1 and the gate insulating layer GI and is electrically connected to the second end of the first channel PSI1; preferably, the array substrate further includes a second connecting portion 120, which is located in the first conductive layer M1, the second connecting portion 120 is connected to the anode Anode1, a third insulating layer ILD3 is provided between the first conductive layer M1 and the second conductive layer M2, the second connecting portion 120 penetrates the third insulating layer ILD3 and the second insulating layer ILD2 and is connected to the second electrode 12 of the first transistor T1.

[0040] Specifically, a gate insulating layer GI is provided to isolate the fourth conductive layer M4 and the active layer PSI to prevent short circuit. A via hole is provided on the gate insulating layer GI so that the first electrode 11 of the first transistor T1 penetrates the first insulating layer ILD1 and the gate insulating layer GI to be electrically connected to the first end of the first channel PSI1, and the second electrode 12 of the first transistor T1 penetrates the first insulating layer ILD1 and the gate insulating layer GI to be electrically connected to the second end of the first channel PSI1, thereby realizing the flow path of the current in the first channel PSI1. A second connecting portion 120 is provided on the first conductive layer M1, which is directly connected to the anode Anode1. A third insulating layer ILD3 is provided to isolate the first conductive layer M1 and the second conductive layer M2 to prevent short circuit. A via hole is provided on the third insulating layer ILD3 so that the second connecting portion 120 penetrates the third insulating layer ILD3 and the second insulating layer ILD2 to be connected to the second electrode 12 of the first transistor T1, thereby forming an electrical connection path between the second electrode 12 of the first transistor T1 and the anode Anode1. The bright and dark state of the light-emitting device can be controlled by controlling the on-off state of the first transistor T1. The advantage of such a configuration is that after the capacitor and the first transistor T1 are stacked, the connection structure between the first electrode 11 and the second electrode 12 of the first transistor T1 and the first channel PSI1, as well as the connection structure between the second electrode 12 of the first transistor T1 and the anode Anode1 is optimized through the configuration of multiple insulating layers, which is beneficial to further improve the pixel arrangement density and improve the resolution of the display panel.

[0041] In one embodiment, see Figure 3 , at least one transistor 102 also includes a second transistor T2, the second transistor T2 includes a second channel PSI2 and a second gate G2, the second channel PSI2 is located in the active layer PSI, the second gate G2 is located in the fourth conductive layer M4, and the orthographic projection of the second gate G2 on the active layer PSI covers the second channel PSI2; preferably, the orthographic projection of the second gate G2 on the substrate 100 is at least partially located within the orthographic projection of the second electrode plate 201 on the substrate 100; preferably, the orthographic projection of the second channel PSI2 on the substrate 100 is at least partially located within the orthographic projection of the common electrode plate 301 on the substrate 100; preferably, the array substrate also includes a second scanning signal line, and the second gate G2 is located on the second scanning signal line; preferably, the second transistor T2 is a data writing transistor.

[0042] Specifically, a second channel PSI2 of a second transistor T2 is also provided on the active layer PSI. A second gate G2 of the second transistor T2 is also provided on the fourth conductive layer M4. The second gate G2 covers the second channel PSI2 in the positive projection of the active layer PSI, and the second gate G2 controls the flow of charge in the second channel PSI2 through an electric field. When a voltage is applied to the second gate G2, the second channel PSI2 allows current to flow between the source and the drain of the second transistor T2. The first gate G1 is electrically connected to the first electrode plate 101 of the first capacitor C1, so that the first transistor T1 is electrically connected to the first capacitor C1, and the on-off state of the first transistor T1 can be controlled by the first terminal voltage of the first capacitor C1.

[0043] The array substrate further includes a second scanning signal line, which is used to activate the second transistor T2. The second transistor T2 is used as a data writing transistor to write display data into the pixel circuit, thereby adjusting the voltage or current of the pixel.

[0044] The orthographic projection of the second gate G2 on the substrate 100 is at least partially located within the orthographic projection of the second electrode plate 201 on the substrate 100, and the orthographic projection of the second channel PSI2 on the substrate 100 is at least partially located within the orthographic projection of the common electrode plate 301 on the substrate 100, thereby realizing a stacked arrangement structure of the second transistor T2 and the second capacitor C2, which has the advantage of further improving the resolution of the display device.

[0045] In one embodiment, see Figure 3 The first electrode 21 of the second transistor T2 is located in the third conductive layer M3, and the first electrode 21 of the second transistor T2 penetrates the first insulating layer ILD1 and the gate insulating layer GI and is electrically connected to the first end of the second channel PSI2; preferably, the first electrode 21 of the second transistor T2 is connected to the data voltage signal Vdata; preferably, the second electrode 22 of the second transistor T2 is located in the third conductive layer M3, and the second electrode 22 of the second transistor T2 penetrates the first insulating layer ILD1 and the gate insulating layer GI and is electrically connected to the second end of the second channel PSI2; preferably, the common electrode 301 penetrates the third insulating layer ILD3 and the second insulating layer ILD2 and is electrically connected to the second electrode 22 of the second transistor T2.

[0046] Specifically, the third conductive layer M3 is also provided with a first electrode 21 and a second electrode 22 of the second transistor T2. Vias are provided on the first insulating layer ILD1 and the gate insulating layer GI, so that the first electrode 21 of the second transistor T2 penetrates the first insulating layer ILD1 and the gate insulating layer GI to be electrically connected to the first end of the first channel PSI1, and the second electrode 22 of the second transistor T2 penetrates the first insulating layer ILD1 and the gate insulating layer GI to be electrically connected to the second end of the second channel PSI2, thereby realizing the flow path of the current in the second channel PSI2. The first electrode 21 of the second transistor T2 is connected to the data voltage signal Vdata. When the second scanning signal line activates the second transistor T2, the second transistor T2 writes the data voltage signal Vdata into the pixel circuit, thereby adjusting the voltage or current of the pixel. Vias are provided on the third insulating layer ILD3 and the second insulating layer ILD2, so that the common electrode plate 301 penetrates the third insulating layer ILD3 and the second insulating layer ILD2 and is electrically connected to the second electrode 22 of the second transistor T2, so as to realize the electrical connection between the second transistor T2 and the first capacitor C1 and the electrical connection between the second transistor T2 and the second capacitor C2. Such a setting has the advantage that after the second capacitor C2 and the second transistor T2 are stacked, the connection structure between the second electrode 22 of the second transistor T2 and the common electrode plate 301 is optimized through the setting of multiple insulating layers, which is conducive to further improving the pixel arrangement density and the resolution of the display panel.

[0047] In one embodiment, at least one transistor 102 further includes a third transistor T3, the third transistor T3 includes a third channel and a third gate, the third channel is located in the active layer PSI, the third gate is located in the fourth conductive layer M4, the third gate covers the third channel in the positive projection of the active layer PSI, and the second end of the third channel is electrically connected to the second end of the first channel PSI1 through the active layer PSI; preferably, the positive projection of the third channel on the substrate 100 is at least partially located within the positive projection of the common electrode plate 301 on the substrate 100; preferably, the first end of the third channel is electrically connected to the first electrode plate 101; preferably, the first electrode of the third transistor T3 is located in the third conductive layer M3, the first electrode plate 101 penetrates the second insulating layer ILD2 and is electrically connected to the first electrode of the third transistor T3, and the first electrode of the third transistor T3 penetrates the first insulating layer ILD1 and the gate insulating layer GI and is electrically connected to the first end of the third channel; preferably, the array substrate further includes a first scanning signal line, and the third gate is located on the first scanning signal line; preferably, the third transistor T3 is a threshold compensation transistor

[0048] Specifically, a third channel of a third transistor T3 is also provided on the active layer PSI. A third gate of the third transistor T3 is also provided on the fourth conductive layer M4. The third gate covers the third channel in the positive projection of the active layer PSI, and the third gate controls the flow of charge in the third channel through an electric field. When a voltage is applied to the third gate, the third channel allows current to flow between the source and the drain of the third transistor T3. The second end of the third channel and the second end of the first channel PSI1 are connected together through a portion of the active layer PSI therebetween.

[0049] The third conductive layer M3 is also provided with a first electrode and a second electrode of the third transistor T3. Vias are provided on the first insulating layer ILD1 and the gate insulating layer GI, so that the first electrode of the third transistor T3 passes through the first insulating layer ILD1 and the gate insulating layer GI and is electrically connected to the first end of the third channel, completing the flow path of the current in the third channel. A via is provided on the second insulating layer ILD2, so that the first electrode plate 101 passes through the second insulating layer ILD2 and is electrically connected to the first electrode of the third transistor T3, so that the third transistor T3 and the first capacitor C1 are electrically connected, and the voltage of the first electrode plate 101 can be input into the first electrode of the third transistor T3. The advantage of such a setting is that after the capacitor and the third transistor T3 are stacked, the connection structure between the first electrode of the third transistor T3 and the first electrode plate 101 is optimized through the setting of multiple insulating layers, which is conducive to further improving the pixel arrangement density and the resolution of the display panel.

[0050] The array substrate further includes a first scanning signal line, which is used to activate the third transistor T3. The third transistor T3 is used as a threshold compensation transistor. When the first scanning signal line activates the third transistor T3, the third transistor T3 is turned on to compensate for the threshold voltages of other transistors in the pixel circuit, thereby reducing the brightness difference between pixels and improving the uniformity of the entire display panel.

[0051] The orthographic projection of the third channel on the substrate 100 is at least partially located within the orthographic projection of the common electrode plate 301 on the substrate 100, realizing a stacked arrangement structure of the third transistor T3 and the capacitor, which is beneficial in further improving the resolution of the display device.

[0052] The embodiment of the present application preferably uses a 3T2C pixel circuit to illustrate the technical solution provided by the present application. Of course, the array substrate provided by the embodiment of the present application includes but is not limited to the 3T2C pixel circuit.

[0053] Figure 4 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present application, such as Figure 4As shown, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a second capacitor C2. Related technology In order to achieve high resolution, the parameters of the 3T2C pixel circuit are designed as follows: the size of the first transistor T1 is 2 / 8um, the size of the second transistor T2 is 2um, the size of the third transistor T3 is 1.5um, the minimum capacity of the first capacitor C1 is 30f, and the minimum capacity of the second capacitor C2 is 40f. The area of ​​the first capacitor C1 is 61um 2 , the area of ​​the second capacitor C2 is 82um 2 . For example, in a sub-pixel rendering (SPR) structure, a pixel includes two sub-pixels, and the aspect ratio of each sub-pixel is 2:1. In this way, the length of each pixel is 31.7um, and the width of each pixel is 15.85um. The size of each pixel is 1004.89um 2 , the size of each sub-pixel is 502.445um 2 By adopting the above parameter design scheme, the resolution of the existing display panel can reach 800PPI. In the embodiment of the present application, by stacking the capacitor in the pixel circuit with at least one transistor 102, the size of each pixel can be compressed to 645.16um when the same parameter design scheme and process capability as the prior art are adopted. 2 , the size of each sub-pixel can be compressed to 322.58um 2 , the resolution of the display panel can reach 1000PPI, further improving the resolution.

[0054] Figure 5 FIG. 1 is a schematic diagram of a pixel circuit structure provided by another embodiment of the present application. Figure 5 As shown, on the basis of the above embodiment, the pixel circuit also includes a light-emitting device OLED. The first end of the first transistor T1 and the first end of the second capacitor C2 are electrically connected to the first power signal VDD, the second end of the first transistor T1 and the second end of the third transistor T3 are connected to the first end of the light-emitting device OLED at the first node Anode, and the control end of the first transistor T1 and the first end of the third transistor T3 are connected to the first end of the first capacitor C1 at the second node DTFT-G. The second end of the first capacitor C1 and the second end of the second capacitor C2 are connected to the second end of the second transistor T2 at the third node N1. The control end of the third transistor T3 is connected to the first scan signal S1. The first end of the second transistor T2 is connected to the data voltage signal Vdata, and the control end of the second transistor T2 is connected to the second scan signal S2. The second end of the light-emitting device OLED is electrically connected to the second power terminal VSS.

[0055] Figure 6A schematic layout diagram of an array substrate provided in one embodiment of the present application, Figure 7 This is a schematic layout diagram of an array substrate provided in another embodiment of the present application. Figure 6 FIG. 1 shows the layout of the layer where the first transistor T1, the second transistor T2 and the third transistor T3 are located. Figure 7 The figure shows the layout of the layer where the first capacitor C1 and the second capacitor C2 are located. Figure 6 and Figure 7 Vias are provided at the first node Anode, the second node DTFT-G and the third node N1 shown in the figure, so that the first transistor T1, the second transistor T2 and the third transistor T3 can be connected to the first capacitor C1 and the second capacitor C2 respectively.

[0056] Figure 8 FIG. 1 is a schematic diagram of a method for preparing an array substrate according to an embodiment of the present application. The method can be applied to the case of preparing an array substrate. Figure 8 As shown, the method includes:

[0057] S110, preparing at least one transistor on a substrate.

[0058] Specifically, Fig. 9 FIG. 1 is a schematic diagram of a process for preparing an array substrate provided by an embodiment of the present application. Fig. 9 , an array substrate is formed layer by layer through a photolithography mask process. Fig.10 FIG. 1 is a schematic diagram of the structure of an array substrate provided in another embodiment of the present application. Fig. 9 and Fig.10 , before preparing at least one transistor 102 on the substrate 100, it also includes sequentially preparing a first inorganic layer SI1 and a second inorganic layer SI2 on the substrate 100 to isolate water and oxygen. On the side of the second inorganic layer SI2 away from the substrate 100, an active layer PSI, a gate insulating layer GI, a fourth conductive layer M4, a first insulating layer ILD1 and a third conductive layer M3 are sequentially prepared to form at least one transistor 102 structure together. The gate insulating layer GI and the first insulating layer ILD1 are both provided with a plurality of vias, and the signal lines arranged on each conductive layer are routed through a plurality of vias to facilitate the formation of a circuit connection structure. The third conductive layer M3 and the fourth conductive layer M4 include metal materials and can be made by physical vapor deposition. Exemplarily, the metal material may include molybdenum, tungsten, titanium or an alloy thereof. The materials of the first inorganic layer SI1, the second inorganic layer SI2, the gate insulating layer GI and the first insulating layer ILD1 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride and their stacks, which may be realized by a chemical vapor deposition process.

[0059] S120, preparing a second conductive layer on a side of at least one transistor facing away from the substrate, and preparing a first electrode plate and a second electrode plate spaced apart from each other on the second conductive layer.

[0060] Specifically, see Fig. 9 and Fig.10 , before preparing the second conductive layer M2 on the side of at least one transistor 102 facing away from the substrate 100, it also includes preparing a second insulating layer ILD2 on the substrate 100. The second conductive layer M2 is prepared on the side of the second insulating layer ILD2 facing away from the substrate 100. A plurality of vias are formed on the second insulating layer ILD2, and the signal lines arranged on each conductive layer are routed through the plurality of vias. The second conductive layer M2 includes a metal material and can be manufactured by physical vapor deposition. Exemplarily, the metal material may include molybdenum, tungsten, titanium or an alloy thereof. The material of the second insulating layer ILD2 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride and their stacks, which may be implemented by a chemical vapor deposition process.

[0061] S130, prepare a first conductive layer on the side of the second conductive layer facing away from the substrate, and prepare a common electrode plate on the first conductive layer; wherein the first electrode plate and the common electrode plate constitute a first capacitor, the second electrode plate and the common electrode plate constitute a second capacitor, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate are both at least partially located within the orthographic projection of the common electrode plate on the substrate, and the orthographic projection of the transistor on the substrate is at least partially located within the orthographic projection of the common electrode plate on the substrate.

[0062] Specifically, see Fig. 9 and Fig.10 , before preparing the first conductive layer M1 on the side of the second conductive layer M2 facing away from the substrate 100, it also includes preparing a third insulating layer ILD3 on the substrate 100. The first conductive layer M1 is prepared on the side of the third insulating layer ILD3 facing away from the substrate 100. A plurality of vias are opened on the third insulating layer ILD3, and the signal lines arranged on each conductive layer are routed through the plurality of vias. The first conductive layer M2 includes a metal material and can be manufactured by physical vapor deposition. Exemplarily, the metal material may include molybdenum, tungsten, titanium or an alloy thereof. The material of the third insulating layer ILD3 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride and their stacks, which may be realized by a chemical vapor deposition process.

[0063] Furthermore, after the first conductive layer M1 is prepared on the side of the second conductive layer M2 facing away from the substrate 100 , a planarization layer PIN, an anode Anode1, a pixel definition layer PDL and a support layer SPC are sequentially prepared on the side of the first conductive layer M1 facing away from the substrate.

[0064] The preparation method provided in this embodiment prepares at least one transistor on a substrate, and then sequentially prepares a second conductive layer and a first conductive layer on the side of at least one transistor away from the substrate, so as to form a common electrode plate, a first electrode plate and a second electrode plate, thereby realizing a stacked arrangement of capacitors and transistors. In this way, when the space occupied by the transistor is constant, compared with the prior art, the area of ​​the first capacitor and the second capacitor is increased to meet the high-resolution requirements, so that the pixel size meets the high-resolution requirements, further improves the pixel arrangement density, is conducive to improving the resolution of the display panel, and is conducive to the application of display devices in the AR / VR field.

[0065] The embodiment of the present application further provides a display panel, which includes the array substrate mentioned in the above embodiment. The technical principles and effects produced are similar and will not be described in detail here.

[0066] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer, located on one side of the substrate; a second conductive layer, located between the first conductive layer and the substrate; A first capacitor, the first capacitor comprising a first electrode plate, the first electrode plate being located in the second conductive layer; a second capacitor, wherein the second capacitor comprises a second electrode plate, the second electrode plate is located in the second conductive layer, the first capacitor and the second capacitor comprise a common electrode plate, the common electrode plate is located in the first conductive layer, the first electrode plate and the second electrode plate are spaced apart, and an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the second electrode plate on the substrate are at least partially located within an orthographic projection of the common electrode plate on the substrate; as well as At least one transistor is located between the first conductive layer and the substrate, and an orthographic projection of the at least one transistor on the substrate is at least partially located within an orthographic projection of the common electrode plate on the substrate.

2. The array substrate according to claim 1, characterized in that: Also includes: an active layer, located between the second conductive layer and the substrate; a fourth conductive layer, located between the active layer and the second conductive layer; The at least one transistor includes a first transistor, the first transistor includes a first channel and a first gate, the first channel is located in the active layer, the first gate is located in the fourth conductive layer, the orthographic projection of the first gate on the active layer covers the first channel, and the first gate is electrically connected to the first plate of the first capacitor; Preferably, the orthographic projection of the first grid electrode on the substrate is at least partially located within the orthographic projection of the first electrode plate on the substrate.

3. The array substrate according to claim 2, characterized in that: Also includes: a third conductive layer, the third conductive layer being located between the fourth conductive layer and the second conductive layer; a first connecting portion, located in the third conductive layer, wherein the first grid is electrically connected to the first electrode plate through the first connecting portion; Preferably, a second insulating layer is provided between the second conductive layer and the third conductive layer, a first insulating layer is provided between the third conductive layer and the fourth conductive layer, the first electrode plate penetrates through the second insulating layer and is connected to the first connecting portion, and the first connecting portion penetrates through the first insulating layer and is connected to the first gate; Preferably, the first transistor is a driving transistor.

4. The array substrate according to claim 3, characterized in that: It also includes an anode located on a side of the first conductive layer away from the substrate, a first electrode of the first transistor located on the third conductive layer, a second electrode plate penetrating through the second insulating layer and connected to the first electrode of the first transistor, and the first electrode of the first transistor is electrically connected to a first end of the first channel; Preferably, the second electrode plate is connected to a first power supply signal; Preferably, the second electrode of the first transistor is located in the third conductive layer, the second electrode of the first transistor is electrically connected to the second end of the first channel, and the second electrode of the first transistor is connected to the anode.

5. The array substrate according to claim 4, characterized in that: A gate insulating layer is provided between the fourth conductive layer and the active layer, a first electrode of the first transistor penetrates the first insulating layer and the gate insulating layer and is electrically connected to a first end of the first channel, and a second electrode of the first transistor penetrates the first insulating layer and the gate insulating layer and is electrically connected to a second end of the first channel; Preferably, the array substrate also includes a second connecting portion, which is located in the first conductive layer, the second connecting portion is connected to the anode, a third insulating layer is provided between the first conductive layer and the second conductive layer, and the second connecting portion passes through the third insulating layer and the second insulating layer and is connected to the second electrode of the first transistor.

6. The array substrate according to claim 5, characterized in that: The at least one transistor further includes a second transistor, the second transistor includes a second channel and a second gate, the second channel is located in the active layer, the second gate is located in the fourth conductive layer, and the orthographic projection of the second gate on the active layer covers the second channel; Preferably, the orthographic projection of the second grid on the substrate is at least partially located within the orthographic projection of the second electrode plate on the substrate; Preferably, the orthographic projection of the second channel on the substrate is at least partially located within the orthographic projection of the common electrode plate on the substrate; Preferably, the array substrate further comprises a second scanning signal line, and the second gate is located on the second scanning signal line; Preferably, the second transistor is a data writing transistor.

7. The array substrate according to claim 6, characterized in that: The first electrode of the second transistor is located in the third conductive layer, and the first electrode of the second transistor passes through the first insulating layer and the gate insulating layer and is electrically connected to the first end of the second channel; Preferably, the first electrode of the second transistor is connected to a data voltage signal; Preferably, the second electrode of the second transistor is located in the third conductive layer, and the second electrode of the second transistor penetrates the first insulating layer and the gate insulating layer and is electrically connected to the second end of the second channel; Preferably, the common electrode plate passes through the third insulating layer and the second insulating layer and is electrically connected to the second electrode of the second transistor.

8. The array substrate according to claim 7, characterized in that: The at least one transistor further includes a third transistor, the third transistor including a third channel and a third gate, the third channel is located in the active layer, the third gate is located in the fourth conductive layer, the orthographic projection of the third gate on the active layer covers the third channel, and the second end of the third channel is electrically connected to the second end of the first channel through the active layer; Preferably, the orthographic projection of the third channel on the substrate is at least partially located within the orthographic projection of the common electrode on the substrate; Preferably, the first end of the third channel is electrically connected to the first electrode plate; Preferably, the first electrode of the third transistor is located in the third conductive layer, the first electrode plate penetrates the second insulating layer and is electrically connected to the first electrode of the third transistor, and the first electrode of the third transistor penetrates the first insulating layer and the gate insulating layer and is electrically connected to the first end of the third channel; Preferably, the array substrate further comprises a first scanning signal line, and the third gate is located on the first scanning signal line; Preferably, the third transistor is a threshold compensation transistor.

9. A method for preparing an array substrate, characterized in that: include: fabricating at least one transistor on a substrate; A second conductive layer is prepared on a side of the at least one transistor away from the substrate, and a first electrode plate and a second electrode plate are prepared on the second conductive layer. A first conductive layer is prepared on the side of the second conductive layer facing away from the substrate, and a common electrode plate is prepared on the first conductive layer; wherein the first electrode plate and the common electrode plate constitute a first capacitor, the second electrode plate and the common electrode plate constitute a second capacitor, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate are both at least partially located within the orthographic projection of the common electrode plate on the substrate, and the orthographic projection of the transistor on the substrate is at least partially located within the orthographic projection of the common electrode plate on the substrate.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 8.

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