Display panel and electronic equipment

Abstract

The invention provides a display panel and electronic equipment, and relates to the technical field of display panels, the display panel comprises a substrate, an array function layer located on one side of the substrate and a light-emitting function layer located on the side, away from the substrate, of the array function layer, the array function layer comprises a plurality of pixel circuits, and the light-emitting function layer comprises a plurality of light-emitting devices. The pixel circuits are electrically connected with the corresponding light-emitting devices, and the array function layer comprises a first active layer, a first conductive layer, a second conductive layer and a gate layer which are arranged in a stacked mode in the direction away from the substrate. And at least part of wires in the gate layer are electrically connected with at least part of wires in the first active layer and / or the first conductive layer and / or the second conductive layer through the first via holes. According to the display panel, direct connection between at least part of wires in the gate layer and at least part of wires in the first active layer and / or the first conductive layer and / or the second conductive layer can be achieved through the first via holes, the technological process can be simplified, the wiring space can be saved, and the display effect of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] In order to overcome the above-mentioned deficiencies in the prior art, the object of the present application is to provide a display panel, the display panel comprising:

[0005] substrate;

[0006] An array function layer located on one side of the substrate, the array function layer comprising a plurality of pixel circuits;

[0007] A light-emitting functional layer located on a side of the array functional layer away from the substrate, the light-emitting functional layer comprising a plurality of light-emitting devices, the pixel circuit being electrically connected to the corresponding light-emitting devices;

[0008] The array functional layer includes a first active layer, a first conductive layer, a second conductive layer and a gate layer stacked in a direction away from the substrate;

[0009] At least part of the routing lines in the gate layer include a via region, and an orthographic projection of the via region on the substrate at least partially overlaps with an orthographic projection of at least part of the routing lines in the first active layer and / or the first conductive layer and / or the second conductive layer on the substrate; at least part of the routing lines in the gate layer are electrically connected to at least part of the routing lines in the first active layer and / or the first conductive layer and / or the second conductive layer through a first via, and an orthographic projection of the first via on the substrate is located within an orthographic projection of the via region on the substrate;

[0010] At least part of the switching devices in the pixel circuit is composed of at least part of the wiring located in the gate layer, the first active layer and / or the first conductive layer and / or the second conductive layer.

[0011] In a possible implementation, the display panel further includes a first initialization voltage wiring;

[0012] The first initialization voltage wiring is located at the gate layer;

[0013] The pixel circuit includes a first reset transistor; the first reset transistor includes a first semiconductor routing segment located in the first active layer and a first metal routing segment located in the first conductive layer, and an orthographic projection of the first semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the first metal routing segment on the substrate;

[0014] The source of the first reset transistor located in the first active layer and the first initialization voltage wiring located in the gate layer are connected through at least one of the first vias;

[0015] Preferably, the first conductive layer includes a first scanning signal routing, the first reset transistor includes a first semiconductor routing segment and the first scanning signal routing located in the first active layer, and the orthographic projection of the first semiconductor routing segment on the substrate at least partially overlaps with the orthographic projection of the first scanning signal routing on the substrate.

[0016] In a possible implementation, the pixel circuit further includes a driving transistor; the driving transistor includes a second semiconductor routing segment located in the first active layer and a second metal routing segment located in the first conductive layer, and an orthographic projection of the second semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the second metal routing segment on the substrate;

[0017] The drain of the first reset transistor located in the first active layer and the first end of the first connecting wire located in the gate layer are connected through at least one of the first via holes;

[0018] The drain of the driving transistor located in the first active layer and the second end of the first connecting wire located in the gate layer are connected through at least one of the first via holes;

[0019] Preferably, the first reset transistor includes a first sub-transistor and a second sub-transistor;

[0020] The source of the first sub-transistor located in the first active layer and the first initialization voltage wiring located in the gate layer are connected through at least one of the first vias;

[0021] The drain of the first sub-transistor is connected to the source of the second sub-transistor;

[0022] The drain of the second sub-transistor located in the first active layer and the first end of the first connecting wire located in the gate layer are connected through at least one of the first via holes.

[0023] In a possible implementation, the pixel circuit further includes a connection point connected to the light-emitting device, and the display panel further includes a second initialization voltage wiring;

[0024] The second initialization voltage wiring is located at the gate layer;

[0025] The pixel circuit further includes a second reset transistor, the second reset transistor including a third semiconductor routing segment located in the first active layer and a third metal routing segment located in the first conductive layer, an orthographic projection of the third semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the third metal routing segment on the substrate;

[0026] The source of the second reset transistor located in the first active layer and the second initialization voltage wiring located in the gate layer are connected through at least one of the first vias;

[0027] Preferably, the second reset transistor comprises a third semiconductor routing segment and the first scanning signal routing segment located in the first active layer; an orthographic projection of the third semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the first scanning signal routing segment on the substrate;

[0028] Preferably, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor, and the display panel further includes a first power supply line; the source of the driving transistor is connected to the first power supply line through the first light emission control transistor, and the drain of the driving transistor is also connected to the anode of the light emitting device through the second light emission control transistor;

[0029] The connection point is connected to the second initialization voltage wiring via the second reset transistor.

[0030] In a possible implementation, the first semiconductor routing segment includes a first portion extending along a first direction and a second portion extending along a second direction, the first metal routing segment includes a third portion extending along the first direction and a fourth portion extending along the second direction, and the first direction is perpendicular to the second direction;

[0031] The first sub-transistor includes a first portion of the first semiconductor routing segment and a fourth portion of the first metal routing segment, and an orthographic projection of the first portion of the first semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the fourth portion of the first metal routing segment on the substrate;

[0032] The second sub-transistor includes a second portion of the first semiconductor routing segment and a third portion of the first metal routing segment, and an orthographic projection of the second portion of the first semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the third portion of the first metal routing segment on the substrate.

[0033] In a possible implementation, the array function layer further includes a second active layer; the pixel circuit further includes a compensation transistor and a storage capacitor;

[0034] The compensation transistor comprises a fourth metal routing segment located in the first conductive layer or the second conductive layer, a fourth semiconductor routing segment located in the second active layer, and a second connecting routing segment located in the gate layer; the orthographic projection of the fourth metal routing segment on the substrate, the orthographic projection of the fourth semiconductor routing segment on the substrate, and the orthographic projection of the second connecting routing on the substrate at least partially overlap;

[0035] The fourth metal routing segment and the second connecting routing are connected through at least one of the first vias;

[0036] Preferably, the display panel further includes a second scanning signal wiring;

[0037] The second scan signal routing line includes the fourth metal routing line segment, or the second scan signal routing line includes the second connecting routing line;

[0038] Preferably, the first electrode of the compensation transistor is connected to the drain of the driving transistor, the second electrode of the compensation transistor is connected to the first power supply line through the storage capacitor, the first electrode of the compensation transistor is one of the source and the drain, and the second electrode of the compensation transistor is the other of the source and the drain.

[0039] In a possible implementation manner, the pixel circuit further includes a third reset transistor;

[0040] The third reset transistor includes a fifth metal routing segment located in the first conductive layer or the second conductive layer, a fifth semiconductor routing segment located in the second active layer, and a third connecting routing segment located in the gate layer; the orthographic projection of the five metal routing segments on the substrate, the orthographic projection of the fifth semiconductor routing segment on the substrate, and the orthographic projection of the third connecting routing segment on the substrate at least partially overlap;

[0041] The fifth metal routing segment and the third connecting routing are connected through at least one of the first vias;

[0042] Preferably, the display panel further includes a third scanning signal wiring;

[0043] The third scan signal routing line includes the fifth metal routing line segment, or the second scan signal routing line includes the second connection routing line;

[0044] Preferably, the display panel also includes a third initialization voltage routing; the first electrode of the third reset transistor is connected to the third initialization voltage routing, the second electrode of the third reset transistor is connected to the first power routing via the compensation transistor and the storage capacitor in sequence, the first electrode of the third reset transistor is one of the source and the drain, and the second electrode of the third reset transistor is the other of the source and the drain.

[0045] In a possible implementation, the pixel circuit further includes a data writing transistor and a storage capacitor;

[0046] The display panel also includes data signal routing;

[0047] The first electrode of the data writing transistor is connected to the data signal wiring, the second electrode of the data writing transistor is connected to the source electrode of the driving transistor, the first electrode of the data writing transistor is one of the source and the drain, and the second electrode of the data writing transistor is the other of the source and the drain;

[0048] Preferably, the data writing transistor comprises a sixth semiconductor routing segment located in the first active layer and a sixth metal routing segment located in the first conductive layer; the orthographic projection of the sixth semiconductor routing segment on the substrate at least partially overlaps with the orthographic projection of the sixth metal routing segment on the substrate; the storage capacitor comprises a seventh metal routing segment located in the first conductive layer and an eighth metal routing segment located in the second conductive layer; the orthographic projection of the seventh metal routing segment on the substrate at least partially overlaps with the orthographic projection of the eighth metal routing segment on the substrate;

[0049] Preferably, the first conductive layer also includes a fourth scanning signal routing, and the data writing transistor includes a sixth semiconductor routing segment and a fourth scanning signal routing located in the first active layer; the orthographic projection of the sixth semiconductor routing segment on the substrate at least partially overlaps with the orthographic projection of the fourth scanning signal routing on the substrate.

[0050] In a possible implementation, the display panel further includes a third conductive layer; the display panel further includes a third initialization voltage wiring;

[0051] The third initialization voltage wiring is located in the third conductive layer;

[0052] The first initialization voltage wiring, the second initialization voltage wiring and the third initialization voltage wiring have the same extension direction;

[0053] The display panel further includes a fourth conductive layer; the display panel further includes a fourth initialization voltage wiring;

[0054] The fourth initialization voltage wiring is located in the fourth conductive layer;

[0055] The extension direction of the fourth initialization voltage line intersects with the extension directions of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line; the fourth initialization voltage line is used to provide the first initialization signal, the second initialization signal or the third initialization signal.

[0056] Another object of the present application is to provide an electronic device, which includes the display panel provided in the present application.

[0057] Compared with the prior art, this application has the following beneficial effects:

[0058] The embodiments of the present application provide a display panel and an electronic device, in which at least part of the wiring in the gate layer can be directly connected to at least part of the wiring in the first active layer and / or the first conductive layer and / or the second conductive layer through a first via hole, without setting an additional metal layer, thereby simplifying the process flow, saving wiring space, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0061] Figure 2 A partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0062] Figure 3 is a partial cross-sectional schematic diagram of a display panel in the prior art;

[0063] Figure 4 A schematic diagram of the structure of the gate layer provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0065] Figure 6 A schematic diagram of the structure of the first active layer provided in an embodiment of the present application;

[0066] Figure 7 A schematic diagram of the structure of the first conductive layer provided in an embodiment of the present application;

[0067] Figure 8 A schematic diagram of the structure of the second conductive layer provided in an embodiment of the present application;

[0068] Fig. 9 A schematic diagram of the structure of the second active layer provided in an embodiment of the present application;

[0069] Fig.10 A schematic diagram of the structure of the third conductive layer provided in an embodiment of the present application;

[0070] Fig.11 A schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present application;

[0071] Fig.12 A schematic diagram of the distribution of the initialization voltage routing provided in an embodiment of the present application;

[0072] Fig.13 A schematic diagram of the structure of the third conductive layer and the fourth conductive layer provided in an embodiment of the present application.

[0073] Icons: 100', 100-first active layer; 101-first semiconductor routing segment; 101a-first part; 101b-second part; 102-second semiconductor routing segment; 103-third semiconductor routing segment; 104-sixth semiconductor routing segment; 200', 200-first conductive layer; 201-first metal routing segment; 201a-third part; 201b-fourth part; 202-second metal routing segment; 203-third metal routing Segment; 204-fifth metal routing segment; 205-sixth metal routing segment; 210-first scan signal routing; 220-light-emitting control signal routing; 230-third scan signal routing; 240-fourth scan signal routing; 300', 300-second conductive layer; 301-fourth metal routing segment; 400-second active layer; 401-fourth semiconductor routing segment; 402-fifth semiconductor routing segment; 500', 500-gate layer; 501-first Via hole; 502-first connecting line; 503-second connecting line; 504-third connecting line; 510-first initialization voltage line; 520-second initialization voltage line; 530-second scanning signal line; 600-pixel circuit; 610-first reset transistor; 611-first sub-transistor; 612-second sub-transistor; 620-driving transistor; 630-second reset transistor; 640-first light-emitting control transistor; 650-second light-emitting control transistor; 660-compensation transistor; 670-third reset transistor; 680-data writing transistor; 700', 700-third conductive layer; 701'-second via hole; 702'-third via hole; 710-third initialization voltage line; 720-first connecting line; 800-fourth conductive layer; 810-first power supply line; 820-data signal line; 830-fourth initialization voltage line; 840-second connecting line. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0075] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0076] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0077] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0078] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0079] The inventors have found that, in order to achieve a narrow frame, the fan-out lines located in the fan-out area of ​​the display panel can be laid out to the display area, and the fan-out lines are routed from the display area and led out to the fan-out area. This fan-out method is called FIAA fan-out. However, the display panel manufacturing process using this fan-out method is relatively complicated, and multiple metal layers are usually set on the display panel. In addition, the resolution of the display panel using this fan-out method is relatively low, and the pixel density (Pixels Per Inch, PPI) is only 460.

[0080] In view of this, this embodiment provides a solution that can solve the above-mentioned problem, and the solution provided by this embodiment is described in detail below.

[0081] Please refer to Figure 1 , Figure 1 The structural schematic diagram of the display panel provided in the present embodiment is shown as an example. The display panel may include a substrate, an array function layer located on one side of the substrate, and a light-emitting function layer located on a side of the array function layer away from the substrate, the array function layer may include a plurality of pixel circuits 600, the light-emitting function layer may include a plurality of light-emitting devices EL, and the plurality of pixel circuits 600 may be electrically connected to corresponding light-emitting devices EL, respectively.

[0082] The array functional layer may further include a first active layer 100, a first insulating layer, a first conductive layer 200, a second insulating layer, a second conductive layer 300, a third insulating layer, a second active layer 400, a fourth insulating layer and a gate layer 500 stacked in a direction away from the substrate.

[0083] Optionally, the material of the first active layer 100 and the second active layer 400 may be polysilicon, the material of the first conductive layer 200 and the second conductive layer 300 may be metal, for example, molybdenum, the material of the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be silicon oxide and / or silicon nitride, etc., and the material of the gate layer 500 may be metal, for example, molybdenum or titanium.

[0084] At least part of the routing in the gate layer may include a via area, the orthographic projection of the via area on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and / or the orthographic projection of the via area on the substrate at least partially overlaps with the orthographic projection of the first conductive layer on the substrate, and / or the orthographic projection of the via area on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate.

[0085] Please refer to Figure 2 , at least part of the wiring in the gate layer 500 can be connected to at least part of the wiring in the first active layer 100 and / or the first conductive layer 200 and / or the second conductive layer 300 through the first via 501. The orthographic projection of the first via on the substrate can be located within the orthographic projection of the via region on the substrate. The first via 501 can penetrate the fourth insulating layer, and the first via 501 can also penetrate at least one of the third insulating layer, the second insulating layer and the first insulating layer.

[0086] In this embodiment, the display panel may include multiple first vias 501, which can be used to connect the gate layer 500 to the first active layer 100, to connect the gate layer 500 to the first conductive layer 200, and to connect the gate layer 500 to the second conductive layer 300.

[0087] In the prior art, please refer to Figure 3 When at least part of the wiring in the gate layer 500' is connected to at least part of the wiring in the first active layer 100' and / or the first conductive layer 200' and / or the second conductive layer 300', it is necessary to achieve this through the third conductive layer 700' located on the side of the gate layer 500' away from the substrate. For example, when at least part of the wiring in the gate layer 500' is connected to at least part of the wiring in the first active layer 100', the gate layer 500' can be first connected to the third conductive layer 700' through the second via 701', and then the third conductive layer 700' can be connected to the first active layer 100' through the third via 702'. In this way, at least part of the wiring in the gate layer 500' can be connected to at least part of the wiring in the first active layer 100'. However, this method has a complex process and a high density of metal wiring, which is easy to affect the display effect of the display panel.

[0088] Based on the above design, in the display panel provided in this embodiment, at least part of the wiring in the gate layer 500 can be directly connected to at least part of the wiring in the first active layer 100 and / or the first conductive layer 200 and / or the second conductive layer 300 through the first via 501, without setting an additional metal layer, which can simplify the process flow, save wiring space, and improve the display effect of the display panel. The resolution of the display panel can reach Quad High Definition (QHD), and the pixel density (Pixels Per Inch, PPI) can be 500.

[0089] In one possible implementation, see Figure 4 The display panel may further include a first initialization voltage line 510 extending along the first direction D1. The first initialization voltage line 510 may be used to transmit a first initialization voltage Vref3. The first initialization voltage line 510 may be located in the gate layer 500.

[0090] Please refer to Figure 5 The display panel may further include a plurality of pixel circuits 600, and the pixel circuit 600 may adopt an 8T1C circuit form.

[0091] Please refer to Figure 6 and Figure 7 The pixel circuit 600 may include a first reset transistor 610 ( T8 ), and the first reset transistor 610 ( T8 ) may be formed by overlapping a first semiconductor wiring segment 101 located in the first active layer 100 and a first metal wiring segment 201 located in the first conductive layer 200 .

[0092] The source of the first reset transistor 610 ( T8 ) may be located in the first active layer 100 , and the source of the first reset transistor 610 ( T8 ) may be connected to the first initialization voltage trace 510 located in the gate layer 500 through a first via 501 .

[0093] The first conductive layer 200 may include a first scan signal line 210 extending along the first direction D1, and the first scan signal line 210 may be used to transmit a first scan signal S4, and an orthographic projection of the first scan signal line 210 on the substrate and an orthographic projection of the first initialization voltage line 510 on the substrate at least partially overlap.

[0094] The first reset transistor 610 ( T8 ) may be formed by overlapping the first semiconductor wiring segment 101 located in the first active layer 100 and the first scan signal wiring 210 , and a gate of the first reset transistor 610 ( T8 ) may be connected to the first scan signal wiring 210 .

[0095] In one possible implementation, please refer again to Figure 6 and Figure 7 The pixel circuit 600 may further include a driving transistor 620 ( T1 ), which may be formed by overlapping a second semiconductor wiring segment 102 located in the first active layer 100 and a second metal wiring segment 202 located in the first conductive layer 200 .

[0096] The drain of the first reset transistor 610 (T8) may be located in the first active layer 100, and the drain of the driving transistor 620 (T1) may also be located in the first active layer 100. Figure 4 The drain of the first reset transistor 610 (T8) and the drain of the driving transistor 620 (T1) can be connected through a first connecting wire 502 located in the gate layer 500. Specifically, the drain of the first reset transistor 610 (T8) located in the first active layer 100 can be connected to a first end of the first connecting wire 502 located in the gate layer 500 through a first via 501, and the drain of the driving transistor 620 (T1) located in the first active layer 100 can be connected to a second end of the first connecting wire 502 located in the gate layer 500 through another first via 501.

[0097] Please refer again Figure 1 , the first reset transistor 610 ( T8 ) may include a first sub-transistor 611 and a second sub-transistor 612 .

[0098] The source of the first sub-transistor 611 can be located in the first active layer 100, and the source of the first sub-transistor 611 can be connected to the first initialization voltage wiring 510 located in the gate layer 500 through the first via 501. The drain of the first sub-transistor 611 can be connected to the source of the second sub-transistor 612, and the drain of the second sub-transistor 612 can be located in the first active layer 100. The drain of the second sub-transistor 612 can be connected to the first end of the first connecting wiring 502 located in the gate layer 500 through the first via 501.

[0099] In one possible implementation, please refer again to Figure 6 and Figure 7 The pixel circuit 600 may further include a connection point A connected to the anode of the light emitting device EL and a second reset transistor 630 (T7). The second reset transistor 630 (T7) may be formed by overlapping a third semiconductor wiring segment 103 located in the first active layer 100 and a third metal wiring segment 203 located in the first conductive layer 200.

[0100] Please refer again Figure 4The display panel may further include a second initialization voltage line 520, which is located in the gate layer 500. The second initialization voltage line 520 may be used to transmit a second initialization voltage Vref2. The second initialization voltage line 520 has the same extension direction as the first initialization voltage line 510, and the second initialization voltage line 520 also extends along the first direction D1.

[0101] The source of the second reset transistor 630 ( T7 ) is located in the first active layer 100 , and the source of the second reset transistor 630 ( T7 ) may be connected to the second initialization voltage wiring 520 through the first via 501 .

[0102] The second reset transistor 630 ( T7 ) may be formed by overlapping the third semiconductor wiring segment 103 located in the first active layer 100 and the first scan signal wiring 210 .

[0103] Please refer again Figure 5 The pixel circuit 600 may further include a first light emission control transistor 640 (T5) and a second light emission control transistor 650 (T6), and the display panel may further include a first power supply line 810, which may be used to transmit a first power supply voltage VDD.

[0104] The first light emission control transistor 640 ( T5 ) and the second light emission control transistor 650 ( T6 ) may be formed by overlapping a portion of a routing segment located in the first active layer 100 and a portion of a routing segment located in the first conductive layer 200 .

[0105] The source of the driving transistor 620 (T1) can be connected to the first power supply line 810 through the first light emission control transistor 640 (T5), and the drain of the driving transistor 620 (T1) can be connected to the connection point A through the second light emission control transistor 650 (T6). The connection point A can also be connected to the second initialization voltage line 520 through the second reset transistor 630 (T7).

[0106] The display panel may further include a second power supply line, which may be used to transmit a second power supply voltage VSS. The cathode of the light emitting device EL may be connected to the second power supply line.

[0107] The display panel may further include a light emitting control signal line 220 extending along the first direction D1. The light emitting control signal line 220 may be used to provide a light emitting control signal EM. The gate of the first light emitting control transistor 640 (T5) and the gate of the second light emitting control transistor 650 (T6) may be respectively connected to the light emitting control signal line 220.

[0108] In one possible implementation, see Figure 6 and Figure 7The first semiconductor routing segment 101 may include a first portion 101a extending along a first direction D1 and a second portion 101b extending along a second direction D2, and the first metal routing segment 201 may include a third portion 201a extending along the first direction D1 and a fourth portion 201b extending along the second direction D2, and the first direction D1 may be perpendicular to the second direction D2.

[0109] The first sub-transistor 611 may include a first portion 101a of the first semiconductor routing segment 101 and a fourth portion 201b of the first metal routing segment 201 , and an orthographic projection of the first portion 101a of the first semiconductor routing segment 101 on the substrate may at least partially overlap with an orthographic projection of the fourth portion 201b of the first metal routing segment 201 on the substrate.

[0110] The second sub-transistor 612 may include the second portion 101b of the first semiconductor routing segment 101 and the third portion 201a of the first metal routing segment 201 , and the orthographic projection of the second portion 101b of the first semiconductor routing segment 101 on the substrate may at least partially overlap with the orthographic projection of the third portion 201a of the first metal routing segment 201 on the substrate.

[0111] In one possible implementation, see Figure 4 , Figure 8 and Fig. 9 The pixel circuit 600 may further include a compensation transistor 660 (T3) and a storage capacitor (Cst). The compensation transistor 660 (T3) may include a fourth metal wiring segment 301 located in the first conductive layer 200 or the second conductive layer 300, a fourth semiconductor wiring segment 401 located in the second active layer 400, and a second connection wiring 503 located in the gate layer 500.

[0112] The compensation transistor 660 (T3) may be a dual-gate structure, wherein the fourth metal routing segment 301 located in the first conductive layer 200 or the second conductive layer 300 may form a first gate of the compensation transistor 660 (T3), and the second connecting routing segment 503 located in the gate layer 500 may form a second gate of the compensation transistor 660 (T3). The first gate located in the first conductive layer 200 or the second conductive layer 300 and the second gate located in the gate layer 500 may be connected through a first via 501. The first gate is located on the side of the fourth semiconductor routing segment 401 close to the substrate, forming the bottom gate of the compensation transistor 660 (T3); the second gate is located on the side of the fourth semiconductor routing segment 401 away from the substrate, forming the top gate of the compensation transistor 660 (T3).

[0113] The display panel may further include a second scan signal line 530, which may extend along the first direction D1 and may be used to transmit a second scan signal S3. The second scan signal line 530 may be located not only at Figure 1 The gate layer 500 shown may also be located in the first conductive layer 200 or the second conductive layer 300 .

[0114] In a first possible implementation, when the second scanning signal routing 530 is located in the gate layer 500, the first gate of the compensation transistor 660 (T3) can be formed by a fourth metal routing segment 301 located in the first conductive layer 200 or the second conductive layer 300, the fourth metal routing segment 301 can be located only at the first gate of the compensation transistor 660 (T3), and the second gate of the compensation transistor 660 (T3) can be formed by the second scanning signal routing 530 located in the gate layer 500.

[0115] In this embodiment, by arranging the second scan signal wiring 530 to be located in the gate layer 500 , the wiring spacing between the second scan signal wiring 530 and the second conductive layer 300 can be reduced, thereby saving space for metal wiring.

[0116] In a second possible implementation, when the second scanning signal line 530 is located in the first conductive layer 200, the first gate of the compensation transistor 660 (T3) can be formed by the second scanning signal line 530 located in the first conductive layer 200, and the second gate of the compensation transistor 660 (T3) can be formed by the second connecting line 503 located in the gate layer 500, and the second connecting line 503 can be located only at the second gate of the compensation transistor 660 (T3).

[0117] In this embodiment, by arranging the second scan signal wiring 530 to be located in the first conductive layer 200 , the wiring spacing between the second scan signal wiring 530 and the second conductive layer 300 can also be reduced, thereby saving space for metal wiring.

[0118] In a third possible implementation, when the second scanning signal line 530 is located in the second conductive layer 300, the first gate of the compensation transistor 660 (T3) can be formed by the second scanning signal line 530 located in the second conductive layer 300, and the second gate of the compensation transistor 660 (T3) can be formed by the second connecting line 503 located in the gate layer 500, and the second connecting line 503 can be located only at the second gate of the compensation transistor 660 (T3).

[0119] In this embodiment, the spacing between the first gate and the second gate of the compensation transistor 660 (T3) formed by the second conductive layer 300 and the gate layer 500 can be smaller than the spacing between the first gate and the second gate of the compensation transistor 660 (T3) formed by the first conductive layer 200 and the gate layer 500. By setting the second scanning signal line 530 in the second conductive layer 300, the switching efficiency of the compensation transistor 660 (T3) can be improved.

[0120] In the prior art, the second scanning signal line 530 may include two metal layers: a second conductive layer 300 and a gate layer 500, while the second scanning signal line 530 in the present application may be located on only one metal layer, which effectively reduces the number of metal lines, saves wiring space, and is less likely to cause short circuits between metal lines, thereby achieving higher resolution.

[0121] The gate of the compensation transistor 660 (T3) can be connected to the second scanning signal line 530, the first electrode of the compensation transistor 660 (T3) can be connected to the drain of the driving transistor 620 (T1), the second electrode of the compensation transistor 660 (T3) can be connected to the first power line 810 via the storage capacitor (Cst), the first electrode of the compensation transistor 660 (T3) can be one of the source and the drain, and the second electrode of the compensation transistor 660 (T3) can be the other of the source and the drain.

[0122] In one possible implementation, please refer again to Figure 4 , Figure 7 and Fig. 9 The pixel circuit 600 may further include a third reset transistor 670 (T4). The third reset transistor 670 (T4) may include a fifth metal routing segment 204 located in the first conductive layer 200 or the second conductive layer 300, a fifth semiconductor routing segment 402 located in the second active layer 400, and a third connecting routing 504 located in the gate layer 500.

[0123] The third reset transistor 670 (T4) can be a dual-gate structure, the fifth metal routing segment 204 located in the first conductive layer 200 or the second conductive layer 300 can form the third gate of the third reset transistor 670 (T4), and the second connecting routing 503 located in the gate layer 500 can form the fourth gate of the third reset transistor 670 (T4). The third gate located in the first conductive layer 200 or the second conductive layer 300 and the fourth gate located in the gate layer 500 can be connected through the first via 501. The third gate is located on the side of the fifth semiconductor routing segment 402 close to the substrate, forming the bottom gate of the third reset transistor 670 (T4); the fourth gate is located on the side of the fifth semiconductor routing segment 402 away from the substrate, forming the top gate of the third reset transistor 670 (T4).

[0124] The display panel may further include a third scan signal line 230, which may extend along the first direction D1 and may be used to transmit a third scan signal S1. The third scan signal line 230 may be located not only at Figure 1 The first conductive layer 200 shown may also be located in the second conductive layer 300 or the gate layer 500 .

[0125] In a first possible implementation, when the third scan signal routing 230 is located in the gate layer 500, the third gate of the third reset transistor 670 (T4) can be formed by the fifth metal routing segment 204 located in the first conductive layer 200 or the second conductive layer 300, the fifth metal routing segment 240 can be located only at the third gate of the third reset transistor 670 (T4), and the fourth gate of the third reset transistor 670 (T4) can be formed by the third scan signal routing 230 located in the gate layer 500.

[0126] In a second possible implementation, when the third scanning signal line 230 is located in the first conductive layer 200, the third gate of the third reset transistor 670 (T4) can be formed by the third scanning signal line 230 located in the first conductive layer 200, and the fourth gate of the third reset transistor 670 (T4) can be formed by the third connecting line 504 located in the gate layer 500, and the third connecting line 504 can be located only at the fourth gate of the third reset transistor 670 (T4).

[0127] In a third possible implementation, when the third scanning signal line 230 is located in the second conductive layer 300, the third gate of the third reset transistor 670 (T4) can be formed by the third scanning signal line 230 located in the second conductive layer 300, and the fourth gate of the third reset transistor 670 (T4) can be formed by the third connecting line 504 located in the gate layer 500, and the third connecting line 504 can be located only at the fourth gate of the third reset transistor 670 (T4).

[0128] In the above design, if the third scan signal line 230 is located in the gate layer 500 or the first conductive layer 200, the space of the metal line can be saved. If the third scan signal line 230 is located in the second conductive layer 300, the switching efficiency of the third reset transistor 670 (T4) can be improved.

[0129] In addition, in the prior art, the third scanning signal line 230 may include two metal layers: a second conductive layer 300 and a gate layer 500, while the third scanning signal line 230 in the present application may be located only on one metal layer, which effectively reduces the number of metal lines, saves wiring space, and is less likely to cause short circuits between metal lines, thereby achieving higher resolution.

[0130] The display panel may further include a third initialization voltage wiring 710 , and the third initialization voltage wiring 710 may be used to transmit a third initialization voltage Vref1 .

[0131] The gate of the third reset transistor 670 (T4) can be connected to the third scan signal wiring 230, the first electrode of the third reset transistor 670 (T4) can be connected to the third initialization voltage wiring 710, the second electrode of the third reset transistor 670 (T4) can be connected to the first power wiring 810 via the compensation transistor 660 (T3) and the storage capacitor (Cst) in sequence, the first electrode of the third reset transistor 670 (T4) can be one of the source and the drain, and the second electrode of the third reset transistor 670 (T4) can be the other of the source and the drain.

[0132] In one possible implementation, please refer again to Figure 5 , the pixel circuit 600 may further include a data writing transistor 680 (T2) and a storage capacitor (Cst).

[0133] The display panel may further include a data signal wiring 820 . The data signal wiring 820 may be used to transmit a data signal Data. The data signal wiring 820 may extend along the second direction D2 .

[0134] Please refer again Figure 1 The first conductive layer 200 may further include a fourth scan signal line 240. The first scan signal line 210, the second scan signal line 530, the third scan signal line 230 and the fourth scan signal line 240 may all extend along the first direction D1. The fourth scan signal line 240 may be used to transmit a fourth scan signal S2.

[0135] The gate of the data write transistor 680 (T2) can be connected to the fourth scanning signal line 240, the first electrode of the data write transistor 680 (T2) can be connected to the data signal line 820, the second electrode of the data write transistor 680 (T2) can be connected to the source of the driving transistor 620 (T1), the first electrode of the data write transistor 680 (T2) can be one of the source and the drain, and the second electrode of the data write transistor 680 (T2) can be the other of the source and the drain.

[0136] One end of the storage capacitor (Cst) can be connected to the first power line 810, the other end of the storage capacitor (Cst) can be connected to the compensation transistor 660 (T3), and the other end of the storage capacitor (Cst) can also be connected to the gate of the driving transistor 620 (T1).

[0137] Please refer to Figure 6 and Figure 7The data writing transistor 680 (T2) may be formed by overlapping the sixth semiconductor routing segment 104 located in the first active layer 100 and the sixth metal routing segment 205 located in the first conductive layer 200. The storage capacitor (Cst) may be formed by overlapping a portion of the metal routing segment located in the first conductive layer 200 and a portion of the metal routing segment located in the second conductive layer 300.

[0138] Specifically, the data writing transistor 680 ( T2 ) may be formed by overlapping the sixth semiconductor wiring segment 104 and the fourth scanning signal wiring 240 located in the first active layer 100 .

[0139] In one possible implementation, see Fig.10 The display panel may further include a third conductive layer 700 , and the third conductive layer 700 may be located on a side of the gate layer 500 away from the substrate, wherein the material of the third conductive layer 700 may be titanium-aluminum-titanium.

[0140] The display panel may further include a third initialization voltage line 710 located in the third conductive layer 700, the first initialization voltage line 510 and the second initialization voltage line 520 are both located in the gate layer 500, the first initialization voltage line 510, the second initialization voltage line 520 and the third initialization voltage line 710 have the same extension direction, and the first initialization voltage line 510, the second initialization voltage line 520 and the third initialization voltage line 710 all extend along the first direction D1.

[0141] In one possible implementation, see Fig.11 The display panel may further include a fourth conductive layer 800, which may be located on a side of the third conductive layer 700 away from the substrate, wherein the material of the fourth conductive layer 800 may be the same as that of the third conductive layer 700, both being titanium-aluminum-titanium (Ti-Al-Ti).

[0142] The display panel may further include a plurality of fourth initialization voltage lines 830, which may be used to provide the first initialization signal, the second initialization signal, or the third initialization signal, respectively. The plurality of fourth initialization voltage lines 830 may be arranged along the first direction D1, and the plurality of fourth initialization voltage lines 830 may extend along the second direction D2, and the second direction D2 may be perpendicular to the first direction D1.

[0143] Please refer to Fig.12In the first direction D1, the fourth initialization voltage routing 830 for providing a third initialization signal Vref1, for providing a second initialization signal Vref2, and for providing a first initialization signal Vref3 are arranged in sequence, the fourth initialization voltage routing 830 for providing the third initialization signal Vref1 can be connected to the third initialization voltage routing 710, the fourth initialization voltage routing 830 for providing the second initialization signal Vref2 can be connected to the second initialization voltage routing 520, and the fourth initialization voltage routing 830 for providing the first initialization signal Vref3 can be connected to the first initialization voltage routing 510.

[0144] In the above design, the first initialization voltage line 510, the second initialization voltage line 520, the third initialization voltage line 710 and the fourth initialization voltage line 830 can be meshed in the first direction D1 and the second direction D2, which is beneficial to improving the low grayscale display effect of the display panel.

[0145] The fourth initialization voltage wiring 830 , the first power wiring 810 , and the data signal wiring 820 may all be located in the fourth conductive layer 800 .

[0146] The display panel may further include a first organic layer between the third conductive layer 700 and the fourth conductive layer 800 , at least some of the wiring in the fourth conductive layer 800 may be connected to at least some of the wiring in the third conductive layer 700 through a fourth via hole, and the fourth via hole may penetrate the first organic layer.

[0147] The display panel may further include an electrode layer located on the side of the fourth conductive layer 800 away from the substrate. The electrode layer may be an anode. A second organic layer may be included between the fourth conductive layer 800 and the electrode layer. At least part of the wiring in the fourth conductive layer 800 may be connected to the anode through a fifth via hole. The fifth via hole may penetrate the second organic layer.

[0148] Please refer to Fig.13 The display panel may further include a first connection line 720 and a second connection line 840. The first connection line 720 may extend along a first direction D1, and the second connection line 840 may extend along a second direction D2. The first connection line 720 may be located in the third conductive layer 700, and the second connection line 840 may be located in the fourth conductive layer 800. The first connection line 720 and the second connection line 840 may be used to implement a FIAA fan-out design.

[0149] In the above design, compared with the 3TAT process in the prior art, the display panel adopts a 2TAT process, that is, only two layers of titanium-aluminum-titanium (Ti-Al-Ti) are set as the third conductive layer 700 and the fourth conductive layer 800, which effectively reduces the process.

[0150] The embodiment of the present application also provides an electronic device, which may include the display panel provided in the embodiment. The electronic device may include a display, a spliced ​​display screen, a mobile phone, a tablet computer, a laptop computer, a television, and other devices with display functions.

[0151] In summary, the embodiments of the present application provide a display panel and an electronic device, in which at least part of the wiring in the gate layer can be directly connected to at least part of the wiring in the first active layer and / or the first conductive layer and / or the second conductive layer through a first via, without setting up an additional metal layer, which can simplify the process flow, save wiring space, and improve the display effect of the display panel.

[0152] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; An array function layer located on one side of the substrate, the array function layer comprising a plurality of pixel circuits; A light-emitting functional layer located on a side of the array functional layer away from the substrate, the light-emitting functional layer comprising a plurality of light-emitting devices, the pixel circuit being electrically connected to the corresponding light-emitting devices; The array functional layer includes a first active layer, a first conductive layer, a second conductive layer and a gate layer stacked in a direction away from the substrate; At least part of the routing lines in the gate layer include a via region, and an orthographic projection of the via region on the substrate at least partially overlaps with an orthographic projection of at least part of the routing lines in the first active layer and / or the first conductive layer and / or the second conductive layer on the substrate; at least part of the routing lines in the gate layer are electrically connected to at least part of the routing lines in the first active layer and / or the first conductive layer and / or the second conductive layer through a first via, and an orthographic projection of the first via on the substrate is located within an orthographic projection of the via region on the substrate; At least part of the switching devices in the pixel circuit is composed of at least part of the wiring located in the gate layer, the first active layer and / or the first conductive layer and / or the second conductive layer.

2. The display panel according to claim 1, characterized in that: The display panel further includes a first initialization voltage wiring; The first initialization voltage wiring is located at the gate layer; The pixel circuit includes a first reset transistor; the first reset transistor includes a first semiconductor routing segment located in the first active layer and a first metal routing segment located in the first conductive layer, and an orthographic projection of the first semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the first metal routing segment on the substrate; The source of the first reset transistor located in the first active layer and the first initialization voltage wiring located in the gate layer are connected through at least one of the first vias; Preferably, the first conductive layer includes a first scanning signal routing, the first reset transistor includes a first semiconductor routing segment and the first scanning signal routing located in the first active layer, and the orthographic projection of the first semiconductor routing segment on the substrate at least partially overlaps with the orthographic projection of the first scanning signal routing on the substrate.

3. The display panel according to claim 2, characterized in that: The pixel circuit further includes a driving transistor; the driving transistor includes a second semiconductor routing segment located in the first active layer and a second metal routing segment located in the first conductive layer, and an orthographic projection of the second semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the second metal routing segment on the substrate; The drain of the first reset transistor located in the first active layer and the first end of the first connecting wire located in the gate layer are connected through at least one of the first via holes; The drain of the driving transistor located in the first active layer and the second end of the first connecting wire located in the gate layer are connected through at least one of the first via holes; Preferably, the first reset transistor includes a first sub-transistor and a second sub-transistor; The source of the first sub-transistor located in the first active layer and the first initialization voltage wiring located in the gate layer are connected through at least one of the first vias; The drain of the first sub-transistor is connected to the source of the second sub-transistor; The drain of the second sub-transistor located in the first active layer and the first end of the first connecting wire located in the gate layer are connected through at least one of the first via holes.

4. The display panel according to claim 3, characterized in that: The pixel circuit further includes a connection point connected to the light emitting device, and the display panel further includes a second initialization voltage wiring; The second initialization voltage wiring is located at the gate layer; The pixel circuit further includes a second reset transistor, the second reset transistor including a third semiconductor routing segment located in the first active layer and a third metal routing segment located in the first conductive layer, an orthographic projection of the third semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the third metal routing segment on the substrate; The source of the second reset transistor located in the first active layer and the second initialization voltage wiring located in the gate layer are connected through at least one of the first vias; Preferably, the second reset transistor comprises a third semiconductor routing segment and the first scanning signal routing segment located in the first active layer; an orthographic projection of the third semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the first scanning signal routing segment on the substrate; Preferably, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor, and the display panel further includes a first power supply line; the source of the driving transistor is connected to the first power supply line through the first light emission control transistor, and the drain of the driving transistor is also connected to the anode of the light emitting device through the second light emission control transistor; The connection point is connected to the second initialization voltage wiring via the second reset transistor.

5. The display panel according to claim 3, characterized in that: The first semiconductor routing segment includes a first portion extending along a first direction and a second portion extending along a second direction, the first metal routing segment includes a third portion extending along the first direction and a fourth portion extending along the second direction, the first direction being perpendicular to the second direction; The first sub-transistor includes a first portion of the first semiconductor routing segment and a fourth portion of the first metal routing segment, and an orthographic projection of the first portion of the first semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the fourth portion of the first metal routing segment on the substrate; The second sub-transistor includes a second portion of the first semiconductor routing segment and a third portion of the first metal routing segment, and an orthographic projection of the second portion of the first semiconductor routing segment on the substrate at least partially overlaps with an orthographic projection of the third portion of the first metal routing segment on the substrate.

6. The display panel according to claim 2, characterized in that: The array function layer further includes a second active layer; the pixel circuit further includes a compensation transistor and a storage capacitor; The compensation transistor comprises a fourth metal routing segment located in the first conductive layer or the second conductive layer, a fourth semiconductor routing segment located in the second active layer, and a second connecting routing segment located in the gate layer; the orthographic projection of the fourth metal routing segment on the substrate, the orthographic projection of the fourth semiconductor routing segment on the substrate, and the orthographic projection of the second connecting routing on the substrate at least partially overlap; The fourth metal routing segment and the second connecting routing are connected through at least one of the first vias; Preferably, the display panel further includes a second scanning signal wiring; The second scan signal routing line includes the fourth metal routing line segment, or the second scan signal routing line includes the second connecting routing line; Preferably, the first electrode of the compensation transistor is connected to the drain of the driving transistor, the second electrode of the compensation transistor is connected to the first power supply line through the storage capacitor, the first electrode of the compensation transistor is one of the source and the drain, and the second electrode of the compensation transistor is the other of the source and the drain.

7. The display panel according to claim 6, characterized in that: The pixel circuit further includes a third reset transistor; The third reset transistor includes a fifth metal routing segment located in the first conductive layer or the second conductive layer, a fifth semiconductor routing segment located in the second active layer, and a third connecting routing segment located in the gate layer; the orthographic projection of the five metal routing segments on the substrate, the orthographic projection of the fifth semiconductor routing segment on the substrate, and the orthographic projection of the third connecting routing segment on the substrate at least partially overlap; The fifth metal routing segment and the third connecting routing are connected through at least one of the first vias; Preferably, the display panel further includes a third scanning signal wiring; The third scan signal routing line includes the fifth metal routing line segment, or the second scan signal routing line includes the second connection routing line; Preferably, the display panel also includes a third initialization voltage routing; the first electrode of the third reset transistor is connected to the third initialization voltage routing, the second electrode of the third reset transistor is connected to the first power routing via the compensation transistor and the storage capacitor in sequence, the first electrode of the third reset transistor is one of the source and the drain, and the second electrode of the third reset transistor is the other of the source and the drain.

8. The display panel according to claim 3, characterized in that: The pixel circuit also includes a data writing transistor and a storage capacitor; The display panel also includes data signal routing; The first electrode of the data writing transistor is connected to the data signal wiring, the second electrode of the data writing transistor is connected to the source electrode of the driving transistor, the first electrode of the data writing transistor is one of the source and the drain, and the second electrode of the data writing transistor is the other of the source and the drain; Preferably, the data writing transistor comprises a sixth semiconductor routing segment located in the first active layer and a sixth metal routing segment located in the first conductive layer; the orthographic projection of the sixth semiconductor routing segment on the substrate at least partially overlaps with the orthographic projection of the sixth metal routing segment on the substrate; the storage capacitor comprises a seventh metal routing segment located in the first conductive layer and an eighth metal routing segment located in the second conductive layer; the orthographic projection of the seventh metal routing segment on the substrate at least partially overlaps with the orthographic projection of the eighth metal routing segment on the substrate; Preferably, the first conductive layer also includes a fourth scanning signal routing, and the data writing transistor includes a sixth semiconductor routing segment and a fourth scanning signal routing located in the first active layer; the orthographic projection of the sixth semiconductor routing segment on the substrate at least partially overlaps with the orthographic projection of the fourth scanning signal routing on the substrate.

9. The display panel according to claim 4, characterized in that: The display panel further includes a third conductive layer; the display panel further includes a third initialization voltage wiring; The third initialization voltage wiring is located in the third conductive layer; The first initialization voltage wiring, the second initialization voltage wiring and the third initialization voltage wiring have the same extension direction; The display panel further includes a fourth conductive layer; the display panel further includes a fourth initialization voltage wiring; The fourth initialization voltage wiring is located in the fourth conductive layer; The extension direction of the fourth initialization voltage line intersects with the extension directions of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line; the fourth initialization voltage line is used to provide the first initialization signal, the second initialization signal or the third initialization signal.

10. An electronic device, characterized in that: The invention comprises the display panel described in claims 1 to 9.

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