Display panel and display equipment

Abstract

The display panel comprises a first thin film transistor located in a display area, the first thin film transistor comprises a first grid electrode and a second grid electrode, the first grid electrode is located on the side, away from a first electrode, of the second grid electrode, and the first grid electrode comprises a semiconductor part and a conductor part which are connected; the conductor part is located on the side, close to the second electrode, of the semiconductor part, in the thickness direction of the display panel, the second grid electrode and the first channel are overlapped, and the semiconductor part is partially overlapped with the first channel and the second grid electrode at the same time. According to the embodiment of the invention, the semiconductor part is overlapped with the first channel, the conductor part is arranged at one side close to the output electrode of the first thin film transistor, and the semiconductor part and the conductor part synergistically form a gradual change potential to regulate the electric field distribution of the output region of the first thin film transistor based on the large impedance of the semiconductor part and the small impedance of the conductor part. The output saturation characteristic of the first thin film transistor is controlled, and the stability of the first thin film transistor is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the organic light-emitting diode display panel, the display area uses conventional IGZO thin-film transistors to achieve high-stability drive current output, and the gate drive circuit area uses high-mobility oxide thin-film transistors to achieve smaller device size and high-strength drive capability. Compared with the gate drive circuit area, the display area has more gate insulation layers, and the more gate insulation layers there are, the greater the difference in the uniformity of its stacking structure, which in turn affects the uniformity and stability of the thin-film transistor; while the high-mobility oxide thin-film transistor in the gate drive circuit area is a single-layer gate insulation layer. During the dry etching process of the gate insulation layer, the over-etching amount is large, making it difficult to control the length of the channel. In addition, the drive thin-film transistor in the display area is single-gate controlled, which cannot control the output characteristics of the drive thin-film transistor. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display device, which can control the output saturation characteristics of the first thin film transistor and improve its stability.

[0004] An embodiment of the present application provides a display panel, including a display area and a gate driving circuit area located on at least one side of the display area, wherein the display panel includes:

[0005] substrate;

[0006] a first thin film transistor, arranged in the display area, the first thin film transistor comprising a first gate, a first insulating layer, a first active layer, a second insulating layer, a second gate, a first electrode and a second electrode, the first active layer comprising a first contact portion, a first channel and a second contact portion, the first gate being arranged on the substrate, the first insulating layer covering the first gate, the first active layer being arranged on a side of the first insulating layer away from the substrate, the second insulating layer being arranged on a side of the first active layer away from the substrate, the second gate being arranged on a side of the second insulating layer away from the substrate, the first electrode being connected to the first contact portion, and the second electrode being connected to the second contact portion;

[0007] Among them, the first gate is located on the side of the second gate away from the first electrode, the first gate includes a semiconductor part and a conductor part connected, the conductor part is located on the side of the semiconductor part close to the second electrode, in the thickness direction of the display panel, the second gate is overlapped with the first channel, and the semiconductor part overlaps with the first channel and the second gate part at the same time.

[0008] Optionally, in some embodiments of the present application, the carrier mobility of the semiconductor portion is greater than the carrier mobility of the first channel.

[0009] Optionally, in some embodiments of the present application, in the thickness direction of the display panel, the conductor portion at least partially overlaps with the second contact portion, and the conductor portion partially overlaps with the second electrode.

[0010] Optionally, in some embodiments of the present application, part of the first insulating layer covers the first gate to form a structure with a height difference, and the first active layer covers the first insulating layer to form the first channel with a height difference.

[0011] Optionally, in some embodiments of the present application, the material of the first channel is a metal oxide semiconductor, the material of the first insulating layer is a first silicon oxide, the material of the second insulating layer is a second silicon oxide, and the oxygen content of the second silicon oxide is greater than that of the first silicon oxide.

[0012] Optionally, in some embodiments of the present application, the width of the second insulating layer is greater than the width of the second gate.

[0013] An edge of the second insulating layer exceeds an edge of the second gate by at least 0.5 micrometers.

[0014] Optionally, in some embodiments of the present application, the display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a second active layer, an etch stop layer, a third insulating layer, a third gate, a third electrode and a fourth electrode, the second active layer includes a third contact portion, a second channel and a fourth contact portion, the second active layer is disposed on the substrate, the etch stop layer, the third insulating layer and the third gate are sequentially stacked on the second active layer, the third gate is overlapped with the second channel, the third electrode is connected to the third contact portion, and the fourth electrode is connected to the fourth contact portion;

[0015] The carrier mobility of the second channel is greater than the carrier mobility of the first channel, the second active layer and the first gate are provided in the same layer, and the material of the second channel is the same as that of the semiconductor part.

[0016] Optionally, in some embodiments of the present application, the conductivity of the third contact portion and the fourth contact portion are both greater than the conductivity of the conductor portion.

[0017] Optionally, in some embodiments of the present application, the width of the etch stop layer is greater than the width of the third insulating layer.

[0018] The edge of the etch stop layer exceeds the edge of the third insulating layer by at least 0.5 micrometers.

[0019] Optionally, in some embodiments of the present application, the etching stop layer and the first insulating layer are made of the same material and are made using the same photomask, the third insulating layer and the second insulating layer are made of the same material and are made using the same photomask, the second active layer and the first gate are made using the same photomask, and the second gate and the third gate are made of the same material and are made using a photomask.

[0020] Optionally, in some embodiments of the present application, the display panel is an electroluminescent panel, and the second electrode is connected to an anode.

[0021] Correspondingly, an embodiment of the present application further provides a display device, comprising a display panel as described in any one of the above embodiments.

[0022] The display panel and display device of the embodiments of the present application include a first thin film transistor located in the display area, the first thin film transistor includes a first gate and a second gate, the first gate is located on the side of the second gate away from the first electrode, the first gate includes a semiconductor part and a conductor part connected, the conductor part is located on the side of the semiconductor part close to the second electrode, in the thickness direction of the display panel, the second gate is overlapped with the first channel, and the semiconductor part overlaps with the first channel and the second gate part at the same time.

[0023] It can be understood that the first gate is arranged on the side close to the second electrode to adjust the output saturation characteristics of the output electrode region of the first thin film transistor to improve the output characteristics of the pixel driving transistor. The semiconductor part overlaps with the first channel, and the conductor part is arranged on the side close to the output electrode of the first thin film transistor. Since the impedance of the semiconductor part is large and the impedance of the conductor part is small, the potential of the semiconductor part is smaller than the potential of the conductor part, which can reduce the intensity of the influence of the electric field of the first gate on the first channel and improve the service life of the first thin film transistor. In addition, two different potentials can be formed based on the first gate, which can coordinately adjust the electric field distribution of the output region of the first thin film transistor to achieve control of the output saturation characteristics of the first thin film transistor and improve the stability of the first thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0026] Figure 3is a schematic diagram of step B01 in the method for preparing a display panel provided in an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of step B02 in the method for preparing a display panel provided in an embodiment of the present application;

[0028] Figure 5 is a schematic diagram of step B03 in the method for preparing a display panel provided in an embodiment of the present application;

[0029] Figure 6 is a schematic diagram of step B04 in the method for preparing a display panel provided in an embodiment of the present application;

[0030] Figure 7 is a schematic diagram of step B05 in the method for preparing a display panel provided in an embodiment of the present application;

[0031] Figure 8 is a schematic diagram of step B06 in the method for preparing a display panel provided in an embodiment of the present application;

[0032] Fig. 9 is a schematic diagram of step B07 in the method for preparing a display panel provided in an embodiment of the present application;

[0033] Fig.10 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the various embodiments can be combined with each other but will not be repeated one by one, and in the absence of contrary instructions, the directional words used, such as "upper" and "lower", usually refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0035] The embodiments of the present application provide a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] Please refer to Figure 1 and Figure 2 The embodiment of the present application provides a display panel 100, including a display area AA and a gate driving circuit area DA located at least on one side of the display area AA. The display panel 100 includes a substrate 11, a first thin film transistor T1 and a second thin film transistor T2. The first thin film transistor T1 is disposed in the display area AA, and the second thin film transistor T2 is disposed in the gate driving circuit area DA.

[0037] The first thin film transistor T1 includes a first gate 101, a first insulating layer 102, a first active layer 103, a second insulating layer 104, a second gate 105, a first electrode 106, and a second electrode 107. The first active layer 103 includes a first contact portion 1a, a first channel 1b, and a second contact portion 1c. The first gate 101 is disposed on a substrate 11. The first insulating layer 102 covers the first gate 101. The first active layer 103 is disposed on a side of the first insulating layer 102 away from the substrate 11. The second insulating layer 104 is disposed on a side of the first active layer 103 away from the substrate 11. The second gate 105 is disposed on a side of the second insulating layer 104 away from the substrate 11. The first electrode 106 is connected to the first contact portion 1a, and the second electrode 107 is connected to the second contact portion 1c.

[0038] The first gate 101 is located on a side of the second gate 105 away from the first electrode 106. The first gate 101 includes a semiconductor portion y1 and a conductor portion y2 connected to each other, and the conductor portion y2 is located on a side of the semiconductor portion y1 close to the second electrode 107. In the thickness direction of the display panel 100, the second gate 105 is overlapped with the first channel 1b, and the semiconductor portion y1 overlaps with the first channel 1b and the second gate 105.

[0039] Optionally, the display panel 100 is an electroluminescent panel, and the second electrode 107 is connected to the anode 12. The following description will be made by taking the display panel 100 as an electroluminescent panel as an example.

[0040] It can be understood that the first gate 101 is arranged on the side close to the second electrode 107 to adjust the output saturation characteristics of the output electrode region of the first thin film transistor T1 to improve the output characteristics of the pixel driving transistor. The semiconductor portion y1 overlaps with the first channel 1b, and the conductor portion y2 is arranged on the side close to the output electrode of the first thin film transistor T1. Based on the larger impedance of the semiconductor portion y1 and the smaller impedance of the conductor portion y2, the potential of the semiconductor portion y1 is smaller than the potential of the conductor portion y2, which can reduce the intensity of the influence of the electric field of the first gate 101 on the first channel 1b and improve the service life of the first thin film transistor T1. In addition, based on the first gate 101, two different potentials can be formed, which can coordinately adjust the electric field distribution of the output region of the first thin film transistor T1 to achieve the control of the output saturation characteristics of the first thin film transistor T1 and improve the stability of the first thin film transistor T1.

[0041] It should be noted that the second electrode 107 is the output electrode of the first thin film transistor T1 , which is connected to the anode 12 .

[0042] Secondly, optionally, the display panel 100 further includes an interlayer dielectric layer 13, a passivation layer 14, a planarization layer 15, a light shielding layer 16, and a buffer layer 17. The interlayer dielectric layer 13 covers the second gate 105 and the substrate 11, and the first electrode 106 and the second electrode 107 are arranged on the side of the interlayer dielectric layer 13 away from the substrate 11. The passivation layer 14 covers the first electrode 106, the second electrode 107, and the interlayer dielectric layer 13. The planarization layer 15 covers the passivation layer 14. The anode 12 is arranged on the side of the planarization layer 15 away from the substrate 11. The light shielding layer 16 is arranged on the substrate 11 and overlaps with the first thin film transistor T1. The buffer layer 17 covers the light shielding layer 16 and the substrate 11. The first gate 101 is arranged on the side of the buffer layer 17 away from the substrate 11.

[0043] In some embodiments, the interlayer dielectric layer 13 may be omitted so that the first electrode 106 and the second electrode 107 directly overlap the first active layer 103 .

[0044] The display panel 100 further includes a light emitting functional layer and a cathode, which are sequentially stacked on the anode 12 .

[0045] Optionally, the material of the light-emitting layer of the light-emitting functional layer may be an organic material, such as Alq3, bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), DPVBi, Almq3, and 3-tert-butyl-9,10-di(2-naphthalene)anthracene (TBADN).

[0046] The material of the light-emitting layer may also be an inorganic material, for example, it may be one or more selected from group IV semiconductor nanocrystals, group II-V semiconductor nanocrystals, group II-VI semiconductor nanocrystals, group IV-VI semiconductor nanocrystals, group III-V semiconductor nanocrystals and group III-VI semiconductor nanocrystals, etc. As an example, it may be one or more selected from silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots and gallium nitride quantum dots, etc.

[0047] Optionally, the material of the first active layer 103 at least includes an amorphous metal oxide material containing indium, gallium, and zinc. Optionally, the material of the first channel 1b is an amorphous metal oxide material containing indium, gallium, and zinc.

[0048] Optionally, the first thin film transistor T1 and the second thin film transistor T2 may be P-type or N-type. In the embodiment of the present application, the first thin film transistor T1 and the second thin film transistor T2 are N-type as an example for description.

[0049] Optionally, in some embodiments of the present application, the carrier mobility of the semiconductor portion y1 is greater than the carrier mobility of the first channel 1b, so that the conductivity of the semiconductor portion y1 is greater than the conductivity of the first channel 1b.

[0050] It should be understood that according to the saturation current formula of the thin film transistor, when Vds gradually increases, the local electric field of the drain (output electrode) forms a pinch-off of the channel carrier channel due to the mutual cancellation of Vds and Vgs, and the current no longer increases with the increase of Vds and presents a saturation state. Setting the first gate 101 close to the output electrode and at a certain potential can regulate the local electric field of the output electrode area and increase the saturation current. As a part of the first gate 101, the semiconductor part y1 needs a certain conductivity to provide a potential, and then form an electric field to fine-tune the saturation output characteristics of the thin film transistor. Therefore, the conductivity of the semiconductor part y1 is set between the conductivity of the first channel 1b and the conductor part y2, so that the first gate 101 has a gradual potential to form a more adaptable local electric field, so as to better control the saturation output characteristics of the first thin film transistor T1.

[0051] Optionally, the material of the semiconductor part y1 may be an amorphous or polycrystalline high-mobility metal oxide material. The material of the conductor part y2 includes all the materials of the semiconductor part y1 and conductive ions, and the conductive ions may be N-type or P-type ions.

[0052] Optionally, in some embodiments of the present application, in the thickness direction of the display panel 100 , the conductor portion y2 at least partially overlaps with the second contact portion 1 c , and the conductor portion y2 partially overlaps with the second electrode 107 .

[0053] It can be understood that the conductor part y2 is used to correspond to the second contact part 1c, and the second contact part 1c is raised so that the second electrode 107 can be connected to the second contact part 1c through a shallower via hole, thereby shortening the distance between the second electrode 107 and the second contact part 1c and improving signal transmission efficiency.

[0054] Optionally, in some embodiments of the present application, part of the first insulating layer 102 covers the first gate 101 to form a structure with a height difference, and the first active layer 103 covers the first insulating layer 102 along the structure to form a first channel 1b with a height difference.

[0055] It is understandable that the first gate 101 raises part of the first channel 1b so that the first channel 1b is stepped, thereby increasing the length of the first channel 1b, reducing the risk of leakage current, and further improving the stability of the first thin film transistor T1.

[0056] Optionally, in some embodiments of the present application, the material of the first channel 1b is a metal oxide semiconductor, the material of the first insulating layer 102 is a first silicon oxide, and the material of the second insulating layer 104 is a second silicon oxide, and the oxygen content of the second silicon oxide is greater than that of the first silicon oxide.

[0057] It is understandable that a greater oxygen content in the gate insulating layer means a lower oxygen vacancy concentration therein. Oxygen vacancies are one of the main sources of carriers in oxide semiconductors. Reducing oxygen vacancies is beneficial to reducing the concentration of carriers, thereby reducing mobility.

[0058] In the embodiment of the present application, the first insulating layer 102 and the second insulating layer 104 serve as gate insulating layers, and the oxygen content of the first insulating layer 102 is less than that of the second insulating layer 104, so that the mobility of the carrier channel of the second insulating layer 104 is larger and the mobility of the carrier channel of the first insulating layer 102 is smaller, so as to regulate the carrier mobility and improve the stability of the first thin film transistor T1.

[0059] Optionally, in some embodiments of the present application, the thickness of the first insulating layer 102 is less than the thickness of the second insulating layer 104 .

[0060] It is understandable that, under the same gate voltage and gate material, the smaller the thickness of the gate insulating layer, the larger the gate capacitance, and the lower the required threshold voltage. Therefore, based on the weak conductivity of the first gate 101, the thickness of the first insulating layer 102 can be reduced to increase the electric field strength, so as to better control the output saturation characteristics of the first thin film transistor T1.

[0061] Optional, see Figure 2 In some embodiments of the present application, a width L2 of the second insulating layer 104 is greater than a width L1 of the second gate 105 .

[0062] It is understandable that during the dry etching process of the second insulating layer 104, oxygen vacancies will diffuse toward the first channel 1b, causing the channel to become shorter. Therefore, the width of the second insulating layer 104 is set to be greater than the width of the second gate 105, so that the oxygen vacancies do not diffuse into the first channel 1b, and the length of the first channel 1b can be accurately controlled, thereby improving the stability of the first thin film transistor T1.

[0063] Secondly, optionally, the width L1 of the second gate 105 is the length of the first channel 1 b .

[0064] Optionally, the edge of the second insulating layer 104 exceeds the edge of the second gate 105 by at least 0.5 micrometers. Such a configuration can greatly reduce the risk of oxygen vacancies diffusing into the first channel 1b during the dry etching of the second insulating layer 104.

[0065] Optionally, the edge of the second insulating layer 104 may extend beyond the edge of the second gate 105 by 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, or 1 micrometer.

[0066] Optionally, in some embodiments of the present application, the display panel 100 further includes a second thin film transistor T2 located in the gate driving circuit area DA. The second thin film transistor T2 includes a second active layer 201, an etch stop layer 202, a third insulating layer 203, a third gate 204, a third electrode 205, and a fourth electrode 206. The second active layer 201 includes a third contact portion 2a, a second channel 2b, and a fourth contact portion 2c. The second active layer 201 is disposed on the substrate 11. The etch stop layer 202, the third insulating layer 203, and the third gate 204 are sequentially stacked on the second active layer 201. The third gate 204 is disposed overlapping the second channel 2b. The third electrode 205 is connected to the third contact portion 2a, and the fourth electrode 206 is connected to the fourth contact portion 2c.

[0067] The carrier mobility of the second channel 2b is greater than that of the first channel 1b. The second active layer 201 and the first gate 101 are disposed in the same layer, and the material of the second channel 2b is the same as that of the semiconductor portion y1.

[0068] It can be understood that the carrier mobility of the second channel 2b is greater than that of the first channel 1b, so that the second thin film transistor T2 located in the gate driving circuit area DA has a high mobility characteristic to meet the requirements of the gate driving circuit.

[0069] Secondly, in the embodiment of the present application, the second active layer 201 and the first gate 101 are formed by the same photomask process, which saves process steps and simplifies the structure of the display panel 100 on the one hand, and on the other hand, uses a high-mobility semiconductor material as the first gate 101 to optimize the local electric field formed by the first gate 101, so as to better regulate the output saturation characteristics of the first thin film transistor T1.

[0070] Optionally, the second active layer 201 is disposed on a side of the buffer layer 17 away from the substrate 11. The material of the second active layer 201 may be an amorphous or polycrystalline high-mobility metal oxide material.

[0071] Optionally, in some embodiments of the present application, the conductivity of the third contact portion 2a and the fourth contact portion 2c are both greater than the conductivity of the conductor portion y2.

[0072] The conductivity of the third contact portion 2a and the fourth contact portion 2c are both greater than the conductivity of the first contact portion 1a and the second contact portion 1c.

[0073] It can be understood that the conductivity of the conductor portion y2 is between the conductivity of the second contact portion 1c and the semiconductor portion y1, so that the conductivity of the conductor portion y2 will not be too large, and the amount of charge in the conductor portion y2 will not be too large per unit time, so as to regulate the capacitance of the first gate 101, and further better adjust the output saturation characteristics of the first thin film transistor T1.

[0074] Secondly, the third contact portion 2a and the fourth contact portion 2c have higher conductivity, while the first contact portion 1a and the second contact portion 1c have lower conductivity, so as to further meet the requirements of high stability of the first thin film transistor T1 and high mobility of the second thin film transistor T2.

[0075] Optionally, in some embodiments of the present application, the width L3 of the etch stop layer 202 is greater than the width L4 of the third gate 204. The width L3 of the etch stop layer 202 is greater than the width of the third insulating layer 203.

[0076] It is understandable that during the dry etching process of the etch stop layer 202, oxygen vacancies will diffuse toward the second channel 2b, causing the channel to shorten. Therefore, the width of the etch stop layer 202 is set to be greater than the width of the third insulating layer 203, so that the oxygen vacancies do not diffuse into the second channel 2b, and the length of the second channel 2b can be accurately controlled.

[0077] Secondly, the thickness of the etch barrier layer 202 is less than the thickness of the third insulating layer 203. When the third insulating layer 203 is etched, the etch barrier layer 202 can block the etching gas from etching the second active layer 201. When the etch barrier layer 202 is subsequently dry-etched, the etching time is short due to the small thickness of the etch barrier layer 202, which can reduce the diffusion time of oxygen vacancies, thereby more accurately controlling the length of the second channel 2b.

[0078] Optionally, in some embodiments, the edge of the etch stop layer 202 exceeds the edge of the third gate 204 by at least 0.5 micrometers. This configuration can greatly reduce the risk of oxygen vacancies diffusing into the second channel 2b during the dry etching process of etching the etch stop layer 202.

[0079] Optionally, the edge of the etch stop layer 202 may extend beyond the edge of the third gate 204 by 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, or 1 micrometer.

[0080] Optionally, in some embodiments of the present application, the material of the second channel 2b is a metal oxide semiconductor, the material of the etching stop layer 202 is the first oxygen silicon, the material of the third insulating layer 203 is the second oxygen silicon, and the oxygen content of the second oxygen silicon is greater than that of the first oxygen silicon.

[0081] The etch stop layer 202 of the embodiment of the present application serves as a gate insulating layer directly contacting the second channel 2 b . The etch stop layer 202 has a low oxygen content, so that the mobility of the carrier channel of the etch stop layer 202 is relatively large, thereby improving the mobility of the second thin film transistor T2 .

[0082] Optionally, in some embodiments, the etch stop layer 202 and the first insulating layer 102 may each be a single film layer, or may be formed by stacking at least two film layers.

[0083] Optionally, in some embodiments of the present application, the etch stop layer 202 and the first insulating layer 102 are made of the same material and are made using the same photomask, the third insulating layer 203 and the second insulating layer 104 are made of the same material and are made using the same photomask, the second active layer and the first gate 101 are made using the same photomask, and the second gate 105 and the third gate 204 are made of the same material and are made using a photomask.

[0084] It can be understood that forming partial film layers of the first thin film transistor T1 and the second thin film transistor T2 by using the same photomask process can save the number of photomasks and simplify the structure to the greatest extent.

[0085] Optionally, the method for preparing the display panel 100 of the embodiment of the present application includes the following steps:

[0086] like Figure 3 As shown, in step B01, a light shielding layer 16, a buffer layer 17, a first semiconductor layer and a first insulating material layer p1 are sequentially formed on a substrate 11.

[0087] Optionally, the material of the light shielding layer 16 may be a stacked structure of a molybdenum alloy and copper. The buffer layer 17 may be a single layer or a stacked layer structure, and the material of the buffer layer 17 is at least one of silicon oxide / silicon nitride / silicon oxynitride.

[0088] The first semiconductor layer includes a first gate electrode 101 located in the display area AA and a second active layer 201 located in the gate driving circuit area DA. The material of the first semiconductor layer may be an amorphous or polycrystalline high-mobility metal oxide material.

[0089] The first insulating material layer p1 may consist of only a single film layer, or may be a stack of at least two film layers. The material of the first insulating material layer p1 may be silicon oxide, which has a first oxygen content.

[0090] like Figure 4As shown, step B02, a first active layer 103 and a second insulating material layer p2 are sequentially formed on the first insulating material layer p1, and a portion of the first active layer 103 covers the first gate 101. The second insulating material layer p2 covers the first active layer 103 and the first insulating material layer p1.

[0091] Optionally, the first active layer 103 is an amorphous metal oxide material containing indium, gallium, and zinc. The material of the second insulating material layer p2 may be silicon oxide, which has a second oxygen content. The second oxygen content is greater than the first oxygen content.

[0092] like Figure 5 As shown, in step B03, a second gate 105 and a third gate 204 are formed on the second insulating material layer p2, the second gate 105 overlaps with the first channel 1b of the first active layer 103, and the third gate 204 overlaps with the second channel 2b of the second active layer 201.

[0093] Optionally, the material of the second gate 105 and the third gate 204 may be a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, cobalt, an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. In addition, the second gate 105 and the third gate 204 may have a single-layer structure or a stacked structure of two or more layers.

[0094] like Figure 6 As shown, in step B04 , the second insulating material layer and the first insulating material layer are patterned and etched in sequence to form a third insulating layer 203 , a second insulating layer 104 , an etching stop layer 202 and a first insulating layer 102 .

[0095] like Figure 7 As shown, in step B05, the first contact portion 1a and the second contact portion 1c of the first active layer 103, the third contact portion 2a and the fourth contact portion 2c of the second active layer 201, and the conductor portion y2 of the first gate 101 are simultaneously subjected to conductorization processing using the second gate 105 and the third gate 204 as masks.

[0096] Optionally, an ion implantation process is used for conducting treatment, and the implanted ions may be N-type or P-type, depending on the type of the thin film transistor.

[0097] like Figure 8 As shown, in step B06, an interlayer dielectric layer 13 and a source-drain metal layer are sequentially formed on the second gate 105 and the third gate 204, and the source-drain metal layer includes a first electrode 106, a second electrode 107, a third electrode 205 and a fourth electrode 206.

[0098] The first electrode 106 and the second electrode 107 are connected to the first active layer 103 through a via hole g1 , respectively. The third electrode 205 and the fourth electrode 206 are connected to the second active layer 201 through a via hole g1 , respectively.

[0099] Optionally, the via hole g1 is formed by dry etching. It should be noted that the etching stop layer 202 may also extend toward the via hole g1 and partially overlap with the third electrode 205 and / or the fourth electrode 206 .

[0100] It is understandable that once the via hole g1 is overetched, the aperture of the via hole g1 will increase, so that the distance that the oxygen vacancies diffuse toward the channel direction will be reduced. The etching stop layer 202 extends to the vicinity of the via hole g1. Once the via hole g1 is overetched, the aperture will increase, and the side of the via hole g1 close to the channel will be blocked by the etching stop layer 202, and the second active layer 201 covered by the etching stop layer 202 cannot be etched, which reduces the risk of oxygen vacancies continuing to diffuse toward the channel direction, so as to accurately control the length of the second channel 2b of the second active layer 201.

[0101] Optionally, the interlayer dielectric layer 13 may be a single layer or a stacked layer structure, and the material may be silicon oxide. The source-drain metal layer may be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy with any of the above metal elements as a component, or an alloy combining any of the above metal elements. In addition, the source-drain metal layer may have a single layer structure or a stacked structure of two or more layers.

[0102] like Fig. 9 As shown, in step B07, a passivation layer 14, a planarization layer 15 and an anode 12 are sequentially formed on the source-drain metal layer.

[0103] Please refer to Fig.10 Accordingly, an embodiment of the present application further provides a display device 1000, comprising a display panel 100 as described in any one of the above embodiments.

[0104] It should be noted that the structure of the display panel 100 of the display device 1000 of the embodiment of the present application is similar to or the same as the structure of the display panel 100 of the above-mentioned embodiments. Figures 1 to 9 The relevant explanation is not repeated here.

[0105] The display device 1000 of the embodiment of the present application includes a first thin film transistor T1 located in the display area AA, the first thin film transistor T1 includes a first gate 101 and a second gate 105, the first gate 101 is located on a side of the second gate 105 away from the first electrode 106, the first gate 101 includes a semiconductor portion y1 and a conductor portion y2 connected to each other, the conductor portion y2 is located on a side of the semiconductor portion y1 close to the second electrode 107. In the thickness direction of the display panel 100, the second gate 105 is overlapped with the first channel 1b, and the semiconductor portion y1 overlaps with the first channel 1b and the second gate 105 at the same time.

[0106] It can be understood that the first gate 101 is arranged on the side close to the second electrode 107 to adjust the output saturation characteristics of the output electrode region of the first thin film transistor T1 to improve the output characteristics of the pixel driving transistor. The semiconductor portion y1 overlaps with the first channel 1b, and the conductor portion y2 is arranged on the side close to the output electrode of the first thin film transistor T1. Based on the larger impedance of the semiconductor portion y1 and the smaller impedance of the conductor portion y2, the potential of the semiconductor portion y1 is smaller than the potential of the conductor portion y2, which can reduce the intensity of the influence of the electric field of the first gate 101 on the first channel 1b and improve the service life of the first thin film transistor T1. In addition, based on the first gate 101, two different potentials can be formed, which can coordinately adjust the electric field distribution of the output region of the first thin film transistor T1 to achieve the control of the output saturation characteristics of the first thin film transistor T1 and improve the stability of the first thin film transistor T1.

[0107] Optionally, the display device 1000 may be applied to and used in various products including, for example, televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation, and ultra mobile personal computers (UMPCs).

[0108] In addition, the display device 1000 according to some embodiments may be applied to a wearable device and may be used in a wearable device, including a smart watch, a watch phone, a glasses-type display, and a head-mounted display. In addition, according to some embodiments, the display device 1000 may be applied to an instrument panel for a car, a display screen in a central dashboard or a central information display arranged on a dashboard for a car, an interior mirror display replacing a side mirror of a car, and a display of an entertainment system arranged on the back of a front seat for rear seat passengers in a car.

[0109] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising a display area and a gate driving circuit area located at at least one side of the display area, characterized in that: The display panel comprises: substrate; a first thin film transistor, arranged in the display area, the first thin film transistor comprising a first gate, a first insulating layer, a first active layer, a second insulating layer, a second gate, a first electrode and a second electrode, the first active layer comprising a first contact portion, a first channel and a second contact portion, the first gate being arranged on the substrate, the first insulating layer covering the first gate, the first active layer being arranged on a side of the first insulating layer away from the substrate, the second insulating layer being arranged on a side of the first active layer away from the substrate, the second gate being arranged on a side of the second insulating layer away from the substrate, the first electrode being connected to the first contact portion, and the second electrode being connected to the second contact portion; Among them, the first gate is located on the side of the second gate away from the first electrode, the first gate includes a semiconductor part and a conductor part connected, the conductor part is located on the side of the semiconductor part close to the second electrode, in the thickness direction of the display panel, the second gate is overlapped with the first channel, and the semiconductor part overlaps with the first channel and the second gate part at the same time.

2. The display panel according to claim 1, characterized in that: The carrier mobility of the semiconductor portion is greater than the carrier mobility of the first channel.

3. The display panel according to claim 2, characterized in that: In the thickness direction of the display panel, the conductor portion at least partially overlaps with the second contact portion, and the conductor portion partially overlaps with the second electrode.

4. The display panel according to claim 3, characterized in that: Part of the first insulating layer covers the first gate to form a structure with a height difference, and the first active layer covers the first insulating layer to form the first channel with a height difference.

5. The display panel according to any one of claims 1 to 4, characterized in that: The material of the first channel is a metal oxide semiconductor, the material of the first insulating layer is a first silicon oxide, and the material of the second insulating layer is a second silicon oxide, wherein the oxygen content of the second silicon oxide is greater than that of the first silicon oxide.

6. The display panel according to any one of claims 1 to 4, characterized in that: The width of the second insulating layer is greater than the width of the second gate.

7. The display panel according to claim 4, characterized in that: The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a second active layer, an etch stop layer, a third insulating layer, a third gate, a third electrode and a fourth electrode, the second active layer includes a third contact portion, a second channel and a fourth contact portion, the second active layer is arranged on the substrate, the etch stop layer, the third insulating layer and the third gate are sequentially stacked on the second active layer, the third gate is arranged to overlap with the second channel, the third electrode is connected to the third contact portion, and the fourth electrode is connected to the fourth contact portion; The carrier mobility of the second channel is greater than the carrier mobility of the first channel, the second active layer and the first gate are provided in the same layer, and the material of the second channel is the same as that of the semiconductor part.

8. The display panel according to claim 7, characterized in that: The conductivity of the third contact portion and the fourth contact portion is greater than the conductivity of the conductor portion.

9. The display panel according to claim 7, characterized in that: The width of the etch stop layer is greater than the width of the third gate.

10. The display panel according to any one of claims 7 to 9, characterized in that: The etching stop layer and the first insulating layer are made of the same material and are made using the same photomask, the third insulating layer and the second insulating layer are made of the same material and are made using the same photomask, the second active layer and the first gate are made using the same photomask, and the second gate and the third gate are made of the same material and are made using a photomask.

11. The display panel according to any one of claims 1 to 4, characterized in that: The display panel is an electroluminescent panel, and the second electrode is connected to the anode.

12. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-11.

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