Ferroelectric diode content addressable memory with low thermal budget and preparation method thereof

Abstract

A low thermal budget ferroelectric diode content addressable memory comprises a top electrode, an insertion layer, a ferroelectric film and a bottom electrode which are arranged in sequence. The insertion layer is a natural oxide layer formed on the surface of the ferroelectric film exposed in the air. The preparation method comprises the following steps: depositing the bottom electrode on the substrate; depositing a ferroelectric film on the bottom electrode; exposing the ferroelectric film in air to naturally oxidize the surface of the ferroelectric film to obtain an insertion layer; a top electrode is deposited on the insertion layer. According to the invention, the ferroelectric diode device is obtained by using the natural oxide layer, so that the storage and XNOR Boolean logic functions can be simultaneously realized on the single diode device, the power consumption and the area overhead are obviously reduced compared with the traditional content addressable memory, and the energy efficiency bottleneck of the integrated circuit industry in the later Moire era is expected to be broken through. The subsequent process compatible ferroelectric diode has a low process temperature of 330 DEG C, three-dimensional integration is facilitated, and the integration density limitation of the content addressable memory is broken through.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a low thermal budget ferroelectric diode content addressable memory and a preparation method thereof. Background Art

[0002] In today's big data era, the real-time transmission data generated by IoT devices, Internet search engines and user edge devices has increased dramatically, while the traditional von Neumann architecture has inevitable data transmission delays and energy losses, the development of processors and memory has slowed down, and the gap between performance and demand has continued to increase. Content-addressable memory (CAM) is a special memory suitable for fast parallel pattern search and matching. It compares the input data with all the data stored in the array at the same time and outputs the corresponding matching information. It can realize search and similarity detection operations in the memory with high parallelism and high energy efficiency, reducing data transmission. In recent years, it has shown great potential in completing tasks such as edge intelligent computing.

[0003] However, traditional SRAM-based CAM cells require at least 10 transistors, resulting in significant energy consumption and area overhead, limiting the density increase of computationally intensive algorithm mapping. With the exponential growth of data, breakthroughs in CAM energy efficiency and area cost have become increasingly urgent. Although various emerging non-volatile memories (NVMs), such as RRAM, PCM, and FeFET, have been used to build CAM cells with low hardware costs, their implementations are all based on dual complementary circuit branch paths to achieve XNOR-type matching operations of CAMs with at least two entry states, which still have problems such as large hardware overhead and high computational energy consumption. In addition, the process temperature is high (>400°C), which is not conducive to achieving three-dimensional integration and improving the integration density of CAM. Summary of the invention

[0004] In view of the area, energy efficiency and process temperature problems of existing content addressable memories, the purpose of the present invention is to provide a low thermal budget ferroelectric diode content addressable memory and a preparation method thereof, aiming to simultaneously achieve low process temperature, small area and low power consumption characteristics, thereby breaking through the CAM integration density limitation.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A low thermal budget ferroelectric diode content addressable memory comprises a top electrode, an insertion layer, a ferroelectric film and a bottom electrode arranged in sequence; the insertion layer is a natural oxide layer formed on the surface of the ferroelectric film when the ferroelectric film is exposed to air.

[0007] In one embodiment, the top electrode is Pt, Ru, Au, Cu, Ni or Ti, the bottom electrode is Pt, TiN, TaN, W or Mo, and the ferroelectric thin film is AlScN.

[0008] In one embodiment, the content of Sc in the AlScN is 18% to 40% based on the total molar amount of Al and Sc. 0.82 Sc 0.18 N to Al 0.6 Sc 0.4 N.

[0009] In one embodiment, the top electrode has a thickness ranging from 20 to 100 nm, the bottom electrode has a thickness ranging from 50 to 200 nm, the ferroelectric film has a thickness ranging from 30 to 100 nm, and the insertion layer has a thickness ranging from 3 to 5 nm.

[0010] In one embodiment, the write operation and the read operation are performed on the ferroelectric diode as follows:

[0011] The write operation flips the ferroelectric domain in a positive direction by a positive write voltage to obtain a storage state 0, and flips the ferroelectric domain in a negative direction by a negative write voltage to obtain a storage state 1;

[0012] The read operation queries the storage state 1 through a positive search voltage and queries the storage state 0 through a negative search voltage, and both the positive search voltage and the negative search voltage are lower than the ferroelectric coercive voltage.

[0013] In one embodiment, a plurality of the low thermal budget ferroelectric diode content addressable memories are constructed into an array and are independently connected to an external electric field, wherein the external electric field is used to control the realization of a storage state of 1 or 0.

[0014] The present invention also provides a method for preparing the low thermal budget ferroelectric diode content addressable memory, comprising the following steps:

[0015] depositing the bottom electrode on a substrate;

[0016] depositing the ferroelectric thin film on the bottom electrode;

[0017] Exposing the ferroelectric thin film to air to allow its surface to naturally oxidize to obtain the insertion layer;

[0018] The top electrode is deposited on the insertion layer.

[0019] In one embodiment, the deposition is achieved by a magnetron sputtering process, the ferroelectric film is AlScN, and the deposition process is as follows:

[0020] Sputtering from two separate Al and Sc targets, reacting with nitrogen plasma, the gas flow ratio of nitrogen and argon in the carrier gas is (1-3):1, which reduces the deposition temperature to 330°C.

[0021] In one embodiment, the ferroelectric thin film is exposed to air to allow its surface to be naturally oxidized to obtain the insertion layer; or,

[0022] The ferroelectric thin film is placed in an oxidation device, and the surface of the thin film is naturally oxidized by setting the humidity, temperature and oxygen content in the environment to obtain the insertion layer.

[0023] In one embodiment, the ferroelectric thin film is exposed to air for 4 to 6 minutes.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention utilizes a natural oxide layer to obtain a ferroelectric diode device, thereby being able to simultaneously implement storage and XNOR Boolean logic functions on a single diode device, significantly reducing power consumption and area overhead compared to traditional content addressable memory, and is expected to break through the energy efficiency bottleneck of the integrated circuit industry in the post-Moore era.

[0026] The back-end process-compatible ferroelectric diode of the present invention has a low process temperature of 330° C., which is conducive to realizing three-dimensional integration and breaking through the integration density limit of content addressable memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of the ferroelectric content addressable memory device of the present invention.

[0028] Figure 2 It is the hysteresis loop of ferroelectric thin film.

[0029] Figure 3 It is a characteristic diagram of ferroelectric capacitance.

[0030] Figure 4 is the DC characteristic of a ferroelectric diode.

[0031] Figure 5 is the Boolean logic truth table for a ferroelectric diode.

[0032] Figure 6 It is a schematic diagram of transient timing response characteristics of the ferroelectric diode content addressable memory of the present invention. DETAILED DESCRIPTION

[0033] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0034] In view of the area, energy efficiency and process temperature problems of existing content addressable memory, the present invention proposes a single resistor architecture (4F 2) and a method for preparing the same, wherein the ferroelectric diode content addressable memory comprises a top electrode, an insertion layer, a ferroelectric film and a bottom electrode arranged in sequence, wherein the insertion layer is a natural oxide layer formed on the surface of the ferroelectric film when it is exposed to air.

[0035] According to the above description, the ferroelectric diode content addressable memory of the present invention is a standard capacitor structure with upper and lower metal plates and a high-k dielectric in the middle. The present invention mainly utilizes the variable resistance property of the diode. Therefore, the present invention is a special resistance type memory structure combining the ferroelectric polarization property and the diode property, that is, a single resistor architecture (4F 2 ). Among them, F 2 It is a specification of the device area in the integrated circuit manufacturing industry, that is, how much square area of ​​the characteristic size is occupied. Generally, if there is no special design constraint, a single resistor structure is 4F. 2 .

[0036] In the ferroelectric capacitor structure, when the ferroelectric domain is forward biased, the forward resistance is low and the reverse resistance is high. After the domain is flipped, the forward resistance is high and the reverse resistance is low, so it is a reconfigurable ferroelectric diode.

[0037] In the present invention, the top electrode needs to have high conductivity and anti-oxidation ability, and typical materials that can be selected include Pt, Ru, Au, Cu, Ni or Ti, etc. The bottom electrode has a low thermal budget and excellent interface compatibility, and is suitable for CMOS compatible processes, and typical materials that can be selected include Pt, TiN, TaN, W or Mo, etc.

[0038] The insertion layer of the present invention needs to have an effect on the ferroelectric film, but its effect on some oxide ferroelectric materials such as HZO is limited, so the ferroelectric film material of the present invention is selected as AlScN. For example, in AlScN, the Sc component has ferroelectricity when it is 18% to 40% based on the total molar amount of Al and Sc, that is, the range of AlScN is from Al 0.82 Sc 0.18 N to Al 0.6 Sc 0.4 N, in the embodiment of the present invention, can be specifically selected as Al 0.7 Sc 0.3 N.

[0039] The thickness of the top electrode of the present invention is in the range of 20-100nm, the thickness of the bottom electrode is in the range of 50-200nm, the thickness of the ferroelectric film is in the range of 30-100nm, and the thickness of the insertion layer is in the range of 3-5nm.

[0040] Figure 1The present invention shows a three-dimensional structure Ti / IL / AlScN / Mo ferroelectric non-volatile memory device of a ferroelectric diode content addressable memory, wherein IL is an insertion layer with a thickness of 3nm, the thickness of the top electrode Ti is 40nm, and AlScN is specifically Al 0.7 Sc 0.3 N, thickness is 40nm, and the thickness of the bottom electrode Mo is 100nm.

[0041] The preparation method is as follows:

[0042] The 40nm thick Al 0.7 Sc 0.3 The N ferroelectric film is deposited between a 100nm thick Mo bottom electrode (BE) and a 40nm thick Ti top electrode (TE) by magnetron sputtering. The bottom electrode is deposited on a 50nm AlN substrate and is deposited using the same magnetron sputtering process as the top electrode. 0.7 Sc 0.3 The deposition process of N is sputtered from two separate Al and Sc targets (the power of Al and Sc sources is adjusted to make the Sc component 30%), and reacts with nitrogen plasma, and the gas flow ratio of nitrogen and argon is (1-3):1, preferably 2:1, which increases the energy generated by the plasma, thereby enabling the deposition temperature to be reduced to 330° C. Before the deposition of the top electrode Ti, the AlScN ferroelectric film is exposed to air for about 5 minutes, and a natural oxide layer with a thickness of about 3 nm is formed on its surface, i.e., the insertion layer of the present invention.

[0043] In more embodiments, the AlScN ferroelectric film may be placed in an oxidation device, and the surface thereof may be naturally oxidized to obtain an insertion layer by setting the humidity, temperature and oxygen content in the environment.

[0044] Figure 2 and Figure 3 The hysteresis loop and capacitance characteristics of the ferroelectric material are shown. The polarization (P) vs. voltage (V) characteristics were measured using the PUND method at a frequency of 100kHz, showing a typical hysteresis loop with a remanent polarization intensity (Pr) of +125 / -123μC / cm 2 , with a coercive voltage (VC) of +21.1 / -20.9 V. Quasi-static capacitance characterization highlights the butterfly-like behavior and polarization switching phenomena occurring at -10 and +9 V under DC conditions. These results confirm the ferroelectricity of the deposited AlScN and highlight its inherent annealing-free advantage.

[0045] Figure 4 and Figure 5The DC current (I) versus voltage (V) curves for the same batch of ferroelectric diodes under a double swept voltage from -13 to +16V are shown. As shown in the blue curve, the +16V forward write voltage polarizes the ferroelectric dipole of the ferroelectric diode downward, causing the device to reconfigure as a forward diode. Here, the current under forward bias (point "A") exceeds the current under negative bias (point "B") by 19 times, indicating a stored state "0" in the ferroelectric diode. Conversely, as shown in the red curve, the ferroelectric diode when activated by a negative write voltage of -13V polarizes its ferroelectric domain upward, resulting in a current under negative bias (point "C") that is 14 times greater than the current under forward bias (point "D"), behaving as a reverse diode and storing a state "1".

[0046] This reconfigurable diode property of ferroelectric diodes is attributed to their polarization modulated Schottky contacts. Here, the read behavior query 1 and 0 is performed at +7.5V forward search voltage and -6V negative search voltage, which are much smaller than the coercive voltage to minimize the impact of the query on the memory state. The ferroelectric diode exhibits a high resistance state (HRS) only when the input query matches the memory entry, otherwise it transitions to a low resistance state (LRS), which indicates the XNOR Boolean logic embedded in the ferroelectric diode and its potential as a CAM cell.

[0047] Therefore, the writing operation and reading operation of the ferroelectric diode of the present invention can be described as:

[0048] The write operation uses a large voltage to set the ferroelectric polarization state. Specifically, the ferroelectric domain is flipped forward by a +16V positive write voltage to obtain a storage state 0, and the ferroelectric domain is flipped negatively by a -13V negative write voltage to obtain a storage state 1.

[0049] In the read operation, a search voltage lower than the ferroelectric coercive voltage is used to measure the forward and negative resistance of the diode. Specifically, a +7.5V forward search voltage is used to query the storage state 1, and a -6V negative search voltage is used to query the storage state 0. Both the positive search voltage and the negative search voltage are lower than the ferroelectric coercive voltage.

[0050] For example, if the diode stores data 0, and you want to search for all diodes with data 0 in the storage array, you can use a search voltage of -6V to search. The diodes storing data 0 will output low current, and the diodes storing data 1 will output high current, which verifies the typical CAM operation function. Through the corresponding array and peripheral circuit design, content addressable memory can be realized.

[0051] Figure 6The transient timing response characteristics of a single AlScN ferroelectric diode cam were systematically monitored. The figure above shows the transient input waveform, which includes two sections: 1) writing 0 and searching 1 / 0; 2) writing 1 and searching 1 / 0. As shown in the figure, the ferroelectric diode exhibits HRS only when the storage state and the search state match, otherwise it will transition to LRS, and the discernible ratio of HRS / LRS is about 3:5.

Claims

1. A low thermal budget ferroelectric diode content addressable memory, characterized in that: The invention comprises a top electrode, an insertion layer, a ferroelectric film and a bottom electrode which are arranged in sequence; the insertion layer is a natural oxide layer formed on the surface of the ferroelectric film when the ferroelectric film is exposed to air.

2. The low thermal budget ferroelectric diode content addressable memory according to claim 1, characterized in that: The top electrode is Pt, Ru, Au, Cu, Ni or Ti, the bottom electrode is Pt, TiN, TaN, W or Mo, and the ferroelectric film is AlScN.

3. The low thermal budget ferroelectric diode content addressable memory according to claim 2, characterized in that: In the AlScN, the content of Sc is 18% to 40% based on the total molar amount of Al and Sc, that is, the range of AlScN is from Al 0.82 Sc 0.18 N to Al 0.6 Sc 0.4 N.

4. The low thermal budget ferroelectric diode content addressable memory according to claim 1, 2 or 3, characterized in that: The thickness of the top electrode is in the range of 20-100 nm, the thickness of the bottom electrode is in the range of 50-200 nm, the thickness of the ferroelectric film is in the range of 30-100 nm, and the thickness of the insertion layer is in the range of 3-5 nm.

5. The low thermal budget ferroelectric diode content addressable memory according to claim 1, characterized in that: Writing and reading operations on a ferroelectric diode are performed as follows: The write operation flips the ferroelectric domain in a positive direction by a positive write voltage to obtain a storage state 0, and flips the ferroelectric domain in a negative direction by a negative write voltage to obtain a storage state 1; The read operation queries the storage state 1 through a positive search voltage and queries the storage state 0 through a negative search voltage, and both the positive search voltage and the negative search voltage are lower than the ferroelectric coercive voltage.

6. The low thermal budget ferroelectric diode content addressable memory according to claim 1, characterized in that: A plurality of the low thermal budget ferroelectric diode content addressable memories are constructed into an array and are independently connected to an external electric field, wherein the external electric field is used to control the realization of a storage state of 1 or 0.

7. The method for preparing the low thermal budget ferroelectric diode content addressable memory according to any one of claims 1 to 6, characterized in that: The steps include: depositing the bottom electrode on a substrate; depositing the ferroelectric thin film on the bottom electrode; Exposing the ferroelectric thin film to air to allow its surface to naturally oxidize to obtain the insertion layer; The top electrode is deposited on the insertion layer.

8. The method for preparing a low thermal budget ferroelectric diode content addressable memory according to claim 7, characterized in that: The deposition is achieved by magnetron sputtering process, the ferroelectric film is AlScN, and the deposition process is as follows: Sputtering from two separate Al and Sc targets, reacting with nitrogen plasma, the gas flow ratio of nitrogen and argon in the carrier gas is (1-3):1, which reduces the deposition temperature to 330°C.

9. The method for preparing a low thermal budget ferroelectric diode content addressable memory according to claim 7, characterized in that: Exposing the ferroelectric thin film to air to allow its surface to naturally oxidize to obtain the insertion layer; or, The ferroelectric thin film is placed in an oxidation device, and the surface of the thin film is naturally oxidized by setting the humidity, temperature and oxygen content in the environment to obtain the insertion layer.

10. The method for preparing the low thermal budget ferroelectric diode content addressable memory according to claim 9, characterized in that: The ferroelectric film is exposed to air for 4 to 6 minutes.

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