Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a method for manufacturing a semiconductor device, capable of suppressing deformation of a lead member due to pressurization, and capable of suppressing occurrence of non-bonding between a semiconductor chip and a bonding layer. This method for manufacturing a semiconductor device is provided with: a step for preparing a lead member (4) provided with a bonding part (41) and a beam part (42) continuous from the bonding part (41); preparing a pressurizing jig (8) with an opening part (8a); a bonding portion (41) is disposed on a semiconductor chip (3) via a sintered material (2x). The semiconductor chip (3) is provided on a conductive layer (12a) of an insulating circuit board (1) having an insulating plate (11) and the conductive layer (12a) provided on the insulating plate (11). A step in which a pressing jig (8) is disposed on the bonding portion (41), the sintered material (2x), the semiconductor chip (3), and the conductive layer (12a) such that the opening portion (8a) overlaps the beam portion (42); and pressurizing and heating the bonding portion (41), the sintered material (2x), the semiconductor chip (3), and the conductive layer (12a) using a pressurizing jig (8).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Patent document 1 discloses a semiconductor device, which comprises: a semiconductor element having an element main surface and an element back side, a main surface electrode formed on the element main surface, and a back side electrode formed on the element back side; a first conductive member, which is opposite to the element back side and is conductively bonded to the back side electrode; a second conductive member, which is arranged separately from the first conductive member and is conductively bonded to the main surface electrode; and a lead member, which has a lead main surface facing the same direction as the element main surface, the lead member connecting the main surface electrode and the second conductive member, the lead member including a protrusion protruding from the lead main surface in the thickness direction, and is bonded to the main surface electrode by means of a lead bonding layer, the protrusion utilizing a structure that overlaps with the main surface electrode when viewed in the thickness direction, thereby suppressing deformation of the connecting member caused by pressure during sintering.

[0003] Patent document 2 discloses a method for manufacturing a power module, wherein a power module substrate, a semiconductor element, and a lead member are stacked with a silver paste layer interposed between a circuit layer of the power module substrate and a semiconductor element, and between the semiconductor element and a lead member, and these members are heated while a pressure is applied in the stacking direction to sinter the silver paste layer, and the circuit layer and the semiconductor element, and the semiconductor element and the lead member are joined respectively to suppress the occurrence of warping, and the semiconductor element and the lead member are joined without causing poor joining, damage to the semiconductor element, etc., thereby simply manufacturing the power module.

[0004] Patent document 3 discloses a semiconductor device, which comprises: a substrate; a semiconductor chip, which is mounted on the substrate and has a surface electrode and a back electrode located on the opposite side of the surface electrode; a lead member, which is arranged opposite to the surface electrode of the semiconductor chip; a first bonding portion, which is formed between the substrate and the back electrode of the semiconductor chip; and a second bonding portion, which is formed between the surface electrode of the semiconductor chip and the lead member, the lead member having: an electrode portion, which is connected to the surface electrode by means of the second bonding portion; a bridge portion, which connects the electrode portions; and a resin layer, which is formed on the upper surface of the electrode portion, the resin layer is formed on the lower surface of the bridge portion and the portion of the lower surface of the electrode portion that is not bonded to the surface electrode, so as to apply a uniform load to the entire surface of the semiconductor chip and to simultaneously press-bond the bonding portions of the surface and back of the semiconductor chip.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2020 / 075549

[0008] Patent Document 2: Japanese Patent Application Publication No. 2018-116995

[0009] Patent Document 3: Japanese Patent Application Publication No. 2018-6492 Summary of the invention

[0010] Problem that the invention aims to solve

[0011] A technique for bonding a semiconductor chip and a lead member disposed on an insulating circuit substrate using a bonding layer including a sintering material has been studied. However, sometimes, due to the pressure and heat for sintering the bonding layer, the lead member is deformed, resulting in a disconnection between the lead member and the bonding layer.

[0012] In view of the above problems, an object is to provide a semiconductor device and a method for manufacturing the same, which can suppress deformation of the lead member caused by pressurization when a semiconductor chip and a lead member are joined using a joining layer including a sintered material, and can suppress the occurrence of non-joining between the semiconductor chip and the joining layer.

[0013] Solutions for solving problems

[0014] The main purpose of a technical solution disclosed in the present invention is a semiconductor device, wherein the semiconductor device comprises: an insulating circuit substrate, which has an insulating plate and a conductive layer arranged on the insulating plate; a semiconductor chip, which is arranged on the conductive layer; a bonding layer, which is arranged on the semiconductor chip and includes a sintering material; and a lead member, which has a bonding portion arranged on the bonding layer and a beam portion continuous from the bonding portion, the bonding layer having a central area directly below the bonding portion and a peripheral area further outward than the central area, and the sintering density of the portion directly below the lead member in the peripheral area is lower than the sintering density of the portion other than the portion directly below the lead member in the peripheral area.

[0015] The main purpose of another technical solution of the present invention is a method for manufacturing a semiconductor device, wherein the method for manufacturing a semiconductor device includes the following steps: preparing a lead member, the lead member having a joint portion and a beam portion continuous from the joint portion; preparing a press jig having an opening portion; configuring the joint portion on a semiconductor chip with the aid of a sintered material, the semiconductor chip being arranged on a conductive layer of an insulating circuit substrate having an insulating plate and a conductive layer arranged on the insulating plate; configuring a press jig on the joint portion, the sintered material, the semiconductor chip, and the conductive layer in a manner such that the opening portion overlaps with the beam portion; and pressurizing and heating the joint portion, the sintered material, the semiconductor chip, and the conductive layer using the press jig.

[0016] Effects of the Invention

[0017] According to the present disclosure, a semiconductor device and a method for manufacturing the same can be provided, which can suppress deformation of the lead member caused by pressurization when a semiconductor chip and a lead member are bonded using a bonding layer including a sintered material, and can suppress the occurrence of non-bonding between the semiconductor chip and the bonding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a cross-sectional view of the semiconductor device according to the first embodiment.

[0019] Figure 2 It is a cross-sectional view of a part of the semiconductor device according to the first embodiment.

[0020] Figure 3 It is a top view of a part of the semiconductor device according to the first embodiment.

[0021] Figure 4 It is a cross-sectional view of the sintered material of the semiconductor device according to the first embodiment.

[0022] Figure 5 This is a cross-sectional view of another sintered material of the semiconductor device according to the first embodiment.

[0023] Figure 6 The diagram is a cross-sectional view showing the steps of the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Figure 7 The method for manufacturing a semiconductor device according to the first embodiment Figure 6 Process cross-sectional view.

[0025] Figure 8 The method for manufacturing a semiconductor device according to the first embodiment Figure 7 Process cross-sectional view.

[0026] Fig. 9 The method for manufacturing a semiconductor device according to the first embodiment Figure 8 Process cross-sectional view.

[0027] Fig.10 is with Fig. 9 The corresponding top view.

[0028] Fig.11 It is a cross-sectional view showing the steps of the method for manufacturing the semiconductor device according to the first comparative example.

[0029] Fig.12 It is a cross-sectional view showing the steps of a method for manufacturing a semiconductor device according to the second comparative example.

[0030] Fig.13 It is a process plan view of the method for manufacturing the semiconductor device according to the second embodiment.

[0031] Fig.14 It is a process plan view of the manufacturing method of the semiconductor device of the third embodiment.

[0032] Fig.15 It is a cross-sectional view showing the steps of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0033] Fig.16 It is a cross-sectional view showing the steps of the method for manufacturing a semiconductor device according to the fifth embodiment.

[0034] Fig.17 It is a cross-sectional view showing the steps of the method for manufacturing a semiconductor device according to the sixth embodiment.

[0035] Fig.18 It is a cross-sectional view showing the steps of the method for manufacturing a semiconductor device according to the seventh embodiment.

[0036] Fig.19 It is a cross-sectional view of the process of the manufacturing method of the semiconductor device of the 8th embodiment. DETAILED DESCRIPTION

[0037] Hereinafter, the first to eighth embodiments will be described with reference to the accompanying drawings. In the description of the accompanying drawings, the same or similar parts are marked with the same or similar figure marks, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane dimensions, the ratio of thickness of each layer, etc. are sometimes different from the actual. In addition, the drawings also include parts with different dimensional relationships and ratios. In addition, the first to eighth embodiments shown below illustrate devices and methods for concretizing the technical idea of ​​the present invention. The technical idea of ​​the present invention does not specify the material, shape, structure, configuration, etc. of the structural components as the following.

[0038] In addition, the definitions of up and down directions in the following description are only for the convenience of explanation and do not limit the technical concept of the present invention. For example, it is natural that if the object is rotated 90° to observe, the up and down is converted to the left and right reading, and if it is rotated 180° to observe, the up and down is reversed to read.

[0039] (First embodiment)

[0040] <Structure of Semiconductor Device>

[0041] like Figure 1 As shown, the semiconductor device (semiconductor module) of the first embodiment includes an insulating circuit substrate 1, a semiconductor chip 3 provided on the insulating circuit substrate 1, and a lead member (also called "lead frame" or "terminal", etc.) 4 provided on the semiconductor chip 3 and the insulating circuit substrate 1.

[0042] The insulating circuit substrate 1 includes an insulating plate 11, conductive layers (metal pattern layers) 12a and 12b provided on the main surface (upper surface) of one side of the insulating plate 11 and separated from each other, and a conductive layer (metal pattern layer) 13 provided on the main surface (lower surface) of the other side of the insulating plate 11. A semiconductor chip 3 is bonded to the conductive layer 12a of the insulating circuit substrate 1 via a bonding layer 2a. One end of a lead member 4 is bonded to the semiconductor chip 3 via a bonding layer 2b. The other end of the lead member 4 is bonded to the conductive layer 12b of the insulating circuit substrate 1 via a bonding layer 2c.

[0043] The insulating circuit substrate 1 may be, for example, a direct copper bonded (DCB) substrate, an active brazing (AMB) substrate, etc. The insulating plate 11 may be, for example, a ceramic substrate made of any material such as alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or a resin insulating substrate made of a polymer material. The conductive layers 12a, 12b, and the conductive layer 13 may be, for example, made of a conductor foil of copper (Cu), aluminum (Al), or the like.

[0044] The bonding layers 2a to 2c are bonding layers (also referred to as "sintered bonding layers") made of porous (porous) sintered materials, respectively, and have voids (pores) between metal particles constituting the sintered materials. As metal particles constituting the sintered materials, for example, gold (Au), silver (Ag), or copper (Cu) having a particle size of several nanometers or more and several micrometers or less is used. The bonding layers 2a to 2c have, for example, a thermal conductivity of 150 W / mK or more and 400 W / mK or less, a thermal conductivity of about 19×10 -16 / ℃ thermal expansion coefficient and melting point of about 960℃. Therefore, the bonding layers 2a~2c have stable strength at the operating temperature of the semiconductor device (for example, above 150℃ and below 170℃). The sintering material before sintering the bonding layers 2a~2c is a mixture of fine metal particles coated with organic matter and an organic solvent. By pressurizing and heating the sintering material while arranging it between the bonding objects, the organic solvent and the coated organic matter are vaporized, and the exposed fine metal particles are fused and sintered to form the bonding layers 2a~2c.

[0045] The bonding layers 2a to 2c may be made of the same material or different materials. The bonding layers 2a to 2c may have the same thickness or different thicknesses. The bonding layers 2a to 2c may be formed simultaneously or separately. For example, when the bonding layers 2a and 2b are formed simultaneously, it is preferred that the bonding layers 2a and 2b have the same thickness.

[0046] The semiconductor chip 3 is arranged in a manner that the lower surface is opposite to the upper surface of the conductive layer 12a. As the semiconductor chip 3, for example, an insulated gate bipolar transistor (IGBT), a field effect transistor (FET), an electrostatic induction (SI) thyristor, a gate turn-off (GTO) thyristor, a reflux diode (FWD), etc. can be used. The semiconductor chip 3 can be composed of a silicon (Si) substrate, for example, or it can be composed of a compound semiconductor substrate using wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3). The conductive layer 12a is bonded to the lower surface electrode of the semiconductor chip 3 by means of a bonding layer 2a. The lead member 4 is bonded to the upper surface electrode of the semiconductor chip 3 by means of a bonding layer 2b. For example, when the semiconductor chip 3 is an IGBT, the lower surface electrode is a collector and the upper surface electrode is an emitter.

[0047] exist Figure 1 One semiconductor chip 3 is shown as an example, but the number of semiconductor chips can be appropriately set according to the current capacity of the semiconductor module, and more than two semiconductor chips may be provided. Figure 1 Although one lead member 4 is illustrated in the figure, the number of lead members can be appropriately set according to the number of semiconductor chips, and two or more lead members may be provided.

[0048] The semiconductor device of the first embodiment further includes a sealing resin 5 that seals the insulating circuit substrate 1 , the semiconductor chip 3 , the lead members 4 , the bonding layers 2 a to 2 c , and the like, and a case 6 that is provided around the sealing resin 5 .

[0049] The sealing resin 5 includes, for example, epoxy resin, phenolic resin, maleimide resin and other resins as a main agent. The sealing resin 5 may include an inorganic filler (filler) in addition to the main agent. The inorganic filler may be, for example, a metal oxide or a metal nitride, such as a monomer of fused silica, silicon dioxide (silicon oxide), aluminum oxide, aluminum hydroxide, titanium dioxide, zirconium oxide, aluminum nitride, talc, clay, mica or glass fiber, or a mixture of two or more thereof.

[0050] The housing 6 is made of, for example, a resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT). An external terminal (not shown) that can be connected to an external circuit may be mounted on the housing 6. The external terminal (not shown) may be connected to the semiconductor chip 3 or the conductive layers 12a and 12b via a bonding wire (not shown), or may be connected to the semiconductor chip 3 or the conductive layers 12a and 12b via a bonding layer (not shown) such as solder or a sintered material.

[0051] The semiconductor device of the first embodiment further includes a cooler (heat sink) 14 provided under the insulating circuit substrate 1. The cooler 14 is bonded to the conductive layer 13 of the insulating circuit substrate 1 by means of a bonding layer 2d. The bonding layer 2d is composed of, for example, a sintered material, solder, or a thermal interface material (TIM). As a TIM, a thermally conductive material (thermal conductive compound) such as a thermally conductive grease, an elastomer sheet, a room temperature curing (RTV) rubber, a gel, a phase change material, or a silver solder can be used. The cooler 14 is made of a metal such as copper (Cu) or aluminum (Al). The cooler 14 may be a structure in which a heat sink is provided on the top plate, or may be a flat plate-like structure in which no heat sink is provided under the top plate.

[0052] Figure 2 Yes Figure 1 The insulating circuit substrate 1, the semiconductor chip 3, the lead member 4, and the bonding layers 2a to 2c are shown in a cross-sectional view with extraction. Figure 3 is with Figure 2 The corresponding top view. Figure 3 The cross section observed in the AA direction is Figure 2 correspond. Figure 4 It is a top view of the bonding layer 2b. Figure 5 It is a top view of the bonding layer 2c.

[0053] like Figure 2 and Figure 3 As shown, the lead member 4 includes a bonding portion 41, a beam portion 42 provided in a manner extending continuously from the bonding portion 41, and a bonding portion 43 provided continuously from the beam portion 42. The bonding portion 41 is a portion bonded to the upper surface of the semiconductor chip 3 by means of the bonding layer 2b. The bonding portion 41 has a substantially rectangular planar pattern and has a lower surface parallel to the upper surface of the semiconductor chip 3. The bonding portion 43 is a portion bonded to the upper surface of the conductive layer 12b of the insulating circuit substrate 1 by means of the bonding layer 2c. The bonding portion 43 has a substantially rectangular planar pattern and has a lower surface parallel to the upper surface of the conductive layer 12b. The horizontal height (height in the vertical direction) of the bonding portion 41 is higher than the horizontal height (height in the vertical direction) of the bonding portion 43 by an amount corresponding to the thickness of the bonding layer 2a and the semiconductor chip 3.

[0054] The beam portion 42 includes: a first erected portion, which is erected from the upper surface of the joint portion 41 and extends in the vertical direction; a second erected portion, which is erected from the upper surface of the joint portion 43 and extends in the vertical direction; and a central portion, which is bent in an L-shape from the upper ends of the first erected portion and the second erected portion and extends in the horizontal direction. The length of the first erected portion in the vertical direction is shorter than the length of the second erected portion in the vertical direction, so that the central portion of the beam portion 42 is horizontal.

[0055] like Figure 3As shown, the insulating plate 11 and the conductive layers 12a and 12b of the insulating circuit substrate 1 have a substantially rectangular planar pattern. The configuration position and number of the conductive layers 12a and 12b are not limited thereto. The bonding layer 2a has a substantially rectangular planar pattern. The semiconductor chip 3 has a substantially rectangular planar pattern. The size of the planar pattern of the semiconductor chip 3 is smaller than the size of the planar pattern of the bonding layer 2a. The periphery of the semiconductor chip 3 is located on the inner side than the periphery of the bonding layer 2a.

[0056] like Figure 2 to Figure 4 As shown, the bonding layer 2b has a substantially rectangular planar pattern. The size of the planar pattern of the bonding layer 2b is smaller than the size of the planar pattern of the semiconductor chip 3, and larger than the size of the planar pattern of the bonding portion 41. The periphery of the bonding layer 2b is located at an inner side than the periphery of the semiconductor chip 3, and is located at an outer side than the periphery of the bonding portion 41.

[0057] The bonding layer 2b includes a central region 21 and peripheral regions 22 and 23 provided around the central region 21. The central region 21 is located directly below the bonding portion 41 of the lead member 4 and is bonded to the bonding portion 41.

[0058] The peripheral regions 22 and 23 are located outside the central region 21 when viewed from above, and are not joined to the joint 41. The peripheral region 22 of the peripheral regions 22 and 23 includes a portion located directly below (below) the beam portion 42 of the lead member 4. The peripheral region 22 is adjacent to one side of a rectangle that is a plane pattern of the central region 21, and has a substantially rectangular plane pattern. The peripheral region 23 of the peripheral regions 22 and 23 is a portion other than the peripheral region 22 including a portion located directly below (below) the beam portion 42 of the lead member 4. The peripheral region 23 surrounds the central region 21 and the peripheral region 22, and has a substantially C-shaped plane pattern. The peripheral region 23 includes an area on the side opposite to the peripheral region 22 relative to the central region 21 in the extension direction of the beam portion 42 of the lead member 4.

[0059] The central region 21 and the peripheral region 23 are pressurized when the bonding layer 2b is bonded, and the peripheral region 22 is not pressurized when the bonding layer 2b is bonded. Therefore, the sintering density of the central region 21 and the peripheral region 23 is higher than the sintering density of the peripheral region 22. In this specification, the sintering density refers to the density of the metal particles constituting the sintered material, which is the ratio of the volume of the bonding layer excluding the open pores and the closed pores to the overall volume of the bonding layer including the open pores and the closed pores. In addition, the porosity between the metal particles constituting the sintered material of the central region 21 and the peripheral region 23 is lower than the porosity between the metal particles constituting the sintered material of the peripheral region 22.

[0060] like Figure 2 , Figure 3 as well as Figure 5 As shown, the bonding layer 2c has a substantially rectangular planar pattern. The planar pattern of the bonding layer 2c has a size larger than the planar pattern of the bonding portion 43. The outer periphery of the bonding layer 2c is located outside the outer periphery of the bonding portion 43.

[0061] The bonding layer 2c includes a central region 24 and peripheral regions 25 and 26 provided around the central region 24. The central region 24 is located directly below the bonding portion 43 of the lead member 4 and is bonded to the bonding portion 43.

[0062] The peripheral regions 25 and 26 are located outside the central region 24 in a plan view and are not joined to the joint 43. The peripheral region 25 of the peripheral regions 25 and 26 includes a portion located directly below (below) the beam portion 42 of the lead member 4. The peripheral region 25 is adjacent to one side of a rectangle that is a plane pattern of the central region 24 and has a substantially rectangular plane pattern. The peripheral region 26 of the peripheral regions 25 and 26 is a portion other than the peripheral region 25 including a portion located directly below (below) the beam portion 42 of the lead member 4. The peripheral region 26 surrounds the central region 24 and the peripheral region 25 and has a substantially C-shaped plane pattern.

[0063] The central region 24 and the peripheral region 26 are pressurized when the bonding layer 2c is bonded, and the peripheral region 25 is not pressurized when the bonding layer 2c is bonded. Therefore, the sintering density of the central region 24 and the peripheral region 26 is higher than the sintering density of the peripheral region 25. In addition, the porosity between the metal particles constituting the sintered material of the central region 24 and the peripheral region 26 is lower than the porosity between the metal particles constituting the sintered material of the peripheral region 25.

[0064] According to the semiconductor device of the first embodiment, by bonding the semiconductor chip 3 to the lead member 4 via the bonding layer 2 a made of a sintered material, higher heat resistance, higher heat dissipation, and higher reliability can be achieved compared to the case of bonding via solder.

[0065] <Method for manufacturing semiconductor device>

[0066] Next, an example of a method for manufacturing (assembling method) the semiconductor device according to the first embodiment will be described.

[0067] First, an insulating circuit substrate 1 having conductive layers 12a and 12b provided on the upper surface of an insulating plate 11 is prepared (see Figure 6 Then, the semiconductor chip 3 is arranged on the conductive layer 12a of the insulating circuit substrate 1 via a sintering material (see Figure 6). The sintered material may be a sheet-like sintered material (sintered sheet) or a paste-like sintered material (sintered paste). The sintered material may be arranged on the conductive layer 12a by paste printing or dispensing. Alternatively, the sintered material may be installed on the lower surface of the semiconductor chip 3, and the sintered material installed on the lower surface of the semiconductor chip 3 may be arranged on the conductive layer 12a.

[0068] Next, using a mold (not shown) disposed on the lower surface side of the insulating circuit substrate 1 and a mold (not shown) disposed on the upper surface side of the semiconductor chip 3, the insulating circuit substrate 1, the sintering material, and the semiconductor chip 3 are pressurized and heated in their stacking direction, so that the sintering material produces a sintering reaction. For example, the pressure is set to a level of 1 MPa to 60 MPa, the heating temperature is set to a level of 150°C to 350°C, and the heating time is set to a level of 1 minute to 5 minutes. As a result, Figure 6 As shown, the semiconductor chip 3 is bonded to the conductive layer 12a of the insulating circuit substrate 1 via the bonding layer 2a.

[0069] Then, if Figure 7 As shown, the lead member 4 is arranged on the upper surface of the semiconductor chip 3 and the conductive layer 12b with the help of sintered materials 2x and 2y. The sintered materials 2x and 2y can be arranged on the upper surface of the semiconductor chip 3 and the conductive layer 12b in the form of a sheet of sintered material (sintered sheet), or a paste of sintered material (sintered paste) can be applied on the upper surface of the semiconductor chip 3 and the conductive layer 12b. Alternatively, the sintered materials 2x and 2y can be installed on the lower surface of the lead member 4, and the sintered materials 2x and 2y installed on the lower surface of the lead member 4 can be arranged on the upper surface of the semiconductor chip 3 and the conductive layer 12b.

[0070] Then, if Figure 8 As shown, a protective sheet 7, a pressurizing jig 8, and a pressurizing plate 9 are prepared (prepared). The protective sheet 7 is made of a material and thickness that can be deformed by pressurization. As the material of the protective sheet 7, for example, a fluorine-based resin such as polytetrafluoroethylene (PTFE) or a polyimide resin can be used. The thickness of the protective sheet 7 is, for example, 0.1 mm or more and 1.0 mm or less, but is not limited thereto.

[0071] The press jig 8 is made of metal such as stainless steel (SUS). The press jig 8 is provided with an opening 8a. Steps 8b and 8c are provided on the lower surface of the press jig 8. The step portions 8b and 8c have shapes corresponding to the step portions formed by laminating the insulating circuit substrate 1, the bonding layer 2a, the semiconductor chip 3, the sintered materials 2x and 2y, and the lead member 4.

[0072] The pressurizing plate 9 is made of metal such as stainless steel (SUS). The pressurizing plate 9 has a flat plate shape. In addition, the protective sheet 7 and the pressurizing plate 9 may not necessarily be arranged. In addition, a buffer material such as a carbon sheet may be arranged between the protective sheet 7 and the pressurizing jig 8.

[0073] Then, if Fig. 9 As shown, a press jig 8 is arranged on the insulating circuit substrate 1, the bonding layer 2a, the semiconductor chip 3, the sintered materials 2x, 2y and the lead member 4 through a protective sheet 7, and a press plate 9 is arranged on the press jig 8. The opening 8a of the press jig 8 overlaps with the beam portion 42 of the lead member 4, and the beam portion 42 is accommodated inside. In this state, the insulating circuit substrate 1, the bonding layer 2a, the semiconductor chip 3, the sintered materials 2x, 2y and the lead member 4 are pressurized and heated in their stacking direction using a mold (not shown) arranged on the lower surface side of the insulating circuit substrate 1 and a mold (not shown) arranged on the upper surface side of the press plate 9, so that the sintered materials 2x, 2y produce a sintering reaction. For example, the pressure is set to a level of 1 MPa or more and 60 MPa or less, the heating temperature is set to a level of 150°C or more and 350°C or less, and the heating time is set to a level of 1 minute or more and 5 minutes or less.

[0074] Fig. 9 The arrows in the figure schematically indicate the pressurized state. By pressurizing the press jig 8, the conductive layers 12a, 12b, the sintered materials 2x, 2y, the semiconductor chip 3, and the bonding portions 41, 43 of the insulating circuit substrate 1 are selectively pressurized through the protective sheet 7. The beam portion 42 of the lead member 4 is accommodated in the opening portion 8a of the press jig 8, and is therefore not pressurized by the press jig 8.

[0075] Fig.10 is with Fig. 9 The corresponding top view, Fig.10 The protective sheet 7 and the pressurizing plate 9 are omitted, and the components hidden under the pressurizing jig 8 are schematically indicated by dotted lines. Fig.10 As shown, the outer periphery of the press jig 8 is substantially consistent with the outer periphery of the conductive layers 12a and 12b. In addition, the outer periphery of the press jig 8 may be located inside the outer periphery of the conductive layers 12a and 12b, or may be located outside the outer periphery of the conductive layers 12a and 12b. The press jig 8 applies pressure to the ends of the conductive layers 12a and 12b of the insulating circuit substrate 1, but it is not necessary to apply pressure to the ends.

[0076] The opening 8a of the press jig 8 overlaps with the beam 42 of the lead member 4. The size of the plane pattern of the opening 8a is larger than the size of the plane pattern of the beam 42. In the direction orthogonal to the extension direction of the beam 42 (the width direction of the beam 42), the width W2 of the opening 8a is wider than the width W1 of the beam 42. In the extension direction of the beam 42 (the length direction of the beam 42), the length L1 of the opening 8a is longer than the length L2 of the beam 42. The opening 8a has a substantially rectangular plane pattern, but the shape of the plane pattern is not limited to a rectangle, and may be, for example, a circle.

[0077] As a result, the sintered materials 2x and 2y are sintered to form the bonding layers 2b and 2c. Figure 2 and Figure 3 As shown, the semiconductor chip 3 is bonded to the bonding portion 41 of the lead member 4 by means of the bonding layer 2b, and the conductive layer 12b is bonded to the bonding portion 43 of the lead member 4 by means of the bonding layer 2c. The central region 21 and the peripheral region 23 of the bonding layer 2b in the bonding layer 2b are pressurized, but the peripheral region 22 is not pressurized. Therefore, the sintering density of the central region 21 and the peripheral region 23 is higher than the sintering density of the peripheral region 22. In addition, the void ratio between the metal particles in the central region 21 and the peripheral region 23 is lower than the void ratio between the metal particles in the peripheral region 22. In addition, the central region 24 and the peripheral region 26 of the bonding layer 2c in the bonding layer 2c are pressurized, but the peripheral region 25 is not pressurized. Therefore, the sintering density of the central region 24 and the peripheral region 26 is higher than the sintering density of the peripheral region 25. In addition, the void ratio between the metal particles in the central region 24 and the peripheral region 26 is lower than the void ratio between the metal particles in the peripheral region 25.

[0078] Fig.10 The region including the portion of the sintered material 2x directly below the beam portion 42 and the portion of the sintered material 2x exposed in the opening 8a becomes the non-pressurized peripheral region 22 of the bonding layer 2b. Fig.10 The region including the portion of the sintered material 2y directly below the beam portion 42 and the portion of the sintered material 2y exposed in the opening 8a becomes the non-pressurized peripheral region 25 of the bonding layer 2c. Figure 4 The planar pattern of the peripheral region 22 of the illustrated bonding layer 2b and Figure 5 The planar pattern of the peripheral region 25 of the bonding layer 2c shown is similar to that of the Fig.10The width W2 of the opening 8a shown is close to being substantially the same as the width W1 of the beam 42 and corresponds to the shape formed when there is almost no portion of the sintered materials 2x and 2y exposed in the opening 8a. In this case, the portion directly below the beam 42 of the sintered material 2x is substantially consistent with the peripheral region 22 of the bonding layer 2b, and the portion directly below the beam 42 of the sintered material 2y is substantially consistent with the peripheral region 25 of the bonding layer 2c. Then, the protective sheet 7, the press jig 8, and the press plate 9 are removed from the laminated structure of the insulating circuit substrate 1, the bonding layers 2a to 2c, the semiconductor chip 3, and the lead member 4.

[0079] Next, the cooler 14 is bonded to the lower surface of the insulating circuit substrate 1 via the bonding layer 2d. Next, the housing 6 is arranged on the cooler 14 so as to surround the insulating circuit substrate 1, the semiconductor chip 3, the lead member 4, and the bonding layers 2a to 2d. Next, the sealing resin 5 is filled inside the housing 6 to seal the insulating circuit substrate 1, the semiconductor chip 3, the lead member 4, and the bonding layers 2a to 2d. As a result, the Figure 1 A semiconductor device according to the first embodiment is shown.

[0080] Here, a method for manufacturing a semiconductor device according to a first comparative example is described. In the method for manufacturing a semiconductor device according to the first comparative example, Fig.11 As shown, the method for manufacturing the semiconductor device of the first embodiment is different from that of manufacturing the semiconductor device of the first embodiment in that a mold (not shown) is used to pressurize the entire lead member 4 via a cushioning material 7x made of a carbon sheet. Fig.11 The arrows in the figure schematically indicate the pressurized state. In the method for manufacturing the semiconductor device of the first comparative example, not only the bonding portions 41 and 43 of the lead member 4 are pressurized, but also the beam portion 42 is pressurized. Therefore, the beam portion 42 is sometimes deformed to cause the bonding portions 41 and 43 to be suspended, resulting in non-bonding between the bonding portions 41 and 43 and the sintered materials 2x and 2y.

[0081] On the other hand, according to the method for manufacturing a semiconductor device according to the first embodiment, Fig. 9 and Fig.10 As shown, by overlapping the opening 8a of the press jig 8 with the beam 42 of the lead member 4, pressurization is performed while the beam 42 is exposed from the opening 8a, thereby suppressing the beam 42 from being pressurized. Therefore, deformation of the lead member 4 can be suppressed, and non-bonding between the bonding portions 41, 43 and the sintered materials 2x, 2y can be suppressed.

[0082] Next, a method for manufacturing a semiconductor device according to a second comparative example is described. In the method for manufacturing a semiconductor device according to the second comparative example, Fig.12As shown, the method for manufacturing the semiconductor device of the first embodiment is different from that of manufacturing the semiconductor device of the first embodiment in that the pressurizing jigs 8y and 8z individually pressurize the bonding portions 41 and 43 of the lead member 4 . Fig.12 The arrows in the figure schematically indicate the pressurized state. In the method for manufacturing a semiconductor device of the second comparative example, only the portion of the lead member 4 directly below the bonding portions 41 and 43 is pressurized, and the portion of the conductive layer 12a and 12b other than the portion directly below the bonding portions 41 and 43 is not pressurized, so that warping sometimes occurs in the insulating circuit substrate 1, and uniform pressurization cannot be performed.

[0083] On the other hand, according to the method for manufacturing a semiconductor device according to the first embodiment, Fig. 9 and Fig.10 As shown, the press jig 8 applies pressure not only to the areas directly below the bonding portions 41 and 43 of the lead member 4, but also to the areas of the conductive layers 12a and 12b other than the areas directly below the bonding portions 41 and 43. Therefore, the warping of the insulating circuit board 1 can be suppressed (corrected) and the pressure can be applied uniformly.

[0084] (Second embodiment)

[0085] In the method for manufacturing a semiconductor device according to the second embodiment of the present disclosure, Fig.13 As shown in FIG. 1 , the pressurizing jig 8 for pressurizing the sintering materials 2x and 2y is divided into a first member 81 and a second member 82. Fig.10 The semiconductor device according to the first embodiment shown has a different method of manufacturing.

[0086] The first member 81 and the second member 82 have a substantially rectangular planar pattern. The first member 81 and the second member 82 are arranged to be separated from each other. The space between the first member 81 and the second member 82 constitutes an opening 8a. The other steps of the method for manufacturing a semiconductor device according to the second embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore repeated descriptions are omitted.

[0087] According to the method for manufacturing a semiconductor device of the second embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the pressurizing jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0088] (Third embodiment)

[0089] In the method for manufacturing a semiconductor device according to the third embodiment of the present disclosure, Fig.14 As shown in FIG. 1 , the pressurizing jig 8 for pressurizing the sintering materials 2x and 2y is divided into a first member 81 and a second member 82. Fig.10 The semiconductor device according to the first embodiment shown has a different method of manufacturing.

[0090] The first member 81 and the second member 82 have an L-shaped plane pattern. The first member 81 and the second member 82 are arranged so that their ends overlap each other. The thickness of the overlapping ends of the first member 81 and the second member 82 is thinner than the thickness of other parts, and the thickness of the overlapping ends of the first member 81 and the second member 82 is the same as the thickness of other parts. The space between the first member 81 and the second member 82 constitutes an opening 8a. The other steps of the method for manufacturing a semiconductor device according to the third embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore repeated descriptions are omitted.

[0091] According to the method for manufacturing a semiconductor device of the third embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the pressurizing jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0092] (Fourth embodiment)

[0093] In the method for manufacturing a semiconductor device according to the fourth embodiment of the present disclosure, Fig.15 As shown in FIG. 1 , the opening 8a of the pressurizing jig 8 for pressurizing the sintering materials 2x and 2y is narrow. Fig. 9 The manufacturing method of the semiconductor device of the first embodiment shown is different. The end of the opening 8a is located on the bent portion of the beam 42 of the lead member 4. The length L1 of the opening 8a in the extending direction of the beam 42 is shorter than the length L2 of the beam 42. The other steps of the manufacturing method of the semiconductor device of the fourth embodiment are substantially the same as those of the manufacturing method of the semiconductor device of the first embodiment, and therefore repeated descriptions are omitted.

[0094] According to the method for manufacturing a semiconductor device of the fourth embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the pressurizing jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0095] (Fifth embodiment)

[0096] In the method for manufacturing a semiconductor device according to the fifth embodiment of the present disclosure, Fig.16 As shown, the shapes of the lead member 4 and the pressurizing jig 8 are similar to Fig. 9 The manufacturing method of the semiconductor device of the first embodiment shown is different. The lead member 4 has a C-shaped cross-sectional shape. The lead member 4 has joints 41, 43 and a beam portion 42 continuous from the joints 41, 43. The beam portion 42 does not have a portion standing up in the vertical direction, but only has a portion extending in the horizontal direction. The step portions 8b, 8c on the lower surface side of the press jig 8 have a shape corresponding to the shape of the lead member 4. The other steps of the manufacturing method of the semiconductor device of the fifth embodiment are substantially the same as the manufacturing method of the semiconductor device of the first embodiment, so repeated descriptions are omitted.

[0097] According to the method for manufacturing a semiconductor device of the fifth embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the pressurizing jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0098] (Sixth embodiment)

[0099] In the method for manufacturing a semiconductor device according to the sixth embodiment of the present disclosure, Fig.17 As shown in FIG. 1 , the protective sheet 7 is provided with an opening 7a. Fig. 9 The manufacturing method of the semiconductor device of the first embodiment shown is different. The opening 7a of the protection sheet 7 is provided at a position corresponding to the opening 8a of the press jig 8. The other steps of the manufacturing method of the semiconductor device of the sixth embodiment are substantially the same as those of the manufacturing method of the semiconductor device of the first embodiment, and therefore repeated descriptions are omitted.

[0100] According to the method for manufacturing a semiconductor device of the sixth embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the press jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0101] (Seventh Implementation Method)

[0102] Regarding the method for manufacturing a semiconductor device according to the seventh embodiment of the present disclosure, Fig.18 As shown in FIG. 1 , the step portions 8b and 8c on the lower surface side of the pressurizing jig 8 have finer steps. Fig. 9 The manufacturing method of the semiconductor device of the seventh embodiment is different from that of the first embodiment. The step portions 8b and 8c are set to a shape corresponding to the step formed by the bonding layer 2a, the semiconductor chip 3, the sintered materials 2x and 2y, and the bonding portions 41 and 43, but they do not have to be consistent layer by layer. For example, the step portions 8b and 8c may also have a step layer opposite to the upper surface of the bonding portions 41 and 43. The other steps of the manufacturing method of the semiconductor device of the seventh embodiment are substantially the same as those of the manufacturing method of the semiconductor device of the first embodiment, so repeated descriptions are omitted.

[0103] According to the method for manufacturing a semiconductor device of the seventh embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the pressurizing jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0104] (Eighth Implementation Method)

[0105] In the method for manufacturing a semiconductor device according to the eighth embodiment of the present disclosure, Fig.19 As shown, the lower surface of the pressurizing jig 8 is flat without a step portion. Fig. 9The manufacturing method of the semiconductor device of the first embodiment shown is different. A buffer material 15 is provided between the lower surface of the pressurizing jig 8 and the protective sheet 7. The buffer material 15 can be compressed and deformed by the pressurization of the pressurizing jig 8. The buffer material 15 is composed of, for example, a carbon sheet or a PTFE sheet. The other steps of the manufacturing method of the semiconductor device of the eighth embodiment are substantially the same as those of the manufacturing method of the semiconductor device of the first embodiment, and therefore repeated descriptions are omitted.

[0106] According to the method for manufacturing a semiconductor device of the eighth embodiment, the opening 8a overlaps with the beam 42 of the lead member 4, exposing the beam 42, thereby suppressing deformation of the lead member 4 and suppressing non-bonding between the sintered materials 2x, 2y and the bonding portions 41, 43. In addition, the press jig 8 presses not only the portion directly below the bonding portions 41, 43 of the lead member 4 but also the portion of the conductive layers 12a, 12b other than the portion directly below the bonding portions 41, 43, thereby suppressing warping of the insulating circuit substrate 1 and enabling uniform pressurization.

[0107] (Other embodiments)

[0108] As described above, the present invention has been described using the first to eighth embodiments, but the description and drawings constituting part of the present disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and application techniques will be apparent to those skilled in the art from the present disclosure.

[0109] For example, in the first to eighth embodiments, the case where one opening 8a is provided in the press jig 8 is exemplified. However, in the case where there are a plurality of semiconductor chips and a plurality of lead members connected to the plurality of semiconductor chips, a plurality of openings respectively overlapping with the beams of the plurality of lead members may be provided in the press jig 8. Alternatively, one opening collectively overlapping with the beams of the plurality of lead members may be provided in the press jig 8.

[0110] In addition, in the first to eighth embodiments, the case where the sintered materials 2x and 2y are sintered to form the bonding layers 2b and 2c after the sintered material for bonding the insulating circuit substrate 1 and the semiconductor chip 3 is sintered to form the bonding layer 2a is illustrated. However, the sintered material for bonding the insulating circuit substrate 1 and the semiconductor chip 3 may be arranged but not sintered, and the sintered materials 2x and 2y may be sintered by pressurization and heating to form the bonding layers 2b and 2c, while the sintered material for bonding the insulating circuit substrate 1 and the semiconductor chip 3 may be sintered to form the bonding layer 2a.

[0111] In addition, the structures disclosed in the first to eighth embodiments can be appropriately combined within the scope that no contradiction occurs. In this way, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specific matters of the claims that are appropriate based on the above description.

[0112] Description of Reference Numerals

[0113] 1. Insulating circuit substrate; 2a~2d, bonding layer; 2x, 2y, sintering material; 3. Semiconductor chip; 4. Lead member; 5. Sealing resin; 6. Shell; 7. Protective sheet; 7a, opening; 7x, cushioning material; 8, 8x~8z, pressurizing jig; 8a, opening; 8b, 8c, step; 9, pressurizing plate; 11, insulating plate; 12a, 12b, 13, conductive layer; 14, cooler; 15, cushioning material; 21, 24, central area; 22, 23, 25, 26, peripheral area; 41, 43, bonding part; 42, beam part.

Claims

1. A semiconductor device, wherein: The semiconductor device comprises: An insulating circuit substrate comprising an insulating plate and a conductive layer disposed on the insulating plate; a semiconductor chip disposed on the conductive layer; a bonding layer, which is disposed on the semiconductor chip and includes a sintered material; as well as a lead member having a bonding portion provided on the bonding layer and a beam portion continuous from the bonding portion, The bonding layer includes a central region directly below the bonding portion and a peripheral region outside the central region. A sintering density of a portion of the peripheral region directly below the lead member is lower than a sintering density of a portion of the peripheral region other than directly below the lead member.

2. A method for manufacturing a semiconductor device, wherein: The method for manufacturing a semiconductor device comprises the following steps: preparing a lead member including a joining portion and a beam portion continuous from the joining portion; preparing a pressurizing jig having an opening; The bonding portion is arranged on a semiconductor chip by means of a sintered material, the semiconductor chip being arranged on the conductive layer of an insulating circuit substrate having an insulating plate and a conductive layer arranged on the insulating plate; disposing the pressurizing jig on the bonding portion, the sintered material, the semiconductor chip, and the conductive layer in such a manner that the opening portion overlaps the beam portion; as well as The bonding portion, the sintered material, the semiconductor chip, and the conductive layer are pressurized and heated by the press jig.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: A step portion is provided on the lower surface side of the pressurizing jig.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein: The size of the opening portion is larger than the size of the beam portion.

5. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein: In the length direction of the beam portion, the length of the opening portion is longer than the length of the beam portion.

6. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein: In the length direction of the beam portion, the length of the opening portion is shorter than the length of the beam portion.

7. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein: In the step of applying pressure using the press jig, the bonding portion, the sintered material, the semiconductor chip, and the conductive layer are pressurized by the press jig via a protective sheet.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: An opening is provided at a position of the protection sheet corresponding to the opening.

9. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein: In the step of applying pressure using the press jig, a press plate is disposed on the upper surface side of the press jig, and the bonding portion, the sintered material, the semiconductor chip, and the conductive layer are pressurized by the press plate and the press jig.

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