Stacked FET contact formation

Abstract

A semiconductor device and a method of manufacturing the same include a first lower device and a second lower device on a substrate. The first upper device is over the first lower device, and the second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and is in electrical contact with a top surface and sidewall surfaces of the first lower device. A second lower contact extends from a height above the second upper device and is in electrical contact with a top surface and sidewall surfaces of the second lower device. An insulating barrier is located between the first lower contact and the second lower contact.

Description

Background Art

[0001] The present invention relates generally to semiconductor device fabrication and, more particularly, to stacked transistor devices.

[0002] Forming transistor devices on top of each other can help increase the area density of integrated circuits, for example by forming complementary field effect transistors using two connecting devices of opposite polarity. However, when forming transistor devices on top of each other, it may be challenging to form contacts to the lower device, especially in the case of close spacing between horizontally adjacent devices. When forming stacked devices, contacts may need to penetrate multiple layers to reach the device below. Although the larger surface area at the interface between the contact and the device helps to reduce resistance, increasing the size of the lower device may make it difficult to bring adjacent devices closer. In addition, the electrical contact formed for devices that are very close together creates the risk of electrical short circuits between the contact and the upper device, as well as the risk of short circuits to adjacent devices. Summary of the invention

[0003] A semiconductor device includes a first lower device and a second lower device on a substrate. The first upper device is above the first lower device, and the second upper device is above the second lower device. The first lower contact extends from a certain height above the first upper device, and is in electrical contact with the top surface and sidewall surface of the first lower device, and extends laterally below the first upper device. The second lower contact extends from a certain height above the second upper device, and is in electrical contact with the top surface and sidewall surface of the second lower device, and extends laterally below the second upper device. The first lower contact extends from a certain height above the first upper device, and is in electrical contact with the top surface and sidewall surface of the first lower device. The second lower contact extends from a certain height above the second upper device, and is in electrical contact with the top surface and sidewall surface of the second lower device. An insulating barrier is located between the first lower contact and the second lower contact. The insulating barrier provides reliable electrical isolation between contacts to the lower device without the risk of shorting between adjacent structures. Furthermore, the lateral extension of the lower contact beneath the upper device increases the surface area of ​​the interface between the lower contact and the lower device, which reduces resistance.

[0004] A method for forming a semiconductor device includes forming a placeholder structure above a first lower device and a second lower device on a substrate. The first upper device and the second upper device are formed on a dielectric layer above the corresponding first lower device and the second lower device. The placeholder structure is selectively etched away to expose the top surface and sidewall surface of each of the first lower device and the second lower device. A conductive material is deposited, which is electrically in contact with the top surface and sidewall surface of each of the first lower device and the second lower device. A trench is etched in the conductive material, which divides the conductive material into a first lower contact and a second lower contact. A barrier structure is formed in the trench to electrically isolate the first lower contact and the second lower contact. The barrier structure provides reliable electrical isolation separated between contacts to the lower device without the risk of short circuits between adjacent structures. In addition, the placeholder structure creates a space for the lateral extension of the lower contact below the upper device, which increases the surface area of ​​the interface between the lower contact and the lower device and reduces the resistance.

[0005] A method of forming a semiconductor device includes forming a placeholder structure above and between a pair of lower devices. A dielectric layer is formed above the placeholder structure. The placeholder structure is etched away to leave a gap between the pair of lower devices and the dielectric layer. A conductor is deposited to fill the gap. A trench is etched in the conductor to form a contact to each device in the pair of lower devices. The trench provides reliable electrical isolation between the contacts to the lower devices without the risk of shorting between adjacent structures. In addition, the placeholder provides a lateral extension for the lower contact below the upper device, which increases the surface area of ​​the interface between the lower contact and the lower device and reduces the resistance.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following description will provide details of the preferred embodiments with reference to the following drawings, in which:

[0008] Figure 1 is a cross-sectional view of a step in fabricating contacts to a vertically stacked collection of semiconductor devices, showing the use of shallow trench isolation on a semiconductor substrate to form different device mesa regions, in accordance with an embodiment of the present invention;

[0009] Figure 2 is a cross-sectional view of a step in fabricating contacts to a vertically stacked set of semiconductor devices according to an embodiment of the present invention, showing formation of a pair of lower devices on respective device mesa regions of a semiconductor substrate;

[0010] Figure 3is a cross-sectional view of a step in fabricating contacts to a vertically stacked collection of semiconductor devices in accordance with an embodiment of the present invention showing a sacrificial placeholder structure formed in contact with a top surface and a side surface of each device in a lower portion of the device;

[0011] Figure 4 is a cross-sectional view of a step in fabricating a contact to a vertically stacked collection of semiconductor devices showing formation of an upper layer over a placeholder structure in accordance with an embodiment of the present invention;

[0012] Figure 5 is a cross-sectional view of a step in fabricating contacts to a vertically stacked set of semiconductor devices showing the formation of an upper semiconductor device in an upper layer vertically aligned over a corresponding lower device in accordance with an embodiment of the present invention;

[0013] Figure 6 is a cross-sectional view of a step in fabricating a contact to a vertically stacked set of semiconductor devices showing an etch penetrating an upper layer and exposing at a top surface of a placeholder structure in accordance with an embodiment of the present invention;

[0014] Figure 7 is a cross-sectional view of a step in fabricating a contact to a vertically stacked set of semiconductor devices showing etching that removes a placeholder structure to leave a gap that exposes a top surface and sidewall surfaces of an underlying device in accordance with an embodiment of the present invention;

[0015] Figure 8 is a cross-sectional view of a step in fabricating a contact to a vertically stacked set of semiconductor devices showing deposition of conductive material in the gap by removing placeholder structures to form a center contact structure in accordance with an embodiment of the present invention;

[0016] Fig. 9 is a cross-sectional view of a step in fabricating contacts to a vertically stacked set of semiconductor devices showing formation of a trench in the conductive material of a center contact structure to separate the center contact structure into two distinct contacts in accordance with an embodiment of the present invention;

[0017] Fig.10 is a cross-sectional view of a step in fabricating a contact to a vertically stacked set of semiconductor devices according to an embodiment of the present invention showing the formation of an electrical barrier structure in a trench that provides further electrical isolation between two contacts;

[0018] Fig.11 is a block diagram / flow chart of a method of forming a semiconductor device having vertically stacked transistor devices according to an embodiment of the present invention;

[0019] Fig.12is a cross-sectional view of a step in fabricating contacts to a vertically stacked collection of semiconductor devices showing back end wiring layers in electrical communication with the device contacts in accordance with an embodiment of the present invention; and

[0020] Fig.13 is a cross-sectional view of a step in fabricating contacts to a vertically stacked collection of semiconductor devices showing back end wiring layers in electrical communication with the device contacts, where the device contacts are formed off-center, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Stacked field effect transistors (FETs) can increase the area density of integrated chips, where devices are formed on multiple vertically stacked layers of a chip. To make electrical contact with the buried device, a via can be formed through the cover layer. The via can be filled with a conductive material that contacts the underlying device(s).

[0022] However, when forming devices close to each other, the conductive vias to the underlying device can be made thinner to reduce the risk of creating shorts between adjacent devices. Thinner vias are more likely to include defects, such as voids in their metal fill, which can interfere with device function. In addition, narrow vias can reduce the contact area between the via and the underlying device, as placement of the via can be challenging. Electrical contact with the sidewalls of the underlying device can also be challenging, further reducing the potential electrical contact area.

[0023] Instead of using a narrow via, a contact to the lower device can be formed by dividing a relatively thick via into two contacts connected to different corresponding devices. The thicker via can be etched to form a trench that divides the conductive material into two separate vias, with a dielectric liner formed between them to prevent short circuits. The relatively thick original contact structure reduces the risk of voids when depositing the conductive material and also makes it possible to make electrical contact along the sidewalls of the lower device, thereby reducing contact resistance.

[0024] Reference now Figure 1 , shows a cross-sectional view of a step in the fabrication of a stacked semiconductor device. A semiconductor substrate 102 is shown, which is divided into device regions 104 by shallow trench isolation (STI) regions 106. The device regions 104 establish locations where semiconductor devices can be formed in subsequent steps.

[0025] The semiconductor substrate 102 may be a bulk semiconductor substrate. In one example, the bulk semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for bulk semiconductor substrates include, but are not limited to, silicon, silicon germanium, silicon carbide, polycrystalline silicon, epitaxial silicon, amorphous silicon, and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not depicted in the current figures, the semiconductor substrate 102 may also be a semiconductor on insulator (SOI) substrate.

[0026] The STI regions 106 may be formed by any suitable process. For example, a photolithographic patterning process may be used to define a mask covering the device region 104, thereby exposing other portions of the substrate 102. A timed selective anisotropic etch (e.g., reactive ion etching (RIE)) may be used to remove substrate material in the exposed regions, leaving trenches in the substrate 102. The trenches in the substrate 102 may then be filled with any suitable dielectric material (e.g., silicon dioxide), which may be deposited using a chemical vapor deposition (CVD) process, which may then be polished to below the level of the top surface of the substrate 102 (or any other suitable height) using a chemical mechanical planarization (CMP) process.

[0027] In the photolithography process, a pattern is created by applying a photoresist to the surface to be etched. The photoresist is subjected to a pattern of radiation. A resist developer is then used to develop the pattern into the photoresist. After the patterning of the photoresist is completed, the portions covered by the photoresist are protected while the exposed areas are removed using a selective etching process that removes the unprotected areas.

[0028] RIE is a form of plasma etching in which the surface to be etched is placed on a radio frequency powered electrode during etching. Furthermore, during RIE, the surface to be etched presents an electrical potential that accelerates the etching species extracted from the plasma towards the surface, where the chemical etching reaction occurs in a direction perpendicular to the surface. Other examples of anisotropic etching include ion beam etching, plasma etching, or laser ablation.

[0029] As used herein, the term "selective" in reference to a material removal process means that the material removal rate for a first material is greater than the removal rate for at least another material of the structure to which the material removal process is being applied.

[0030] CMP can be performed using, for example, chemical or particulate slurries and mechanical forces to gradually remove upper layers of the device. The slurry can be formulated to be insoluble in, for example, the work function metal layer material, resulting in the CMP process being unable to proceed anywhere further than that layer.

[0031] Reference now Figure 2 , shows a cross-sectional view of a step in the fabrication of a stacked semiconductor device. A set of lower devices 200 are formed on a corresponding device region 104 of a substrate 102. The cross section shows a cut through a source / drain portion 202 of the device 200, and it should be understood that other portions of the device, such as a channel and gate stack, are present but are not shown.

[0032] Source / drain portions 202 may be formed of epitaxially grown semiconductor material extending laterally from a channel of device 200. For example, device 200 may be a nanosheet FET, in which sheets of semiconductor material are formed in a vertically stacked arrangement, in which gates are stacked between and around the sheets of semiconductor material, and in which epitaxially grown source / drain material conductively connects the sheets to a corresponding transistor device. Other types of devices are also contemplated, including fin FETs and nanowire FETs using different channel geometries.

[0033] As used herein, the terms "epitaxial growth" and / or "epitaxial deposition" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has substantially the same crystal properties as the semiconductor material of the deposition surface. The term "epitaxial material" refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are correctly set, the deposited atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystal surface will exhibit a {100} orientation.

[0034] Device 200 may be formed of any suitable semiconductor material. For example, the nanosheet channel (not shown) of device 200 may be formed of silicon or silicon germanium, and source / drain portion 202 may be formed of the same semiconductor material or a similar compatible material that may include n-type or p-type dopants. Source / drain portion 202 may be doped in situ during formation, or may be doped afterwards by an ion implantation process.

[0035] Reference now Figure 3, a cross-sectional view of a step in the manufacture of a stacked semiconductor device is shown. An interlayer dielectric 302 is deposited above and around the device 200, with a height higher than the height of the device 200. The interlayer dielectric 302 may be formed of any suitable dielectric material, such as silicon dioxide, and may be deposited using any suitable deposition process. Although CVD is particularly contemplated, any other deposition process may be used instead, such as atomic layer deposition (ALD), physical vapor deposition (PVD), or gas cluster ion beam (GCIB) deposition.

[0036] CVD is a deposition process in which a deposited material is formed by a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). The solid product of the reaction is deposited on a surface on which a film, coating or layer of the solid product will be formed. Variations of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD) and metal organic CVD (MOCVD), and combinations thereof may also be used. In alternative embodiments using PVD, the sputtering device may include a DC diode system, radio frequency sputtering, magnetron sputtering or ionized metal plasma sputtering. In alternative embodiments using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In alternative embodiments using GCIB deposition, high pressure gas is allowed to expand in a vacuum and then condensed into clusters. Clusters may be ionized and directed onto the surface, thereby providing highly anisotropic deposition.

[0037] Portions of the interlayer dielectric 302 may be etched away, for example using a photolithography patterning process and a selective anisotropic etch (e.g., RIE). The etch may form a gap that exposes the top surface of the device 200. Although it is shown that the entire top surface of the device 202 may be exposed through the gap, it should be understood that any amount of the top surface may be exposed.

[0038] The gap may then be filled with a placeholder material that is selected to be selectively etched relative to device 200 and interlayer dielectric 302. The placeholder material may be deposited by any suitable process, such as CVD, and may be polished down to the level of the top surface of interlayer dielectric 302 using a CMP process to form placeholder 304. Exemplary placeholder materials may include titanium oxide or aluminum oxide, which may be cleanly removed without damaging the semiconductor structure of device 200.

[0039] It is particularly contemplated that the placeholder structure 304 may be confined to the area above and between the source / drain portions 202 of the device 200. The placeholder structure 304 defines the area where the lower contacts will eventually be formed, and therefore the placeholder structure should not contact more than one area of ​​a particular device 200 unless those contacted areas are meant to be electrically connected to each other. Thus, the placeholder structure 304 may contact the source, drain, or gate of the lower device 200, and in some cases may contact the gate and one of the source and drain areas, but in most cases may not contact all three areas.

[0040] Reference now Figure 4 , a cross-sectional view of a step in the fabrication of a stacked semiconductor device is shown. Additional interlayer dielectric material is deposited over placeholder 304 to form interlayer dielectric 402, thereby increasing the height of interlayer dielectric 402 above placeholder structure 304. A bonding layer 404 is then deposited over interlayer dielectric 402 using any suitable deposition process, such as formed from a suitable dielectric oxide material. A semiconductor material layer 406 is then deposited over bonding layer 404 by any suitable process. Semiconductor material layer 406 is used in subsequent steps to form upper layers of the device.

[0041] Reference now Figure 5 , showing a cross-sectional view of a step in the manufacture of a stacked semiconductor device. A semiconductor material layer 406 is processed to form an upper device 502. As with the lower device 200, the cross-sectional view shows a profile through the source / drain portion of the upper device 502. The upper device 502 can be manufactured using a process similar to that of the lower device 200, or can be different. For example, the upper device 502 can be a FET formed around a fin-shaped channel structure, or a large portion of a nanosheet or nanowire channel structure. As with the lower device 200, the upper device 502 can include any suitable gate stack and source / drain composition. An upper interlayer dielectric 504 can be formed above and around the upper device 502 using any suitable deposition method and dielectric material, and its height is higher than the height of the upper device 502.

[0042] Reference now Figure 6 , a cross-sectional view of a step in the fabrication of a stacked semiconductor device is shown. Using any suitable patterning process, after anisotropic etching (such as RIE), contact openings 602 / 604 are etched into the interlayer dielectrics 402 and 504. For example, an upper contact opening 604 can be formed that exposes the top surface of the source / drain region of the upper device 502. A central contact opening 602 can also be formed that penetrates the bonding layer 404 and the interlayer dielectric 402 / 504 to expose the top surface of the placeholder structure 304 in the area between the source / drain portions 202 of the lower device 200.

[0043] The top surface of the source / drain region of the upper device 502 may be exposed, while the source / drain portion 202 of the lower device 200 is protected by the placeholder structure 304. The exposed source / drain surface may be selectively modified to form a good electrical contact to the upper device.

[0044] Electrical contacts between dissimilar conductive materials can have an interfacial contact resistance that impedes the flow of current. The interfacial contact resistance is inversely proportional to the contact area and directly proportional to an interfacial material property known as the specific contact resistivity. The specific contact resistivity between elemental metals can be between 1e-12 and 1e-11 Ω-cm. 2 In the range of 1e-11 to 1e-10 Ω-cm, the specific contact resistivity can be between 1e-11 and 1e-10 Ω-cm for metal compounds such as silicides, germanium silicides, and metal nitrides or carbides. 2 Between doped semiconductors and metal compounds or metals, the specific contact resistivity can be between 3e-9 and 1e-7 Ω-cm 2 within the range.

[0045] Because the metal-semiconductor contact resistance dominates, the interface can be designed to obtain a low specific interface resistivity of 1e-7 Ω-cm 2 The interface engineering may include adding dopant atoms to the semiconductor surface and non-equilibrium activation of the surface dopant, and forming a suitable metal compound at the interface. Complementary metal oxide semiconductor (CMOS) technology may include at least two sets of electronic devices of opposite polarity, such as n-type FET (nFET) and p-type FET (pFET). The interface contact engineering for these device sets may be different, because a surface modifier that reduces the specific contact resistivity for one device type may reduce the specific contact resistivity for another device type.

[0046] In one embodiment, the upper devices can have the same polarity. Therefore, their exposed top source / drain surfaces can be modified by adding surface dopants of the same polarity: for example, boron, gallium or indium for pFETs, or phosphorus, arsenic or antimony for nFETs. Other elements can also be added to the top surface of the source / drain to further reduce the specific contact resistivity. In one example, germanium and / or tin can be added for pFETs, or carbon, niobium, lanthanum and / or scandium can be added for nFETs. These electrically neutral elements can reduce the scattering of electric carriers at the semiconductor-metal interface and can help activate surface dopants via non-equilibrium processes. For example, germanium and tin pin the semiconductor valence band to the metal Fermi level, thereby reducing the interface Schottky barrier for p-type contacts. Niobium, lanthanum and scandium can help reduce the interface Schottky barrier for n-type contacts. Similar to dopants of opposite polarity, these elements only contribute to one device type and may degrade another type.

[0047] Dopants and additional elements may be introduced to the exposed top surface of the source / drain via low temperature (less than 500° C.) epitaxy, surface ion implantation, surface plasma treatment, and / or gas doping. At the end of this process step, the exposed top source / drain surface may be modified from about 3 nm to about 10 nm. The conditions of the low temperature epitaxy may be selected to achieve selective growth so that there is no continuous growth film on the structure 304 and other dielectric surfaces.

[0048] In one example, low temperature selective epitaxy can be a CVD process using high order silicon or germanium precursors (e.g., disilane or digermane). Such high order precursors enable low temperature (less than 500°C) epitaxial growth on exposed semiconductor surfaces, which helps preserve the metastable surface compounds formed. Enhanced epitaxial selectivity can be achieved using an in-situ deposition-etch sequence.

[0049] The epitaxial growth process can also act as a non-equilibrium dopant activation process, where the dopant is forced and locked into the semiconductor lattice substitutional position. Alternatively, the surface dopant may need to be activated to produce a dopant with a value of about 1e21 cm -3 A highly degenerate semiconductor with a low number of active electrical carriers (electrons or holes). The non-equilibrium dopant activation process can involve amorphization of the exposed top semiconductor surface followed by regrowth of the amorphized region. The regrowth process acts similarly to epitaxial growth, where dopants are locked into semiconductor lattice substitutional positions during thermally driven atomic rearrangement.

[0050] The surface amorphization process can be performed by ion implantation of dopants with the correct polarity or electrically neutral elements such as argon, xenon or germanium. The ion implantation can be performed at a temperature below room temperature to enhance amorphization at low implantation doses. The ion implantation energy is selected to produce an amorphous layer of the desired thickness, but can be less than about 10 nm to avoid interaction with the internal device structure of the upper device 502. Thermally driven surface recrystallization can be performed after a later step in the process flow, or immediately thereafter.

[0051] Short duration annealing, such as laser or flash annealing, is a preferred recrystallization process, with exemplary durations ranging from tens of milliseconds to tens of nanoseconds, and the peak annealing temperature can be selected to complete the recrystallization. In some cases, the recrystallization process can involve melting of the top semiconductor surface. In this embodiment, all exposed top source / drain surfaces of the upper device 502 can be modified using a selected process sequence that is beneficial to the polarity of the upper device 502. The top surface of the placeholder structure 304 in the region between the source / drain portions 202 of the lower device 200 can remain exposed.

[0052] In other embodiments, the upper device 502 can be of mixed polarity, with both nFETs and pFETs present within the upper level. In such embodiments, the order for modifying the top source / drain surfaces is different. During the processing step, patterning can be used to block one device polarity and expose the device of the other polarity, followed by new patterning for the next process. Blocking can involve the use of a suitable hard mask material, such as silicon nitride, that prevents nucleation of low temperature CVD epitaxy. After sequentially modifying the exposed top source / drain surfaces of the upper device 502, the top surface of the placeholder structure 304 in the region between the source / drain portions 202 of the lower device 200 remains exposed using a selected process sequence that is beneficial to devices of each polarity.

[0053] Reference now Figure 7 , showing a cross-sectional view of a step in the fabrication of a stacked semiconductor device. The placeholder structures 304 and any contaminants introduced during the surface modification are etched away using any suitable isotropic etch (e.g., a wet or dry chemical etch). The etch removes material from between the lower source / drain structures 202 and the lower interlayer dielectric 402, thereby exposing the top surface of the lower source / drain structures 202 and the sidewalls of the lower source / drain structures 202 to leave gaps 702. Thus, the removal of the placeholder structures 304 creates gaps 702 above and between the source / drain structures 202, but may leave at least one sidewall of each of the lower source / drain structures 202 covered by the lower interlayer dielectric 402.

[0054] The exposed surface of the lower source / drain structure 202 may be selectively modified to form a good electrical contact with the underlying device, with an exemplary specific contact resistivity of 1e-9 Ω-cm 2 or less than 1e-9Ω-cm 2 . The surface modification process may include chemical deposition and treatment that may penetrate into the gap 702 to modify the exposed horizontal surface of the lower source / drain 202. In addition, the presence of the exposed and modified surface of the upper source / drain 502 imposes additional constraints on the surface modification processes of the lower source / drain structure so that they do not interfere with forming an electrical contact with the upper source / drain structure 502 with a specific contact resistivity equal to or lower than 1e-9 Ω-cm 2 .

[0055] In one embodiment, all lower devices may have the same polarity. Low temperature (less than 500°C) selective epitaxy may be employed to modify the surface of the lower source / drain 202 according to its polarity as described above while retaining the modified surface of the upper source / drain structure 502 and the dielectric surface. Low temperature epitaxy enables epitaxial growth on the exposed semiconductor surface of the lower source / drain structure 202 without growing on the modified surface of the upper source / drain structure due to the different semiconductor materials (e.g., silicon versus silicon germanium) employed in the source / drain structures of the upper and lower devices. Epitaxial selectivity may be further enhanced by keeping the modified surface of the upper source / drain structure 502 amorphous after the ion implantation amorphization process and by this selective epitaxy step.

[0056] Even if epitaxial growth is not present or prevented on the modified surface of the upper source / drain structure 501, the surface may also be contaminated by dopants or elements of different polarity. The low temperature of epitaxial growth limits this contamination to within 3nm from the surface. After the selective epitaxial growth, a directional etching process, such as RIE, can be performed to remove contaminated surface material from the modified surface of the upper source / drain structure 502 while retaining the growth epitaxy on the surface of the lower source / drain structure 202. The epitaxial growth process on the surface of the lower source / drain structure 202 can also be used as an unbalanced dopant activation process as mentioned above. Short duration annealing, such as laser or flash annealing, can be performed to further activate the dopants in the grown epitaxial layer and to recrystallize any amorphous layer that may still exist in the source / drain structure.

[0057] Reference now Figure 8, showing a cross-sectional view of a step in the fabrication of a stacked semiconductor device. A first conductive material is deposited to form an interface contact with the modified semiconductor surface. The first conductive material may be in the form of a thin liner only a few nm thick. The purpose of the first conductive material is to form a suitable metal compound at the interface with the adjacent semiconductor so that the specific contact resistivity of these semiconductor-metal interfaces is low, for example, below 1e-9 Ω-cm 2 The bulk resistivity of the first conductive material is not critical as long as it can achieve a low contact resistivity.

[0058] The first conductive material may be the same or different for the lower device and the upper device. In an embodiment where the first conductive material is different for the lower device and the upper device, the first material type may be first deposited by a directional deposition process such as PVD, followed by a conformal deposition of the second material type using a CVD or ALD process. The first material type only coats the exposed horizontal surfaces, but does not exist in the gap 702 and on the vertical surfaces, while the second material type coats all surfaces. In an embodiment where all upper devices have a first polarity and all lower devices have a second polarity, the type of the first conductive material may be used to independently reduce the specific contact resistivity of semiconductor-metal interfaces of different polarities. For example, if all upper devices are pFETs and all lower devices are nFETs, the first material type may be a thin layer of nickel or platinum deposited by PVD, and the second material type may be a thin layer of titanium deposited by CVD. In this case, the nFET contact interface will be between titanium silicide and the degraded n-type semiconductor, while the pFET contact interface will be between nickel and / or platinum germanium silicide and the degraded p-type semiconductor.

[0059] In some embodiments, the first conductive material is the same for the lower device and the upper device. For example, if all upper devices are pFETs and all lower devices are nFETs, the common first conductive material can be a thin layer of titanium deposited by CVD. In this case, the nFET contact interface will be between the titanium silicide and the degenerate n-type semiconductor, and the pFET contact interface will be between the titanium germanium silicide and the degenerate p-type semiconductor.

[0060] The second conductive material may be deposited using a conformal deposition process such as CVD or ALD that coats the first conductive material in the upper trench 604 and in the center trench 602 and gap 702, thereby filling gap 702. The second conductive material fills these spaces and may then be polished down to the level of the upper interlayer dielectric 504 to produce a composite upper contact 802 and a composite center contact structure 804.

[0061] The second conductive material reduces the bulk resistance of the contact structure. Therefore, the second conductive material can be selected from metals and metal compounds with low effective bulk resistivity (bulk resistivity adjusted for the smaller size of the grooves and gaps). The second conductive material of the upper contact composite structure 802 and the center contact composite structure 804 can be formed of any suitable conductive metal, such as tungsten, nickel, titanium, molybdenum, tantalum, copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, cobalt and alloys thereof. The first conductor and the second conductor can be separated by a thin (e.g., less than 2nm) conductive diffusion barrier to prevent mixing. In some cases, the first conductor and the second conductor can be made of the same material or alloy that forms a corresponding interface silicide and germanium silicide at the semiconductor interface.

[0062] The center contact composite structure 804 is in electrical contact with two of the lower source / drain regions 202 along its top surface and along its sidewalls, in some cases achieving less than 1e-9 Ω-cm over the entire metal-semiconductor interface. 2 The multiple metal-metal interfaces that may be present in the composite structure 804 do not significantly affect the overall contact resistance because the metal-metal specific contact resistivity is at least an order of magnitude lower than the resistivity of the semiconductor-metal interface. Due to the relatively large width of the central contact structure 804, the second conductor material with its lower effective bulk resistivity achieves a lower bulk resistance. During the deposition process, very few metal voids should be generated, thereby improving the electrical contact between the central composite contact structure 804 and the source / drain structure 202 and reducing the overall contact resistance.

[0063] At the same time, in some cases, the upper contact composite structure 802 is in electrical contact with the upper source / drain region 502, thereby achieving a resistance of less than 1e-9 Ω-cm over the entire metal-semiconductor interface. 2 The multiple metal-metal interfaces that may be present in the composite structure 802 do significantly affect the overall contact resistance because the metal-metal specific contact resistivity is at least an order of magnitude lower than the resistivity of the semiconductor-metal interface. Due to the relatively low effective bulk resistivity of the second conductor material within the composite structure 802 and the low specific contact resistivity of the interface with the upper source / drain structure 502, the upper contact composite structure 802 provides an improved electrical contact with the upper source / drain structure 502 while substantially reducing the overall contact resistance.

[0064] Reference now Fig. 9, showing a cross-sectional view of a step in the fabrication of a stacked semiconductor device. A trench 902 is etched downward through the center contact structure 804 and into the lower STI region 106 using any suitable patterning process and anisotropic etching. The etch may include a non-selective etch that removes material from the center contact structure and the STI region 106, or may include two separate etches that are selective to the conductive material of the center contact structure 804 and the STI region 106, respectively. The trench 902 divides the center contact structure 804 into two vias / contacts 904, each of which is in electrical contact with a corresponding lower source / drain portion 202. The trench 902 electrically isolates the two lower devices 200 from each other.

[0065] Although the trenches 902 are shown as being positioned along the center line of the center contact structure 804 so that the resulting vias / contacts 904 are of approximately equal size, it should be understood that the trenches 902 may alternatively be positioned off-center. The location of the trenches 902 may be selected to provide vias / contacts 904 that align with subsequently added signal or power lines in the overlying back-end of line (BEOL) layers. These alternative embodiments refer to Fig.13 Provide explanation.

[0066] Reference now Fig.10 , a cross-sectional view of a step in the manufacture of a stacked semiconductor device is shown. The trench 902 is filled with an electrically insulating structure including a dielectric liner 1002 and an interlayer dielectric fill 1004. The dielectric liner 1002 and the interlayer dielectric fill 1004 can be formed using any suitable conformal deposition process, such as CVD or ALD, respectively. Before depositing the interlayer dielectric fill 1004, the deposited liner material can be removed from the horizontal surface by anisotropic etching (e.g., RIE).

[0067] The dielectric liner 1002 may be formed of a high-k dielectric material, where a high-k material may refer to a material having a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, metal oxides such as silicon nitride, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The interlayer dielectric fill 1004 may be formed of any suitable dielectric material, such as silicon dioxide.

[0068] Reference now Fig.11, a method of manufacturing a stacked device is shown. Block 1102 forms a lower device 200 on a device region 104 of a substrate 102. The lower device 200 may be any suitable semiconductor device, but in particular, it is contemplated that such a device may include a fin FET, a nanosheet FET, or a nanowire FET. In block 1104, a placeholder structure 304 is formed across a portion of the lower device 200, for example, contacting the lower source / drain structure 202. An interlayer dielectric 402 may be formed over and around the placeholder structure 304.

[0069] Block 1106 forms a bonding layer 404 over the placeholder structure 304, outlining the lower portion from the upper layer. Block 1108 forms an upper device 502 on the bonding layer 404, which may be any suitable semiconductor device and may be directly above the lower device 200. Block 1110 forms an upper interlayer dielectric 504 over the upper device 502, and block 1112 forms trenches in the upper dielectric layer 504, including an upper trench 604 and a central trench 602, which expose the top surfaces of the upper device 502 and the placeholder structure 304, respectively.

[0070] Block 1114 etches away the placeholder structure 304 using any suitable isotropic etch, thereby exposing the top surface and sidewall surfaces of the lower device 200. Block 1116 then deposits a conductive material in electrical contact with the lower device 200 using a conformal deposition process, thereby forming the center conductor structure 804. Block 1118 etches a trench 902 in the center conductor structure, thereby dividing the center conductor structure 804 into two vias / contacts 904. Block 1120 then fills the trench 902 with an insulating structure including, for example, a dielectric liner 1002 and a dielectric fill 1004.

[0071] Reference now Fig.12 , a cross-sectional view of a stacked semiconductor device is shown. In this view, the back end of line (BEOL) layer includes a BEOL dielectric 1202 with metal lines 1206 and vias 1204 connecting some of the metal lines 1206 to contacts 802 and contacts 904. Power rails 1208 carry a ground voltage or operating voltage. In this embodiment, lower contacts 904 are shown as being in electrical contact with metal lines 1206, for example, for signal communication with other devices on the integrated chip.

[0072] Reference now Fig.13 , shows a cross-sectional view of a stacked semiconductor device. In this view, the BEOL layers are as shown in Fig.12. However, to make contact with the power rail 1208, the trench 902 and barrier structure 1002 / 1004 may be positioned off-center so that one of the resulting lower contacts is wider than the other. The barrier structure 1002 / 1004 may be located at any suitable point to facilitate contact between the via 1204, the lower contact 904, and any suitable conductive structure in the BEOL.

[0073] It should be understood that various aspects of the invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may be varied within the scope of various aspects of the invention.

[0074] It will also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0075] This embodiment may include a design for an integrated circuit chip that can be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or a virtual hard drive such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may directly or indirectly transfer the resulting design to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted to an appropriate format (e.g., GDSII) for manufacturing photolithography masks, which typically include multiple copies of the chip design in question to be formed on a wafer. Photolithography masks are used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0076] The method described herein can be used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier having leads fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as (a) an intermediate product, such as a motherboard; or (b) part of a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0077] It should also be understood that material compounds will be described in terms of the listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound, e.g., SiGe includes SixGe1-x, where x is less than or equal to 1, and so on. In addition, other elements can be included in the compound and still function according to the present principles. Compounds with additional elements will be referred to herein as alloys.

[0078] References in the specification to "one embodiment" or "an embodiment" and other variations mean that a particular feature, structure, characteristic, etc. described in conjunction with the embodiment is included in at least one embodiment. Therefore, the appearance of the phrases "in one embodiment" or "in an embodiment" and any other variations in various places throughout the specification do not necessarily refer to the same embodiment.

[0079] It will be understood that, for example, in the case of "A / B," "A and / or B," and "at least one of A and B," the use of any of the following " / ," "and / or," and "at least one of" is intended to encompass selection of only the first listed option (A), or only the second listed option (B), or both options (A and B). As yet another example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such wording is intended to encompass selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first listed option and the second listed option (A and B), or only the first listed option and the third listed option (A and C), or only the second listed option and the third listed option (B and C), or all three options (A and B and C). This can be extended to many of the items listed, as will be apparent to one of ordinary skill in this and related arts.

[0080] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. It will also be understood that the terms "consisting of", "including", "comprising" and / or "containing" when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0081] For ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (multiple) elements or (multiple) features, as shown in the accompanying drawings. It should be understood that spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, the elements described as being "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers can also be present.

[0082] It will be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of this concept, the first element discussed below can be referred to as the second element.

[0083] Having described preferred embodiments of stacked FET contact formation (which are intended to be illustrative and not limiting), it is noted that modifications and variations may be made by those skilled in the art in light of the above description. It will be appreciated, therefore, that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described various aspects of the invention with the details and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a first lower device and a second lower device on a substrate; a first upper device over the first lower device and a second upper device over the second lower device; a first lower contact extending from a height above the first upper device and in electrical contact with a top surface and a sidewall surface of the first lower device and extending laterally below the first upper device; a second lower contact extending from a height above the second upper device and in electrical contact with a top surface and a sidewall surface of the second lower device and extending laterally below the second upper device; as well as An insulating barrier is between the first lower contact and the second lower contact. 2 . The semiconductor device according to claim 1 , wherein the insulating barrier comprises a dielectric liner and a dielectric filler formed of different dielectric materials. 3 . The semiconductor device according to claim 2 , wherein the dielectric liner is formed of a high-k dielectric material, and the dielectric filler is formed of silicon dioxide. 4 . The semiconductor device according to claim 1 , wherein the first lower contact has a width different from a width of the second lower contact. 5 . The semiconductor device of claim 1 , wherein the substrate comprises a shallow trench isolation (STI) region between the first lower device and the second lower device, and wherein the insulating barrier extends to a depth below a top surface of the STI region. 6 . The semiconductor device of claim 1 , wherein a sidewall of the first lower contact in a portion extending laterally below the first upper contact is sloped.

7. The semiconductor device of claim 1, wherein the first lower contact is in electrical contact with a source / drain portion of the first lower device, and the second lower contact is in electrical contact with a source / drain portion of the second lower device. 8 . The semiconductor device of claim 1 , further comprising a back-end-of-line (BEOL) layer, the BEOL layer comprising a first line electrically contacting the first lower contact and a second line electrically contacting the second lower contact. 9 . The semiconductor device according to claim 1 , wherein the first lower contact and the second lower contact have no gap.

10. A method of forming a semiconductor device, comprising: forming a placeholder structure over the first lower device and the second lower device on the substrate; forming a first upper device and a second upper device on the dielectric layer above the respective first lower device and the second lower device; selectively etching away the placeholder structure to expose a top surface and sidewall surfaces of each of the first lower device and the second lower device; depositing a conductive material in electrical contact with the top surface and the sidewall surfaces of each of the first lower device and the second lower device; etching a trench in the conductive material, the trench dividing the conductive material into a first lower contact and a second lower contact; as well as A barrier structure is formed in the trench to electrically isolate the first lower contact from the second lower contact.

11. The method of claim 10, wherein forming the barrier structure comprises: conformally depositing a first dielectric material in the trench; as well as A second dielectric material is deposited to fill the trench.

12. The method of claim 11, wherein the first dielectric material is a high-k dielectric material and the second dielectric material is silicon dioxide.

13. The method of claim 10, wherein etching the trench comprises an anisotropic etch extending to a depth below a top surface of the substrate.

14. The method of claim 10, wherein etching the trench comprises etching the trench at an off-center location of the conductive material such that the first lower contact is formed to have a greater width than the second lower contact.

15. The method of claim 10, wherein forming the placeholder structure comprises: depositing a first dielectric material over and around the first lower device and the second lower device; etching away the first dielectric material over and between the first lower device and the second lower device to expose a first sidewall of each of the first lower device and the second lower device; as well as A placeholder material is deposited over and between the first lower device and the second lower device. The method of claim 15 , wherein depositing the placeholder material comprises a conformal deposition process. 17 . The method of claim 15 , wherein etching away the first dielectric material leaves a portion of the first dielectric material covering the second sidewall of each of the first lower device and the second lower device.

18. A method of forming a semiconductor device, comprising: forming a placeholder structure over and between a pair of lower devices; forming a dielectric layer over the placeholder structure; etching away the placeholder structure to leave a gap between the pair of lower devices and the dielectric layer; depositing a conductor to fill the gap; and A trench is etched in the conductor to form a contact to each of the pair of lower devices.

19. The method of claim 18, further comprising forming a barrier structure in the trench to electrically isolate the contacts.

20. The method of claim 18, wherein etching the trench comprises etching the trench at an off-center location of the conductor such that a first contact is formed to have a greater width than a second contact.

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