Enhanced interconnection ball grid array design, semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a chip packaging structure. The disclosed semiconductor structure includes a printed circuit board, a chip package structure, and a ball grid array connected between the printed circuit board and the chip package structure. The ball grid array includes first solder balls each having a first lateral dimension and second solder balls each having a second lateral dimension greater than the first lateral dimension. The second solder balls are located at the corners of the ball grid array respectively.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology and, more particularly, to enhanced interconnect ball grid array designs, related semiconductor structures, and methods of making the same. Background Art

[0002] When a semiconductor package with a ball grid array (BGA) is attached to a printed circuit board (PCB), warping problems may occur on different parts of the structure due to differences in the coefficient of thermal expansion (CTE) of different materials in different parts of the structure. When the operating environment temperature changes, both the PCB and the semiconductor package may suffer from warping and deformation problems during operation, and cause the solder balls to crack or break. Failure of the mechanical connection of the BGA may cause a short circuit or an open circuit in the semiconductor device, making the semiconductor device unable to operate normally. Summary of the invention

[0003] Embodiments of semiconductor structures and methods of making the same are described in this disclosure.

[0004] One aspect of the present disclosure provides a semiconductor structure, including: a printed circuit board; a chip packaging structure; and a ball grid array connected between the printed circuit board and the chip packaging structure, the ball grid array including: first solder balls, each of which has a first lateral dimension; and second solder balls, each of which has a second lateral dimension greater than the first lateral dimension, wherein the second solder balls are respectively located at corners of the ball grid array.

[0005] In some embodiments, each second solder ball occupies at least one corner position of the ball grid array and extends laterally along a diagonal direction of the ball grid array.

[0006] In some embodiments, each second solder ball occupies at least one corner position of the ball grid array and includes: a first portion extending laterally along a first direction, wherein the first direction is along a row of the ball grid array; and a second portion extending laterally along a second direction, wherein the second direction is along a column of the ball grid array.

[0007] In some embodiments, each second solder ball partially surrounds a corner first solder ball of the ball grid array and includes: a first portion extending laterally along a first direction, wherein the first direction is along a row of the ball grid array; and a second portion extending laterally along a second direction, wherein the second direction is along a column of the ball grid array.

[0008] In some embodiments, the first solder ball is electrically connected between the printed circuit board and the chip packaging structure; and the second solder ball is electrically disconnected from the printed circuit board or the chip packaging structure.

[0009] In some embodiments, a chip packaging structure includes: a substrate; at least one chip attached to a first surface of the substrate; a conductive wiring structure embedded in the substrate and electrically connected to the at least one chip, wherein a ball grid array is attached to a second surface of the substrate opposite to the first side, a first solder ball is electrically connected to the conductive wiring structure, and a second solder ball is electrically disconnected from the conductive wiring structure.

[0010] In some embodiments, the chip packaging structure also includes: an array of ball pads located on the second surface of the substrate, including: first ball pads, each of which has a first area and is electrically connected to the conductive wiring structure; and second ball pads, each of which has a second area and is electrically disconnected from the conductive wiring structure, wherein the first area is smaller than the second area.

[0011] In some embodiments, a first material of the first solder ball is different than a second material of the second solder ball.

[0012] In some embodiments, the first material has a first mechanical strength and a first coefficient of thermal expansion; and the second material has a second mechanical strength greater than the first mechanical strength and a second coefficient of thermal expansion less than the first coefficient of thermal expansion.

[0013] Another aspect of the present disclosure provides a method for forming a semiconductor structure, comprising: providing a chip packaging structure, comprising: attaching at least one chip on a first surface of a substrate, and forming a ball grid array on a second surface of the substrate, the ball grid array comprising: first solder balls, each of which has a first lateral dimension, and second solder balls, each of which has a second lateral dimension greater than the first lateral dimension, wherein the second solder balls are respectively located at corners of the ball grid array; and attaching the chip packaging structure to a printed circuit board so that the ball grid array is connected between the chip packaging structure and the printed circuit board.

[0014] In some embodiments, providing a chip packaging structure includes: forming a conductive wiring structure embedded in a substrate; and forming an array of ball pads on a second surface of the substrate, the array of ball pads including: first ball pads, each first ball pad having a first area and being electrically connected to the conductive wiring structure; and second ball pads, each second ball pad having a second area and being electrically disconnected from the conductive wiring structure, wherein the first area is smaller than the second area.

[0015] In some embodiments, providing a chip packaging structure also includes: attaching at least one chip on a first surface of a substrate; wiring at least one chip to a conductive wiring structure; forming a ball grid array on an array of ball pads, wherein forming a ball grid array on an array of ball pads includes: forming first solder balls on first ball pads, respectively; and forming second solder balls on second ball pads, respectively.

[0016] In some embodiments, the first solder ball and the second solder ball are formed simultaneously in the same process.

[0017] In some embodiments, the method further includes: forming an array of ball openings in the mounting area of ​​the printed circuit board, the array of ball openings including: first ball openings, each of the first ball openings having a third area and exposing a contact pad, the contact pad being electrically connected to a circuit of the printed circuit board, and second ball openings, each of the second ball openings having a fourth area greater than the third area, wherein the second ball openings are respectively located at corners of the mounting area.

[0018] In some embodiments, attaching a chip package structure to a printed circuit board includes: aligning the chip package structure to a mounting area of ​​the printed circuit board; attaching the chip package structure to the mounting area of ​​the printed circuit board so that each first solder ball is located in a corresponding first ball opening and each second solder ball is located in a corresponding second ball opening; and sequentially heating and cooling the ball grid array so that the chip package structure is mechanically connected to the printed circuit board through the first solder balls and the second solder balls.

[0019] Another aspect of the present disclosure provides a chip packaging structure, comprising: a substrate; at least one chip attached to a first surface of the substrate; a conductive wiring structure embedded in the substrate and electrically connected to the at least one chip; and an array of ball pads located on a second surface of the substrate opposite to the first surface, the array of ball pads comprising: first ball pads, each first ball pad having a first area, and second ball pads, each second ball pad having a second area greater than the first area, wherein the second ball pads are respectively located at corners of the array of ball pads.

[0020] In some embodiments, each second ball pad occupies at least one corner position of the array of ball pads and extends laterally along a diagonal direction of the array of ball pads.

[0021] In some embodiments, each second ball pad occupies at least one corner position of the array of ball pads and includes: a first portion extending laterally along a first direction, wherein the first direction is along the rows of the array of ball pads; and a second portion extending laterally along a second direction, wherein the second direction is along the columns of the array of ball pads.

[0022] In some embodiments, each second ball pad partially surrounds a corner first ball pad of the array of ball pads and includes: a first portion extending laterally along a first direction, wherein the first direction is along the rows of the array of ball pads; and a second portion extending laterally along a second direction, wherein the second direction is along the columns of the array of ball pads.

[0023] In some embodiments, the first ball pad is electrically connected to at least one chip through a conductive wiring structure; and the second ball pad is electrically disconnected from the at least one chip and the conductive wiring structure.

[0024] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0026] Figure 1 A schematic diagram showing a perspective side view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0027] Figure 2A A schematic diagram showing a top view of a ball grid array according to some embodiments of the present disclosure.

[0028] Figure 2B A schematic diagram showing a top view of another ball grid array according to some other embodiments of the present disclosure.

[0029] Figure 2C A schematic diagram showing a top view of another ball grid array according to some other embodiments of the present disclosure.

[0030] Figure 3 A flow chart of a method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0031] Figure 4 According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a perspective side view of a semiconductor structure at a particular fabrication step of the method shown in .

[0032] Figure 5A According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of a semiconductor structure at a particular fabrication step of the method shown in .

[0033] Figure 5B According to some other embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of another semiconductor structure at a particular fabrication step of the method shown in .

[0034] Figure 5C According to some other embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of another semiconductor structure at a particular fabrication step of the method shown in .

[0035] Figure 6 According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a perspective side view of a semiconductor structure at a particular fabrication step of the method shown in .

[0036] Fig. 7A According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of a semiconductor structure at a particular fabrication step of the method shown in .

[0037] Figure 7B According to some other embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of another semiconductor structure at a particular fabrication step of the method shown in .

[0038] Figure 7C According to some other embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of another semiconductor structure at a particular fabrication step of the method shown in .

[0039] Figure 8 According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a perspective side view of a semiconductor structure at a particular fabrication step of the method shown in .

[0040] Fig. 9A According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of a semiconductor structure at a particular fabrication step of the method shown in .

[0041] Fig. 9B According to some other embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of another semiconductor structure at a particular fabrication step of the method shown in .

[0042] Fig. 9C According to some other embodiments of the present disclosure, Figure 3 Schematic diagram of a top view of another semiconductor structure at a particular fabrication step of the method shown in .

[0043] Fig.10 According to some embodiments of the present disclosure, Figure 3 Schematic diagram of a perspective side view of a semiconductor structure at a particular fabrication step of the method shown in .

[0044] Fig.11 According to some embodiments of the present disclosure, Figure 3Schematic diagram of a perspective side view of a semiconductor structure at a particular fabrication step of the method shown in .

[0045] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements throughout the drawings. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost (multiple) digits in the corresponding reference numeral.

[0046] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0047] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used for various other applications.

[0048] Note that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0049] In general, terms can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage. In addition, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described.

[0050] It should be readily understood that the meaning of "on", "over", and "on" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween. Furthermore, "over" or "on" not only means "over something" or "on something", but can also include the meaning of "over something" or "on something" with no intervening features or layers therebetween (i.e., directly on something).

[0051] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0052] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The front surface of the substrate is typically where the semiconductor device is formed, and therefore, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the front surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic or sapphire wafers.

[0053] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is adjacent to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire lower layer or overlying structure, or can have a range less than the range of the lower layer or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure, which has a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided thereon, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect channels (VIA) are formed) and one or more dielectric layers.

[0054] As used herein, the term "nominal / nominal" refers to an expected or target value for a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0055] In this disclosure, the term “horizontal / horizontally / lateral / laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical / vertically” means nominally perpendicular to a lateral surface of a substrate.

[0056] As described above, when a semiconductor package having a ball grid array (BGA) is attached to a printed circuit board (PCB), warping problems may occur on different parts of the structure due to differences in the coefficient of thermal expansion (CTE) of different materials of different parts of the structure. When the operating environment temperature changes, both the PCB and the semiconductor package may suffer from warping and deformation problems during operation, and cause the solder balls to crack or break. Failure of the mechanical connection of the BGA may cause a short circuit or an open circuit in the semiconductor device, making the semiconductor device unable to operate normally.

[0057] In order to solve the above problems, the present disclosure provides a package substrate BGA PAD structure design to improve the BGA connection strength. Under the premise of meeting the package shape requirements, the solder ball structure around the substrate side can be optimized to enhance the mechanical interconnection between the semiconductor device and the PCB, thereby reducing the mechanical interconnection failure of the semiconductor device in a rapid temperature change environment. Therefore, the semiconductor device can be protected and the product reliability can be improved.

[0058] The disclosed enhanced interconnect ball grid array design does not change the external dimensions of the package. The manufacturing process is simple and does not require additional processes. Therefore, conventional manufacturing equipment can be used without increasing investment costs. A modular packaging solution can be adopted, which is conducive to mass production. The disclosed manufacturing process can significantly improve product reliability, enhance the mechanical interconnection between the semiconductor device and the PCB, enhance the heat dissipation capability of the package, and improve product performance.

[0059] refer to Figure 1 , a schematic diagram showing a perspective side view of an exemplary semiconductor device structure according to some embodiments of the present disclosure. As shown in the figure, the semiconductor device structure 100 may include a chip package structure 110, a printed circuit board (PCB) 120, and a ball grid array (BGA) 150 connected between the PCB 120 and the chip package structure 110. Note that the semiconductor device structure 100 may also include Figure 1 Any other suitable components not shown.

[0060] The chip package structure 110 may include a base substrate 130, a die / die stack 140, and a molding compound layer 145. The base substrate 130 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polysilicon single layer substrate, a polysilicon and metal multilayer substrate, etc. The base substrate 130 may include a conductive wiring structure 135 embedded therein. The conductive wiring structure 135 may include any suitable conductive interconnect structure, such as a conductive via and a patterned conductive layer, etc.

[0061] The base substrate 130 may also include an array of ball pads 139 on the bottom surface to accommodate the BGA 150, thereby achieving electrical connection and / or mechanical fastening connection. The array of ball pads 139 may include: first ball pads 139_1, each of which has a first area and is electrically connected to the conductive wiring structure 135; and second ball pads 139_2, each of which has a second area and is electrically disconnected from the conductive wiring structure 139. In some embodiments, the first area is smaller than the second area.

[0062] The array of conductive wiring structures 135 and ball pads 139 may include any suitable conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the second ball pad 139_2 may include a material different from that of the first ball pad 139_1. For example, the first ball pad 139_1 may include a conductive material, while the second ball pad 139_2 may include a dielectric material.

[0063] The die / die stack 140 can be attached to the base substrate 130 by an adhesive film (not shown). In some embodiments, the die / die stack 140 can be any suitable semiconductor die / die stack including one or more semiconductor chips. The adhesive film can be any suitable die attach film (DAF). In some embodiments, a plurality of bonding pads (not shown, also referred to as contact pads, redistribution pads, or similar structures known to those skilled in the art) can be located on the die / die stack 140. In some embodiments, a plurality of signal wirings (not shown) can be electrically connected between the plurality of bonding pads of the die / die stack 140 and the conductive wiring structure 135.

[0064] The chip package structure 110 may further include a molding compound layer 145 on the base substrate 130 to completely cover the die / die stack 140 and the plurality of signal connections. In some embodiments, the molding compound layer 145 may be a heat-curable epoxy molding compound or a heat-curable epoxy molding resin. For example, the molding compound layer 145 includes an inorganic filler (e.g., silicon dioxide), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable components known to those skilled in the art.

[0065] PCB 120 may include a laminated sandwich structure of conductive layers 180 and insulating layers. Each of conductive layers 180 may be designed with a pattern of traces, planes, and other features etched from one or more conductive sheets laminated on and / or between sheets of non-conductive substrate 170 (similar to wiring on a flat surface).

[0066] PCB 120 may further include an array of contact pads 190 on the top surface, which are designed to accommodate the shape of terminals (e.g., BGA 150) of chip package structure 110 to electrically connect chip package structure 110 to PCB 120 and / or mechanically fasten to PCB 120. The array of contact pads 190 may include first contact pads 190_1, each of which has a first area and is electrically connected to conductive layer 180, and second contact pads 190_2, each of which has a second area and is electrically disconnected from conductive layer 180. In some embodiments, the first area is smaller than the second area.

[0067] In some embodiments, PCB 120 may further include vias (not shown), such as plated through holes that allow interconnection between layers. Conductive layer 180, contact pad 190, and vias may be formed using any suitable conductive material (e.g., Cu, Ni, Au, Ag, Pt, Co, Ti, Cr, Zr, Mo, Ru, Hf, W, Re, graphite, carbon black, or any suitable combination thereof). In some embodiments, second contact pad 190_2 may include a material different from that of first contact pad 190_1. For example, first contact pad 190_1 may include a conductive material, while second contact pad 190_2 may include a dielectric material.

[0068] In some embodiments, a ball grid array (BGA) 150 may include a plurality of solder balls 160 / 165 sandwiched between the bottom surface of the base substrate 130 and the top surface of the PCB 120. The BGA 150 may include: a first solder ball 165, which is electrically and mechanically connected between the first ball pad 139_1 and the first contact pad 190_1; and a second solder ball, which is mechanically connected between the second ball pad 139_2 and the second contact pad 190_2. That is, the first solder ball 165 is electrically connected between the PCB 120 and the chip package structure 110, thereby providing transmission of electrical signals between the circuit located on the PCB 120 and the chip 140 located on the chip package structure 110. The second solder ball 160 may be electrically disconnected from the PCB 120 or the chip package structure 110, and is configured to provide mechanical connection support. In some embodiments, the first lateral dimension of each first solder ball 165 is smaller than the second lateral dimension of each second solder ball 160.

[0069] In some embodiments, the first solder ball 165 and the second solder ball 160 may include the same material and may be formed in the same process. For example, the first solder ball 165 and the second solder ball 160 may include any suitable metal material, such as aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc., and any suitable alloy thereof. In some other embodiments, the first solder ball 165 and the second solder ball 160 may include different materials. For example, the second solder ball 160 may include a material having high mechanical strength and low thermal expansion coefficient.

[0070] Figure 2A-2C Schematic diagrams of top views of various designs of BGAs 200A, 200B, and 200C, respectively, are shown in accordance with various embodiments of the present disclosure.

[0071] In such Figure 2A In some embodiments shown in , each first solder ball 165 may have an approximately circular shape in a transverse plane, and each second solder ball 261 may have an approximately elliptical shape in a transverse plane. The second solder balls 261 may be located at the corners of the BGA 200A, respectively. Each second solder ball 261 may occupy at least one corner position of the BGA 200A and extend laterally along the diagonal direction of the BGA 200A.

[0072] In such Figure 2B In some other embodiments shown in , each second solder ball 263 also occupies at least one corner position of the BGA 200B, and is formed by connecting three adjacent first solder balls 165 located at the corner positions of the BGA 200B. Therefore, each second solder ball 263 includes a first portion extending laterally along a first direction along the row of the BGA 200B, and a second portion extending laterally along a second direction along the column of the BGA 200B.

[0073] In such Figure 2C In some other embodiments shown in FIG. 1 , each second solder ball 265 partially surrounds the corner first solder ball 165 of BGA 200C. Each second solder ball 265 includes a first portion extending laterally along a first direction along the row of BGA 200C, and a second portion extending laterally along a second direction along the column of BGA 200C.

[0074] The disclosed enhanced interconnect ball grid array design and related semiconductor structure can optimize the solder ball structure located at the peripheral side of the base substrate and improve the mechanical strength of the interconnect ball structure, thereby enhancing the mechanical interconnection between the chip package structure 110 and the PCB 120. Therefore, the mechanical interconnection failure of the semiconductor device in a rapid temperature change environment can be reduced, the surface mount technology (SMT) yield can be improved, and the heat dissipation capability of the product can be improved.

[0075] refer to Figure 3 , shows a flow chart of a method for forming an electromagnetic interference shielding packaging structure according to some embodiments of the present disclosure. It should be understood that, Figure 3 The operations and / or steps shown in the drawings are not exhaustive, and other operations may also be performed before, after, or between any of the operations shown.

[0076] like Figure 3 As shown in , method 300 begins at operation 310 , where a chip package structure may be provided. Figure 4 According to some embodiments of the present disclosure, Figure 3 4 is a schematic diagram of a perspective side view of a semiconductor structure 400 after operation 310 of method 300 shown in FIG. Figure 5A-5C According to some embodiments of the present disclosure, Figure 3 3 is a schematic diagram of a top view of various semiconductor structures after operation 310 of method 300 shown in FIG.

[0077] like Figure 4 As shown in , in some embodiments, operation 310 of providing a chip package structure includes forming a base substrate 420. Forming the base substrate 420 includes providing a substrate 430. The substrate 430 can be any suitable semiconductor substrate having any suitable structure, such as a single crystal single-layer substrate, a polycrystalline silicon single-layer substrate, a polycrystalline silicon and metal multi-layer substrate, etc.

[0078] Forming the base substrate 420 also includes forming a conductive wiring structure 440 embedded in the substrate 430. The conductive wiring structure 440 may include any suitable conductive interconnect structure, such as a conductive via, a patterned conductive layer, and the like.

[0079] Forming the base substrate 420 also includes forming an array of ball pads 450 on a surface of the substrate 430. The array of ball pads 450 may include: first ball pads 450_1, each of which has a first area and is electrically connected to the conductive wiring structure 440; and second ball pads 450_2, each of which has a second area and is electrically disconnected from the conductive wiring structure 440. In some embodiments, the first area is smaller than the second area.

[0080] The array of conductive wiring structures 440 and ball pads 450 may include any suitable conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof and / or other materials known to those skilled in the art.

[0081] In some embodiments, operation 310 of providing a chip package structure further includes attaching the die / die stack 415 on the first surface of the base substrate 420 by using any suitable bonding or fastening means known in the art. In some embodiments, an adhesive film (not shown) such as a die attach film (DAF) may be attached to the bottom surface of the bottom chip of the die / die stack 415. And then the die / die stack 415 may be permanently attached or fixed to the surface of the base substrate (the other surface of the base substrate 420 away from the array of ball pads 450).

[0082] In some embodiments, operation 310 of providing a chip package structure further includes wiring at least one chip of the die / die stack 415 to the conductive wiring structure 440. For example, a plurality of signal wires (not shown) may be formed to electrically connect the die / die stack 415 and the base substrate 420. Note that Figure 4 A single die is shown as an example. In this example, a plurality of signal wires are formed to respectively connect a plurality of signal pads (not shown) located on the die to the conductive wire structure 440 of the base substrate 420. Figure 4 In some other embodiments not shown in the figure, the die stack may include multiple layers of dies stacked in a vertical direction. In this case, the plurality of signal connections may include signal connections of various groups connecting a plurality of signal pads and / or redistribution pads respectively located on each layer of the die stack.

[0083] In some embodiments, the operation 310 of providing a chip package structure further includes forming a molding compound layer 412 on the base substrate 420 to cover the die / die stack 415 and the plurality of signal connections. In some embodiments, the molding compound layer 415 can be formed of any suitable material (e.g., a heat-curable epoxy molding compound material or a heat-curable epoxy molding resin). For example, the molding compound layer can be formed by using an inorganic filler (e.g., silicon dioxide), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable components known to those skilled in the art.

[0084] refer to Figure 5A-5C, respectively, show schematic diagrams of top views of various designs of arrays 500A, 500B, and 500C of ball pads according to various embodiments of the present disclosure. In some embodiments, the arrays 500A, 500B, and 500C of ball pads may be Figure 4 Various examples of arrays of ball pads 450 are shown in FIG.

[0085] In such Figure 5A In some embodiments shown in , each first ball pad 550 may have an approximately circular shape in a transverse plane, and each second ball pad 561 may have an approximately elliptical shape in a transverse plane. The second ball pads 561 may be located at the corners of the array 500A of ball pads, respectively. Each second ball pad 561 may occupy at least one corner position of the array 500A of ball pads and extend laterally along the diagonal direction of the array 500A of ball pads.

[0086] In such Figure 5B In some other embodiments shown in , each second ball pad 563 also occupies at least one corner position of the ball pad array 500B, and is formed by connecting three adjacent first ball pads 550 located at the corner positions of the ball pad array 500B. Therefore, each second ball pad 563 includes a first portion extending laterally along a first direction along the rows of the ball pad array 500B, and a second portion extending laterally along a second direction along the columns of the ball pad array 500B.

[0087] In such Figure 5C In some other embodiments shown in , each second ball pad 565 partially surrounds a corner first ball pad 550 of the array 500C of ball pads. Each second ball pad 565 includes a first portion extending laterally along a first direction along the rows of the array 500C of ball pads, and a second portion extending laterally along a second direction along the columns of the array 500C of ball pads.

[0088] Return to reference Figure 3 , method 300 may proceed to operation 320 , where a ball grid array (BGA) may be formed on a surface of the chip package structure. Figure 6 According to some embodiments of the present disclosure, Figure 3 6 is a schematic diagram of a perspective side view of a semiconductor structure 600 after operation 320 of method 300 shown in FIG. Figure 7A-7C According to some embodiments of the present disclosure, Figure 3 3 is a schematic diagram of a top view of various semiconductor structures after operation 320 of method 300 shown in FIG.

[0089] like Figure 6As shown in , a ball grid array (BAG) 600 may be formed on a second surface of a base substrate 420 opposite to the first surface. BAG 600 may include a first solder ball 660_1, each of which has a first lateral dimension; and a second solder ball 660_2, each of which has a second lateral dimension greater than the first lateral dimension. Each first solder ball 660_1 may be formed on a corresponding first ball pad 450_1, and each second solder ball 660_2 may be formed on a corresponding second ball pad 450_2. That is, the first solder ball 660_1 is electrically connected to the chip package structure 110 to provide transmission of electrical signals. The second solder ball 660_2 may be electrically disconnected from the chip package structure 110 and configured to provide only mechanical connection support. In some embodiments, the first lateral dimension of each first solder ball 660_1 is less than the second lateral dimension of each second solder ball 660_2.

[0090] In some embodiments, the first solder ball 660_1 and the second solder ball 660_2 can be formed using the same material and can be formed simultaneously in the same process. For example, the first solder ball 660_1 and the second solder ball 660_2 can be formed by including any appropriate metal material described above. In some other embodiments, the first solder ball 660_1 and the second solder ball 660_2 can be formed by using different materials. For example, the second solder ball 660_2 can be formed by using a material having high mechanical strength and low thermal expansion coefficient.

[0091] refer to Figure 7A-7C , respectively, show schematic diagrams of top views of various designs of BGA 700A, 700B, and 700C according to various embodiments of the present disclosure. In some embodiments, BGA 700A, 700B, and 700C may be Figure 6 Various examples of BGA 660 are shown in FIG.

[0092] In such Fig. 7A In some embodiments shown in , each first solder ball 760 may have an approximately circular shape in a transverse plane, and each second solder ball 771 may have an approximately elliptical shape in a transverse plane. The second solder balls 771 may be located at the corners of the BGA 700A, respectively. Each second solder ball 771 may occupy at least one corner position of the BGA 700A and extend laterally along the diagonal direction of the BGA 700A.

[0093] In such Figure 7BIn some other embodiments shown in , each second solder ball 773 also occupies at least one corner position of the BGA 700B, and is formed by connecting three adjacent first solder balls 760 at the corner positions of the BGA 700B. Therefore, each second solder ball 773 includes a first portion extending laterally along a first direction along the row of the BGA 700B, and a second portion extending laterally along a second direction along the column of the BGA 700B.

[0094] In such Figure 7C In some other embodiments shown in FIG. 7 , each second solder ball 775 partially surrounds the corner first solder ball 760 of BGA 700C. Each second solder ball 775 includes a first portion extending laterally along a first direction along the row of BGA 700C, and a second portion extending laterally along a second direction along the column of BGA 700C.

[0095] Return to reference Figure 3 , method 300 may proceed to operation 330 where a printed circuit board (PCB) may be provided. Figure 8 According to some embodiments of the present disclosure, Figure 3 8 is a schematic diagram of a perspective side view of a semiconductor structure 800 after operation 330 of method 300 shown in FIG. Figure 9A-9C According to some embodiments of the present disclosure, Figure 3 3 is a schematic diagram of a top view of various semiconductor structures after operation 330 of method 300 shown in FIG.

[0096] like Figure 8 As shown in , operation 330 of providing PCB 810 may include forming a laminated sandwich structure of conductive layers 830 and insulating layers. Each of conductive layers 830 may be patterned to form a plurality of traces, planes, and other features etched from one or more conductive sheets laminated on and / or between sheets of non-conductive substrate 820 (similar to wiring on a flat surface).

[0097] The top conductive layer of the PCB 810 may include an array of contact pads 870 located in the mounting area 840. The array of contact pads 870 may include first contact pads 870_1, each of which has a first area and is electrically connected to the conductive layer 830, and second contact pads 870_2, each of which has a second area and is electrically disconnected from the conductive layer 830. In some embodiments, the first area is smaller than the second area.

[0098] The conductive layer 830 and the contact pad 870 may be formed by using any suitable conductive material (e.g., Cu, Ni, Au, Ag, Pt, Co, Ti, Cr, Zr, Mo, Ru, Hf, W, Re, graphite, carbon black, or any suitable combination thereof). In some embodiments, the second contact pad 870_2 may be formed of a material different from the material forming the first contact pad 870_1. For example, the first contact pad 870_1 may be formed by using a conductive material, and the second contact pad 870_2 may be formed by using a dielectric material.

[0099] like Figure 8 As shown in , operation 330 of providing PCB 810 may include forming an array of ball openings 880 in mounting area 840. Each first ball opening 880_1 may have a third area and expose a first contact pad 870_1, which is electrically connected to the circuit of the PCB. Each second ball opening 880_2 may have a fourth area greater than the third area and expose a second contact pad 870_2, which is electrically disconnected from the conductive layer 830 of PCB 810.

[0100] refer to Figure 9A-9C , respectively, show schematic diagrams of top views of various designs of PCBs 900A, 900B, and 900C according to various embodiments of the present disclosure. In some embodiments, PCBs 900A, 900B, and 900C may be Figure 8 800. In some embodiments, mounting areas 941, 943, and 945 may be Figure 8 Various examples of mounting area 840 are shown in .

[0101] In such Fig. 9A In some embodiments shown in , the mounting area 941 can be located in any suitable area of ​​the PCB 900A. Each first contact pad 970 can have an approximately circular shape in a transverse plane, and each second contact pad 991 can have an approximately elliptical shape in a transverse plane. The second contact pads 991 can be located at the corners of the mounting area 941, respectively. Each second contact pad 991 can occupy at least one corner position of the mounting area 941 and extend laterally along the diagonal direction of the array of contact pads.

[0102] In such Fig. 9BIn some other embodiments shown in , the mounting area 943 can be located in any appropriate area of ​​the PCB 900B. Each second contact pad 993 also occupies at least one corner position of the mounting area 943, and is formed by connecting three adjacent first contact pads 970 located at the corner positions of the mounting area 943. Therefore, each second contact pad 993 includes a first portion extending laterally along a first direction along the rows of the array of contact pads, and a second portion extending laterally along a second direction along the columns of the array of contact pads.

[0103] In such Fig. 9C In some other embodiments shown in , the mounting area 945 can be located in any suitable area of ​​the PCB 900C. Each second contact pad 995 partially surrounds a corner first contact pad 970 located at a corner of the mounting area 941. Each second contact pad 995 includes a first portion extending laterally along a first direction along the rows of the array of contact pads, and a second portion extending laterally along a second direction along the columns of the array of contact pads.

[0104] Return to reference Figure 3 , method 300 may proceed to operation 340 , where the chip package structure may be attached to a PCB. Fig.10 and Fig.11 According to some embodiments of the present disclosure, Figure 3 Schematic diagrams of perspective side views of semiconductor structures 1000 and 1100 at particular stages of operation 330 of method 300 are shown in FIG.

[0105] like Fig.10 As shown in FIG. 1 , the combined structure including the chip package structure 1010 and the BAG 660 can be turned over and aligned with the mounting area of ​​the PCB 810 (eg, Figure 8 Thus, each first solder ball 660_1 and / or each second solder ball 660_2 may be matched with the corresponding first ball opening 880_1 and / or second ball opening 880_2.

[0106] like Fig.11 As shown in FIG. 8 , the chip package structure 1010 may be placed in a mounting area (eg, Figure 8840), wherein each first solder ball 660_1 contacts the corresponding first contact pad 870_1, and each second solder ball 660_2 contacts the corresponding second contact pad 870_2. The assembly 1100 can then be heated in a reflow oven or by an infrared heater to melt the array of solder balls 660. Surface tension causes the melted solder balls 660 to keep the chip package structure 1010 aligned with the PCB 810 at the correct separation distance. After the solder balls 660 are cooled and solidified, a solder connection can be formed between the chip package structure 1010 and the PCB 810.

[0107] The disclosed method for forming an enhanced interconnect ball grid array semiconductor structure can optimize the solder ball structure located at the peripheral side of the base substrate and improve the mechanical strength of the interconnect ball structure, thereby enhancing the mechanical interconnection between the chip packaging structure and the PCB. Therefore, the mechanical interconnection failure of the semiconductor device in a rapid temperature change environment can be reduced, the surface mount technology (SMT) yield can be improved, and the heat dissipation capability of the product can be improved.

[0108] The foregoing description of specific embodiments will so fully reveal the general nature of the present disclosure that others can easily modify and / or adjust such specific embodiments for various applications by applying knowledge within the technical scope of the art without undue experimentation and without departing from the general concept of the present disclosure. Therefore, based on the disclosure and guidance given herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It will be understood that the words or terms herein are for descriptive purposes rather than for limiting purposes, so that the terms or terms of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0109] The embodiments of the present disclosure have been described above with the help of functional building blocks that illustrate the embodiments of specific functions and their relationships. For ease of description, the limits of these functional building blocks have been arbitrarily defined herein. As long as the specified functions and their relationships are properly performed, alternative limits can be defined.

[0110] The Summary and Abstract sections may set forth one or more, but not all, embodiments of the present disclosure contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0111] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor structure comprising: Printed circuit boards; Chip packaging structure; as well as A ball grid array is connected between the printed circuit board and the chip packaging structure, and the ball grid array includes: first solder balls, each of the first solder balls having a first lateral dimension, and Second solder balls, each of the second solder balls having a second lateral dimension greater than the first lateral dimension, wherein the second solder balls are respectively located at corners of the ball grid array.

2. The semiconductor structure according to claim 1, wherein: Each second solder ball occupies at least one corner position of the ball grid array and extends laterally along a diagonal direction of the ball grid array.

3. The semiconductor structure according to claim 1, wherein: Each second solder ball occupies at least one corner position of the ball grid array and comprises: a first portion extending laterally along a first direction, wherein the first direction is along a row of the ball grid array; and The second portion extends laterally along a second direction, wherein the second direction is along the columns of the ball grid array.

4. The semiconductor structure according to claim 1, wherein: Each second solder ball partially surrounds a corner first solder ball of the ball grid array and comprises: a first portion extending laterally along a first direction, wherein the first direction is along a row of the ball grid array; and The second portion extends laterally along a second direction, wherein the second direction is along the columns of the ball grid array.

5. The semiconductor structure of claim 1, wherein: The first solder ball is electrically connected between the printed circuit board and the chip packaging structure; and The second solder ball is electrically disconnected from the printed circuit board or the chip packaging structure.

6. The semiconductor structure according to claim 1, wherein: The chip packaging structure comprises: substrate; at least one chip attached to the first surface of the substrate; a conductive wiring structure embedded in the substrate and electrically connected to the at least one chip, The ball grid array is attached to a second surface of the substrate opposite to the first side, the first solder balls are electrically connected to the conductive wiring structure, and the second solder balls are electrically disconnected from the conductive wiring structure.

7. The semiconductor structure according to claim 6, wherein: The chip packaging structure further includes: an array of ball pads, located on the second surface of the substrate, the array of ball pads comprising: first ball pads, each of which has a first area and is electrically connected to the conductive wiring structure, and second ball pads, each of which has a second area and is electrically disconnected from the conductive wiring structure, Wherein, the first area is smaller than the second area.

8. The semiconductor structure according to claim 1, wherein: A first material of the first solder ball is different from a second material of the second solder ball.

9. The semiconductor structure of claim 8, wherein: The first material has a first mechanical strength and a first coefficient of thermal expansion; and The second material has a second mechanical strength greater than the first mechanical strength and a second thermal expansion coefficient less than the first thermal expansion coefficient.

10. A method of forming a semiconductor structure, comprising: Provide chip packaging structure, including: attaching at least one chip to the first surface of the substrate, and A ball grid array is formed on the second surface of the substrate, the ball grid array comprising: first solder balls, each of the first solder balls having a first lateral dimension, and second solder balls, each of the second solder balls having a second lateral dimension greater than the first lateral dimension, wherein The second solder balls are respectively located at corners of the ball grid array; and The chip package structure is attached to a printed circuit board such that the ball grid array is connected between the chip package structure and the printed circuit board.

11. The method according to claim 10, wherein: Providing the chip packaging structure includes: forming a conductive wiring structure embedded in the substrate; and An array of ball pads is formed on the second surface of the substrate, the array of ball pads comprising: first ball pads, each of which has a first area and is electrically connected to the conductive wiring structure, and second ball pads, each of which has a second area and is electrically disconnected from the conductive wiring structure, Wherein, the first area is smaller than the second area.

12. The method according to claim 11, wherein: Providing the chip packaging structure also includes: attaching the at least one chip to the first surface of the substrate; wiring the at least one chip to the conductive wiring structure; The ball grid array is formed on the array of ball pads, and the ball grid array is formed on the array of ball pads, comprising: forming the first solder balls on the first ball pads, respectively; and The second solder balls are formed on the second ball pads, respectively.

13. The method according to claim 12, wherein: The first solder ball and the second solder ball are formed simultaneously in the same process.

14. The method according to claim 12, further comprising: An array of ball openings is formed in a mounting area of ​​the printed circuit board, the array of ball openings comprising: first ball openings, each of the first ball openings having a third area and exposing a contact pad electrically connected to a circuit of the printed circuit board, and Second ball openings, each of the second ball openings has a fourth area greater than the third area, wherein the second ball openings are respectively located at corners of the mounting area.

15. The method according to claim 14, wherein: Attaching the chip package structure to the printed circuit board includes: aligning the chip package structure to the mounting area of ​​the printed circuit board; attaching the chip package structure to the mounting area of ​​the printed circuit board such that each first solder ball is located in a corresponding first ball opening and each second solder ball is located in a corresponding second ball opening; and The ball grid array is heated and cooled sequentially so that the chip package structure is mechanically connected to the printed circuit board through the first solder balls and the second solder balls.

16. A chip packaging structure, comprising: substrate; at least one chip attached to the first surface of the substrate; a conductive wiring structure embedded in the substrate and electrically connected to the at least one chip; as well as an array of ball pads located on a second surface of the substrate opposite to the first surface, the array of ball pads comprising: first ball pads, each of the first ball pads having a first area, and Second ball pads, each of the second ball pads has a second area greater than the first area, wherein the second ball pads are respectively located at corners of the array of the ball pads.

17. The chip packaging structure according to claim 16, wherein: Each second ball pad occupies at least one corner position of the array of ball pads and extends laterally along a diagonal direction of the array of ball pads.

18. The chip packaging structure according to claim 16, wherein: Each second ball pad occupies at least one corner position of the array of ball pads and comprises: a first portion extending laterally along a first direction, wherein the first direction is along a row of the array of ball pads; and The second portion extends laterally along a second direction, wherein the second direction is along a column of the array of ball pads.

19. The chip packaging structure according to claim 16, wherein: Each second ball pad partially surrounds a corner first ball pad of the array of ball pads and comprises: a first portion extending laterally along a first direction, wherein the first direction is along a row of the array of ball pads; and The second portion extends laterally along a second direction, wherein the second direction is along a column of the array of ball pads.

20. The chip packaging structure according to claim 16, wherein: The first ball pad is electrically connected to the at least one chip through the conductive wiring structure; and The second ball pad is electrically disconnected from the at least one chip and the conductive wiring structure.

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