Semiconductor package, semiconductor module, semiconductor device, and semiconductor package manufacturing method

Abstract

The semiconductor package disclosed herein includes: a semiconductor chip configured such that a circuit is mounted on one of two surfaces of the semiconductor chip, the circuit forming surface constituting a circuit forming surface; a first shielding layer configured to cover a side surface of the semiconductor chip and the other surface of the semiconductor chip; and a second shielding layer configured to cover the circuit forming surface.

Description

[0001] Related Applications

[0002] This application claims the benefit of Japanese Priority Patent Application JP 2022-180705 filed Nov. 11, 2022, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] The present technology relates to a semiconductor package, and more particularly to a chip-sized semiconductor package, a semiconductor module, a semiconductor device, and a method for manufacturing the semiconductor package. Background Art

[0004] In the past, shielding has been used in various semiconductor packages and electronic devices to protect their circuits from electromagnetic noise. For example, a semiconductor package has been proposed in which a shielding layer is formed on the back and side surfaces of a semiconductor chip, the front side of the semiconductor chip opposite to the back side being a circuit surface (for example, see PTL 1).

[0005] [Citation List]

[0006] [Patent Document]

[0007] [PTL 1]

[0008] Japanese Patent Application Publication No. 2010-103574 Summary of the invention

[0009] [Technical issues]

[0010] According to the above-mentioned prior art, the back and side of the semiconductor chip are covered with a shielding layer to protect the circuit in the chip from electromagnetic noise. However, in this semiconductor package, the surface of the semiconductor chip (i.e., its circuit surface) is not shielded. Therefore, if electromagnetic noise occurs in a manner that propagates from the front to the back, there may be a problem that the electrical characteristics of the circuit are degraded due to EMI (electromagnetic interference).

[0011] The present technology has been devised in view of the above circumstances, and it is desirable to improve the resistance of a semiconductor package including a semiconductor chip to EMI.

[0012] [Solution to the problem]

[0013] According to a first mode of the present technology, a semiconductor package and a method for manufacturing the semiconductor package are provided, the semiconductor package comprising: a semiconductor chip configured to have a circuit mounted on one of its two surfaces (the circuit forming surface constitutes a circuit forming surface); a first shielding layer configured to cover a side surface of the semiconductor chip and the other surface thereof, and a second shielding layer configured to cover the circuit forming surface. This provides an effect of improving the resistance of the circuit in the semiconductor package to EMI.

[0014] In addition, according to the first mode of the present technology, the semiconductor package may further include an under bump metal, wherein the second shield layer includes a portion of a seed layer for growing the under bump metal. This provides an effect of obtaining the shield layer by etching the seed layer.

[0015] In addition, according to the first mode of the present technology, the semiconductor package may further include an insulating layer configured to cover the circuit formation surface, wherein the second shielding layer covers a portion of the insulating layer except for a predetermined area around the UBM when viewed from a direction perpendicular to the semiconductor chip. This provides an effect of insulating the UBM from the surroundings.

[0016] In addition, according to the first mode of the present technology, the semiconductor package may further include: a first redistribution layer formed outside the protection region as a part of the circuit formation surface, wherein the second shielding layer includes a second redistribution layer covering the shielding region and connected to the ground. This provides an effect of improving the resistance of the circuit on the protection region to EMI.

[0017] According to a second mode of the present technology, there is provided a semiconductor module, comprising: a semiconductor package, the semiconductor package comprising: a first semiconductor chip configured so that one of the two surfaces of the first semiconductor chip is mounted with a circuit, the circuit forming surface constituting a circuit forming surface; a first shielding layer configured to cover the side surface of the semiconductor chip and the other surface of the semiconductor chip; and a second shielding layer configured to cover the circuit forming surface; and a substrate configured to mount a semiconductor package on the substrate. This provides an effect of improving the resistance of the circuit in the semiconductor module to EMI.

[0018] In addition, according to the second mode of the present technology, the semiconductor module may further include: a signal via configured to penetrate the substrate; and a plurality of ground vias configured to penetrate the substrate in a manner surrounding the signal via when viewed from a direction perpendicular to the substrate. This provides an effect of further improving resistance to EMI.

[0019] In addition, according to the second mode of the present technology, the semiconductor module may further include: a first circuit formed in the first semiconductor chip and a second circuit configured to generate noise, wherein the first circuit and the second circuit are each connected to a different ground. This provides an effect of improving the resistance of the first circuit to EMI.

[0020] Furthermore, according to the second mode of the present technology, the second circuit can be formed in the substrate. This provides an effect of suppressing degradation of electrical characteristics to noise from the substrate side.

[0021] Furthermore, according to the second mode of the present technology, the semiconductor package and the second circuit can be provided on the surface of the substrate. This provides an effect of suppressing the degradation of the circuit electrical characteristics on the circuit caused by noise.

[0022] Furthermore, according to the second mode of the present technology, the semiconductor module may further include: a shield configured to surround the semiconductor package when viewed from a direction perpendicular to the substrate. This provides an effect of further improving resistance to EMI.

[0023] Moreover, according to the second mode of the present technology, the substrate may include: a wiring layer configured to mount a semiconductor package at a predetermined position on one of the two surfaces of the substrate; a protrusion configured to protrude in a direction perpendicular to the other surface of the substrate; a first shielding layer configured to cover an inner wall of the protrusion; and a signal via configured to penetrate the protrusion. This provides an effect of allowing the semiconductor module to be electrically connected to an external device or an external circuit.

[0024] In addition, according to the second mode of the present technology, the substrate may further include: a heat dissipation portion provided at a position corresponding to the predetermined position on the other surface of the substrate; and a ground via configured to penetrate the heat dissipation portion and have a ground potential. This provides an effect of improving heat dissipation performance.

[0025] Moreover, according to the second mode of the present technology, the semiconductor module may further include an integrated circuit arranged on the other surface of the substrate, wherein the wiring layer includes a second shielding layer, and when viewed from a direction perpendicular to the other surface of the substrate, the integrated circuit is surrounded by a portion of the raised portion. This provides an effect of improving resistance to EMI.

[0026] Moreover, according to the second mode of the present technology, the semiconductor module may further include a second semiconductor chip mounted on the inner wall of the raised portion. This provides an effect of improving electrical characteristics.

[0027] In addition, according to the second mode of the present technology, the substrate may further include: a wiring layer configured to mount the semiconductor package on one of the two surfaces of the substrate; a connector mounted on the other surface of the substrate in a manner protruding in a direction perpendicular to the other surface; and a shielding layer configured to cover the inner wall of the connector. This provides an effect of improving reworkability.

[0028] Furthermore, according to a third mode of the present technology, there is provided an electronic device including a semiconductor package, the semiconductor package including: a semiconductor chip configured so that one of the two surfaces of the semiconductor chip is mounted with a circuit, the circuit forming surface constituting a circuit forming surface; a first shielding layer configured to cover the side surface of the semiconductor chip and the other surface thereof; and a second shielding layer configured to cover the circuit forming circuit surface; and a substrate configured so that the semiconductor chip is mounted on the substrate. This provides an effect of improving the resistance of the circuit in the electronic device to EMI. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A sectional view and a bottom view showing a configuration example of a semiconductor package as a first embodiment of the present technology are included.

[0030] Figure 2 1 is an exemplary bottom view of a semiconductor package as a first embodiment of the present technology.

[0031] Figure 3 A set of views illustrating steps up to application of a resist in the first embodiment of the present technology.

[0032] Figure 4 A set of views illustrating steps up to forming solder balls in the first embodiment of the present technology.

[0033] Figure 5 A set of views illustrating steps up to forming the shielding layer on the back surface and the side surface in the first embodiment of the present technology.

[0034] Figure 6 is an exemplary flow chart showing an exemplary method of manufacturing a semiconductor package as a first embodiment of the present technology.

[0035] Figure 7 is a cross-sectional view showing a configuration example of a semiconductor package as a second embodiment of the present technology.

[0036] Figure 8 1 is an exemplary bottom view of a semiconductor package as a second embodiment of the present technology.

[0037] Fig. 9 is a cross-sectional view showing a configuration example of a semiconductor module as a third embodiment of the present technology.

[0038] Fig.10 is a cross-sectional view showing a configuration example of a semiconductor module as a fourth embodiment of the present technology.

[0039] Fig.11 is a cross-sectional view showing a configuration example of a semiconductor module as a fifth embodiment of the present technology.

[0040] Fig.12 is a block diagram showing a configuration example of a semiconductor module as a fifth embodiment of the present technology.

[0041] Fig.13 is a cross-sectional view showing another configuration example of the digital circuit in the fifth embodiment of the present technology.

[0042] Fig.14 is a cross-sectional view showing a configuration example of a semiconductor module as a sixth embodiment of the present technology.

[0043] Fig.15 is an exemplary top view of a semiconductor module as a sixth embodiment of the present technology.

[0044] Fig.16 is an exemplary perspective view of an electronic device as a seventh embodiment of the present technology.

[0045] Fig.17 is a block diagram showing a configuration example of an electronic device as a seventh embodiment of the present technology.

[0046] Fig.18 is a cross-sectional view showing a configuration example of a semiconductor module as an eighth embodiment of the present technology.

[0047] Fig.19 1 is an exemplary bottom view of a substrate in an eighth embodiment of the present technology.

[0048] Fig. 20 is a cross-sectional view showing a configuration example of a semiconductor module as a first modification example of the eighth embodiment of the present technology.

[0049] Fig.21 It is an exemplary bottom view of the substrate in the first modification example of the eighth embodiment of the present technology.

[0050] Fig. 22 is a cross-sectional view showing a configuration example of a semiconductor module as a second modification example of the eighth embodiment of the present technology.

[0051] Fig.23 is a cross-sectional view showing a configuration example of a semiconductor module as a ninth embodiment of the present technology.

[0052] Fig.24 1 is an exemplary bottom view of a substrate in a ninth embodiment of the present technology.

[0053] Fig.25 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0054] Fig.26 : is a diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0055] Preferred embodiments for implementing the present technology (hereinafter referred to as embodiments) are described below. Descriptions will be given under the following headings in the following order.

[0056] 1. First Embodiment (Example of Forming a Shielding Layer on a Circuit Formation Surface)

[0057] 2. Second Embodiment (Example of Forming a Redistribution Layer as a Shielding Layer on a Circuit Formation Surface)

[0058] 3. Third Embodiment (Example of Mounting a Semiconductor Package Having a Shielding Layer Formed on a Circuit Formation Surface)

[0059] 4. Fourth Embodiment (Example in which a shielding layer is formed on a circuit forming surface and through-hole vias are coaxial structures)

[0060] 5. Fifth Embodiment (Example in which a shielding layer is formed on a circuit forming surface and the circuit ground is separated)

[0061] 6. Sixth Embodiment (Example in which a shielding layer is formed on a circuit formation surface and a shielding member is arranged)

[0062] 7. Seventh Embodiment (Example of Electronic Device Equipped with a Semiconductor Package Having a Shielding Layer Formed on a Circuit Formation Surface)

[0063] 8. Eighth Embodiment (Example in which a semiconductor package having a shielding layer formed on a circuit formation surface is mounted on a substrate equipped with a heat dissipation portion)

[0064] 9. Ninth Embodiment (Example in which a semiconductor package having a shield layer formed on a circuit formation surface is mounted on a substrate equipped with a connector)

[0065] 10. Application examples for mobile objects

[0066] <1. First Embodiment>

[0067] [Semiconductor package configuration example]

[0068] Figure 1 A cross-sectional view and a bottom view showing a configuration example of a semiconductor package 300 as a first embodiment of the present technology are included. Figure 1 The view “a” in FIG. 1 is a cross-sectional view of the semiconductor package 300 , and Figure 1 The view “b” in FIG. 3 is a partial bottom view of the semiconductor package 300 .

[0069] The semiconductor package 300 is a CSP (chip size package) including a semiconductor chip 311. A circuit such as an IC (integrated circuit) is formed on one of the two surfaces of the semiconductor chip 311. This surface is hereinafter referred to as a "circuit forming surface" or "surface". In addition, the direction from this surface to the back side relative to this surface is referred to as the "upward" direction. In addition, the axis perpendicular to the surface of the semiconductor chip 311 is referred to as the "Z axis", and the direction parallel to the surface is referred to as the "X axis". The axis perpendicular to the X axis and the Z axis is referred to as the "Y axis". Figure 1 View "a" in FIG. 1 is a cross-sectional view viewed from the Y-axis direction.

[0070] A predetermined number of pads 321 are formed on the circuit forming surface (surface) of the semiconductor chip 311. The surface is covered with a passivation layer 322 having an opening that exposes each pad 321. The bottom surface of the passivation layer 322 is covered with an insulating layer 323 having an opening that partially exposes each pad 321.

[0071] The bottom surfaces of each pad 321 and the insulating layer 323 are covered by the shield layer 331. In addition, on the bottom surface of the shield layer 331, an under bump metal 351 is formed at a position corresponding to each pad 321. To each under bump metal 351, a solder ball 352 is connected.

[0072] In addition, the side and back sides of the semiconductor chip 311, a total of 5 faces, are covered by the shielding layer 340. In the case where the shielding layer 331 covers the circuit forming surface (surface) of the semiconductor chip 311 and the shielding layer 340 covers the side and back sides thereof, the resistance to EMI is made greater than the case where only the side and back sides of the semiconductor chip 311 are covered. Incidentally, the shielding layer 340 is an example of the first shielding layer described in the appended claims, and the shielding layer 331 is an example of the second shielding layer also described in the appended claims.

[0073] Figure 1The view "b" in FIG. 3 shows an area around an under bump metal 351 on the bottom surface of the semiconductor package 300 before the solder ball 352 is formed thereon. As shown in the view "b", when viewed from the Z-axis direction, the insulating layer 323 is covered by the shielding layer 331 except for some areas around the under bump metal 351. The area indicated by the oblique line hatching is an area where the shielding layer 331 is not formed, exposing the insulating layer 323. The exposed insulating layer 323 insulates the under bump metal 351 and the solder ball 352 from their surroundings. Assuming that X2 represents the edge of the under bump metal 351, the insulating layer 323 is exposed in the range of the coordinate X1 to the coordinate X2. The distance between the coordinates X1 and X2 represents the width of the exposed area (in other words, the distance represents the spacing between the under bump metal 351 and the shielding layer 331). For example, the spacing is set to at least 5 micrometers (μm).

[0074] exist Figure 1 In view “b” of FIG. 3 , when viewed from the Z-axis direction, the insulating layer 323 is exposed along a plurality of linear paths.

[0075] By the way, if Figure 2 As shown, the insulating layer 323 may be exposed along a circular path around the perimeter of the under bump metallurgy 351 .

[0076] [Semiconductor package manufacturing method]

[0077] The following reference Figures 3 to 5 A method for manufacturing the semiconductor package 300 will be described. Figure 3 A set of views illustrating the steps of applying the resist in the first embodiment of the present technology. Figure 3 As shown in view "a" in FIG. 1 , a pad 321 including an Al-based metal such as aluminum (Al), an aluminum-neodymium (Al-Nd) alloy, or an aluminum-titanium (Al-Ti) alloy is formed on the surface of the wafer 310. The surface of the wafer 310 is then covered with a passivation layer 322 having an opening that partially exposes the pad 321. The passivation layer 322 is made of, for example, silicon dioxide (SiO 2 ), silicon nitride (SiN) or TEOS (tetraethylorthosilicate).

[0078] Next, if Figure 3 As shown in view “b” in FIG. 1 , an insulating layer 323 including, for example, polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO) is formed by using exposure and development techniques.

[0079] Next, if Figure 3As shown in view "c" in the figure, a seed layer 330 serving as a plating seed is formed on substantially the entire surface of the wafer 310 having the pad 321 and the insulating layer 323 formed thereon by vapor deposition, sputtering, CVD (chemical vapor deposition), or electroless plating.

[0080] The seed layer 330 is configured as a multilayer structure in which a chromium (Cr) or titanium (Tr) layer of about 1,300 angstroms thick and a copper (Cu) layer of about 5,000 angstroms thick are stacked one above the other by a sputtering method. Incidentally, the chromium (Cr) or titanium (Ti) layer may be replaced with a multilayer structure in which a nickel (Ni), palladium (Pd) or platinum (Pt) layer and a copper (Cu) layer are stacked on top of each other. Alternatively, a three-layer structure may be provided in which a nickel (Ni), palladium (Pd) or platinum (Pt) layer; a titanium (Ti) or chromium (Cr) layer; and a copper (Cu) layer are stacked one above the other.

[0081] Next, if Figure 3 As shown in view "d" in FIG. 3 , a resist 400 is applied onto the seed layer 330. Electroplating or electroless plating is performed using the resist 400 as a mask.

[0082] Figure 4 A set of views illustrating steps up to the formation of solder balls 352 in the first embodiment of the present technology. Figure 4 As shown in view "a" of FIG. 3 , the under bump metal 351 is formed by electroplating. For example, a possible material of the under bump metal 351 may be copper (Cu), and nickel (Ni) is used as a barrier metal.

[0083] Next, as in Figure 4 As depicted in view "b" of FIG. 4 , the resist 400 is removed. Figure 4 As shown in view "c" in FIG. 3 , the seed layer 330 is then removed by etching, leaving a portion serving as the shield layer 331. The shield layer 331 on the circuit formation surface of the semiconductor package 300 may be alternatively formed of aluminum wiring, copper rewiring, or under bump metal in addition to the above-mentioned seed layer 330. The area ratio of the shield layer 331 including the wiring and the pad 321 should preferably be at least 50% of the chip area.

[0084] Next, as in Figure 4 As depicted in view "d" of FIG. 3 , solder balls 352 are mounted. The bumps are formed by reflow soldering.

[0085] Figure 5 A set of views illustrating the steps up to forming the shielding layer 340 on the back surface and the side surface in the first embodiment of the present technology. Figure 5 As shown in view "a" of FIG. 3 , dicing is performed in a dicing region, thereby dicing the wafer 310 into pieces. Individualization provides a plurality of semiconductor chips 311 .

[0086] Next, as in Figure 5 As shown in the view "b" of FIG. 3, a shielding layer 340 is formed on five surfaces of the semiconductor chip 311 except its circuit forming surface. The shielding layer 340 is a multilayer film deposited to a thickness of at least several micrometers (μm) by using at least one of metals such as copper, titanium, nickel and gold. The shielding layer 340 is formed by, for example, sputtering, ion plating, spraying, CVD, inkjet or screen printing. In addition, the shielding layer 340 can also be formed by a vacuum lamination method in which a metal film having the above-mentioned multilayer film is attached to the back and side of the semiconductor chip 311 in a vacuum atmosphere. In this way, a total of six faces including the back and side of the semiconductor chip 311 and the circuit forming surface (surface) are covered by the shielding layers 331 and 340.

[0087] Figure 6 1 is an exemplary flowchart describing an exemplary method of manufacturing a semiconductor package 300 as a first embodiment of the present technology. The manufacturing system forms a pad 321 on a wafer 310, and forms a passivation layer 322 in a manner that partially exposes the pad 321 (step S901). Then, the manufacturing system forms an insulating layer 323 (step S902), and forms a seed layer 330 (step S903). The manufacturing system applies a resist 400 (step S904), and forms an under-bump metal 351 by plating (step S905).

[0088] The manufacturing system continues to remove the resist 400 (step S906), and etches the seed layer 330 so that it partially enters the shielding layer 331 (step S907). Then, the manufacturing system forms solder balls 352 (step S908) before dividing the wafer (step S909). Next, the manufacturing system forms the shielding layer 340 on the side and back of the semiconductor chip 311 (step S910). This completes the manufacturing process of the semiconductor package 300.

[0089] According to the first embodiment of the present technology, as described above, the back and side surfaces of the semiconductor chip 311 are covered by the shield layer 340, and the circuit forming surface (surface) is also covered by the shield layer 331. This makes the resistance to EMI higher than the case where only the back and side surfaces are covered by the shield layer 340.

[0090] <2. Second Embodiment>

[0091] In the first embodiment described above, part of the seed layer 330 is used as the shielding layer 331. Alternatively, a portion other than the seed layer 330 may be arranged to be used as a shielding layer. The semiconductor package 300 as the second embodiment of the present technology is different from the first embodiment in that a redistribution layer (RDL: ReDistribution layer) is used as a shielding layer.

[0092] Figure 7 2 is a cross-sectional view showing a configuration example of a semiconductor package 300 as a second embodiment of the present technology. The semiconductor package 300 as the second embodiment is different from the first embodiment in that an RDL is used as a shield layer 362 .

[0093] In the second embodiment, the circuit forming surface is also covered with a passivation layer 322 in a manner that the pad 321 is exposed. The bottom surface of the passivation layer 322 is covered with a seed layer 324A. The seed layer 324A does not play a shielding role. A predetermined number of under bump metals 351 are formed on the seed layer 324B. Solder balls 352 are formed on each under bump metal 351.

[0094] In addition, RDLs 361 and 362 are formed on the bottom surface of the seed layer 324A. The RDL 361 is linearly formed to be electrically connected to the pad 321. When viewed from the Z-axis direction, the other RDL 362 is formed solid and connected to the ground. The RDL 362 serves as a shielding layer. Figure 7 , the RDL 362 is formed in the region on the right side of the coordinate X2, and the RDL 361 is wired on the left side thereof.

[0095] Furthermore, bottom surfaces of the RDL 361 , the RDL 362 , and the insulating layer 323 are covered with an insulating layer 325 .

[0096] Figure 8 1 is an exemplary bottom view of a semiconductor package 300 as a second embodiment of the present technology. Figure 8 3 is a typical bottom view showing the semiconductor package 300 in a state where the insulating layer 325 located below the insulating layer 323 and the shielding layer 340 on the side surface have not yet been formed.

[0097] like Figure 8 As shown, part of the bottom surface of the insulating layer 323 is covered by the RDL 362, and the covered area is used as a shielding layer. The RDL 362 is further grounded through the solder ball 352. The area covered by the RDL 362 is called the "shielding area". The circuit to be shielded is set on the top of the shielding area.

[0098] In the region on the bottom surface of the insulating layer 323, the region other than the shielding region is wired with a linear RDL 361. The RDL 361 is wired between the solder ball 352 and the pad 321, for example, to provide an electrical connection therebetween.

[0099] Incidentally, a portion of the seed layer 330 is used as a shielding layer 331 in the first embodiment, and the RDL 362 is used as a shielding layer in the second embodiment. Moreover, these configurations do not limit the present technology. For example, the aluminum (Al) wiring layer or the under-bump metal of the semiconductor chip 311 may also be used as a shielding layer.

[0100] According to the second embodiment of the present technology, as described above, part of the RDL 362 is used as a shielding layer, so that only the shielding area of ​​the bottom surface needs to be covered to protect the circuit.

[0101] <3. Third Embodiment>

[0102] Although six surfaces of the semiconductor package 300 are covered by the shielding layer in the first embodiment, the semiconductor package 300 may be placed in a semiconductor module. This third embodiment is different from the first embodiment in that the semiconductor package 300 of the first embodiment is mounted in a semiconductor module.

[0103] Fig. 9 2 is a cross-sectional view showing a configuration example of a semiconductor module 200 as a third embodiment of the present technology. The semiconductor module 200 as the third embodiment includes a frame substrate 220 and a semiconductor package 300. Incidentally, the frame substrate 220 is an example of a substrate described in the appended claims.

[0104] A wiring layer 221 is formed on one of the two surfaces of the frame substrate 220, which is regarded as the top surface, and a circuit forming surface of the semiconductor package 300 in the first embodiment is provided. In addition, the wiring layer 221 and the semiconductor package 300 are covered with a molding resin 211. The side and top surfaces of the molding resin 211 are covered with a shielding layer 212.

[0105] Furthermore, in the frame substrate 220, a predetermined number of passive elements 223 are mounted, and a predetermined number of through holes 222 are formed. A predetermined number of solder balls 224 are formed on the bottom surface of the frame substrate 220. The solder balls 224 are connected to the wiring layer 221 through the through holes 222.

[0106] As described above, six surfaces of the semiconductor package 300 are covered by the shielding layers 331 and 340. Thus, it is possible to prevent the electrical characteristics of the semiconductor module 200 from being deteriorated due to EMI generated by a group (not shown) mounting the semiconductor module 200.

[0107] Incidentally, the second embodiment can be applied to the third embodiment.

[0108] According to the third embodiment of the present technology, as described above, the semiconductor package 300 covered with the shield layer is mounted in the semiconductor module 200. This improves the resistance of the semiconductor module 200 to EMI.

[0109] <4. Fourth Embodiment>

[0110] In the third embodiment described above, the through hole 222 is formed in the frame substrate 220. However, in this configuration, EMI may degrade the electrical characteristics of the circuit connected to the through hole 222. The semiconductor module 200 of the fourth embodiment is different from the third embodiment in that the through hole is a coaxial structure.

[0111] Fig.10 is a cross-sectional view showing a configuration example of a semiconductor module 200 as a fourth embodiment of the present technology. Fig.10 View “a” in FIG. 1 is an exemplary cross-sectional view of the semiconductor module 200 viewed from the Y-axis direction.

[0112] Fig.10 The view "b" in FIG. 1 is an enlarged view of the portion surrounded by the dotted line in FIG. Fig.10 As shown in view "b" in FIG. 1 , the fourth embodiment forms a signal via 222-1 and a ground via 222-2 in the frame substrate 220. The signal via 222-1 penetrates the frame substrate 220 to transmit an electrical signal. The ground via 222-2 penetrates the frame substrate 220 to be grounded.

[0113] Fig.10 The view "c" in FIG. 1 is a cross-sectional view taken along the line segment A1-A2 in the view "b" in the illustration when viewed from the Z-axis direction. Fig.10 As shown in view "c" in FIG. 1 , a plurality of ground vias 222-2 surround each signal via 222-1. The through-hole vias coaxially configured as described above suppress the degradation of the electrical characteristics of the semiconductor module 200 due to EMI generated by a group (not shown) on which the semiconductor module 200 is mounted.

[0114] Incidentally, the second embodiment can be applied to the fourth embodiment.

[0115] According to the fourth embodiment of the present technology, as described above, through-hole vias are coaxially configured to improve the resistance of the semiconductor module 200 to EMI.

[0116] <5. Fifth embodiment>

[0117] In the third embodiment described above, there is no circuit that can be a noise source inside the semiconductor module 200. However, such a circuit can be provided as needed. The semiconductor module 200 of the fifth embodiment is different from the third embodiment in that a circuit that is a noise source is provided inside the module.

[0118] Fig.112 is a cross-sectional view showing a configuration example of a semiconductor module 200 as a fifth embodiment of the present technology. The semiconductor module 200 of the fifth embodiment is different from the third embodiment in that a digital circuit 225 is additionally provided.

[0119] The digital circuit 225 is mounted in the frame substrate 220 below the wiring layer 221. The digital circuit 225 generates noise, and can be presumed to be, for example, a PMIC (Power Management IC).

[0120] Fig.12 2 is a block diagram showing a configuration example of a semiconductor module 200 as a fifth embodiment of the present technology. The semiconductor module 200 includes a semiconductor package 300 and a digital circuit 225. An analog circuit 371 is provided inside the semiconductor package 300. For example, the analog circuit 371 can be presumed to be an RFIC (Radio Frequency IC).

[0121] In addition, the analog circuit 371 is connected to the power supply 231 and the ground 232. On the other hand, the digital circuit 225 is connected to the power supply 233 and the ground 234. As described above, the digital circuit 225 may be a noise source. In addition, it is assumed that the analog circuit 371 is susceptible to noise from the digital circuit 225. In this case, the digital circuit 225 is an interference source, and the analog circuit 371 is a victim. Incidentally, the analog circuit 371 is an example of a first circuit described in the appended claims, and the digital circuit 225 is an example of a second circuit also described in the appended claims.

[0122] like Fig.12 As shown, the power supply and ground of the analog circuit 371 (the victim) are different from the power supply and ground of the digital circuit 225 (the interference source), and are therefore separated from each other. This prevents the victim from being affected by the electromagnetic noise superimposed on the power supply and ground of the interference source, thereby suppressing the degradation of the electrical characteristics of the victim.

[0123] By the way, if Fig.13 As shown, the digital circuit 225 may be mounted on the top surface of the frame substrate 220 together with the semiconductor package 300 .

[0124] Preferably, the second embodiment or the fourth embodiment may be applied to the fifth embodiment.

[0125] According to the fifth embodiment of the present technology, as described above, the power supply and ground of the analog circuit 371 (victim) are separated from the digital circuit 225. This suppresses degradation of the electrical characteristics of the victim even when an interference source is placed inside the module.

[0126] <6. Sixth Implementation Method>

[0127] In the fifth embodiment described above, the digital circuit 225 used as a noise source is disposed inside the semiconductor module 200. However, the shielding layer of the semiconductor module 200 may not be sufficient as a measure against EMI. The semiconductor module 200 as the sixth embodiment is different from the fifth embodiment in that the semiconductor package 300 is surrounded by a shielding member.

[0128] Fig.14 2 is a cross-sectional view showing a configuration example of a semiconductor module 200 as a sixth embodiment of the present technology. The semiconductor module 200 of the sixth embodiment is different from the fifth embodiment in that a shielding member 213 is provided on the top surface of the frame substrate 220. In addition, in the sixth embodiment, a digital circuit 225 is mounted on the top surface of the frame substrate 220 together with a semiconductor package 300.

[0129] Fig.15 is an exemplary top view of a semiconductor module 200 as a sixth embodiment of the present technology. Fig.15 2 is a top view of the semiconductor module 200 in a state where the molded resin 211 and the shielding layer 212 have not yet been formed. When viewed from the Z-axis direction, the shielding member 213 is provided around the semiconductor package 300. In other words, the semiconductor package 300 is installed in an area separated by the shielding member 213. By providing the shielding member 213 in this manner, it is possible to prevent the electrical characteristics of the circuit in the semiconductor package 300 from being degraded due to EMI from the digital circuit 225 (interference source).

[0130] Incidentally, the second or fourth embodiment can be applied to the sixth embodiment.

[0131] According to the sixth embodiment of the present technology, as described above, the semiconductor package 300 is mounted in the area partitioned by the shield 213. This further improves the resistance to EMI.

[0132] <7. Seventh Implementation Method>

[0133] Although the six surfaces of the semiconductor package 300 are covered by the shielding layer in the above-mentioned first embodiment, the semiconductor package 300 may be placed in an electronic device. This seventh embodiment is different from the first embodiment in that the semiconductor package 300 of the first embodiment is incorporated in an electronic device.

[0134] Fig.16 1 is an exemplary perspective view of an electronic device 100 as a seventh embodiment of the present technology. For example, the electronic device 100 can be used as a game machine.

[0135] Fig.171 is a block diagram describing a configuration example of an electronic device 100 as a seventh embodiment of the present technology. The electronic device 100 includes a main CPU (central processing unit) 110 and a system controller 120. The main CPU 110 and the system controller 120 are powered by a battery or other power source (not shown) in different power supply systems. The main CPU 110 includes a menu processing unit 111 and an application processing unit 112, the menu processing unit 111 generates a menu screen that allows a user to set various information or select an application, and the application processing unit 112 executes the application.

[0136] The electronic device 100 also includes a setting information holding unit 130, such as a memory for holding various information set by a user. User setting information is output from the main CPU 110 to the setting information holding unit 130. The setting information holding unit 130 holds the information output thereby. The system controller 120 includes an operation input receiving unit 121, a communication processing unit 122, and a power control unit 123. The operation input receiving unit 121 detects the state of the operation key. In addition, the communication processing unit 122 processes communication with an external device. The power control unit 123 controls the power supply to the components of the electronic device 100. By the way, the semiconductor package 300 of the first embodiment or the semiconductor module 200 of the third embodiment is incorporated in at least one component including the main CPU 110, the system controller 120, and the setting information holding unit 130.

[0137] The semiconductor package 300 of the first embodiment or the semiconductor module 200 of the third embodiment may be used to prevent the electrical characteristics of the electronic device 100 from being degraded by EMI.

[0138] Incidentally, the second embodiment, the fourth embodiment, the fifth embodiment, or the sixth embodiment can be applied to the seventh embodiment.

[0139] According to the seventh embodiment of the present technology, as described above, the semiconductor package 300 or the semiconductor module 200 is incorporated in the electronic device 100. This improves the resistance of the electronic device 100 to EMI.

[0140] <8. Eighth Implementation Method>

[0141] Although the six surfaces of the semiconductor package 300 in the first embodiment described above are covered by the shielding layer, when the semiconductor package 300 is mounted on a frame substrate, it may cause problems with heat dissipation performance. The eighth embodiment is different from the first embodiment in that the semiconductor package 300 of the first embodiment is mounted on a substrate arranged to promote heat dissipation.

[0142] Fig.182 is a cross-sectional view showing a configuration example of a semiconductor module 200 as an eighth embodiment of the present technology. The semiconductor module 200 as the eighth embodiment includes a substrate 240 and a semiconductor package 300 .

[0143] The substrate 240 includes a wiring layer 241, a protrusion 251, and a heat dissipation portion 252. The semiconductor package 300 is mounted on the top surface of the wiring layer 241. In addition, the wiring layer 241 and the semiconductor package 300 are covered with a molded resin 211. The side and top surfaces of the molded resin 211 are covered with a shielding layer 212. In addition, the protrusion 251 and the heat dissipation portion 252 are provided on the bottom surface of the wiring layer 241.

[0144] The raised portion 251 is a member protruding from the bottom surface of the wiring layer 241 in the Z-axis direction. When viewed from the Z-axis direction, the raised portion 251 extends linearly along at least a portion of the periphery of the substrate 240. The inner wall of the raised portion 251 is covered by a metal film 253. The metal film 253 serves as a shielding layer. The heat dissipation portion 252 is a member for dissipating heat, and is located on the bottom surface of the wiring layer 241 in a manner corresponding to the position where the semiconductor package 300 is mounted on the top surface of the wiring layer 241. For example, in the case where the semiconductor package 300 is mounted in the center of the top surface of the wiring layer 241, the heat dissipation portion 252 is provided in the center of the bottom surface of the wiring layer 241.

[0145] In addition, both the protrusion 251 and the heat dissipation portion 252 are provided with a conductive via that penetrates the protrusion 251 or the heat dissipation portion 252 in the Z-axis direction. The protrusion 251 has a signal via 254-1 as its conductive via, and the heat dissipation portion 252 has a ground via 254-2 as its conductive via. One end of each conductive via is connected to the wiring layer 241, and the other end is connected to the solder ball 224. The signal via 254-1 transmits an electrical signal. The ground via 254-2 is connected to the ground potential.

[0146] Fig.19 1 is an exemplary bottom view of the substrate 240 in the eighth embodiment of the present technology. Fig.19 2 is a bottom view of the substrate 240 in a state where the solder ball 224 has not yet been mounted. The protrusions 251 are provided on the right and left edges of the substrate 240. A predetermined number of signal vias 254-1 are arranged in these protrusions 251. Incidentally, the shape of the protrusions 251 is not limited to Fig.19 As shown in ; when viewed from the Z-axis direction, the protrusion 251 may alternatively have a frame-like shape.

[0147] Furthermore, an island-shaped heat dissipation portion 252 is provided at the center of the bottom surface of the substrate 240. A predetermined number of ground vias 254-2 are provided in the heat dissipation portion 252. These ground vias 254-2 efficiently dissipate heat generated by the semiconductor package 300, thereby improving heat dissipation performance.

[0148] Furthermore, as will be described later, a semiconductor chip and a circuit may be mounted in the space between the raised portion 251 and the heat dissipation portion 252 .

[0149] According to the eighth embodiment of the present technology, as described above, the semiconductor package 300 is mounted on the substrate 240 having the heat dissipation portion 252. This enhances the heat dissipation performance.

[0150] [First Modification]

[0151] Although the semiconductor package 300 is mounted on the substrate 240 in the above-mentioned eighth embodiment, the electrical characteristics of the semiconductor module 200 may be degraded due to noise by providing a noise source or a circuit susceptible to noise on the bottom surface of the substrate 240. The semiconductor module 200 as a first modification of the eighth embodiment is different from the eighth embodiment in that a ground via is provided around the noise source or the circuit susceptible to noise.

[0152] Fig. 20 2 is a cross-sectional view showing a configuration example of a semiconductor module 200 as a first modification of the eighth embodiment of the present technology. The semiconductor module 200 as the first modification of the eighth embodiment is different from the eighth embodiment in that the heat dissipation portion 252 is not provided, and an integrated circuit 261 is mounted on the bottom surface of the wiring layer 241. The integrated circuit 261 is a potential noise source or a circuit susceptible to noise. For example, an RFIC (radio frequency integrated circuit) or a transmission side IC may be mounted as the integrated circuit 261.

[0153] In addition, a part of the raised portion 251 surrounds the integrated circuit 261. A metal film 253 is formed on the inner wall of the part of the raised portion 251. In addition, on the wiring layer 241, a rewiring 241-1 connected to the ground is set on the top of the integrated circuit 261. When viewed from the Z-axis direction, the rewiring 241-1 should preferably cover the top surface of the integrated circuit 261. The rewiring 241-1 includes a material such as a silicon-aluminum (Si-Al) alloy or copper (Cu). The metal film 253 and the rewiring 241-1 are used as a shielding layer for shielding noise. Incidentally, the metal film 253 is an example of the first shielding layer described in the attached claims, and the rewiring 241-1 is an example of the second shielding layer also described in the attached claims.

[0154] Fig.21 2 is an exemplary bottom view of the substrate 240 in the first modification of the eighth embodiment of the present technology. Fig.21 As shown, the protrusion 251 has a frame-shaped portion, which is partially branched together with other portions of the protrusion 251 to surround the integrated circuit 261. Fig.21, the area surrounded by coordinates (X1, Y1), (X1, Y3), (X2, Y1), (X2, Y2), (X3, Y2), and (X3, Y3) corresponds to the branch part.

[0155] Furthermore, among the portions constituting the raised portion 251, the portion surrounding the integrated circuit 261 has a ground via 254-2 provided therein. Fig.21 In FIG. 2 , a bold square indicates a ground via 254 - 2 . The ground via 254 - 2 shields noise together with the above-mentioned electromagnetic shield (metal film 253 and redistribution wiring 241 - 1 ). This improves electrical characteristics.

[0156] In addition, in the first modified example of the eighth embodiment, the heat dissipation portion 252 is not provided, but if space permits, a heat dissipation portion 252 may be provided.

[0157] According to the first modification of the eighth embodiment of the present technology, as described above, the electromagnetic shield and the ground via 254-2 are provided in such a manner as to surround the integrated circuit 261. This makes it possible to shield noise and thereby improve electrical characteristics.

[0158] [Second Modification]

[0159] Although the semiconductor chip is not mounted on the bottom of the frame substrate 220 in the eighth embodiment, a semiconductor chip may be added. The second modification of the eighth embodiment is different from the eighth embodiment in that the semiconductor chip is mounted on the bottom of the frame substrate 220 .

[0160] Fig. 22 1 is a cross-sectional view showing a configuration example of a semiconductor module 200 as a second modification of the eighth embodiment of the present technology. The semiconductor module 200 of the second modification of the eighth embodiment differs from the eighth embodiment in that a heat dissipation portion 252 is not provided and a predetermined number of semiconductor chips 262 and 263 are further mounted.

[0161] The semiconductor chip 262 is connected to the heavy wiring 241-2 arranged on the lower side of the wiring layer 241. The semiconductor chip 263 is connected to the inner wall of the protrusion 251 through the metal film 253. This part of the metal film 253 is used as a wiring connected to the wiring layer 241. When connected to the inner wall, the semiconductor chip 263 is positioned closer to the conductive via than when mounted on the bottom surface. This improves PI (power integrity).

[0162] In addition, when the semiconductor chip 263 is attached to the inner wall of the protrusion 251, the distance from the inner wall to the chip edge becomes shorter than the distance in the case where the semiconductor chip 263 is mounted on the bottom surface. For example, the distance dX2 from the right inner wall to the left edge of the semiconductor chip 263 is shorter than the distance dX1 from the left inner wall to the right edge of the semiconductor chip 262. This leaves a wider space for integrating other chips and circuits.

[0163] Incidentally, although both the semiconductor chips 262 and 263 are included, alternatively, either one of them may be provided. In addition, the semiconductor chip 262 is an example of a second semiconductor chip described in the appended claims.

[0164] In the second modification of the eighth embodiment, the heat dissipation portion 252 is not provided, but if space permits, a heat dissipation portion 252 may be provided. In addition, the third modification may also be applied to the second modification of the eighth embodiment.

[0165] According to the second modification of the eighth embodiment of the present technology, as described above, the semiconductor chips 262 and 263 are mounted on the bottom of the substrate 240. This improves the function of the semiconductor module 200. In particular, attaching the semiconductor chip 263 to the inner wall of the protrusion 251 enhances the PI characteristics.

[0166] <9. Ninth Implementation Method>

[0167] In the eighth embodiment described above, the solder ball 224 is used to connect the semiconductor module 200 to an external circuit or device. However, according to this structure, it is difficult to disassemble and reconnect the semiconductor module 200. The semiconductor module 200 of the ninth embodiment is different from the eighth embodiment in that a connector is provided at the bottom of the substrate.

[0168] Fig.23 2 is a cross-sectional view showing a construction example of a semiconductor module 200 as a ninth embodiment of the present technology. In the semiconductor module 200 of the ninth embodiment, a predetermined number of connectors 271 are installed at the bottom of the substrate 240, replacing the eliminated protrusions 251 and the heat dissipation portion 252. The connectors 271 allow the semiconductor module 200 to be easily disassembled and reconnected, which improves reworkability. The ninth embodiment also provides a high-speed interface.

[0169] In addition, the inner wall of the connector 271 is covered by a metal film 253. The metal film 253 is used as a shielding layer. The semiconductor chip 262 is mounted on the bottom of the substrate 240, and the semiconductor chip 263 is connected to the inner wall through the metal film 253. In addition, although both semiconductor chips 262 and 263 are provided, only one of them may be included. As another alternative, a configuration that does not include a semiconductor chip may be adopted.

[0170] Fig.24 2 is an exemplary bottom view of the substrate 240 in the ninth embodiment of the present technology. Fig.24 As shown, the connectors 271 may be arranged along the left and right sides of the substrate 240. Incidentally, the connectors 271 may also be arranged along the upper and lower sides of the substrate 240.

[0171] In addition, in the ninth embodiment, the heat dissipation portion 252 is not included, but if space permits, a heat dissipation portion 252 may be added. Preferably, the first modification of the eighth embodiment may also be applied to the ninth embodiment.

[0172] According to the ninth embodiment of the present technology, as described above, the connector 271 is mounted on the bottom of the substrate 240. This enhances the reworkability of the module.

[0173] <10. Application examples of mobile objects>

[0174] The technology disclosed herein (the present technology) can be applied to various products. For example, the technology can be implemented as a device installed on a mobile body such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0175] Fig.25 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0176] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.25 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0177] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device to control: a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine, a drive motor, etc., a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle, etc.

[0178] The body system control unit 12020 controls the operation of various types of equipment configured for the body according to various programs. For example, the body system control unit 12020 is used as a control device to control the following items: a keyless entry system, a smart key system, a power window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, the body system control unit 12020 can receive as input radio waves transmitted from a mobile device that replaces the key or signals from various switches. The body system control unit 12020 receives these input radio waves or signals to control the door lock device, power window device, lights, etc. of the vehicle.

[0179] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the vehicle exterior, and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 may perform a process of detecting an object (such as a person, vehicle, obstacle, sign, symbol, etc. on the road), or perform a process of detecting the distance to the object.

[0180] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0181] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 may be connected to a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the driver's fatigue level or the driver's concentration level, or may distinguish whether the driver is dozing off.

[0182] The microcomputer 12051 can calculate a control target value for a driving force generation device, a steering mechanism, or a braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS), including collision avoidance or impact buffering for the vehicle, following driving based on vehicle-to-vehicle distance, vehicle speed maintenance driving, an alarm for vehicle collision, an alarm for vehicle lane deviation, and the like.

[0183] In addition, the microcomputer 12051 can control the driving force generating device, the steering mechanism, and the braking device based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control intended for automatic driving, etc. that is independent of the driver's operation.

[0184] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of the preceding vehicle or oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare by controlling the headlights.

[0185] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify information to the passengers of the vehicle or the outside of the vehicle in a visual or auditory manner. Fig.25 In the example of FIG. 1206 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0186] Fig.26 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0187] exist Fig.26 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0188] The imaging units 12101, 12102, 12103, 12104 and 12105 may be arranged at the positions of the front nose, side mirrors, rear bumper, rear door and the upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield inside the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0189] By the way, Fig.26 An example of the shooting range of the imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of the imaging unit 12101 arranged at the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 arranged at the side mirrors. Imaging range 12114 represents the imaging range of the imaging unit 12104 arranged at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above can be obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0190] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0191] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the leading vehicle, which specifically exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained from the leading vehicle, and perform automatic braking control (including following parking control), automatic acceleration control (including following starting control), etc. Therefore, cooperative control intended for automatic driving, etc. that does not depend on the operation of the driver, can be performed.

[0192] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, and extract the classified three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes whether the obstacles around the vehicle 12100 are obstacles that can be visually identified by the driver of the vehicle 12100, or obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0193] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 is capable of identifying pedestrians by determining whether there are pedestrians in the imaging images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following programs: a program for extracting characteristic points in the imaging images of the imaging units 12101 to 12104 as infrared cameras, and a program for determining whether it is a pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there are pedestrians in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasizing the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon representing a pedestrian at a desired position.

[0194] An example of a vehicle control system to which the technology of the embodiments of the present disclosure can be applied is described above. For example, the present technology can be advantageously applied to the imaging unit 12031 among the above components. Specifically, Figure 1 The semiconductor package 300 in FIG. 1 may be applied to the imaging portion 12031. Applying the technology of the present disclosure to the imaging portion 12031 makes it possible to improve EMI resistance, thereby improving the reliability of the system.

[0195] Incidentally, the above-described embodiments are merely examples of the technology that may be implemented. The details of the embodiments generally correspond to the subject matter of the invention claimed in the appended claims. Likewise, the inventive contents named in the appended claims generally correspond to the details of the embodiments with the same names in the foregoing description of the preferred embodiments of the technology. However, these and other embodiments do not limit the technology that may also be implemented using various modifications and changes of the embodiments, as long as they are within the scope of the appended claims.

[0196] Incidentally, the advantageous effects stated in this specification are examples and do not limit the present disclosure, and the present disclosure may also provide other advantages.

[0197] Incidentally, the present technology may also have the following configurations. (1)

[0199] A semiconductor package, comprising:

[0200] a semiconductor chip configured so that a circuit is mounted on one of two surfaces of the semiconductor chip, the circuit forming surface constituting a circuit forming surface;

[0201] a first shielding layer configured to cover a side surface of the semiconductor chip and another surface of the semiconductor chip; and

[0202] The second shielding layer is configured to cover the circuit forming surface. (2)

[0204] The semiconductor package according to (1), further comprising:

[0205] Under Bump Metal,

[0206] The second shielding layer includes a portion of a seed layer for growing an under-bump metallization (UBM). (3)

[0208] The semiconductor package according to (2), further comprising:

[0209] an insulating layer configured to cover the circuit forming surface,

[0210] When viewed from a direction perpendicular to the semiconductor chip, the second shielding layer covers a portion of the insulating layer except for a predetermined area around the under bump metal. (4)

[0212] The semiconductor package according to (1), further comprising:

[0213] a first redistribution layer formed outside a protection region as a portion of a circuit formation surface,

[0214] The second shielding layer includes a second redistribution layer covering the protection area and connected to the ground. (5)

[0216] A semiconductor module, comprising:

[0217] Semiconductor packaging, including:

[0218] a first semiconductor chip configured such that a circuit is mounted on one of two surfaces of the first semiconductor chip, the circuit forming surface constituting a circuit forming surface,

[0219] a first shielding layer configured to cover the side surface of the semiconductor chip and another surface of the semiconductor chip, and

[0220] a second shielding layer configured to cover the circuit forming surface; and

[0221] The substrate is configured to mount the semiconductor package thereon. (6)

[0223] The semiconductor module according to (5), further comprising:

[0224] a signal via configured to penetrate the substrate; and

[0225] The plurality of ground vias are arranged to penetrate the substrate in a manner surrounding the signal via when viewed from a direction perpendicular to the substrate. (7)

[0227] The semiconductor module according to (5) or (6), further comprising:

[0228] a first circuit formed in a first semiconductor chip; and

[0229] The second circuit is configured to generate noise,

[0230] The first circuit and the second circuit are respectively connected to different grounds. (8)

[0232] The semiconductor module according to (7), wherein the second circuit is formed in the substrate. (9)

[0234] The semiconductor module according to (7), wherein the semiconductor package and the second circuit are provided on a surface of the substrate. (10)

[0236] The semiconductor module according to (9), further comprising:

[0237] The shield is configured to surround the semiconductor package when viewed from a direction perpendicular to the substrate. (11)

[0239] The semiconductor module according to (5), wherein the substrate comprises:

[0240] a wiring layer configured to be mounted in a predetermined position on one of the two surfaces of the substrate together with the semiconductor package;

[0241] The protrusion is configured to protrude in a direction perpendicular to the other surface of the substrate,

[0242] a first shielding layer configured to cover an inner wall of the protrusion, and

[0243] The signal via is configured to penetrate the protrusion. (12)

[0245] The semiconductor module according to (11), wherein the substrate further comprises:

[0246] a heat dissipation portion provided at a position corresponding to the predetermined position on the other surface of the substrate, and

[0247] The ground via is configured to penetrate the heat dissipation portion and has a ground potential. (13)

[0249] The semiconductor module according to (11) or (12), further comprising:

[0250] an integrated circuit disposed on another surface of the substrate,

[0251] Wherein, the wiring layer includes a second shielding layer, and

[0252] When viewed from a direction perpendicular to the other surface of the substrate, the integrated circuit is surrounded by a portion of the protrusion. (14)

[0254] The semiconductor module according to any one of (11) to (13), further comprising:

[0255] The second semiconductor chip is mounted on the inner wall of the raised portion. (15)

[0257] The semiconductor module according to (5), wherein the substrate comprises:

[0258] a wiring layer configured to allow a semiconductor package to be mounted on one of two surfaces of a substrate;

[0259] a connector mounted on the other surface of the substrate in a manner protruding in a direction perpendicular to the other surface, and

[0260] The shielding layer is configured to cover the inner wall of the connector. (16)

[0262] An electronic device, comprising:

[0263] Semiconductor packaging, including:

[0264] A semiconductor chip is configured such that a circuit is mounted on one of two surfaces of the semiconductor chip, the circuit forming surface constituting a circuit forming surface,

[0265] a first shielding layer configured to cover the side surface of the semiconductor chip and another surface of the semiconductor chip, and

[0266] a second shielding layer configured to cover the circuit forming circuit surface; and

[0267] The substrate is configured to have the semiconductor chip mounted thereon. (17)

[0269] A method for manufacturing a semiconductor package, comprising:

[0270] a process of causing a second shielding layer to cover one of two surfaces of a semiconductor chip, the one surface constituting a circuit forming surface; and

[0271] A process in which a first shielding layer covers the side surfaces of a semiconductor chip and the other surface of the semiconductor chip. (18)

[0273] A semiconductor package, comprising:

[0274] Semiconductor chips, including:

[0275] a first surface;

[0276] a second surface, opposite to the first surface; and

[0277] One or more side surfaces, disposed between the first surface and the second surface,

[0278] wherein a circuit is mounted on one of the first surface and the second surface;

[0279] A first shielding layer covering the other of the first surface and the second surface and one or more side surfaces of the semiconductor chip; and

[0280] a second shielding layer covering one of a first surface on which a circuit is mounted and a second surface of the semiconductor chip,

[0281] Wherein, the second shielding layer contains at least one metal. (19)

[0283] The semiconductor package according to (18), further comprising:

[0284] Under Bump Metal,

[0285] The second shielding layer is arranged below the under-bump metal. (20)

[0287] The semiconductor package according to (19), further comprising:

[0288] an insulating layer provided between one of the first surface and the second surface of the semiconductor chip on which the circuit is mounted and the second shielding layer,

[0289] The second shielding layer covers a portion of the insulating layer except for an area defined by the under bump metallization. (twenty one)

[0291] The semiconductor package according to (18), further comprising:

[0292] A redistribution layer is formed on one of the first surface and the second surface of the semiconductor chip, wherein the redistribution layer occupies an area other than an area below the circuit. (twenty two)

[0294] A semiconductor module, comprising:

[0295] substrate; and

[0296] Semiconductor package, mounted on a substrate,

[0297] Among them, semiconductor packaging includes:

[0298] A first semiconductor chip comprising:

[0299] a first surface;

[0300] a second surface, opposite to the first surface; and

[0301] One or more side surfaces, disposed between the first surface and the second surface,

[0302] A first circuit is mounted on one of the first surface and the second surface;

[0303] a first shielding layer covering the other of the first surface and the second surface and one or more side surfaces of the first semiconductor chip; and

[0304] a second shielding layer covering one of a first surface on which the first circuit is mounted and a second surface of the first semiconductor chip,

[0305] Wherein, the second shielding layer contains at least one metal. (twenty three)

[0307] The semiconductor module according to (22), further comprising:

[0308] Signal vias, which penetrate the substrate; and

[0309] Multiple ground vias, penetrating the substrate,

[0310] Wherein, a plurality of ground vias surround the signal via. (twenty four)

[0312] The semiconductor module according to (22) and (23), further comprising:

[0313] A second circuit is provided in the semiconductor module,

[0314] The first circuit and the second circuit are respectively connected to different grounds. (25)

[0316] The semiconductor module according to (22) to (24), wherein the second circuit is mounted to the substrate. (26)

[0318] The semiconductor module according to (22) to (25), wherein the semiconductor package is disposed above the second circuit. (27)

[0320] The semiconductor module according to (22) to (26), further comprising:

[0321] A cover is disposed around the semiconductor package. (28)

[0323] The semiconductor module according to (22), wherein the substrate comprises:

[0324] a wiring layer having a first surface and a second surface, the first surface of the wiring layer being mounted to the semiconductor package;

[0325] at least one protrusion protruding from the second surface of the wiring layer;

[0326] a shielding layer covering an inner wall of at least one protrusion; and

[0327] The signal via penetrates at least one protrusion. (29)

[0329] The semiconductor module according to (28), wherein the substrate further comprises:

[0330] a heat sink disposed on a second surface of the wiring layer below the semiconductor package, and

[0331] A ground via that penetrates the heat sink and has ground potential. (30)

[0333] The semiconductor module according to (22) and (28), further comprising:

[0334] an integrated circuit disposed on the second surface of the wiring layer,

[0335] The integrated circuit is surrounded by at least one raised portion. (31)

[0337] The semiconductor module according to (28), further comprising:

[0338] The second semiconductor chip is mounted on the inner wall of the at least one protruding portion. (32)

[0340] The semiconductor module according to claim (22), wherein the substrate comprises:

[0341] a wiring layer having a first surface and a second surface, the first surface of the wiring layer being mounted to the semiconductor package;

[0342] a connector mounted to the second surface of the wiring layer; and

[0343] Shielding layer, covering the inner wall of the connector. (33)

[0345] The semiconductor module according to (24), wherein the semiconductor package is disposed adjacent to the second circuit. (34)

[0347] The semiconductor module according to (24), further comprising:

[0348] The partition wall is provided between the semiconductor package and the second circuit. (35)

[0350] The semiconductor module according to (28), wherein the at least one protrusion is provided on a side portion of the second surface of the wiring layer. (36)

[0352] An electronic device, comprising:

[0353] substrate; and

[0354] Semiconductor package, mounted on a substrate,

[0355] Among them, semiconductor packaging includes:

[0356] Semiconductor chips, including:

[0357] a first surface;

[0358] a second surface, opposite to the first surface; and

[0359] One or more side surfaces, disposed between the first surface and the second surface,

[0360] wherein a circuit is mounted on one of the first surface and the second surface;

[0361] a first shielding layer covering the other of the first surface and the second surface and one or more side surfaces of the semiconductor chip; and

[0362] a second shielding layer covering one of a first surface on which a circuit is mounted and a second surface of the semiconductor chip,

[0363] Wherein, the second shielding layer contains at least one metal. (37)

[0365] The electronic device according to (36), further comprising:

[0366] Signal vias, which penetrate the substrate; and

[0367] Multiple ground vias, penetrating the substrate,

[0368] Wherein, a plurality of ground vias surround the signal via. (38)

[0370] The electronic device according to (36) and (37), further comprising:

[0371] A second circuit is provided in the electronic device,

[0372] The first circuit and the second circuit are respectively connected to different grounds. (39)

[0374] An electronic device according to (36)-(38), wherein the second circuit is mounted to the substrate. (40)

[0376] The electronic device according to (38)-(39), wherein the semiconductor package is disposed above the second circuit. (41)

[0378] The electronic device according to (36) to (40), further comprising:

[0379] A cover is disposed around the semiconductor package. (42)

[0381] A method for manufacturing a semiconductor package, comprising:

[0382] Covering one of a first surface and a second surface of the semiconductor chip on which a circuit is mounted by a second shielding layer,

[0383] wherein the first surface is opposite to the second surface; and

[0384] The first shielding layer covers the other of the first surface and the second surface of the semiconductor chip and one or more side surfaces of the semiconductor chip disposed between the first surface and the second surface of the semiconductor chip.

[0385] Wherein, the second shielding layer contains at least one metal.

[0386] [Reference Numbers List]

[0387] 100: Electronic devices

[0388] 110: Main CPU

[0389] 111: Menu processing unit

[0390] 112: Application Processing Department

[0391] 120: System controller

[0392] 121: Operation input receiving unit

[0393] 122: Communication Processing Department

[0394] 123: Power Control Department

[0395] 130: Setting information storage unit

[0396] 200: Semiconductor modules

[0397] 211: Molding resin

[0398] 212, 331, 340, 362: Shielding layer

[0399] 213: Shielding

[0400] 220: Frame substrate

[0401] 221: Wiring layer

[0402] 222: Through hole

[0403] 222-1: Signal via

[0404] 222-2: Ground crossing

[0405] 223: Passive components

[0406] 224, 352: Solder balls

[0407] 225: Digital Circuits

[0408] 231, 233: Power supply

[0409] 232, 234: Grounding

[0410] 240: Substrate

[0411] 241: Wiring layer

[0412] 241-1, 241-2: Rewiring

[0413] 251: Raised part

[0414] 252: Heat dissipation

[0415] 253: Metal film

[0416] 254-1: Signal via

[0417] 254-2: Ground via

[0418] 261: Integrated Circuits

[0419] 262, 263: Semiconductor chips

[0420] 271: Connector

[0421] 300: Semiconductor packaging

[0422] 310: Wafer

[0423] 311: Semiconductor chips

[0424] 321: Pad

[0425] 322: Passivation layer

[0426] 323, 325: Insulation layer

[0427] 324, 330: Seed layer

[0428] 351: Under Bump Metal

[0429] 361: RDL

[0430] 371: Analog Circuits

[0431] 400: Resist

[0432] 12031: Imaging department.

Claims

1. A semiconductor package, comprising: Semiconductor chips, including: a first surface; a second surface, opposite to the first surface; and one or more side surfaces disposed between the first surface and the second surface, wherein a circuit is mounted on one of the first surface and the second surface; a first shielding layer covering the other of the first surface and the second surface and the one or more side surfaces of the semiconductor chip; and a second shielding layer covering the one of the first surface and the second surface of the semiconductor chip on which the circuit is mounted, Wherein, the second shielding layer contains at least one metal.

2. The semiconductor package according to claim 1, further comprising: Under Bump Metal, Wherein, the second shielding layer is arranged below the under-bump metal.

3. The semiconductor package according to claim 2, further comprising: an insulating layer provided between the one of the first surface and the second surface of the semiconductor chip on which the circuit is mounted and the second shielding layer, The second shielding layer covers a portion of the insulating layer except for an area defined by the under bump metal.

4. The semiconductor package according to claim 1, further comprising: a redistribution layer formed on the one of the first surface and the second surface of the semiconductor chip, The redistribution layer occupies an area other than an area below the circuit.

5. A semiconductor module, comprising: substrate; as well as a semiconductor package mounted on the substrate, Wherein, the semiconductor package comprises: A first semiconductor chip comprising: a first surface; a second surface, opposite to the first surface; and one or more side surfaces disposed between the first surface and the second surface, A first circuit is mounted on one of the first surface and the second surface; a first shielding layer covering the other of the first surface and the second surface and the one or more side surfaces of the first semiconductor chip; and a second shielding layer covering the one of the first surface and the second surface of the first semiconductor chip on which the first circuit is mounted, Wherein, the second shielding layer contains at least one metal.

6. The semiconductor module according to claim 5, further comprising: A signal via penetrating the substrate; as well as A plurality of ground vias penetrating the substrate, Wherein, the plurality of ground vias surround the signal via.

7. The semiconductor module according to claim 5, further comprising: A second circuit is provided in the semiconductor module, The first circuit and the second circuit are respectively connected to different grounds.

8. The semiconductor module according to claim 7, wherein: The second circuit is mounted to the substrate.

9. The semiconductor module according to claim 7, wherein: The semiconductor package is disposed over the second circuit.

10. The semiconductor module according to claim 9, further comprising: A cover is disposed around the semiconductor package.

11. The semiconductor module according to claim 5, wherein: The substrate comprises: a wiring layer having a first surface and a second surface, the first surface of the wiring layer being mounted to the semiconductor package; at least one protrusion protruding from the second surface of the wiring layer; a shielding layer covering an inner wall of the at least one protrusion; and The signal via penetrates the at least one protrusion.

12. The semiconductor module according to claim 11, wherein: The substrate further comprises: a heat sink disposed on the second surface of the wiring layer below the semiconductor package, and A ground via penetrates the heat sink and has a ground potential.

13. The semiconductor module according to claim 11, further comprising: an integrated circuit disposed on the second surface of the wiring layer, The integrated circuit is surrounded by the at least one raised portion.

14. The semiconductor module according to claim 11, further comprising: The second semiconductor chip is mounted on the inner wall of the at least one protruding portion.

15. The semiconductor module according to claim 5, wherein: The substrate comprises: a wiring layer having a first surface and a second surface, the first surface of the wiring layer being mounted to the semiconductor package; a connector mounted to the second surface of the wiring layer; and The shielding layer covers the inner wall of the connector.

16. The semiconductor module according to claim 7, wherein: The semiconductor package is disposed adjacent to the second circuit.

17. The semiconductor module according to claim 7, further comprising: A partition wall is provided between the semiconductor package and the second circuit.

18. The semiconductor module according to claim 11, wherein The at least one protruding portion is provided on a side portion of the second surface of the wiring layer.

19. An electronic device comprising: substrate; as well as a semiconductor package mounted on the substrate, Wherein, the semiconductor package comprises: Semiconductor chips, including: a first surface; a second surface, opposite to the first surface; and one or more side surfaces disposed between the first surface and the second surface, wherein a circuit is mounted on one of the first surface and the second surface; a first shielding layer covering the other of the first surface and the second surface and the one or more side surfaces of the semiconductor chip; and a second shielding layer covering the one of the first surface and the second surface of the semiconductor chip on which the circuit is mounted, Wherein, the second shielding layer contains at least one metal.

20. The electronic device according to claim 19, further comprising: A signal via penetrating the substrate; as well as A plurality of ground vias penetrating the substrate, Wherein, the plurality of ground vias surround the signal via.

21. The electronic device according to claim 19, further comprising: A second circuit is provided in the electronic device, The first circuit and the second circuit are respectively connected to different grounds.

22. The electronic device according to claim 21, wherein: The second circuit is mounted to the substrate.

23. The electronic device according to claim 21, wherein: The semiconductor package is disposed over the second circuit.

24. The electronic device according to claim 23, further comprising: A cover is disposed around the semiconductor package.

25. A method for manufacturing a semiconductor package, comprising: Covering one of a first surface and a second surface of the semiconductor chip on which a circuit is mounted by a second shielding layer, wherein the first surface is opposite to the second surface; and covering the other of the first surface and the second surface of the semiconductor chip and one or more side surfaces of the semiconductor chip disposed between the first surface and the second surface of the semiconductor chip by a first shielding layer, Wherein, the second shielding layer contains at least one metal.

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