System and method for electrical interface bond detection for inverter for electric vehicle

Abstract

The system comprises an inverter, the inverter includes a first electrical isolator separating a low voltage region from a high voltage region, a second electrical isolator separating the low voltage region from the high voltage region, a first bias network connected to the first electrical isolator, a second bias network connected to the second electrical isolator, and a third bias network connected to the second electrical isolator. The circuit includes a first bias network, a second bias network, a first filter connected to the first bias network, a second filter connected to the second bias network, a first amplifier connected to the first filter, a second amplifier connected to the second filter, and an open circuit detector connected to the first amplifier and the second amplifier.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 18 / 155,141 filed on January 17, 2023, which claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, and U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure generally relate to systems and methods for open bond wire detectors for electrical interfaces of inverters for electric vehicles, and more particularly to systems and methods for open bond wire detectors for electrical interfaces of power modules for inverters for electric vehicles. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for converting high voltage direct current (HVDC) to alternating current (AC) to drive the motor. In an inverter, connection problems across the electrical interface may affect the operation of the gate driver and / or the power device switches, and therefore may affect the operation of the inverter.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a first electrical isolator that separates a low voltage region from a high voltage region, the first electrical isolator having a first electrical isolator output path; a second electrical isolator that separates the low voltage region from the high voltage region, the second electrical isolator having a second electrical isolator output path; a first bias network that is in the high voltage region and connected to the first electrical isolator via the first electrical isolator output path, the first bias network having a first bias network output path; a second bias network that is in the high voltage region and connected to the second electrical isolator via the second electrical isolator output path, the second bias network having a second bias network output path; a first filter a first filter in a high voltage region and connected to a first bias network via a first bias network output path, the first filter having a first filter output path; a second filter in a high voltage region and connected to a second bias network via a second bias network output path, the second filter having a second filter output path; a first amplifier in a high voltage region and connected to the first filter via a first filter output path, the first amplifier having a first amplifier output path; a second amplifier in a high voltage region and connected to the second filter via a second filter output path, the second amplifier having a second amplifier output path; and an open circuit detector in a high voltage region, the open circuit detector being connected to the first amplifier via the first amplifier output path and to the second amplifier via the second amplifier output path.

[0007] In some aspects, the technology described herein relates to a system further comprising: a pulse transceiver, the pulse transceiver is in a low voltage region, the pulse transceiver is connected to a first electrical isolator via a first pulse transceiver output path and to a second electrical isolator via a second pulse transceiver output path.

[0008] In some aspects, the techniques described herein relate to a system further comprising a primary receiver.

[0009] In some aspects, the technology described herein relates to a system in which a pulse transceiver and a main receiver are configured to operate together to transmit a pulse width modulated signal from a low voltage region to a high voltage region.

[0010] In some aspects, the technology described herein relates to a system in which a pulse transceiver is configured to output a first pulse on a first pulse transceiver output path and a second pulse on a second pulse transceiver output path.

[0011] In some aspects, the technology described herein relates to a system wherein the pulse transceiver is further configured to receive a main pulse and output a first pulse and a second pulse based on the received main pulse.

[0012] In some aspects, the technology described herein relates to a system wherein: a first galvanic isolator is configured to receive a first pulse on a first pulse transceiver output path and transmit a first galvanic isolator pulse on the first galvanic isolator output path based on the received first pulse, and a second galvanic isolator is configured to receive a second pulse on a second pulse transceiver output path and transmit a second galvanic isolator pulse on the second galvanic isolator output path based on the received second pulse.

[0013] In some aspects, the technology described herein relates to a system wherein: a first bias network is configured to receive a first electrical isolator pulse on a first electrical isolator output path, process the first electrical isolator pulse based on one or more characteristics of the first bias network, and send a first biased pulse on the first bias network output path based on the processed first electrical isolator pulse, and a second bias network is configured to receive a second electrical isolator pulse on a second electrical isolator output path, process the second electrical isolator pulse based on one or more characteristics of the second bias network, and send a second biased pulse on the second bias network output path based on the processed second electrical isolator pulse.

[0014] In some aspects, the technology described herein relates to a system wherein: a first filter is configured to receive a first biased pulse on a first bias network output path, filter the first biased pulse based on one or more characteristics of the first filter, and send the first filtered pulse on the first filter output path based on the processed first biased pulse, and a second filter is configured to receive a second biased pulse on a second bias network output path, filter the second biased pulse based on one or more characteristics of the second filter, and send the second filtered pulse on the second filter output path based on the processed second biased pulse.

[0015] In some aspects, the techniques described herein relate to a system wherein one or more of the first filter or the second filter is one or more of a bandpass filter, a highpass filter, a lowpass filter, or a notch filter.

[0016] In some aspects, the techniques described herein relate to a system in which one or more of a first filter or a second filter is configured to modify filter characteristics based on an input signal.

[0017] In some aspects, the technology described herein relates to a system in which an open circuit detector is configured to: receive a first filtered pulse on a first filtered output path; receive a second filtered pulse on a second filtered output path; perform a comparison of the first filtered pulse and the second filtered pulse to one or more of each other or one or more reference pulses; and initiate a mitigation action based on the comparison of the first filtered pulse and the second filtered pulse.

[0018] In some aspects, the techniques described herein relate to a system wherein the mitigating action includes asserting a fault signal.

[0019] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to an inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0020] In some aspects, the technology described herein relates to a method comprising: receiving a first pulse by one or more controllers, and transmitting a first electrical isolator pulse by the one or more controllers based on the first pulse; receiving a second pulse by the one or more controllers, and transmitting a second electrical isolator pulse by the one or more controllers based on the second pulse; receiving a first electrical isolator pulse and a second electrical isolator pulse by the one or more controllers, and transmitting a first biased pulse based on the first electrical isolator pulse and transmitting a second biased pulse based on the second electrical isolator pulse by the one or more controllers; receiving a first biased pulse based on the first electrical isolator pulse and a second biased pulse by the one or more controllers, and transmitting a first biased pulse based on the second electrical isolator pulse by the one or more controllers; The one or more controllers transmit a first filtered pulse based on a first biased pulse and a second filtered pulse based on a second biased pulse; the one or more controllers receive the first filtered pulse and the second filtered pulse, and the one or more controllers transmit a first amplified pulse based on the first filtered pulse and a second amplified pulse based on the second filtered pulse; the one or more controllers compare the first amplified pulse and the second amplified pulse with each other or one or more of one or more reference pulses; the one or more controllers determine a mitigation action based on the comparison; and the one or more controllers generate an output pulse based on the mitigation action.

[0021] In some aspects, the technology described herein relates to a method wherein determining a mitigation action comprises: determining, by the one or more controllers, a difference between one or more signal characteristics of a first amplified pulse and one or more signal characteristics of a second amplified pulse; comparing, by the one or more controllers, the difference to a difference threshold; and determining, by the one or more controllers, the mitigation action based on the comparison of the difference to the difference threshold.

[0022] In some aspects, the techniques described herein relate to a method in which a mitigating action includes asserting a fault signal.

[0023] In some aspects, the techniques described herein relate to a method in which one or more of a first filtered pulse or a second filtered pulse is filtered based on a noise signal.

[0024] In some aspects, the technology described herein relates to a method in which comparing a first amplified pulse and a second amplified pulse includes performing a differential comparison.

[0025] In some aspects, the technology described herein relates to a system comprising: a first electrical isolator configured to receive a first pulse from a pulse transceiver and output a first electrical isolator pulse based on the received first pulse; a second electrical isolator configured to receive a second pulse from the pulse transceiver and generate a second electrical isolator pulse based on the received second pulse; and one or more controllers configured to: receive the first electrical isolator pulse and the second electrical isolator pulse, perform a comparison of the received first electrical isolator pulse and the received second electrical isolator pulse with each other or one or more of one or more reference pulses, and determine a fault in one or more of the first electrical isolator or the second electrical isolator based on the comparison of the received first electrical isolator pulse and the received second electrical isolator pulse.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 Depicted are exemplary methods for open bond wire detection in accordance with one or more embodiments.

[0035] Figure 7 Depicted is an exemplary system infrastructure for an open bond wire detector for an electrical interface in accordance with one or more embodiments.

[0036] Figure 8 Depicted is an exemplary graph of signal filtering for an open bond wire detector for an electrical interface in accordance with one or more embodiments. DETAILED DESCRIPTION

[0037] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0038] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0039] Various embodiments of the present disclosure generally relate to systems and methods for open bond wire detectors for electrical interfaces of inverters for electric vehicles, and more particularly to systems and methods for open bond wire detectors for electrical interfaces of power modules for inverters for electric vehicles.

[0040] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three-phase switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the phase switches. The phase switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the phase switch by passing through an isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the phase switching device via the gate driver output.

[0041] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0042] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0043] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0044] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0045] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0046] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point of use ICs have not yet been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0047] As introduced above, electrical isolation may include isolating functional sections of an electrical system to prevent current flow, such that, for example, no direct conduction path is permitted between such functional sections. For example, two circuits may be electrically isolated such that the circuits are configured to communicate with each other but may have respective reference grounds at different potentials. For example, some architectures use a circuit with four electrical isolators, such as four capacitors, to pass data between a low voltage plane and a high voltage plane. For example, electrical isolation may include optical, transformer-based, or capacitance-based isolation.

[0048] The gate driver may be a power amplifier or other electronic component that accepts input from a controller and may generate a drive input for the gate of the transistor. Galvanically isolated gate drivers may be used in automotive and industrial applications to communicate between low voltage planes and high voltage planes without causing harm to the user or equipment.

[0049] One or more embodiments may include a bonding wire that connects the output of the low voltage controller to the high voltage controller across the electrical isolator. The bonding wire may include a conductive material including, but not limited to, aluminum, copper, silver, gold, alloys thereof, or combinations thereof. For example, the bonding wire may be connected to the circuit using any suitable means, such as ball bonding, wedge bonding, or compliant bonding.

[0050] For example, one or more bonding wires may connect a low voltage side transmitter of an integrated circuit to one or more capacitors at a high voltage side of a circuit (such as an integrated circuit). Open bonding wires may cause a loss of differential properties of a given electrical interface. Such loss of differential properties may render the electrical interface and / or the gate driver integrated circuit more susceptible to interference (e.g., electromagnetic interference). For example, such interference may include common mode radio frequency (RF) noise (CMRFI).

[0051] Interference (e.g., electromagnetic interference, CMRFI, etc.) may cause incorrect commands and / or messages to be propagated to the gate driver. For example, due to interference, the high voltage controller may receive and / or apply incorrect commands and / or messages from the low voltage controller. Such incorrect commands and / or messages may increase the risk of a short circuit between the high-side controller or driver and the low-side controller or driver.

[0052] Some electrically isolated integrated circuits may use an initial pulse (e.g., a heartbeat signal) through a signal path during circuit startup to determine wire bond detection, or by comparing waveforms between a transmitter and a receiver to determine the integrity of a given signal path. However, such initial pulses or waveform comparisons may cause a delay between a wire bond problem and the detection of the wire bond problem. Such delays may cause interference, causing incorrect commands and / or messages to be propagated. Depending on the design of the gate drive circuit at the system level, this delay in determining a failure may be catastrophic.

[0053] Some circuit architectures may use differential pairs tied together using a resistor network for biasing. This architecture may cause common mode (CM) noise to couple into open high voltage capacitor terminals, making the architecture unable to detect bond connection problems (e.g., open bond wires) during CM noise events. Some architectures may use separate capacitors to transmit the carrier frequency. This may be used to detect open bond wires, but the architecture requires additional high voltage capacitors that use additional area in the circuit.

[0054] One or more embodiments may perform open bond wire detection in the presence of CMRFI by amplifying the signal path separately followed by a high pass filter and gain block. The amount of filtering may be varied by changing the order and frequency response of the filter. One or more embodiments may provide a bias network for a receiver in which an open cap detection circuit is placed before the main receiver, which may increase the circuit's immunity to common mode RF noise coupling. One or more embodiments may provide a system for detecting open bond wires during mission mode in the presence of CMRFI, which may provide a faster fault response time. One or more embodiments may provide a system that may use significantly smaller circuit area and may not require special test procedures or modes to detect the integrity of the bond wires.

[0055] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0056] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 3 14). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor in the pair carries a complementary data signal from the other capacitor in the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0057] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0058] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0059] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0060] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0061] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0062] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0063] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0064] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0065] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0066] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0067] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0068] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0069] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0070] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0071] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0072] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0073] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0074] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0075] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0076] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0077] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0078] Figure 6An exemplary method 600 for open bond wire detection across an electrical interface is depicted. In operation 602, a pulse transceiver (e.g., a controller transceiver) may generate a first pulse and a second pulse. The first pulse and the second pulse may be based on a main pulse. The first pulse and the second pulse may be generated relative to a ground signal based on, for example, a drain voltage and a PWM input signal. The first pulse and the second pulse may be generated by the pulse transceiver to control a gate device and / or to indicate that a subsequent control signal will be received by the gate device. For example, the gate device may be an upper phase switch 144. The pulse transceiver may be located at a low voltage section of the electrical system. For example, referring to Figure 2 , the low voltage upper phase controller 120 may receive a PWM input signal including a main pulse from the inverter controller 300 , and may generate a first pulse and a second pulse based on the received main pulse.

[0079] For example, the first pulse and the second pulse generated at the pulse transceiver in operation 602 may be complementary (e.g., 180 degree phase-shifted) signals to each other. The first pulse and the second pulse may be transmitted via two different electrical paths, including a first path for the first pulse and a second path for the second pulse. In operation 604, the first pulse may be received at the first electrical isolator via the first path, and the second pulse may be received at the second electrical isolator via the second path. The first path and / or the first electrical isolator may be physically separated from the second path and / or the second electrical isolator.

[0080] In operation 606, a first galvanic isolator pulse may be output from the first galvanic isolator and received at the first bias network, and a second galvanic isolator pulse may be output from the second galvanic isolator and received at the second bias network. The first bias network and the second bias network may include substantially the same circuit. Thus, the first galvanic isolator pulse and the second galvanic isolator pulse may pass through substantially the same circuit via the first bias network and the second bias network, respectively. Alternatively, the first bias network and the second bias network may include different components or the same or similar components configured in different ways.

[0081] In operation 608, the first bias network may process the first electrical isolator pulse, and the second bias network may process the second electrical isolator pulse based on one or more bias network characteristics. For example, the first bias network and / or the second bias network may set direct current (DC) operating conditions (e.g., current and / or voltage) of the first electrical isolator pulse and the second electrical isolator pulse, respectively. The first bias network and / or the second bias network may include one or more electronic components, such as but not limited to one or more diodes or one or more transistors, for example, which may process the first electrical isolator pulse and the second electrical isolator pulse, respectively.

[0082] In operation 610, the first bias network may output a first biased pulse corresponding to the first electrical isolator pulse, and the second bias network may output a second biased pulse corresponding to the second electrical isolator pulse. The first biased pulse may be received at the first filter. The second biased pulse may be received at the second filter. The first filter and the second filter may include substantially the same circuit. Therefore, the first biased pulse and the second biased pulse may pass through substantially the same circuit via the first filter and the second filter, respectively. Alternatively, the first filter and the second filter may include different components or the same or similar components configured in different ways.

[0083] For example, the first filter and / or the second filter may be one or more of a high-pass filter, a band-pass filter, a low-pass filter or a notch filter. The first filter and / or the second filter may be configured to filter out interference frequencies. Such interference frequencies may be predetermined or dynamically determined. The first filter and / or the second filter may be variable filters so that the frequency filtered by the first filter and / or the second filter may be modified. For example, such frequencies may be modified in response to a signal to modify characteristics (e.g., resistance, capacitance, etc.) and / or to modify the configuration of the first filter and / or the second filter (e.g., series connection, parallel connection, switching element, etc.). For example, a signal may be generated in response to a predetermined or detected interference frequency. For example, an applicable electronic component (e.g., a noise detection component) may be used to detect such detected interference frequencies, which may include one or more noise detection sensors, processors or controllers. The signal may have a signal characteristic for determining the type and / or degree of modification.

[0084] In operation 612, the first filter may output a first filtered pulse corresponding to the first biased pulse, and the second filter may output a second filtered pulse corresponding to the second biased pulse. The first filtered pulse may be provided to the first amplifier. The second filtered pulse may be provided to the second amplifier. The first amplifier and the second amplifier may amplify the first filtered pulse and the second filtered pulse, respectively, based on one or more amplifier characteristics. For example, the first amplifier and the second amplifier may increase the voltage, current, and / or power of the first filtered pulse and the second filtered pulse, respectively.

[0085] In operation 614, the first amplifier may output a first amplified pulse corresponding to the first filtered pulse, and the second amplifier may output a second amplified pulse corresponding to the second filtered pulse. Each of the first amplified pulse and the second amplified pulse may be provided to an open circuit detector. The open circuit detector may include one or more electronic components for comparing a signal characteristic of the first amplified pulse to a signal characteristic of the second amplified pulse. For example, the open circuit detector may compare one or more of an amplitude, a frequency, or a phase of the first amplified pulse and the second amplified pulse.

[0086] In operation 616, the open circuit detector may compare the first amplified pulse and the second amplified pulse to determine whether the difference in the signal characteristic of the first amplified pulse and the signal characteristic of the second amplified pulse is within a threshold difference. When the difference in the signal characteristic of the first amplified pulse and the signal characteristic of the second amplified pulse is below the threshold difference, the open circuit detector may take a first mitigation action. The first mitigation action may include outputting a first match signal (e.g., a confirmed match signal) indicating that the first amplified pulse and the second amplified pulse are below the threshold difference. The first mitigation action may include taking no action. The first mitigation action may include causing an electrical component to accept the first pulse and / or the second pulse or otherwise pass the first pulse and / or the second pulse to one or more electrical components.

[0087] Alternatively, when the difference in the signal characteristic of the first amplified pulse and the signal characteristic of the second amplified pulse is above a threshold difference, then the open circuit detector may take a second mitigation action that is different from the first mitigation action. The second mitigation action may include, for example, outputting a second match signal (e.g., a mismatch signal) indicating that the first amplified pulse and the second amplified pulse are above the threshold difference. The second mitigation action may include causing the electrical component to discard or otherwise ignore the first pulse and / or the second pulse.

[0088] Thus, the mitigation action may be a passing action such that the open circuit detector may cause the first pulse and / or the second pulse to be output. Alternatively, when the difference between the first amplified pulse and the second amplified pulse is above a threshold difference, the mitigation action may cause the open circuit detection logic to maintain (e.g., via hysteresis) or prevent the first pulse and the second pulse from being output. In this scenario, according to one or more embodiments, the open circuit detector may cause the first pulse and / or the second pulse to be discarded such that the first pulse and the second pulse are not used to generate an output (e.g., a PWM output signal) via one or more electrical components. In this example, a previous output (e.g., a previous PWM output signal) may be maintained or maintained before the mitigation action occurs or before the difference between the subsequent first amplified pulse and the subsequent second amplified pulse is below a threshold.

[0089] It will be understood that any operation disclosed herein (e.g., such as reference Figure 6 The processes of the present invention are not limited to being performed in any particular order or sequence. As will be appreciated by those skilled in the art, any order or sequence disclosed herein is disclosed only as an example, and one or more of the operations (e.g., of a given process) may be performed in any applicable manner.

[0090] therefore, Figure 6 The technology disclosed in method 600 and Figure 7 The architecture described in the controller 700 of the present invention can be used to mitigate or prevent the use of pulses that can be modified due to interference. The parallel pulse signals disclosed herein can be used to identify interference signals due to, for example, high voltage components. The identification of interference signals can be performed based on common mode rejection. However, common mode rejection may require the absence of bond connection issues, as disclosed herein.

[0091] therefore, Figure 6 The technology disclosed in method 600 and Figure 7 The architecture described in the controller 700 of the embodiment can be used to determine bond connection problems (e.g., open bonds, loose connections, etc.) across electrical interfaces. By ensuring that such bond connection problems are not present, the parallel pulses used herein for interference detection (e.g., using common mode rejection) can be verified. For example, these techniques can prevent or mitigate the undesirable effects of CMRFI.

[0092] These techniques may include comparing two parallel pulses generated by a pulse transceiver and received at a first electrical isolator and a second electrical isolator. The comparison may include determining a difference between the two parallel pulses, where the two parallel pulses may be identical, similar, complementary, or reversed when generated at the pulse transceiver. A bond connection problem (e.g., an open bond, a loose connection, etc.) across an electrical interface may cause the signal characteristics for the two parallel pulses to be different (e.g., above a threshold amount), such that comparing the two parallel pulses as disclosed herein may identify the level of the difference, if any. For example, when comparing the first and second amplified pulses discussed herein, an open bond connection or a high resistance connection may cause a difference above a threshold amount. When a difference above the threshold difference is detected, it may be determined that a bond connection problem exists.

[0093] Thus, bonding problems in the presence of CMRFI can be solved by amplifying the signal paths of two parallel pulses separately, followed by filtering and gain operations. The amount of filtering can be changed by changing the order of the filter. Filtering can exclude noise that interferes with the detection of bonding problems, as discussed herein. Detection of bonding problems can be performed in a continuous manner during operation of the controller (e.g., during a task or operating mode), so that each first and second pulse as disclosed herein is analyzed for such bonding problems before or in parallel with passing through the main receiver. By detecting such bonding problems for each first and second pulse during continuous operation of the circuit, delays in such bonding detection can be alleviated, thereby preventing undesired use of signals affected by interference. By filtering the noise using the first or second filter disclosed herein, the open circuit detector can accurately compare the first and second amplified signals disclosed herein without deviating from the noise interference. Although the bias networks and main receiver disclosed herein may be the same or similar, placement of the open capacitor detection circuit (e.g., first and second bias networks, first and second filters, first and second amplifiers, and / or open capacitor detector) prior to or in parallel with the main receiver results in operation that is less affected by common-mode RF coupling.

[0094] Figure 7 Depicted is an exemplary system infrastructure for an open bond wire detector for an electrical interface in accordance with one or more embodiments. Figure 8 Depicts an exemplary graph of signal filtering for an open bond wire detector for an electrical interface according to one or more embodiments. Figure 2 , the phase controller 700 may be a specific implementation of the low voltage upper phase controller 120 and the high voltage upper phase controller 130. Figure 7 As shown, the phase controller 700 may include a low voltage region 702 and a high voltage region 704. The low voltage region 702 and the high voltage region 704 may be specific implementations of the low voltage upper phase controller 120 and the high voltage upper phase controller 130, respectively. The low voltage region 702 may include a low voltage component relative to the high voltage region 704, be connected to the low voltage component, or be otherwise associated with the low voltage component. The low voltage region 702 may be referred to as a primary region in this article, and the high voltage region 704 may be referred to as a secondary region in this article. The low voltage region 702 may include a pulse transceiver 706.

[0095] The pulse transceiver 706 may include one or more electrical components configured to receive a signal including a main pulse based on a drain voltage VDDL (not shown), a PWM input signal (not shown), and / or a reference ground GNDL (not shown). For example, the PWM input signal may be generated by the inverter controller 300. The pulse transceiver 706 may include one or more electrical components configured to output parallel pulses based on the main pulse. The pulse transceiver 706 may be configured to output parallel pulses via a first pulse transceiver output path 706A and a second pulse transceiver output path 706B. Therefore, the pulse transceiver 706 may output a first pulse in the parallel pulses via the first pulse transceiver output path 706A and output a second pulse in the parallel pulses via the second pulse transceiver output path 706B.

[0096] The first pulse may be received at the first electrical isolator 722 via the first wire bond 720A, and the second pulse may be received by the second electrical isolator 724 via the second wire bond 720B. For example, the first electrical isolator 722 and the second electrical isolator 724 may be specific implementations of the electrical isolator 150. The first wire bond 720A and / or the first electrical isolator 722 may be physically separated from the second wire bond 720B and / or the second electrical isolator 724. The first electrical isolator 722 and / or the second electrical isolator 724 are positioned on the high voltage region 704 and may be configured for operating voltages up to, for example, approximately 5000 volts or more.

[0097] The first galvanic isolator 722 may output a first galvanic isolator pulse on a first galvanic isolator output path 722A, and the second galvanic isolator 724 may output a second galvanic isolator pulse on a second galvanic isolator output path 722B. The first galvanic isolator pulse may be received at the first bias network 708A, and the second galvanic isolator pulse may be received at the second bias network 708B. The first bias network 708A and the second bias network 708B may include substantially the same circuitry. Alternatively, according to an embodiment, the first bias network 708A and the second bias network 708B may include different components, the same or similar components configured in different ways, etc.

[0098] The first bias network 708A can process the first galvanic isolator pulse, and the second bias network 708B can process the second galvanic isolator pulse based on one or more bias network characteristics. For example, the first bias network 708A and / or the second bias network 708B can set the direct current (DC) operating conditions (e.g., current and / or voltage) of the first galvanic isolator pulse and the second galvanic isolator pulse, respectively. The first bias network 708A and / or the second bias network 708B can include one or more electronic components, such as but not limited to one or more diodes, one or more transistors, one or more vacuum tubes, etc., which can process the first galvanic isolator pulse and the second galvanic isolator pulse, respectively. The first bias network 708A and / or the second bias network 708B can form the correct input impedance and bias value for the two paths to minimize the common mode noise amplitude and balance the remaining residual value to reduce the impact on the signal detection integrity.

[0099] The first bias network 708A may output a first biased pulse corresponding to the first electrical isolator pulse via a first bias network output path, and the second bias network 708B may output a second biased pulse corresponding to the second electrical isolator pulse via a second bias network output path. The first biased pulse may be received at the first filter 710A. The second biased pulse may be received at the second filter 710B. The first filter 710A and the second filter 710B may include substantially the same circuit. Alternatively, according to an embodiment, the first filter 710A and the second filter 710B may include different components or the same or similar components configured in different ways.

[0100] For example, the first filter 710A and / or the second filter 710B may be one or more of a high-pass filter, a band-pass filter, a low-pass filter or a notch filter. The first filter 710A and / or the second filter 710B may have a fixed frequency response or may have a dynamically variable frequency response to reduce the harmful effects of RF common mode noise on the detection of the main signal. The first filter 710A and / or the second filter 710B may be configured to filter out interference frequencies. Such interference frequencies may be predetermined or dynamically determined. The first filter 710A and / or the second filter 710B may be variable filters so that the frequency filtered by the first filter and / or the second filter may be modified. For example, such frequencies may be modified in response to a signal to modify characteristics (e.g., resistance, capacitance, etc.) and / or modify the configuration of the first filter 710A and / or the second filter 710B (e.g., series connection, parallel connection, switching element, etc.). For example, a signal may be generated in response to a predetermined or detected interference frequency. For example, such detected interference frequencies may be detected using applicable electronic components (e.g., frequency locked loops, phase locked loops, filter banks, noise detection components), which may include one or more noise detection sensors, processors, or controllers. The signal may have signal characteristics that are used to determine the type and / or extent of the modification.

[0101] The first filter 710A and / or the second filter 710B may be configured to filter out noise frequencies. Figure 8 800 shows an amplitude 802 associated with a frequency 804. As shown, it is known that the signal frequency is in the range of about 20MHz 806A to about 50MHz 806B. Therefore, the first filter 710A and / or the second filter 710B can be configured to block or filter a frequency lower than about 20MHz, higher than about 50MHz and / or allow a frequency between 20MHz and about 50MHz. The first filter 710A and / or the second filter 710B can be variable, as discussed herein. For example, the order of the first filter 710A and / or the second filter 710B can be adjusted (for example, between about 40dB per decade shown at point 808A and about 60dB per decade shown at point 808B). The order can be adjusted, for example, signal or filter frequency. For example, the first filter 710A and / or the second filter 710B can be configured to discard the noise at 20MHz.

[0102] The first filter 710A may output a first filtered pulse corresponding to the first biased pulse via a first filter output path, and the second filter 710B may output a second filtered pulse corresponding to the second biased pulse via a second filter output path. The first filtered pulse may be provided to the first amplifier 712A. The second filtered pulse may be provided to the second amplifier 712B. The first amplifier 712A and the second amplifier 712B may amplify the first filtered pulse and the second filtered pulse, respectively, based on one or more amplifier characteristics. For example, the first amplifier 712A and the second amplifier 712B may increase the voltage, current and / or power of the first filtered pulse and the second filtered pulse, respectively.

[0103] The first amplifier 712A may output a first amplified pulse corresponding to the first filtered pulse via a first amplifier output path, and the second amplifier 712B may output a second amplified pulse corresponding to the second filtered pulse via a second amplifier output path. Each of the first amplified pulse and the second amplified pulse may be provided to an open circuit detector 714. The open circuit detector 714 may include one or more electrical components for comparing a signal characteristic of the first amplified trimmed pulse with a signal characteristic of the second amplified trimmed pulse. For example, the open circuit detector 714 may compare one or more of the amplitude, frequency, or phase of the first amplified trimmed pulse and the second amplified trimmed pulse. For example, the open circuit detector 714 may compare the first filtered output with a reference signal while simultaneously comparing the second filtered output with respect to another reference signal to determine an open wire bond failure.

[0104] The open circuit detector 714 may determine whether the difference in the signal characteristic of the first amplified pulse and the signal characteristic of the second amplified pulse is within a threshold difference. When the difference in the signal characteristic of the first amplified pulse and the signal characteristic of the second amplified pulse is below the threshold difference, the open circuit detector 714 may take a first mitigation action. The first mitigation action may include outputting a first match signal (e.g., a confirmed match signal) indicating that the first amplified pulse and the second amplified pulse are below the threshold difference. The first mitigation action may include taking no action. The first mitigation action may include causing an electrical component to accept the first pulse and / or the second pulse or otherwise pass the first pulse and / or the second pulse to one or more electrical components.

[0105] Alternatively, when the difference in the signal characteristic of the first amplified pulse and the signal characteristic of the second amplified pulse is above a threshold difference, then the open circuit detector 714 may take a second mitigation action that is different from the first mitigation action. The second mitigation action may include, for example, outputting a second match signal (e.g., a mismatch signal) indicating that the first amplified pulse and the second amplified pulse are above the threshold difference. The second mitigation action may include causing the electrical component to discard or otherwise ignore the first pulse and / or the second pulse.

[0106] like Figure 7 As shown, the first bias network 708A, the first filter 710A, the first amplifier 712A, the second bias network 708B, the second filter 710B, the second amplifier 712B and the open circuit detector 714 can be arranged in parallel with the main receiver 716. In this configuration, the main receiver 716 can receive signals from the first electrical isolator output path 722A and the second electrical isolator output path 722B connected in parallel with the open circuit detector 714 component. Therefore, the open circuit detector 714 can perform open wire bond detection without direct impact on the main receiver 716. When the main receiver 716 is operating in a mission mode, for example, during the operation of the inverter 110, the open circuit detector 714 can perform open wire bond detection. When an open wire bond is detected, the open circuit detector 714 can assert a fault signal, which can be used to control the operation of the inverter 110.

[0107] One or more embodiments may perform open bond wire detection in the presence of CMRFI by amplifying the signal path individually followed by a filter (e.g., high pass, band pass, low pass, notch) and a gain block. The amount of filtering may be varied by changing the order of the filter. One or more embodiments may provide a bias network for a receiver in which an open cap detection circuit is placed before the main receiver, which may increase the circuit's immunity to common mode RF coupling. One or more embodiments may provide a system for detecting open bond wires during mission mode in the presence of CMRFI, which may provide a faster fault response time. One or more embodiments may provide a system that may use significantly smaller circuit area and may not require special test procedures or modes to detect the integrity of the bond wires.

[0108] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a first electrical isolator separating a low voltage region from a high voltage region, the first electrical isolator having a first electrical isolator output path; a second electrical isolator separating the low voltage region from the high voltage region, the second electrical isolator having a second electrical isolator output path; a first bias network in the high voltage region and connected to the first electrical isolator via the first electrical isolator output path, the first bias network having a first bias network output path; a second bias network in the high voltage region and connected to the second electrical isolator via the second electrical isolator output path, the second bias network having a second bias network output path; a first filter in the high voltage region and connected to the first bias network via the first bias network output path, the first filter having a first filter output path; a second filter in the high voltage region and connected to the second bias network via the second bias network output path, the second filter having a second filter output path; a first amplifier connected to the first filter in the high voltage region and via the first filter output path, the first amplifier having a first amplifier output path; a second amplifier in the high voltage region and connected to the second filter via the second filter output path, the second amplifier having a second amplifier output path; and An open circuit detector is provided in the high voltage region, the open circuit detector being connected to the first amplifier via the first amplifier output path and to the second amplifier via the second amplifier output path.

2. The system according to claim 1, further comprising: A pulse transceiver is in the low voltage region, the pulse transceiver being connected to the first galvanic isolator via a first pulse transceiver output path and to the second galvanic isolator via a second pulse transceiver output path.

3. The system of claim 2, further comprising a primary receiver. 4 . The system of claim 3 , wherein the pulse transceiver and the master receiver are configured to operate together to transmit a pulse width modulated signal from the low voltage region to the high voltage region. 5 . The system of claim 2 , wherein the pulse transceiver is configured to output a first pulse on the first pulse transceiver output path and to output a second pulse on the second pulse transceiver output path. 6 . The system of claim 5 , wherein the pulse transceiver is further configured to receive a main pulse and output the first pulse and the second pulse based on the received main pulse.

7. The system of claim 5, wherein: The first galvanic isolator is configured to receive the first pulse on the first pulse transceiver output path and transmit a first galvanic isolator pulse on the first galvanic isolator output path based on the received first pulse, and The second galvanic isolator is configured to receive the second pulse on the second pulse transceiver output path and to transmit a second galvanic isolator pulse on the second galvanic isolator output path based on the received second pulse.

8. The system of claim 7, wherein: The first bias network is configured to receive the first galvanic isolator pulse on the first galvanic isolator output path, process the first galvanic isolator pulse based on one or more characteristics of the first bias network, and send a first biased pulse on the first bias network output path based on the processed first galvanic isolator pulse, and The second bias network is configured to receive the second galvanic isolator pulse on the second galvanic isolator output path, process the second galvanic isolator pulse based on one or more characteristics of the second bias network, and send a second biased pulse on the second bias network output path based on the processed second galvanic isolator pulse.

9. The system of claim 8, wherein: The first filter is configured to receive the first biased pulse on the first bias network output path, filter the first biased pulse based on one or more characteristics of the first filter, and transmit a first filtered pulse on the first filter output path based on the processed first biased pulse, and The second filter is configured to receive the second biased pulse on the second bias network output path, filter the second biased pulse based on one or more characteristics of the second filter, and send a second filtered pulse on the second filter output path based on the processed second biased pulse.

10. The system of claim 9, wherein one or more of the first filter or the second filter is one or more of a bandpass filter, a highpass filter, a lowpass filter, or a notch filter.

11. The system of claim 9, wherein one or more of the first filter or the second filter is configured to modify filter characteristics based on an input signal.

12. The system of claim 9, wherein the open circuit detector is configured to: receiving the first filtered pulse on a first filtered output path; receiving the second filtered pulse on a second filtered output path; performing a comparison of the first filtered pulse and the second filtered pulse with one or more of each other or one or more reference pulses; as well as Mitigating action is initiated based on the comparison of the first filtered pulse and the second filtered pulse.

13. The system of claim 12, wherein the mitigating action comprises asserting a fault signal.

14. The system of claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

15. A method comprising: receiving, by one or more controllers, a first pulse, and transmitting, by the one or more controllers, a first electrical isolator pulse based on the first pulse; receiving, by the one or more controllers, a second pulse, and transmitting, by the one or more controllers, a second electrical isolator pulse based on the second pulse; receiving, by the one or more controllers, the first electrical isolator pulse and the second electrical isolator pulse, and transmitting, by the one or more controllers, a first biased pulse based on the first electrical isolator pulse and a second biased pulse based on the second electrical isolator pulse; receiving, by the one or more controllers, the first biased pulse based on and the second biased pulse based on, and transmitting, by the one or more controllers, a first filtered pulse based on the first biased pulse based on and a second filtered pulse based on the second biased pulse based on; receiving, by the one or more controllers, the first filtered pulse based on and the second filtered pulse based on, and transmitting, by the one or more controllers, a first amplified pulse based on the first filtered pulse based on and a second amplified pulse based on the second filtered pulse based on; comparing, by the one or more controllers, the first amplified pulse and the second amplified pulse to one or more of each other or one or more reference pulses; determining, by the one or more controllers, a mitigation action based on the comparison; as well as An output pulse is generated by the one or more controllers based on the mitigating action.

16. The method of claim 15, wherein determining the mitigation action comprises: determining, by the one or more controllers, a difference between one or more signal characteristics of the first amplified pulse and one or more signal characteristics of the second amplified pulse; comparing, by the one or more controllers, the difference to a difference threshold; as well as The mitigating action is determined by the one or more controllers based on comparing the difference to the difference threshold. The method of claim 15 , wherein the mitigating action comprises asserting a fault signal.

18. The method of claim 15, wherein one or more of the first filtered pulse or the second filtered pulse is filtered based on a noise signal.

19. The method of claim 15, wherein comparing the first amplified pulse and the second amplified pulse comprises: Perform a differential comparison.

20. A system comprising: a first galvanic isolator configured to receive a first pulse from the pulse transceiver and output a first galvanic isolator pulse based on the received first pulse; a second galvanic isolator configured to receive a second pulse from the pulse transceiver and to generate a second galvanic isolator pulse based on the received second pulse; as well as One or more controllers, the one or more controllers being configured to: receiving the first galvanic isolator pulse and the second galvanic isolator pulse, performing a comparison of the received first galvanic isolator pulse and the received second galvanic isolator pulse with one or more of each other or one or more reference pulses, and A fault in one or more of the first galvanic isolator or the second galvanic isolator is determined based on the comparison of the received first galvanic isolator pulse and the received second galvanic isolator pulse.

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