Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device including a micro transistor. The semiconductor device includes first and second transistors, the first transistor including first to third conductive layers, a first semiconductor layer, a first insulating layer, a second conductive layer disposed on the first conductive layer, the first semiconductor layer being in contact with a top surface of the first conductive layer and the second conductive layer, the first insulating layer being in contact with a top surface of the first semiconductor layer, and the second insulating layer being in contact with a top surface of the second semiconductor layer. The first transistor comprises a first semiconductor layer and a first insulating layer, the third conductive layer is arranged on the first semiconductor layer and the first insulating layer, the second transistor comprises fourth to sixth conductive layers, the second semiconductor layer, the first insulating layer and the fifth conductive layer are arranged on the fourth conductive layer, and the second semiconductor layer is in contact with the top surface of the fourth conductive layer and the fifth conductive layer; the first insulating layer is in contact with a top surface of the second semiconductor layer, the sixth conductive layer is disposed on the second semiconductor layer and the first insulating layer, and the second insulating layer is disposed between the first conductive layer and the second conductive layer and between the fourth conductive layer and the fifth conductive layer. The thickness between the first conductive layer and the second conductive layer is different from the thickness between the fourth conductive layer and the fifth conductive layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical field. Examples of the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices incorporating these devices, and methods for driving or manufacturing these devices. Background Art

[0003] Semiconductor devices including transistors are widely used in display devices and electronic devices, and they require high integration and high speed. For example, when semiconductor devices are used in high-definition display devices, highly integrated semiconductor devices are required. As one of the methods for increasing the integration density of transistors, research and development of micro-transistors has been conducted.

[0004] In recent years, there has been a high demand for display devices that can be used for virtual reality (VR), augmented reality (AR), substitute reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). In order to enhance the sense of reality and immersion, XR display devices need to have high clarity and high color reproducibility. In addition, as devices that can be used for the above-mentioned display devices, for example, liquid crystal display devices, light-emitting devices including light-emitting devices (also called light-emitting elements) such as organic EL (Electro Luminescence) devices or light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR using an organic EL device (also referred to as an organic EL element). [Prior technical literature] [Patent Document]

[0006] [Patent Document 1] International Patent Application Publication No. 2018 / 087625 Summary of the Invention Technical problem to be solved by the invention

[0007] One of the objects of one embodiment of the present invention is to provide a semiconductor device including a micro transistor and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a small semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a high-performance semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a method for manufacturing the same.

[0008] Note that the inclusion of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily achieve all of the above objectives. Objectives other than the above may be extracted from the description of the specification, drawings, claims, etc. Means of solving technical problems

[0009] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor, the first transistor including a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer and a first insulating layer, the second conductive layer being arranged on the first conductive layer, the first semiconductor layer being in contact with a top surface of the first conductive layer and the second conductive layer, the first insulating layer being in contact with a top surface of the first semiconductor layer, the third conductive layer being arranged on the first insulating layer so as to have a region overlapping with the first semiconductor layer, the second transistor including a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, the second semiconductor layer and the first insulating layer, the fifth conductive layer being arranged on the fourth conductive layer, the second semiconductor layer being in contact with a top surface of the fourth conductive layer and the fifth conductive layer, the first insulating layer being in contact with a top surface of the second semiconductor layer, the sixth conductive layer being arranged on the first insulating layer so as to have a region overlapping with the second semiconductor layer, a second insulating layer being arranged between the first conductive layer and the second conductive layer and between the fourth conductive layer and the fifth conductive layer, the thickness of the second insulating layer between the first conductive layer and the second conductive layer and the thickness of the second insulating layer between the fourth conductive layer and the fifth conductive layer being different from each other.

[0010] Furthermore, in the above semiconductor device, it is preferred that both the first semiconductor layer and the second semiconductor layer contain a metal oxide.

[0011] In the semiconductor device, preferably, the second insulating layer includes a third insulating layer and a fourth insulating layer, the third insulating layer is provided in an island shape on the fourth conductive layer, and the fourth insulating layer is provided on the first conductive layer and the third insulating layer.

[0012] In addition, in the above-mentioned semiconductor device, preferably, the second insulating layer includes a third insulating layer and a fourth insulating layer, the third insulating layer is arranged on the first conductive layer and the fourth conductive layer, and the fourth insulating layer is arranged on the third insulating layer in a manner having an opening in a region overlapping with the first conductive layer.

[0013] In addition, in the above-mentioned semiconductor device, preferably, the second insulating layer includes a third insulating layer and a fourth insulating layer, the third insulating layer is arranged in an island shape, the first conductive layer is arranged on the third insulating layer, and the fourth insulating layer is arranged on the first conductive layer and the fourth conductive layer.

[0014] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive film; processing the first conductive film to form a first conductive layer and a second conductive layer; forming a first insulating film on the first conductive layer and the second conductive layer; processing the first insulating film to form a first insulating layer overlapping with the second conductive layer; forming a second insulating layer on the first conductive layer, the second conductive layer and the first insulating layer; forming a second conductive film on the second insulating layer; processing the second conductive film to form a third conductive layer overlapping with the first conductive layer and a fourth conductive layer overlapping with the second conductive layer; removing a portion of the third conductive layer and the fourth conductive layer to form a fifth conductive layer having a first opening and a sixth conductive layer having a second opening, respectively; removing the second insulating layer in an area overlapping with the first opening and the first insulating layer and the second insulating layer in an area overlapping with the second opening to form a third opening and a fourth opening, respectively; covering the first opening and the second opening , a third opening and a fourth opening to form a metal oxide film in contact with the top surface of the first conductive layer, the top surface of the second conductive layer, the top surface and side surfaces of the fifth conductive layer, the top surface and side surfaces of the sixth conductive layer, the side surfaces of the first insulating layer and the side surfaces of the second insulating layer; processing the metal oxide film into an island shape to form a first semiconductor layer in contact with the top surface of the first conductive layer, the side surfaces of the second insulating layer and the top surface and side surfaces of the fifth conductive layer, and a second semiconductor layer in contact with the top surface of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer and the top surface and side surfaces of the sixth conductive layer; forming a third insulating layer on the first semiconductor layer, the second semiconductor layer, the fifth conductive layer, the sixth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; and processing the third conductive film to form a seventh conductive layer overlapping with the first conductive layer and the first semiconductor layer, and an eighth conductive layer overlapping with the second conductive layer and the second semiconductor layer.

[0015] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive film; processing the first conductive film to form a first conductive layer and a second conductive layer; forming a first insulating layer on the first conductive layer and the second conductive layer and a first insulating film on the first insulating layer; processing the first insulating film to form a second insulating layer having a first opening in a region overlapping with the first conductive layer; forming a second conductive film on the first insulating layer and the second insulating layer; processing the second conductive film to form a third conductive layer overlapping with the first conductive layer and a fourth conductive layer overlapping with the second conductive layer; removing a portion of the third conductive layer and the fourth conductive layer to form a fifth conductive layer having a second opening and a sixth conductive layer having a third opening, respectively; removing the first insulating layer in a region overlapping with the second opening and the first insulating layer and the second insulating layer in a region overlapping with the third opening to form a fourth opening and a fifth opening, respectively; covering the second opening, the third opening, and the sixth conductive layer. The invention relates to a method for manufacturing a semiconductor layer comprising the following steps: forming a first conductive layer and a second conductive layer; forming a metal oxide film in contact with the top surface of the first conductive layer, the top surface of the second conductive layer, the top and side surfaces of the fifth conductive layer, the top and side surfaces of the sixth conductive layer, the side surfaces of the first insulating layer, and the side surfaces of the second insulating layer through the fourth opening and the fifth opening; processing the metal oxide film into an island shape to form a first semiconductor layer in contact with the top surface of the first conductive layer, the side surfaces of the first insulating layer, and the top and side surfaces of the fifth conductive layer, and a second semiconductor layer in contact with the top surface of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, and the top and side surfaces of the sixth conductive layer; forming a third insulating layer on the first semiconductor layer, the second semiconductor layer, the fifth conductive layer, the sixth conductive layer, and the second insulating layer; forming a third conductive film on the third insulating layer; and processing the third conductive film to form a seventh conductive layer overlapping with the first conductive layer and the first semiconductor layer, and an eighth conductive layer overlapping with the second conductive layer and the second semiconductor layer.

[0016] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating film; processing the first insulating film to form a first insulating layer; forming a first conductive film on the first insulating layer; processing the first conductive film to form a first conductive layer on the first insulating layer and a second conductive layer on a region different from the first insulating layer; forming a second insulating film on the first insulating layer, on the first conductive layer, and on the second conductive layer; processing the second insulating film to form a second insulating layer having a flat or substantially flat surface; forming a second conductive film on the second insulating layer; processing the second conductive film to form a third conductive layer overlapping with the first conductive layer and a fourth conductive layer overlapping with the second conductive layer; removing a portion of the third conductive layer and the fourth conductive layer to form a fifth conductive layer having a first opening and a sixth conductive layer having a second opening, respectively; removing the second insulating layer in a region overlapping with the first opening and the second insulating layer in a region overlapping with the second opening to form a third opening and a fourth opening; covering the first opening, the second opening, the third opening and the fourth opening to form a metal oxide film in contact with the top surface of the first conductive layer, the top surface of the second conductive layer, the top surface and side surfaces of the fifth conductive layer, the top surface and side surfaces of the sixth conductive layer and the side surfaces of the second insulating layer; processing the metal oxide film into an island shape to form a first semiconductor layer in contact with the top surface of the first conductive layer, the side surfaces of the second insulating layer and the top surface and side surfaces of the fifth conductive layer, and a second semiconductor layer in contact with the top surface of the second conductive layer, the side surfaces of the second insulating layer and the top surface and side surfaces of the sixth conductive layer; forming a third insulating layer on the first semiconductor layer, the second semiconductor layer, the fifth conductive layer, the sixth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; and processing the third conductive film to form a seventh conductive layer overlapping with the first conductive layer and the first semiconductor layer, and an eighth conductive layer overlapping with the second conductive layer and the second semiconductor layer. Effects of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device including a micro transistor and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a small semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a semiconductor device including a transistor with a large on-state current and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a high-performance semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a highly reliable semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device and a method for manufacturing the same can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A and Figure 1B is a cross-sectional view showing an example of a semiconductor device. Figure 2A is a block diagram showing a structural example of a display device. Figure 2B is a plan view showing a structural example of a pixel. Figure 2C and Figure 2D is a circuit diagram showing a structural example of a pixel. Figure 3A is a block diagram showing a structural example of a display device. Figure 3B is a circuit diagram showing a structural example of a pixel. Figures 4A to 4C is a circuit diagram showing a structural example of a pixel. Figure 5A is a block diagram showing a structural example of a storage device. Figures 5B to 5E is a circuit diagram showing a structural example of a memory cell. Figure 6A is a plan view showing an example of a semiconductor device. Figure 6B is a cross-sectional view showing an example of a semiconductor device. Figure 7A is a plan view showing an example of a transistor. Figure 7B is a cross-sectional view showing an example of a transistor. Figure 8A is a plan view showing an example of a semiconductor device. Figure 8B is a cross-sectional view showing an example of a semiconductor device. Figure 9A is a plan view showing an example of a semiconductor device. Figure 9B is a cross-sectional view showing an example of a semiconductor device. Figure 10A is a plan view showing an example of a semiconductor device. Figure 10B is a cross-sectional view showing an example of a semiconductor device. Figure 11A is a plan view showing an example of a semiconductor device. Figure 11B is a cross-sectional view showing an example of a semiconductor device. Figure 12 is a cross-sectional view showing an example of a semiconductor device. Figure 13 is a cross-sectional view showing an example of a semiconductor device. Figure 14 is a cross-sectional view showing an example of a semiconductor device. Figure 15 is a cross-sectional view showing an example of a semiconductor device. Figure 16 is a cross-sectional view showing an example of a semiconductor device. Figure 17A is a plan view showing an example of a semiconductor device. Figure 17B is a cross-sectional view showing an example of a semiconductor device. Figure 18A is a plan view showing an example of a semiconductor device. Figure 18B is a cross-sectional view showing an example of a semiconductor device. Figure 19A is a plan view showing an example of a semiconductor device. Figure 19B is a cross-sectional view showing an example of a semiconductor device. Figure 20A is a plan view showing an example of a semiconductor device. Figure 20B is a cross-sectional view showing an example of a semiconductor device. Figure 21A is a plan view showing an example of a semiconductor device. Figure 21B is a cross-sectional view showing an example of a semiconductor device. Figure 22A is a plan view showing an example of a semiconductor device. Figure 22B is a cross-sectional view showing an example of a semiconductor device. Figure 23A is a plan view showing an example of a semiconductor device. Figure 23B is a cross-sectional view showing an example of a semiconductor device. Figure 24A is a plan view showing an example of a transistor. Figure 24B is a cross-sectional view showing an example of a transistor. Figure 24C is a circuit diagram illustrating a transistor. Figure 25A is a plan view showing an example of a semiconductor device. Figure 25B is a cross-sectional view showing an example of a semiconductor device. Figure 26A is a plan view showing an example of a semiconductor device. Figure 26B is a cross-sectional view showing an example of a semiconductor device. Figure 27A is a plan view showing an example of a semiconductor device. Figure 27B is a cross-sectional view showing an example of a semiconductor device. Figure 28Ais a plan view showing an example of a semiconductor device. Figure 28B is a cross-sectional view showing an example of a semiconductor device. Figure 29A and Figure 29B is a cross-sectional view showing an example of a transistor. Figure 29C is a circuit diagram illustrating a transistor. Figure 30A and Figure 30B is a cross-sectional view showing an example of a transistor. Figure 30C is a circuit diagram illustrating a transistor. Figure 31A and Figure 31B is a cross-sectional view showing an example of a transistor. Figure 31C is a circuit diagram illustrating a transistor. Figure 32A is a plan view showing an example of a semiconductor device. Figure 32B is a cross-sectional view showing an example of a semiconductor device. Figure 33A is a plan view showing an example of a semiconductor device. Figure 33B is a cross-sectional view showing an example of a semiconductor device. Figure 34A is a plan view showing an example of a semiconductor device. Figure 34B is a cross-sectional view showing an example of a semiconductor device. Figure 35A is a circuit diagram showing a structural example including a pixel circuit. Figure 35B is a plan view showing a structural example including a pixel circuit. Figure 35C and Figure 35D is a cross-sectional view showing a structural example including a pixel circuit. Figure 36A is a plan view showing a structural example including a pixel circuit. Figure 36B is a cross-sectional view showing a structural example including a pixel circuit. Figure 37 is a plan view showing a structural example including a pixel circuit. Figure 38A It is a plan view showing a structural example of a display device. Figure 38B is a cross-sectional view showing a structural example of a display device. Figure 39A It is a plan view showing a structural example of a display device. Figure 39B is a cross-sectional view showing a structural example of a display device. Figures 40A to 40C It is a plan view showing a structural example of a display device. Figures 41A to 41C It is a plan view showing a structural example of a display device. Figure 42A and Figure 42B It is a plan view showing a structural example of a display device. Figures 43A to 43C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 44A to 44C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 45A to 45C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 46A to 46C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 47A to 47C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 48A to 48C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 49A to 49C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 50A to 50C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 51A to 51D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 52A to 52C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 53A to 53C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 54A to 54C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 55 It is a perspective view showing a structural example of a display device. Figure 56 is a cross-sectional view showing a structural example of a display device. Figure 57 is a cross-sectional view showing a structural example of a display device. Figure 58 is a cross-sectional view showing a structural example of a display device. Figure 59 is a cross-sectional view showing a structural example of a display device. Figure 60 is a cross-sectional view showing a structural example of a display device. Figures 61A to 61D is a diagram illustrating an example of an electronic device. Figures 62A to 62F is a diagram illustrating an example of an electronic device. Figures 63A to 63G is a diagram illustrating an example of an electronic device. Modes for Carrying Out the Invention

[0020] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description. A person skilled in the art will readily appreciate that the embodiments and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0021] Note that in the invention structure described below, the same symbols are used to show the same parts or parts with the same function in different drawings, and repeated descriptions are omitted. In addition, when parts with the same function are represented, the same hatching is sometimes used without adding a special reference numeral.

[0022] For ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not necessarily represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0023] In addition, depending on the situation or state, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced with "conductive film." Also, "insulating film" can be replaced with "insulating layer."

[0024] In this specification, etc., a light-emitting device includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier blocking layer (a hole blocking layer and an electron blocking layer).

[0025] In this specification, "island-shaped" refers to a state in which two or more layers formed in the same process and using the same material are physically separated. For example, an island-shaped light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0026] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of a component's side surface is inclined relative to the substrate surface or the surface being formed. For example, this refers to a shape having a region where the angle (also called a taper angle) formed between the inclined side surface and the substrate surface or the surface being formed is less than 90 degrees. Note that the side surface, substrate surface, and surface being formed of a component do not necessarily need to be completely flat; they may be approximately planar with slight curvature or have fine irregularities.

[0027] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of a formed surface (for example, a step, etc.).

[0028] In this specification, etc., the phrase "top surface shapes (also referred to as shapes when viewed from a planar surface or outline shapes) are generally identical" means that at least a portion of the outlines of each layer in the stack overlap. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern, or a portion of the mask pattern is identical. However, in practice, there are cases where the outlines do not overlap, such as when the upper layer is located inside or outside the lower layer. In these cases, "top surface shapes are generally identical."

[0029] In this specification, the top surface shape of a component refers to the outline shape of the component when viewed from a planar perspective. Furthermore, the term "planar perspective" refers to the perspective viewed from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0030] In this specification, “substantially uniform in height” refers to a structure in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are substantially equal when viewed in cross section.

[0031] (Implementation 1) A semiconductor device according to one embodiment of the present invention includes at least two transistors. In the transistors, the source electrode and the drain electrode are located at different heights relative to the substrate surface, and the drain current flows in the height direction (vertical direction). In addition, the thickness of the insulating layer between the source electrode and the drain electrode of the transistor is different for each transistor included in the semiconductor device. In other words, the semiconductor device according to one embodiment of the present invention includes two or more transistors having different distances between the source electrode and the drain electrode (i.e., channel length).

[0032] Figure 1A and Figure 1B A cross-sectional view illustrating a general concept of a semiconductor device according to one embodiment of the present invention is shown.

[0033] like Figure 1A and Figure 1B As shown, a semiconductor device according to one embodiment of the present invention includes two transistors, a transistor M1 and a transistor M2. Figure 1A and Figure 1B , only two transistors are shown, but the present invention is not limited thereto. The semiconductor device according to one embodiment of the present invention may include three or more transistors.

[0034] Both transistor M1 and transistor M2 are provided on substrate 102. Transistor M1 includes a conductive layer 112a on substrate 102, a conductive layer 112b on conductive layer 112a, a semiconductor layer 108 having a region in contact with top surfaces of conductive layer 112a and conductive layer 112b, an insulating layer 106 on semiconductor layer 108, and a conductive layer 104 on insulating layer 106.

[0035] In transistor M1, conductive layer 112a serves as one of a source electrode and a drain electrode. Conductive layer 112b serves as the other of the source electrode and the drain electrode. Insulating layer 106 serves as a gate insulating layer. Conductive layer 104 serves as a gate electrode. A region of semiconductor layer 108 that overlaps conductive layer 104 with insulating layer 106 between conductive layer 112a and conductive layer 112b serves as a channel formation region.

[0036] Transistor M2 includes a conductive layer 202a on the substrate 102 (on a region different from the conductive layer 112a), a conductive layer 202b on the conductive layer 202a, a semiconductor layer 208 having a region in contact with the top surfaces of the conductive layer 202a and the conductive layer 202b, an insulating layer 106 on the semiconductor layer 208, and a conductive layer 204 on the insulating layer 106.

[0037] In transistor M2, conductive layer 202a serves as one of a source electrode and a drain electrode. Conductive layer 202b serves as the other of the source electrode and the drain electrode. Insulating layer 106 serves as a gate insulating layer. Conductive layer 204 serves as a gate electrode. The region of semiconductor layer 208 that overlaps conductive layer 202a and conductive layer 202b with insulating layer 106 interposed therebetween serves as a channel formation region.

[0038] An insulating layer 110 is disposed between the source electrode and the drain electrode of the transistor M1 and between the source electrode and the drain electrode of the transistor M2 .

[0039] Here, in Figure 1A In the semiconductor device shown, conductive layer 112a and conductive layer 202a are each provided in contact with the top surface of substrate 102, and the heights of the formed surfaces of conductive layer 112a and conductive layer 202a are substantially the same. However, the heights of the formed surfaces of conductive layer 112b and conductive layer 202b are different relative to the top surface of substrate 102.

[0040] On the other hand, Figure 1BIn the semiconductor device shown, the heights of the surfaces of the conductive layers 112b and 202b are substantially the same. However, since the conductive layer 202a is provided in contact with the top surface of the substrate 102, and the conductive layer 112a is provided embedded within the insulating layer 110, the heights of the surfaces of the conductive layers 112a and 202a are different.

[0041] That is to say, in Figure 1A and Figure 1B In all semiconductor devices shown, the thickness of the insulating layer 110 is different between the conductive layer 112a and the conductive layer 112b, and the thickness of the insulating layer 110 is different between the conductive layer 202a and the conductive layer 202b. Figure 7B Although details are described in [ 15 ], in a transistor included in a semiconductor device according to one embodiment of the present invention, the thickness of the insulating layer between the source electrode and the drain electrode corresponds to the channel length. Therefore, the channel lengths of transistor M1 and transistor M2 in the semiconductor device according to one embodiment of the present invention are different.

[0042] The shorter the channel length of the transistor, the larger the on-state current and the higher the field-effect mobility can be obtained. On the other hand, the longer the channel length of the transistor, the more it can improve the saturation characteristics of the current flowing through the transistor when it is driven in the saturation region (that is, the magnitude of the drain current hardly changes with respect to the increase in the drain voltage). In one embodiment of the present invention, by making the thickness of the insulating layer 110 different within the substrate surface, a transistor M1 with a short channel length and a transistor M2 with a long channel length can be formed on the same substrate in a manner that shares some of the steps. Therefore, for example, by using transistor M1 for a transistor that requires a large on-state current and using transistor M2 for a transistor that requires high saturation, a high-performance semiconductor device that utilizes the characteristics of each transistor can be realized.

[0043] The semiconductor device according to one embodiment of the present invention can be used in, for example, a display device. Furthermore, the semiconductor device according to one embodiment of the present invention can be used in, for example, a memory device. Specific structural examples of a display device and a memory device in which the semiconductor device according to one embodiment of the present invention can be used are described below.

[0044] <Configuration Example of Display Device> Figure 2A 1 is a block diagram showing a configuration example of a display device 30 as one embodiment of the present invention. The display device 30 includes a display unit 20, a scan line driver circuit 11, a signal line driver circuit 13, and a power supply circuit 15. The display unit 20 includes a plurality of pixels 21 arranged in a matrix.

[0045] The scanning line driving circuit 11 is electrically connected to the pixels 21 via the wiring 41. Specifically, the pixels 21 in the same row are electrically connected to the scanning line driving circuit 11 via the same wiring 41.

[0046] The signal line driving circuit 13 is electrically connected to the pixels 21 via the wiring 43 . Specifically, the pixels 21 in the same column are electrically connected to the signal line driving circuit 13 via the same wiring 43 .

[0047] The power supply circuit 15 is electrically connected to the pixels 21 via the wiring 45. For example, the pixels 21 in the same row may be electrically connected to the power supply circuit 15 via the same wiring 45.

[0048] The pixel 21 includes a display element (also referred to as a display device), which can be used to display an image on the display unit 20. Specifically, the image can be displayed on the display unit 20 by controlling the brightness of the light emitted from the pixel 21 using the display element. As the display element, for example, a light-emitting element can be used, and specifically, an organic EL element can be used. In addition, a liquid crystal element (also referred to as a liquid crystal device) can also be used as the display element.

[0049] The scan line driver circuit 11 has the function of selecting the pixels 21 to which image data is written. Specifically, the scan line driver circuit 11 can select the pixels 21 to which image data is written by outputting a signal to the wiring 41. Here, in the scan line driver circuit 11, after outputting the above-mentioned signal to the wiring 41 of the first row, the above-mentioned signal is output to the wiring 41 of the second row, and the above-mentioned signal is output sequentially until the wiring 41 of the final row, thereby writing image data to the pixels 21. Therefore, the signal output by the scan line driver circuit 11 to the wiring 41 can be said to be a scan signal, and the wiring 41 can be said to be a scan line. Note that the scan line driver circuit is sometimes referred to as a gate driver. In addition, the wiring 41 is sometimes referred to as a gate line.

[0050] The signal line driver circuit 13 generates image data. This image data is supplied to the pixels 21 via the wiring 43. For example, image data can be written to all pixels 21 in the row selected by the scan line driver circuit 11. Here, the image data can be represented as a signal. Therefore, the wiring 43 can be considered a signal line. Note that the signal line driver circuit is sometimes referred to as a source driver. Furthermore, the wiring 43 is sometimes referred to as a source line.

[0051] The power supply circuit 15 has a function of generating a power supply potential and supplying it to the wiring 45. The power supply circuit 15 has, for example, a function of generating a high power supply potential (hereinafter, also referred to as "high potential" or "VDD") and supplying it to the wiring 45. In addition, the power supply circuit 15 may also have a function of generating a low power supply potential (hereinafter, also referred to as "low potential" or "VSS"). In addition, the power supply circuit 15 can sequentially switch between the high power supply potential and the low power supply potential to output a pulse-shaped signal. Alternatively, a pulse-shaped signal can be scanned and output in one row. Since the wiring 45 is supplied with a power supply potential, the wiring 45 can be said to be a power line. In addition, the current flows from the wiring 45 through Figure 2C The current flows to the light emitting element (e.g., light emitting element 60 described later) through the transistor 52 shown in FIG. 45 . Therefore, the wiring 45 is sometimes referred to as a current supply line. In addition, the wiring 45 is sometimes supplied with a pulse signal, so it is sometimes referred to as a pulse line. By supplying a pulse potential to the wiring 45, the current can be corrected. Figure 2C The variations in threshold voltage and mobility of the transistor 52 are shown in FIG.

[0052] A constant potential signal, a pulse signal, and the like are supplied to the wiring 41 , the wiring 43 , and the wiring 45 .

[0053] Figure 2B 2 is a plan view showing a structural example of a pixel 21. The pixel 21 includes a plurality of sub-pixels 23. Figure 2B 23B. Here, when the pixel 21 includes a light-emitting element as a display element, for example, Figure 2B The top surface shape of the sub-pixel shown corresponds to the top surface shape of the light-emitting region of the light-emitting element. Figure 2B While the aperture ratios or light-emitting area sizes of sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B are shown to be equal or substantially equal, one embodiment of the present invention is not limited thereto. The aperture ratios of sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B can be appropriately determined. The aperture ratios of sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B can be different from each other, or two or more of them can be equal or substantially equal.

[0054] In this specification and other documents, for example, when describing common features among sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B, the letters distinguishing these features may be omitted and the sub-pixel 23 may be referred to as sub-pixel 23. When describing common features among other components distinguished by letters, the symbols may be omitted and the letters may be used for the description.

[0055] exist Figure 2BIn the illustrated pixel 21, a stripe arrangement is adopted as an arrangement method of the sub-pixels 23. Alternatively, the sub-pixels 23 may be arranged in an S-stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, or a Pentile arrangement.

[0056] Sub-pixel 23R, sub-pixel 23G and sub-pixel 23B emit light of different colors. As sub-pixel 23R, sub-pixel 23G and sub-pixel 23B, sub-pixels of three colors of red (R), green (G) and blue (B) and sub-pixels of three colors of yellow (Y), cyan (C) and magenta (M) can be cited. In addition, more than four sub-pixels 23 can also be provided in pixel 21. For example, sub-pixels of four colors of R, G, B and white (W) can also be provided in pixel 21. Alternatively, sub-pixels of four colors of R, G, B and infrared light (IR) can also be provided in pixel 21. Thus, the display device 30 can display a full-color image on the display unit 20.

[0057] Figure 2C is a circuit diagram showing a structural example of the sub-pixel 23 . Figure 2C The sub-pixel 23 shown includes a pixel circuit 40A and a light-emitting element 60 .

[0058] The pixel circuit 40A includes a transistor 51, a transistor 52, and a capacitor 57. That is, the pixel circuit 40A is a 2Tr1C type pixel circuit.

[0059] In the pixel circuit 40A, one of the source and drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and drain of the transistor 51 is electrically connected to the gate of the transistor 52. The gate of the transistor 52 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 51 is electrically connected to the wiring 41.

[0060] One of the source and drain of transistor 52 is electrically connected to wiring 45. The other of the source and drain of transistor 52 is electrically connected to the other electrode of capacitor 57. The other electrode of capacitor 57 is electrically connected to one electrode of light-emitting element 60. The other electrode of light-emitting element 60 is electrically connected to wiring 47. Here, one electrode of light-emitting element 60 is also referred to as a pixel electrode. Alternatively, wiring 47 can be shared among all pixels 21, for example. Therefore, the other electrode of light-emitting element 60 can also be referred to as a common electrode.

[0061] As described above, wiring 41 functions as a scan line, wiring 43 functions as a signal line, and wiring 45 functions as a power supply line. Furthermore, wiring 47 functions as a power supply line. For example, when wiring 45 is supplied with a high power supply potential, wiring 47 is supplied with a low power supply potential. Wiring 47 can be electrically connected to power supply circuit 15, for example.

[0062] Transistor 51 functions as a switch, controlling the conduction state or non-conduction state between wiring 43 and the gate of transistor 52 according to the potential of wiring 41. By turning on transistor 51, image data is written to pixel circuit 40A, while by turning off transistor 51, the written image data is retained. Transistor 51 is also called a selection transistor.

[0063] Transistor 52 controls the amount of current flowing through light-emitting element 60 and is also referred to as a drive transistor. Capacitor 57 maintains the gate potential of transistor 52. The brightness of light-emitting element 60 is controlled by the potential supplied to the gate of transistor 52 according to the image data. Specifically, when a high power supply potential is supplied to wiring 45 and a low power supply potential is supplied to wiring 47, the magnitude of the current flowing from wiring 45 to wiring 47 is controlled by the potential of the gate of transistor 52, thereby controlling the brightness of light-emitting element 60.

[0064] Transistors 51 and 52 preferably use transistors using oxide semiconductors (OS) for their semiconductor layers (hereinafter referred to as OS transistors). For example, OS transistors have higher field-effect mobility than transistors using amorphous silicon for their semiconductor layers. Therefore, using OS transistors as transistors 51 and 52 allows for high-speed operation of the display device 30.

[0065] Furthermore, the leakage current between the source and drain of the OS transistor in the off state (hereinafter also referred to as the off-state current) is significantly small. Thus, by using an OS transistor as transistor 51, the charge stored in capacitor 57 can be retained for a long period of time. Therefore, the image data written to the sub-pixel 23 can be retained for a long period of time, thereby reducing the frequency of refresh operations (rewriting image data to the sub-pixel 23). This can reduce the power consumption of the display device 30.

[0066] To increase the brightness of light-emitting element 60, the current flowing through it needs to be increased. To achieve this, the source-drain voltage of transistor 52, which serves as the driving transistor, needs to be increased. Because the source-drain withstand voltage of an OS transistor is higher than that of a transistor using silicon as its semiconductor layer (also known as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as transistor 52, the current flowing through light-emitting element 60 can be increased, thereby improving the brightness of light-emitting element 60.

[0067] When the transistor is driven in the saturation region, an OS transistor can make the change in source-drain current smaller in response to changes in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as transistor 52, the current flowing through the source-drain can be precisely determined based on changes in gate-source voltage, thereby controlling the amount of current flowing through light-emitting element 60. Consequently, the brightness of light emitted by sub-pixel 23 can be precisely controlled. This increases the number of grayscales that can be displayed by sub-pixel 23.

[0068] Regarding the saturation characteristics of the current flowing when the transistor is driven in the saturation region, compared to Si transistors, OS transistors can flow a stable current (saturation current) even when the source-drain voltage is gradually increased. Therefore, by using an OS transistor as transistor 52, a stable current can flow through the light-emitting element 60 even if, for example, the current-voltage characteristics of the light-emitting element 60 deviate. In other words, when the OS transistor is driven in the saturation region, even if the source-drain voltage is increased, the source-drain current remains almost unchanged, thereby stabilizing the light emission brightness of the light-emitting element 60.

[0069] As described above, by using an OS transistor as the transistor 52 , “suppression of black blurring,” “increase in emission luminance,” “multi-gradation,” “suppression of emission luminance variation,” and the like can be achieved.

[0070] As the light-emitting element 60, for example, an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) is preferably used. Examples of the light-emitting substance contained in the light-emitting element 60 include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.). In addition, LEDs such as micro LEDs (Light Emitting Diodes) can also be used as the light-emitting element 60.

[0071] exist Figure 2C In the pixel circuit 40A shown in FIG. 1 , for example, a transistor 51 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length among transistors.

[0072] Figure 2D The illustrated sub-pixel 23 includes a pixel circuit 40A_2 and a light-emitting element 60. In addition to the structure of pixel circuit 40A, pixel circuit 40A_2 also includes a capacitor 57b. That is, pixel circuit 40A_2 is a 2Tr2C type pixel circuit. One electrode of capacitor 57b is electrically connected to the other of the source and drain of transistor 52. The other electrode of capacitor 57b is electrically connected to wiring 47. By configuring capacitor 57b and adjusting its capacitance, variations in the threshold voltage and mobility of transistor 52 can be appropriately corrected.

[0073] exist Figure 2D In the pixel circuit 40A_2 shown in FIG. 1 , for example, a transistor 51 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length among transistors.

[0074] Figure 3A is a block diagram showing an example of the structure of the display device 30, and Figure 2A A modified example of the display device 30 is shown. Figure 3A The display device 30 shown is Figure 2A The display device 30 shown is different in that the wiring 41 includes a wiring 41 a and a wiring 41 b , and a reference potential generating circuit 17 is provided.

[0075] The reference potential generating circuit 17 is electrically connected to the pixel 21 via the wiring 48. For example, all pixels 21 can be electrically connected to the reference potential generating circuit 17 via the wiring 48. The reference potential generating circuit 17 has the function of generating a reference potential and supplying it to the wiring 48. Since the potential of the wiring 48 becomes the reference potential, the wiring 48 can be said to be a reference potential line. Note that the electrical characteristics of each pixel can also be read out to the reference potential generating circuit 17 outside the pixel via the wiring 48. That is, the reference potential generating circuit 17 can also have the function of sensing the electrical characteristics of each pixel. In addition, the degradation and deviation of the elements (transistors or light-emitting elements, etc.) in each pixel can also be sensed by reading the electrical characteristics of each pixel by the reference potential generating circuit 17. Furthermore, the degradation and deviation of the image quality can also be corrected by feeding back the read characteristics to the image signal.

[0076] Figure 3B It shows Figure 3A 2 is a circuit diagram showing a structural example of a sub-pixel 23 included in a pixel 21 in FIG. Figure 3BThe sub-pixel 23 shown includes a pixel circuit 40B and a light-emitting element 60. The pixel circuit 40B has a structure in which a transistor 53 is added to the pixel circuit 40A. That is, the pixel circuit 40B is a 3Tr1C type pixel circuit.

[0077] In pixel circuit 40B, the gate of transistor 51 is electrically connected to wiring 41 a. One of the source and drain of transistor 53 is electrically connected to the other of the source and drain of transistor 52, the other electrode of capacitor 57, and one electrode of light-emitting element 60. The other of the source and drain of transistor 53 is electrically connected to wiring 48. The gate of transistor 53 is electrically connected to wiring 41 b.

[0078] Transistor 53 functions as a switch, controlling the conductive state or non-conductive state between wiring 48 and one electrode of light-emitting element 60 according to the potential of wiring 41b. For example, a reference potential is supplied to wiring 48. The reference potential of wiring 48 supplied by transistor 53 suppresses variations in the gate-source voltage of transistor 52.

[0079] In addition, the wiring 48 can be used to obtain a current value that can be used for setting pixel parameters. More specifically, the wiring 48 can be used as a monitoring line that outputs the current flowing through the transistor 52 or the current flowing through the light-emitting element 60 to the outside of the pixel 21. The current output to the wiring 48 can be converted into a potential by, for example, a source follower circuit. Or, for example, it can be converted into a digital signal by an AD converter. Note that in the case where the wiring 48 is used as a monitoring line, the display device 30 may also not include the reference potential generating circuit 17. In addition, in the case where the wiring 48 is used as a monitoring line, the pixels 21 can be electrically connected to different wirings 48 in columns.

[0080] An OS transistor is preferably used as the transistor 53. As described above, an OS transistor has a higher field effect mobility than a transistor using amorphous silicon as a semiconductor layer. Therefore, using an OS transistor as the transistor 53 allows the display device 30 to be driven at high speed.

[0081] exist Figure 3B In the pixel circuit 40B shown in FIG. 1 , for example, a transistor 51 or a transistor 53 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length among transistors.

[0082] Figure 4A 、 Figure 4B and Figure 4C It shows Figure 3A 2 is a circuit diagram showing a structural example of a sub-pixel 23 included in a pixel 21 in FIG. Figure 4A The sub-pixel 23 shown includes a pixel circuit 40C and a light-emitting element 60. The pixel circuit 40C has a structure in which a transistor 54 and a capacitor 58 are added to the pixel circuit 40B. That is, the pixel circuit 40C is a 4Tr2C type pixel circuit.

[0083] In pixel circuit 40C, one of the source and drain of transistor 52 is electrically connected to one of the source and drain of transistor 54. The other of the source and drain of transistor 54 is electrically connected to wiring 45. The gate of transistor 54 is electrically connected to wiring 41c. One electrode of capacitor 58 is electrically connected to the other of the source and drain of transistor 52, one of the source and drain of transistor 53, the other electrode of capacitor 57, and one electrode of light-emitting element 60. The other electrode of capacitor 58 is electrically connected to wiring 45.

[0084] The wiring 41c is electrically connected to the scanning line driving circuit 11. That is, the sub-pixel 23 included in the pixel 21 has Figure 4A In the case of the illustrated structure, the wiring 41 , which includes a wiring 41 a , a wiring 41 b , and a wiring 41 c , is provided in the display device 30 .

[0085] The transistor 54 functions as a switch and has a function of controlling the conduction state or the non-conduction state between the wiring 45 and one of the source and the drain of the transistor 52 according to the potential of the wiring 41 c .

[0086] When transistor 54 is turned on, a current corresponding to the gate potential of transistor 52 flows from wiring 45 to wiring 47, for example. Consequently, light-emitting element 60 emits light with a brightness corresponding to the gate potential of transistor 52. On the other hand, when transistor 54 is turned off, current does not flow through light-emitting element 60, thereby preventing light-emitting element 60 from emitting light.

[0087] An OS transistor is preferably used as transistor 54. As described above, an OS transistor has a higher field effect mobility than a transistor using amorphous silicon as a semiconductor layer. Therefore, using an OS transistor as transistor 54 allows for high-speed driving of the display device 30.

[0088] exist Figure 4A In the pixel circuit 40C shown in FIG. 1 , for example, a transistor 51 or a transistor 53 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, a transistor 52 or a transistor 54 may be used. Figure 1A and Figure 1BThe semiconductor device shown includes a transistor M2 having a long channel length among transistors.

[0089] Figure 4B The sub-pixel 23 shown includes a pixel circuit 40D and a light-emitting element 60. The pixel circuit 40D has a structure in which a transistor 54 is added to the pixel circuit 40B. That is, the pixel circuit 40D is a 4Tr1C type pixel circuit.

[0090] In the pixel circuit 40D, one of the source and drain of the transistor 54 is electrically connected to the other of the source and drain of the transistor 51, the gate of the transistor 52, and one electrode of the capacitor 57. The other of the source and drain of the transistor 54 is electrically connected to the wiring 49. The gate of the transistor 54 is electrically connected to the wiring 41c. Figure 4B In the case of the illustrated structure, the wiring 41 , which includes a wiring 41 a , a wiring 41 b , and a wiring 41 c , is provided in the display device 30 .

[0091] By turning on the transistor 54, the gate potential of the transistor 52 can be set to the potential of the wiring 49. Therefore, for example, current does not flow through the light emitting element 60, and the light emitting element 60 does not emit light.

[0092] exist Figure 4B In the pixel circuit 40D shown in FIG. 1 , for example, a transistor 51 or a transistor 54 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, a transistor 52 or a transistor 53 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length among transistors.

[0093] Figure 4C The sub-pixel 23 shown includes a pixel circuit 40E and a light-emitting element 60 .

[0094] The pixel circuit 40E includes a transistor 61, a transistor 62, a transistor 63, a transistor 64, a transistor 65, a transistor 66, a capacitor 67, and a capacitor 68. That is, the pixel circuit 40E is a 6Tr2C type pixel circuit.

[0095] In the pixel circuit 40E, one of the source and drain of the transistor 61 is electrically connected to the wiring 45. The other of the source and drain of the transistor 61 is electrically connected to one of the source and drain of the transistor 62. One of the source and drain of the transistor 62 is electrically connected to one of the source and drain of the transistor 63. The gate of the transistor 61 is electrically connected to the wiring 41d.

[0096] The other of the source and the drain of the transistor 62 is electrically connected to the gate of the transistor 63. The gate of the transistor 63 is electrically connected to one electrode of the capacitor 67. The gate of the transistor 62 is electrically connected to the wiring 41e.

[0097] One of the source and drain of transistor 64 is electrically connected to wiring 43. The other of the source and drain of transistor 64 is electrically connected to the other of the source and drain of transistor 63. The other of the source and drain of transistor 63 is electrically connected to one of the source and drain of transistor 65. The gate of transistor 64 is electrically connected to wiring 41f.

[0098] The other of the source and drain of transistor 65 is electrically connected to one of the source and drain of transistor 66. One of the source and drain of transistor 66 is electrically connected to the other electrode of capacitor 67. The other electrode of capacitor 67 is electrically connected to one electrode of capacitor 68. One electrode of capacitor 68 is electrically connected to one electrode of light-emitting element 60. The gate of transistor 65 is electrically connected to wiring 41g.

[0099] The other of the source and the drain of the transistor 66 is electrically connected to the wiring 48. The gate of the transistor 66 is electrically connected to the wiring 41e.

[0100] The other electrode of the capacitor 68 is electrically connected to the wiring 41 f . The other electrode of the light emitting element 60 is electrically connected to the wiring 47 .

[0101] The wiring 41d, wiring 41e, wiring 41f, and wiring 41g are electrically connected to the scanning line driving circuit 11. That is, the sub-pixel 23 included in the pixel 21 has Figure 4C In the case of the illustrated structure, the wiring 41 , namely, the wiring 41 d , the wiring 41 e , the wiring 41 f , and the wiring 41 g are provided in the display device 30 .

[0102] Transistors 61, 62, 64, 65, and 66 function as switches. Transistor 61 controls the conduction or non-conduction between wiring 45 and one of the source and drain of transistor 62 and one of the source and drain of transistor 63, depending on the potential of wiring 41d. Transistor 62 controls the conduction or non-conduction between the other of the source and drain of transistor 61 and one of the source and drain of transistor 63, and the gate of transistor 63 and one of the electrodes of capacitor 67, depending on the potential of wiring 41e. Transistor 64 controls the conduction or non-conduction between wiring 43 and the other of the source and drain of transistor 63 and one of the source and drain of transistor 65, depending on the potential of wiring 41f. Transistor 65 controls the conduction or non-conduction between the other of the source and drain of transistor 63 and the other of the source and drain of transistor 64, and one of the electrodes of light-emitting element 60, depending on the potential of wiring 41g. The transistor 66 has a function of controlling the conduction state or the non-conduction state between the wiring 48 and one electrode of the light emitting element 60 according to the potential of the wiring 41 e .

[0103] OS transistors are preferably used as transistors 61 to 66. For example, OS transistors have higher field-effect mobility than transistors using amorphous silicon as their semiconductor layer. Therefore, using OS transistors as transistors 61 to 66 allows for high-speed operation of the display device 30.

[0104] exist Figure 4C In the pixel circuit 40E shown in FIG. 1 , for example, transistor 61, transistor 62, transistor 63, transistor 64, or transistor 65 may be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 66, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length among transistors.

[0105] <Configuration Example of Storage Device> Figure 5A This is a block diagram illustrating an example structure of a memory device 70 in which a semiconductor device according to one embodiment of the present invention can be used. Memory device 70 includes a memory section 80, a word line driver circuit 71, a bit line driver circuit 73, and a power supply circuit 75. Memory section 80 includes a plurality of memory cells 81 arranged in a matrix. Note that power supply circuit 75 may also be provided external to memory device 70.

[0106] The word line drive circuit 71 is electrically connected to the memory cell 81 via the wiring 41. Figure 2ASimilarly to the display device 30 shown, the wiring 41 extends in the row direction of the matrix, for example. In the memory device 70, the wiring 41 is used as a word line.

[0107] The bit line driver circuit 73 is electrically connected to the memory cell 81 via the wiring 43. Figure 2A Similarly to the display device 30 shown, the wiring 43 extends in the column direction of the matrix. In the memory device 70, the wiring 43 is used as a bit line.

[0108] The power supply circuit 75 is electrically connected to the memory cells 81 via the wiring 45. For example, all the memory cells 81 may be electrically connected to the power supply circuit 75 via the same wiring 45. The wiring 45 serves as a power supply line.

[0109] The word line driver circuit 71 has the function of selecting the memory cells 81 to which data is written, row by row. Furthermore, the word line driver circuit 71 has the function of selecting the memory cells 81 from which data is read, row by row. Specifically, the word line driver circuit 71 outputs a signal to the wiring 41 to select the memory cells 81 to which data is written or the memory cells 81 from which data is read.

[0110] The bit line driver circuit 73 has the function of writing data to the memory cell 81 selected by the word line driver circuit 71 via the wiring 43. The bit line driver circuit 73 also has the function of amplifying the data outputted from the memory cell 81 to the wiring 43 and outputting it, for example, to the outside of the memory device 70, thereby reading the data held by the memory cell 81. Furthermore, the bit line driver circuit 73 has the function of precharging the wiring 43 before reading data from the memory cell 81.

[0111] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 45. The power supply circuit 75 has a function of generating a high potential or a low potential and supplying it to the wiring 45, for example.

[0112] Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E 81 is a circuit diagram showing a configuration example of the storage unit 81. Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E The storage units 81 shown are storage unit 81A, storage unit 81B, storage unit 81C, and storage unit 81D.

[0113] Figure 5B The memory cell 81A shown includes a transistor 51, a transistor 52, and a capacitor 57. That is, the memory cell 81A is a 2Tr1C type memory cell.

[0114] Memory cell 81A is electrically connected to wiring 41a and wiring 41h, which serve as wiring 41, and wiring 43a and wiring 43b, which serve as wiring 43. Specifically, one of the source and drain of transistor 51 is electrically connected to wiring 43a. The other of the source and drain of transistor 51 is electrically connected to one electrode of capacitor 57. One electrode of capacitor 57 is electrically connected to the gate of transistor 52. The gate of transistor 51 is electrically connected to wiring 41a. The other electrode of capacitor 57 is electrically connected to wiring 41h. One of the source and drain of transistor 52 is electrically connected to wiring 43b. The other of the source and drain of transistor 52 is electrically connected to wiring 45.

[0115] In memory cell 81A, when transistor 51 is turned on, data is written to memory cell 81A via wiring 43a. When transistor 51 is turned off, the written data is retained. Thus, in memory cell 81A, wiring 41a can be considered a write word line, and wiring 43a can be considered a write bit line. Furthermore, by controlling the potential of wiring 41h, the gate potential of transistor 52 changes due to capacitive coupling, thereby setting the potential of wiring 43b to a potential corresponding to the data retained in memory cell 81A. This allows bit line driver circuit 73 to read the data retained in memory cell 81A. Thus, in memory cell 81A, wiring 41h can be considered a read word line, and wiring 43b can be considered a read bit line.

[0116] Note that in the memory cell 81A, when an OS transistor is used as the transistor 51, the capacitor 57 may not be included. In this case, the memory cell 81A is a 2Tr0C type memory cell.

[0117] In the memory cell 81A, for example, the transistor 51 may be Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length. Note that the transistor M2 can also be used as the transistor 51, and the transistor M1 can also be used as the transistor 52.

[0118] Figure 5C The illustrated memory cell 81B is a modified example of the memory cell 81A, in which the other of the source and drain of the transistor 52 is electrically connected to the wiring 41h, and the other electrode of the capacitor 57 is electrically connected to the wiring 45. By controlling the potential of the other of the source and drain of the transistor 52 by the word line driver circuit 71, the memory cell 81B can output the data held in the memory cell 81B to the wiring 43b.

[0119] Note that in the memory cell 81B, when an OS transistor is used as the transistor 51, the capacitor 57 may not be included. In this case, the memory cell 81B is a 2Tr0C type memory cell.

[0120] In the memory cell 81B, for example, the transistor 51 may be Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length. Note that the transistor M2 can also be used as the transistor 51, and the transistor M1 can also be used as the transistor 52.

[0121] Figure 5D The memory cell 81C shown is a modified example of the memory cell 81B, and the memory cell 81C differs from the memory cell 81B in that the memory cell 81C includes a transistor 53. That is, the memory cell 81C is a 3Tr1C type memory cell.

[0122] Memory cell 81C is electrically connected to wiring 41a and wiring 41b, which are wiring 41. Specifically, the gate of transistor 53 is electrically connected to wiring 41b. In addition, one of the source and drain of transistor 52 is electrically connected to one of the source and drain of transistor 53. The other of the source and drain of transistor 52 is electrically connected to wiring 45. The other of the source and drain of transistor 53 is electrically connected to wiring 43b.

[0123] Transistor 53 functions as a switch, controlling the conductive state between one of the source and drain of transistor 52 and wiring 43b, depending on the potential of wiring 41b. By turning on transistor 53, the potential of wiring 43b is set to the potential corresponding to the data stored in memory cell 81C. This allows bit line driver circuit 73 to read the data stored in memory cell 81C. Thus, in memory cell 81C, wiring 41b can be said to function as a read word line.

[0124] In the memory cell 81C, for example, a transistor 51 or a transistor 53 can be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length. Note that the transistor M2 can also be used as the transistor 51 or the transistor 53, and the transistor M1 can also be used as the transistor 52.

[0125] Figure 5E The memory cell 81D shown is a modified example of the memory cell 81C and differs from the memory cell 81C in that it does not include the capacitor 57. That is, the memory cell 81D is a 3Tr0C type memory cell. In the memory cell 81D, the wiring 45 is electrically connected to the other of the source and the drain of the transistor 52.

[0126] For example, when the parasitic capacitance such as the gate capacitance of the transistor 52 is sufficiently large, data can be retained in the memory cell even without providing the capacitor 57 .

[0127] In the memory cell 81D, for example, a transistor 51 or a transistor 53 can be used. Figure 1A and Figure 1B The semiconductor device shown includes a transistor M1 having a short channel length. For example, as the transistor 52, Figure 1A and Figure 1B The semiconductor device shown includes a transistor M2 having a long channel length. Note that the transistor M2 can also be used as the transistor 51 or the transistor 53, and the transistor M1 can also be used as the transistor 52.

[0128] As the transistor 51 included in the memory cells 81A to 81D, an OS transistor is preferably used. As described above, the off-state current of the OS transistor is significantly small. Therefore, by using an OS transistor as the transistor 51, the charge stored in the capacitor 57 can be maintained for a long period of time. In addition, the gate potential of the transistor 52 can be maintained for a long period of time. Therefore, the data written to the memory cell 81 can be maintained for a long period of time, so the frequency of the refresh operation (rewriting data to the memory cell 81) can be reduced. As a result, the power consumption of the memory device 70 can be reduced.

[0129] Furthermore, OS transistors are preferably used for transistors 52 and 53. As described above, OS transistors have higher field-effect mobility than transistors using amorphous silicon as their semiconductor layer. Therefore, by using OS transistors as transistors 51 to 53, memory device 70 can be driven at high speed.

[0130] Memory cells 81A to 81D can be described as NOSRAM (registered trademark). NOSRAM stands for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM can read data without destroying it (non-destructive readout). Therefore, NOSRAM is suitable for computational processing that requires only a large number of repetitive data readouts.

[0131] Below, refer to Figures 6A to 42B A specific structural example of a semiconductor device according to one embodiment of the present invention will be described.

[0132] <Structure Example 1> Figure 6A A plan view of the semiconductor device 10 is shown. Figure 6B Shown along Figure 6A The cross-section of the dotted line A1-A2 is shown. Figure 6A A portion of the components of the semiconductor device 10 (such as the insulating layer) is omitted in the figure. Figure 6A Similarly, some components are omitted.

[0133] The semiconductor device 10 includes a transistor 100 and a transistor 200. The transistor 100 and the transistor 200 are both provided on a substrate 102. In the semiconductor device 10, the transistor 100 corresponds to Figure 1A and Figure 1B The transistor M1 in the transistor 200 is equivalent to Figure 1A and Figure 1B The transistor M2 in .

[0134] Transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Conductive layer 104 serves as a gate electrode. A portion of insulating layer 106 serves as a gate insulating layer. Conductive layer 112a serves as one of a source electrode and a drain electrode, and conductive layer 112b serves as the other of the source and drain electrodes. In semiconductor layer 108, the entire region overlapping the gate electrode with the gate insulating layer between the source and drain electrodes serves as a channel formation region. Furthermore, in semiconductor layer 108, the region in contact with the source electrode serves as a source region, and the region in contact with the drain electrode serves as a drain region.

[0135] Transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 202a, and a conductive layer 202b. Conductive layer 204 serves as a gate electrode. A portion of insulating layer 106 serves as a gate insulating layer. Conductive layer 202a serves as one of a source electrode and a drain electrode, and conductive layer 202b serves as the other of the source and drain electrodes. In semiconductor layer 208, the entire region overlapping the gate electrode with the gate insulating layer between the source and drain electrodes serves as a channel formation region. Furthermore, in semiconductor layer 208, the region in contact with the source electrode serves as a source region, and the region in contact with the drain electrode serves as a drain region.

[0136] A conductive layer 112a and a conductive layer 202a are provided on the substrate 102. The conductive layer 112a and the conductive layer 202a can be formed using the same material and process.

[0137] The insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c) is provided over the conductive layer 112a. Figure 6B In the embodiment, the insulating layer 110 has a three-layer stacked structure of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, but the insulating layer 110a and the insulating layer 110c may not be provided. The same applies to the other structural examples shown in this specification. A conductive layer 112b is provided on the insulating layer 110. The insulating layer 110 has a region sandwiched between the conductive layer 112a and the conductive layer 112b. The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. The insulating layer 110 has an opening 141 in the region overlapping with the conductive layer 112a. The conductive layer 112a is exposed in the opening 141. The conductive layer 112b has an opening 143 in the region overlapping with the conductive layer 112a. The opening 143 is provided in the region overlapping with the opening 141.

[0138] Semiconductor layer 108 is provided to cover openings 141 and 143. Semiconductor layer 108 has regions in contact with the top and side surfaces of conductive layer 112b, the side surfaces of insulating layer 110, and the top surface of conductive layer 112a. Semiconductor layer 108 is electrically connected to conductive layer 112a via openings 141 and 143. Semiconductor layer 108 has a shape that follows the top and side surfaces of conductive layer 112b, the side surfaces of insulating layer 110, and the top surface of conductive layer 112a.

[0139] Insulating layer 110a, insulating layer 110_1 on insulating layer 110a, insulating layer 110b on insulating layer 110_1, and insulating layer 110c on insulating layer 110b are provided on conductive layer 202a. Conductive layer 202b is provided on insulating layer 110c. Insulating layers 110a, 110_1, 110b, and 110c have a region sandwiched between conductive layer 202a and conductive layer 202b. Conductive layer 202a has a region overlapping conductive layer 202b via insulating layers 110a, 110_1, 110b, and 110c. Insulating layers 110a, 110_1, 110b, and 110c have openings 241 in the region overlapping conductive layer 202a. Conductive layer 202a is exposed in openings 241. Conductive layer 202 b has opening 243 in a region overlapping conductive layer 202 a . Opening 243 is provided in a region overlapping opening 241 .

[0140] Semiconductor layer 208 is provided to cover openings 241 and 243. Semiconductor layer 208 has regions in contact with the top and side surfaces of conductive layer 202b, the side surfaces of insulating layer 110c, the side surfaces of insulating layer 110b, the side surfaces of insulating layer 110_1, the side surfaces of insulating layer 110a, and the top surface of conductive layer 202a. Semiconductor layer 208 is electrically connected to conductive layer 202a via openings 241 and 243. Semiconductor layer 208 has a shape that extends along the top and side surfaces of conductive layer 202b, the side surfaces of insulating layer 110c, the side surfaces of insulating layer 110b, the side surfaces of insulating layer 110_1, the side surfaces of insulating layer 110a, and the top surface of conductive layer 202a.

[0141] The conductive layer 202b can be formed using the same material and process as the conductive layer 112b. The semiconductor layer 208 can be formed using the same material and process as the semiconductor layer 108.

[0142] The insulating layer 106, which serves as the gate insulating layer of the transistor 100, is provided to cover the opening 141 and the opening 143 via the semiconductor layer 108. Furthermore, the insulating layer 106, which also serves as the gate insulating layer of the transistor 200, is provided to cover the opening 241 and the opening 243 via the semiconductor layer 208. The insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the conductive layer 202b, and the insulating layer 110c. The insulating layer 106 has a region in contact with the top surface of the semiconductor layer 108, the side surfaces of the conductive layer 112b, the top surface of the semiconductor layer 208, the side surfaces of the conductive layer 202b, and the top surface of the insulating layer 110c. The insulating layer 106 has a shape that extends along the top surface of the insulating layer 110c, the side surfaces of the conductive layer 112b, the top surface of the semiconductor layer 108, the side surfaces of the conductive layer 202b, and the top surface of the semiconductor layer 208.

[0143] The conductive layer 104 serving as a gate electrode of the transistor 100 is provided in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 has a shape along the top surface of the insulating layer 106 in this region.

[0144] The conductive layer 204 serving as the gate electrode of the transistor 200 is provided in contact with the top surface of the insulating layer 106. The conductive layer 204 has a region overlapping with the semiconductor layer 208 via the insulating layer 106. The conductive layer 204 has a shape along the top surface of the insulating layer 106 in this region.

[0145] The conductive layer 204 can be formed using the same material and process as the conductive layer 104 .

[0146] Transistors 100 and 200 are so-called top-gate transistors, each including a gate electrode above semiconductor layer 108 and semiconductor layer 208. Furthermore, the bottom surfaces of semiconductor layer 108 (the surface facing substrate 102) and semiconductor layer 208 (the surface facing substrate 102) are in contact with the source electrode and drain electrode of transistor 100 and transistor 200, respectively. Therefore, transistors 100 and 200 can be said to be TGBC (Top Gate Bottom Contact) transistors.

[0147] In transistors 100 and 200, the source and drain electrodes are located at different heights relative to the substrate surface, so drain current flows in the vertical direction. Therefore, transistors 100 and 200 can be referred to as vertical transistors, vertical channel transistors, vertical channel transistors, or VFETs (Vertical Field Effect Transistors).

[0148] As described above, transistor 100 has insulating layers 110a, 110b, and 110c sandwiched between its source and drain electrodes, while transistor 200 has insulating layers 110a, 110_1, 110b, and 110c sandwiched between its source and drain electrodes. Therefore, it can be said that the channel length of transistor 200 is longer than that of transistor 100 by the thickness of insulating layer 110_1. Alternatively, it can be said that the channel length of transistor 100 is shorter than that of transistor 200 by the thickness of insulating layer 110_1.

[0149] The channel length of transistor 100 can be controlled by the thickness of the insulating layer (insulating layer 110a, insulating layer 110b, and insulating layer 110c) provided between conductive layer 112a and conductive layer 112b. Similarly, the channel length of transistor 200 can be controlled by the thickness of the insulating layer (insulating layer 110a, insulating layer 110_1, insulating layer 110b, and insulating layer 110c) provided between conductive layer 202a and conductive layer 202b. Therefore, a transistor having a channel length smaller than the limiting resolution of the exposure device used to manufacture the transistor can be manufactured with high precision. In addition, an extremely small channel length can be formed, thereby realizing a transistor with a large on-state current.

[0150] Furthermore, the channel length can be controlled simply by adjusting the thickness of the insulating layer between the source and drain electrodes of transistors 100 and 200. This allows for reduced characteristic variation between transistors 100 and 200 within the substrate plane when multiple transistors 100 and 200 are manufactured. Consequently, the operation of the semiconductor device including transistors 100 and 200 is stabilized, improving reliability. Furthermore, reduced characteristic variation increases circuit design freedom, allowing for a reduction in the operating voltage of the semiconductor device. Consequently, power consumption of the semiconductor device can be reduced.

[0151] As described above, the transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate by sharing some of the steps. For example, by using the transistor 100 as a transistor requiring a large on-state current and the transistor 200 as a transistor requiring high saturation, a high-performance semiconductor device 10 can be realized.

[0152] For example, when the semiconductor device 10 of one embodiment of the present invention is used in a display device, the transistor 100 can be used as a selection transistor in a pixel circuit included in the display device, and the transistor 200 can be used as a driving transistor in the pixel circuit included in the display device. In addition, the transistor 100 can be used as a transistor constituting a driving circuit (for example, a scanning line driving circuit or a signal line driving circuit) included in the display device, and the transistor 200 can be used as a transistor constituting a pixel circuit included in the display device. An example of a display device that can use a semiconductor device of one embodiment of the present invention is Figures 2A to 4C As described in the .

[0153] Note that in Figure 6A In the embodiment, the shapes of openings 141 and 143, as well as the shapes of openings 241 and 243, when viewed from above, are all circular, but one embodiment of the present invention is not limited thereto. The shapes of the openings when viewed from above can be, for example, circular or elliptical. Alternatively, the shapes of the openings when viewed from above can be polygonal, such as a triangle, a quadrangle (including a rectangle, a rhombus, or a square), or a pentagon, or these polygons can have rounded corners.

[0154] The detailed structures of the transistor 100 and the transistor 200 are described.

[0155] In the transistor 100, the end of the conductive layer 112b on the side of the opening 143 is preferably aligned with or approximately aligned with the end of the insulating layer 110c on the side of the opening 141. The shape of the opening 143 when viewed from a planar perspective can also be said to be aligned with or approximately aligned with the shape of the opening 141 when viewed from a planar perspective. Note that in this specification, etc., the end of the conductive layer 112b on the side of the opening 143 refers to the end of the bottom surface of the conductive layer 112b on the side of the opening 143. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 110c. The end of the insulating layer 110c on the side of the opening 141 refers to the end of the top surface of the insulating layer 110c on the side of the opening 141. The top surface of the insulating layer 110c refers to the surface on the side of the conductive layer 112b. In addition, the shape of the opening 143 when viewed from a planar perspective refers to the shape of the end of the bottom surface of the conductive layer 112b on the side of the opening 143. The shape of the opening 141 when viewed from a planar perspective refers to the shape of the top surface end portion of the insulating layer 110 c on the opening 141 side.

[0156] The opening 141 can be formed, for example, using a resist mask for forming the opening 143. Specifically, an insulating film to become the insulating layer 110, a conductive film to become the conductive layer 112b on the insulating film, and a resist mask on the conductive film are formed. After the opening 143 is formed in the conductive film to become the conductive layer 112b using the resist mask, the opening 141 is formed in the insulating film to become the insulating layer 110 using the same resist mask. This arrangement allows the ends of the opening 141 to coincide or substantially coincide with the ends of the opening 143. This structure simplifies the process.

[0157] The opening 141 may be formed after the opening 143 is formed, in a process different from that of the opening 143. There is no particular limitation on the order in which the openings 141 and 143 are formed. For example, after the opening 141 is formed in the insulating film that will become the insulating layer 110, a conductive film that will become the conductive layer 112b may be formed, and then the opening 143 may be formed in the conductive film.

[0158] Note that in the above description of the transistor 100 , the same description can be applied to the transistor 200 by replacing the conductive layer 112 b , the opening 143 , and the opening 141 with the conductive layer 202 b , the opening 243 , and the opening 241 , respectively.

[0159] Alternatively, the opening 143 and the opening 243 may be formed simultaneously in the same process. Alternatively, the opening 141 and the opening 241 may be formed simultaneously in the same process.

[0160] In the transistor 100, the end of the conductive layer 112b on the side of the opening 143 may not coincide with the end of the insulating layer 110c on the side of the opening 141. That is, the shape of the opening 143 when viewed from a planar surface may not coincide with the shape of the opening 141 when viewed from a planar surface. When viewed from a planar surface, the opening 143 preferably includes the opening 141. The end of the conductive layer 112b on the side of the opening 143 may also be located outside the end of the insulating layer 110c on the side of the opening 141. In this case, the semiconductor layer 108 has a region in contact with the top and side surfaces of the conductive layer 112b, the top and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a. By adopting such a structure, the step of the formed surface of the layer (for example, the semiconductor layer 108) formed on the conductive layer 112a, the insulating layer 110, and the conductive layer 112b can be reduced. Therefore, coverage of the layer formed over the conductive layer 112a, the insulating layer 110, and the conductive layer 112b can be improved, thereby suppressing occurrence of defects such as disconnection and voids in the layer.

[0161] The above contents can be applied to transistor 200 by replacing conductive layer 112b, opening 143, opening 141, semiconductor layer 108, and conductive layer 112a in transistor 100 with conductive layer 202b, opening 243, opening 241, semiconductor layer 208, and conductive layer 202a, respectively.

[0162] Note that in this embodiment, the openings 141 and the openings 143 are provided in the insulating layer 110 and the conductive layer 112b, respectively, and the semiconductor layer 108 is provided so as to cover the openings 141 and the openings 143. However, one embodiment of the present invention is not limited to this. The transistor 100 of one embodiment of the present invention only needs to have a first region in which the insulating layer 110 is provided on the conductive layer 112a and a second region in which the insulating layer 110 is not provided on the conductive layer 112a. In the transistor 100, the semiconductor layer 108 can be provided at the step generated by the first region and the second region. The insulating layer 106 can be provided on the semiconductor layer 108, and the conductive layer 104 can be provided so as to overlap with the semiconductor layer 108 via the insulating layer 106 (see Figures 21A to 23B ).

[0163] Similarly, in this embodiment, the openings 241 and the openings 243 are provided in the insulating layer 110 and the conductive layer 202b, respectively, and the semiconductor layer 208 is provided so as to cover the openings 241 and the openings 243. However, one embodiment of the present invention is not limited thereto. The transistor 200 of one embodiment of the present invention only needs to have a first region in which the insulating layer 110 is provided on the conductive layer 202a and a second region in which the insulating layer 110 is not provided on the conductive layer 202a. In the transistor 200, the semiconductor layer 208 can be provided at the step generated by the first region and the second region. The insulating layer 106 can be provided on the semiconductor layer 208, and the conductive layer 204 can be provided so as to overlap with the semiconductor layer 208 via the insulating layer 106 (see Figures 21A to 23B ).

[0164] In the transistor 100 , the semiconductor layer 108 preferably covers the end portion of the conductive layer 112 b on the opening 143 side. Figure 6B , etc., show a structure in which the end of semiconductor layer 108 is located on conductive layer 112b. The end of semiconductor layer 108 can also be said to be in contact with the top surface of conductive layer 112b. Alternatively, semiconductor layer 108 may extend to cover the end of conductive layer 112b that does not face opening 143. The end of semiconductor layer 108 may also be in contact with the top surface of insulating layer 110c.

[0165] The semiconductor layer 108 is provided in a manner covering the opening 141 and the opening 143. Figure 6B As shown in FIG. 1 , in the opening 141 , the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112 a .

[0166] The above contents can be applied to transistor 200 by replacing semiconductor layer 108, conductive layer 112b, opening 143, opening 141 and conductive layer 112a in transistor 100 with semiconductor layer 208, conductive layer 202b, opening 243, opening 241 and conductive layer 202a, respectively.

[0167] exist Figure 6B Although the semiconductor layer 108 and the semiconductor layer 208 both have a single-layer structure, one embodiment of the present invention is not limited thereto. The semiconductor layer 108 and the semiconductor layer 208 may both have a stacked-layer structure of two or more layers.

[0168] The insulating layer 106 is disposed on the semiconductor layer 108 and the semiconductor layer 208 .

[0169] The conductive layer 104 is provided so as to cover the opening 141 and the opening 143 via the insulating layer 106. The conductive layer 204 is provided so as to cover the opening 241 and the opening 243 via the insulating layer 106.

[0170] like Figure 6BAs shown in Figures 1 and 2, in the transistor 100, the conductive layer 104 has regions in the openings 141 and 143 that overlap with the semiconductor layer 108 via the insulating layer 106. Furthermore, the conductive layer 104 has regions that overlap with the conductive layer 112a and the conductive layer 112b via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 preferably covers the end portion of the conductive layer 112b on the side of the opening 143. By adopting this structure, the entire region of the semiconductor layer 108 that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode can be used as a channel formation region. Alternatively, the conductive layer 104 may extend to cover the end portion of the conductive layer 112b that does not face the opening 143. Alternatively, the conductive layer 104 may extend to cover the end portion of the semiconductor layer 108.

[0171] The above content can be applied to transistor 200 by replacing the conductive layer 104, opening 141, opening 143, semiconductor layer 108, conductive layer 112a and conductive layer 112b in transistor 100 with conductive layer 204, opening 241, opening 243, semiconductor layer 208, conductive layer 202a and conductive layer 202b respectively.

[0172] In transistor 100, conductive layer 112a, conductive layer 112b, and conductive layer 104 can all be used as wiring. Similarly, in transistor 200, conductive layer 202a, conductive layer 202b, and conductive layer 204 can all be used as wiring. Transistors 100 and 200 can be arranged in the region where these wirings overlap, thereby reducing the area occupied by transistors 100, transistor 200, and the wiring in the circuit including the wiring. Therefore, the area occupied by the circuit can be reduced to achieve a small semiconductor device. For example, when a semiconductor device 10 according to one embodiment of the present invention is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced to achieve a high-definition display device. In addition, when a semiconductor device 10 according to one embodiment of the present invention is used in a driver circuit of a display device (for example, a scan line driver circuit or a signal line driver circuit), the area occupied by the driver circuit can be reduced to achieve a display device with a narrow frame. In addition, when a semiconductor device 10 according to one embodiment of the present invention is used in a memory cell of a storage device, the area occupied by the memory cell can be reduced to achieve a micro storage device.

[0173] In the semiconductor device 10 according to one embodiment of the present invention, the conductive layers 112a and 202a, 112b and 202b, and the conductive layers 104 and 204, which also function as wiring, are provided in different layers. Therefore, wiring can be arranged in each layer, improving layout flexibility and reducing the circuit footprint.

[0174] Here, refer to Figure 7A and Figure 7B The channel length and channel width of the transistor 100 will be described. Figure 7A is a plan view of transistor 100 . Figure 7B yes Figure 6B An enlarged view of transistor 100 is shown.

[0175] Note that the description of the channel length and channel width of the transistor 100 shown below can also be applied to the transistor 200 , which is a vertical channel transistor like the transistor 100 .

[0176] In the semiconductor layer 108, the region in contact with the conductive layer 112a serves as one of the source region and the drain region, and the region in contact with the conductive layer 112b serves as the other of the source region and the drain region. Furthermore, in the semiconductor layer 108, the region between the source region and the drain region serves as a channel formation region.

[0177] The channel length of transistor 100 refers to the distance between the source region and the drain region. Figure 7B The dotted double arrow in FIG. 1 represents a channel length L100 of the transistor 100. The channel length L100 is the distance between the end of the semiconductor layer 108 in contact with the conductive layer 112a and the end of the semiconductor layer 108 in contact with the conductive layer 112b when viewed in cross section.

[0178] Here, the channel length L100 of transistor 100 corresponds to the length of the side surface of insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c) on the side of opening 141 when viewed in cross section. Specifically, channel length L100 is determined by the thickness T110 of insulating layer 110 and the angle θ110 formed between the side surface of insulating layer 110 on the side of opening 141 and the surface on which insulating layer 110 is formed (here, the top surface of conductive layer 112a). It is not affected by the performance of the exposure equipment used to manufacture the transistor. Therefore, channel length L100 can be set to a value smaller than the limiting resolution of the exposure equipment, enabling the realization of a micro-transistor. For example, the channel length L100 is preferably 0.010 μm or more and less than 3.0 μm, more preferably 0.050 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and 2.5 μm or less, more preferably 0.20 μm or more and 2.0 μm or less, more preferably 0.20 μm or more and 1.5 μm or less, more preferably 0.30 μm or more and 1.5 μm or less, more preferably 0.30 μm or more and 1.2 μm or less, more preferably 0.40 μm or more and 1.2 μm or less, more preferably 0.40 μm or more and 1.0 μm or less, more preferably 0.50 μm or more and 1.0 μm or less. Figure 7B In FIG. 1 , a double-arrow with a dot-dashed line indicates a thickness T110 of the insulating layer 110 .

[0179] By reducing the channel length L100, the on-state current of the transistor 100 can be increased. By using a transistor 100 with a small channel length L100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, when the semiconductor device 10 of one embodiment of the present invention is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced when the number of wirings increases, thereby suppressing display unevenness. In addition, since the area occupied by the circuit can be reduced, a display device with a narrow frame can be realized.

[0180] On the other hand, by increasing the channel length L100, transistor 100 can be made into a highly saturated transistor. Increasing the transistor's channel length improves the source-drain withstand voltage, allowing the use of transistors 100 with a large channel length L100 in circuits requiring high withstand voltages. Furthermore, for example, when transistors 100 with a large channel length L100 are used in display devices, their high saturation characteristics make them suitable as driver transistors in pixel circuits.

[0181] By adjusting the thickness T110 and the angle θ110 of the insulating layer 110 , the channel length L100 can be controlled.

[0182] The thickness T110 of the insulating layer 110 is preferably greater than or equal to 0.010 μm and less than 3.0 μm, greater than or equal to 0.050 μm and less than or equal to 2.5 μm, greater than or equal to 0.10 μm and less than or equal to 2.0 μm, greater than or equal to 0.15 μm and less than or equal to 1.5 μm, greater than or equal to 0.20 μm and less than or equal to 1.2 μm, greater than or equal to 0.30 μm and less than or equal to 1.0 μm, greater than or equal to 0.40 μm and less than or equal to 1.0 μm, or greater than or equal to 0.50 μm and less than or equal to 1.0 μm.

[0183] The side surface of the insulating layer 110 on the side of the opening 141 is preferably tapered. The angle θ110 formed by the side surface of the insulating layer 110 on the side of the opening 141 and the formed surface of the insulating layer 110 (here, the top surface of the conductive layer 112a) is preferably less than 90 degrees. By reducing the angle θ110, the coverage of the layer (e.g., the semiconductor layer 108) provided on the insulating layer 110 can be improved. However, in some cases, reducing the angle θ110 reduces the contact area between the semiconductor layer 108 and the conductive layer 112a, thereby increasing the contact resistance between the semiconductor layer 108 and the conductive layer 112a. The angle θ110 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and less than 85 degrees, 40 degrees or more and less than 80 degrees, 45 degrees or more and less than 80 degrees, 50 degrees or more and less than 80 degrees, 55 degrees or more and less than 80 degrees, 60 degrees or more and less than 80 degrees, 65 degrees or more and less than 80 degrees, or 70 degrees or more and less than 80 degrees. By setting the angle θ110 within the above range, coverage of layers (e.g., the semiconductor layer 108) formed over the conductive layer 112a and the insulating layer 110 can be improved, thereby suppressing defects such as disconnections and voids in the layers. Furthermore, the contact resistance between the semiconductor layer 108 and the conductive layer 112a can be reduced.

[0184] Note that in Figure 7B , etc., shows a configuration in which the side surface of the insulating layer 110 on the side of the opening 141 is a straight line when viewed in cross section, but one embodiment of the present invention is not limited thereto. The side surface of the insulating layer 110 on the side of the opening 141 may also be a curved line when viewed in cross section, or may include both straight and curved line regions.

[0185] Conductive layer 112b is preferably not provided within opening 141. Specifically, conductive layer 112b preferably does not include a region in contact with the side surface of insulating layer 110 on the side of opening 141. If conductive layer 112b is also provided inside opening 141, channel length L100 of transistor 100 becomes shorter than the length of the side surface of insulating layer 110 on the side of opening 141, making it difficult to control channel length L100. Therefore, it is preferable that the shape of opening 143 when viewed from above coincide with the shape of opening 141 when viewed from above, or that opening 143 includes opening 141 when viewed from above.

[0186] The channel width of the transistor 100 refers to the length of the channel formation region in the direction perpendicular to the channel length direction. In other words, it may also refer to the length of the source region or the length of the drain region in the direction perpendicular to the channel length direction. That is, the channel width refers to the length of the region where the semiconductor layer 108 contacts the conductive layer 112a or the length of the region where the semiconductor layer 108 contacts the conductive layer 112b in the direction perpendicular to the channel length direction. Here, the length of the region where the semiconductor layer 108 contacts the conductive layer 112b in the direction perpendicular to the channel length direction is used as the channel width of the transistor 100. Figure 7A and Figure 7B In FIG, the solid double-headed arrow indicates the channel width W100 of transistor 100. Channel width W100 is the length of the circumference of opening 143 when viewed from a planar perspective. Specifically, channel width W100 is the length of the bottom surface (the surface facing insulating layer 110) end of conductive layer 112b on the side of opening 143 when viewed from a planar perspective.

[0187] Note that in Figure 7A and Figure 7B In the embodiment of the present invention, the channel width of the transistor 100 is defined as the length of the bottom surface of the conductive layer 112 b on the side of the opening 143 (the surface on the side of the insulating layer 110) when viewed from a planar perspective, but the present invention is not limited to this. For example, the outer perimeter of the portion where the top surface of the conductive layer 112 a contacts the semiconductor layer 108 when viewed from a planar perspective may be defined as the channel width of the transistor 100. Alternatively, an intermediate value between the above two values ​​may be defined as the channel width of the transistor 100.

[0188] The channel width W100 is determined by the shape of the opening 143 when viewed from a plane. Figure 7A and Figure 7BIn FIG, a double-dot chain arrow indicates the width D143 of opening 143. Width D143 refers to the length of the short side of the smallest rectangle circumscribing opening 143 when viewed from above. When forming opening 143 using photolithography, width D143 of opening 143 is greater than the limiting resolution of the exposure apparatus. The width D143 is, for example, preferably greater than or equal to 0.01 μm and less than 5.0 μm, more preferably greater than or equal to 0.01 μm and less than 4.5 μm, more preferably greater than or equal to 0.01 μm and less than 4.0 μm, more preferably greater than or equal to 0.01 μm and less than 3.5 μm, more preferably greater than or equal to 0.01 μm and less than 3.0 μm, more preferably greater than or equal to 0.01 μm and 2.5 μm or less, more preferably greater than or equal to 0.01 μm and 2.0 μm or less, more preferably greater than or equal to 0.01 μm and 1.5 μm or less, more preferably greater than or equal to 0.30 μm and 1.5 μm or less, more preferably greater than or equal to 0.30 μm and 1.2 μm or less, more preferably greater than or equal to 0.40 μm and 1.2 μm or less, more preferably greater than or equal to 0.40 μm and 1.0 μm or less, more preferably greater than or equal to 0.50 μm and 1.0 μm or less. Note that when the shape of the opening 143 as viewed from above is circular, the width D143 corresponds to the diameter of the opening 143 , and the channel width W100 can be calculated as “D143×π”.

[0189] As described above, the channel length L100 of the transistor 100 can be set to a value smaller than the limiting resolution of the exposure device. On the other hand, by increasing the thickness of the insulating layer sandwiched by the source electrode and the drain electrode of the transistor 100, the channel length L100 of the transistor 100 can be set to a value greater than the limiting resolution of the exposure device. In this way, in a semiconductor device according to one embodiment of the present invention, by using a vertical channel transistor, the thickness of the insulating layer sandwiched by the source electrode and the drain electrode of the transistor can be adjusted to determine the channel length of the transistor. In addition, in a semiconductor device according to one embodiment of the present invention, by using two or more vertical channel transistors, the thickness of the insulating layer sandwiched by the source electrode and the drain electrode of the transistor is different within the substrate surface, and a transistor with a short channel length and a transistor with a long channel length can be manufactured separately within the substrate surface. For example, a transistor 100 with a short channel length and a transistor 200 with a long channel length can be manufactured separately within the substrate surface. Furthermore, by using the transistor 100 as a transistor requiring a large on-state current and the transistor 200 as a transistor requiring a high saturation characteristic, a high-performance semiconductor device 10 can be realized that utilizes the advantages of each transistor.

[0190] In the semiconductor device 10 according to one embodiment of the present invention, the transistor 100 and the transistor 200 having different channel lengths can be formed on the substrate 102 using a common process. Specifically, the conductive layer 112a and the conductive layer 202a can be formed using the same process. The conductive layer 112b and the conductive layer 202b can be formed using the same process. The semiconductor layer 108 and the semiconductor layer 208 can be formed using the same process. The conductive layer 104 and the conductive layer 204 can be formed using the same process. Consequently, the manufacturing cost of the semiconductor device 10 can be reduced.

[0191] The components included in the semiconductor device of this embodiment will be described below.

[0192] <Components of Semiconductor Devices> [Semiconductor layer 108, semiconductor layer 208] There are no particular limitations on the semiconductor materials that can be used for the semiconductor layers 108 and 208. For example, a single-material semiconductor or a compound semiconductor can be used. For example, silicon or germanium can be used as a single-material semiconductor. For example, gallium arsenide or silicon germanium can be used as a compound semiconductor. As a compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also called an oxide semiconductor) can be used. Note that these semiconductor materials may also contain impurities as dopants.

[0193] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layers 108 and 208. An amorphous semiconductor or a crystalline semiconductor (a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a partial crystalline region thereof) can be used. The use of a crystalline semiconductor is preferred because it can suppress degradation of transistor characteristics.

[0194] Silicon can be used for both the semiconductor layer 108 and the semiconductor layer 208. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS).

[0195] Transistors using amorphous silicon as their semiconductor layer can be formed on large glass substrates, enabling low-cost manufacturing. Transistors using polycrystalline silicon as their semiconductor layer have high field-effect mobility and are capable of high-speed operation. Furthermore, transistors using microcrystalline silicon as their semiconductor layer have higher field-effect mobility than transistors using amorphous silicon, enabling high-speed operation.

[0196] Semiconductor layer 108 and semiconductor layer 208 may also include a layered material that functions as a semiconductor. Layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together through bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0197] Examples of the layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing oxygen group elements (elements belonging to Group 16). In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0198] The semiconductor layer 108 and the semiconductor layer 208 preferably both contain a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a semi-metal element having a high bond energy with oxygen, for example, a metal element or a semi-metal element having a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. In this specification and the like, metal elements and semi-metal elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include semi-metal elements.

[0199] The semiconductor layer 108 and the semiconductor layer 208 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0200] Here, the composition of the metal oxide included in the semiconductor layer 108 and the semiconductor layer 208 has a significant influence on the electrical characteristics and reliability of the transistor 100 and the transistor 200 .

[0201] For example, by increasing the ratio of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, a transistor with high on-state current or high field-effect mobility can be realized. By using this transistor in a transistor requiring a large on-state current, a semiconductor device with excellent electrical characteristics can be realized.

[0202] The metal oxide may also replace In or contain one or more metal elements with a large periodic number in the periodic table in addition to In. There is a trend that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As such metal elements, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0203] The metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field-effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0204] When using an In-Zn oxide as the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a metal oxide in a range thereof, can be used.

[0205] When using an In-Sn oxide as the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a metal oxide in which the atomic ratio of the metal elements is approximately 1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a metal oxide in which the atomic ratio is approximately 1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1 can be used.

[0206] When an In-M-Zn oxide is used as a semiconductor layer, a metal oxide can be used in which the atomic number ratio of indium relative to the sum of the atomic numbers of all metal elements contained is higher than the atomic number ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic number ratio of zinc is higher than the atomic number ratio of element M. For example, the semiconductor layer can use metal element atomic ratios of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M: Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10 or metal oxides thereabouts.

[0207] Note that when multiple metal elements are included as element M, the sum of the atomic number ratios of the metal elements may be the atomic number ratio of element M. For example, when an In-Ga-Al-Zn oxide containing gallium and aluminum as element M is used, the sum of the atomic number ratio of gallium and the atomic number ratio of aluminum may be the atomic number ratio of element M. Furthermore, the atomic number ratio of indium, element M, and zinc is preferably within the above-mentioned range. For example, when an In-Ga-Sn-Zn oxide containing gallium and tin as element M is used, the sum of the atomic number ratio of gallium and the atomic number ratio of tin may be the atomic number ratio of element M. Furthermore, the atomic number ratio of indium, element M, and zinc is preferably within the above-mentioned range.

[0208] It is preferred to use a metal oxide in which the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used as the semiconductor layer, the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is preferably within the above range.

[0209] In this specification, etc., the ratio of the number of indium atoms to the total number of atoms of all metal elements contained may be described as the indium content. The same applies to other metal elements.

[0210] As an analysis of the composition of the metal oxide, for example, energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. In addition, analysis can also be performed by combining multiple methods mentioned above. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0211] In this specification, etc., the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, a composition having an atomic ratio of In:M:Zn = 4:2:3 or a composition thereof includes the following: when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, a composition having an atomic ratio of In:M:Zn = 5:1:6 or a composition thereof includes the following: when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, a composition having an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof includes the following: when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0212] The metal oxide can be formed using sputtering or atomic layer deposition (ALD) as appropriate. Note that when forming the metal oxide using sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of zinc in the target. Specifically, the atomic ratio of zinc may be between approximately 40% and 90% of the atomic ratio of zinc in the target.

[0213] Here, the reliability of transistors is explained. As one of the indicators for evaluating the reliability of transistors, there is a GBT (Gate Bias Temperature) stress test in which an electric field is applied to the gate and maintained at a high temperature. Among them, the test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential and maintained at a high temperature is called the PBTS (Positive Bias Temperature Stress) test, and the test in which a negative potential (negative bias) is applied to the gate and maintained at a high temperature is called the NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and the NBTS test performed under the state of irradiation with light are called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0214] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (current flowing). Therefore, the fluctuation of the threshold voltage in the PBTS test is one of the important factors to be considered as an indicator of transistor reliability.

[0215] By using a metal oxide that contains no gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability when a positive bias is applied can be realized. In other words, a transistor with minimal fluctuation in threshold voltage during PBTS testing can be realized. Furthermore, when using a metal oxide containing gallium, the gallium content is preferably lower than the indium content. This allows for the realization of a highly reliable transistor.

[0216] One of the causes of threshold voltage fluctuations during the PBTS test is carrier capture (in this case, electrons) due to defect states at or near the interface between the semiconductor layer and the gate insulating layer. A higher defect state density increases the amount of carrier capture due to defect states, leading to more significant degradation during the PBTS test. Reducing the gallium content in the region of the semiconductor layer in contact with the gate insulating layer can suppress the generation of these defect states.

[0217] The reason why the threshold voltage fluctuation in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content as the semiconductor layer can be considered as follows. Gallium contained in the metal oxide is more likely to absorb oxygen than other metal elements (such as indium or zinc). Therefore, it can be speculated that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated by bonding between gallium and excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are captured at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage fluctuates.

[0218] More specifically, when using an In-Ga-Zn oxide as the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer. More preferably, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium is used. In other words, a metal oxide in which the atomic ratio of the metal elements satisfies In>Ga and Zn>Ga is used for the semiconductor layer.

[0219] For example, as a semiconductor layer, the atomic ratio of metal elements that can be used is In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga a:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereabouts.

[0220] As the semiconductor layer, it is preferable to use a metal oxide in which the ratio of the number of atoms of gallium to the sum of the number of atoms of all metal elements contained is higher than 0 atomic % and is less than 50 atomic %, preferably greater than 0.1 atomic % and less than 40 atomic %, more preferably greater than 0.1 atomic % and less than 35 atomic %, more preferably greater than 0.1 atomic % and less than 30 atomic %, more preferably greater than 0.1 atomic % and less than 25 atomic %, more preferably greater than 0.1 atomic % and less than 20 atomic %, more preferably greater than 0.1 atomic % and less than 15 atomic %, more preferably greater than 0.1 atomic % and less than 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be realized. Note that by containing gallium in the metal oxide, it is less likely to generate oxygen vacancies (V O : Oxygen Vacancy) effect.

[0221] As a semiconductor layer, a metal oxide that does not contain gallium can also be used. For example, In-Zn oxide can be used for the semiconductor layer. In this case, when the ratio of the number of atoms of indium to the sum of the number of atoms of all metal elements contained in the metal oxide is increased, the field effect mobility of the transistor can be improved. On the other hand, when the ratio of the number of atoms of zinc to the sum of the number of atoms of all metal elements contained in the metal oxide is increased, the metal oxide has high crystallinity, so the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved. In addition, as a semiconductor layer, a metal oxide that does not contain gallium and zinc, such as indium oxide, can also be used. By using a metal oxide that does not contain gallium, the variation of the threshold voltage in the PBTS test can be made extremely small, in particular.

[0222] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic ratio of the metal elements of In:Zn=2:3, In:Zn=4:1, or a ratio thereof can be used.

[0223] Note that although gallium is used as an example in the description, the present invention can also be applied to the case where element M is used instead of gallium. A metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M is preferably used as the semiconductor layer. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M is preferably used.

[0224] By using a metal oxide with a low content of element M as a semiconductor layer, a transistor with high reliability under forward bias can be realized. By using this transistor as a transistor that needs to have high reliability under forward bias, a highly reliable semiconductor device can be realized.

[0225] Next, the reliability of transistors with respect to light will be described.

[0226] Light incident on a transistor can sometimes cause changes in its electrical characteristics. It is particularly desirable that transistors used in areas where light is likely to enter exhibit minimal changes in their electrical characteristics under light irradiation and exhibit high reliability against light. Reliability against light can be evaluated, for example, by measuring the fluctuation in threshold voltage during NBTIS testing.

[0227] By increasing the content of the element M in the metal oxide, a transistor with high reliability against light can be realized. In other words, a transistor with a small fluctuation in threshold voltage during NBTIS testing can be realized. Specifically, a metal oxide in which the atomic number ratio of the element M is greater than or equal to the atomic number ratio of indium has a larger band gap, which can reduce the fluctuation in threshold voltage during NBTIS testing of the transistor. The band gap of the metal oxide included in the semiconductor layer is preferably 2.0 eV or greater, more preferably 2.5 eV or greater, more preferably 3.0 eV or greater, more preferably 3.2 eV or greater, more preferably 3.3 eV or greater, more preferably 3.4 eV or greater, and more preferably 3.5 eV or greater.

[0228] For example, as the semiconductor layer, a metal oxide having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4 or a ratio thereof can be used.

[0229] As a semiconductor layer, the following metal oxide can be particularly appropriately used: the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained is greater than 20 atomic % and less than 70 atomic %, preferably greater than 30 atomic % and less than 70 atomic %, more preferably greater than 30 atomic % and less than 60 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50 atomic % and less than 60 atomic %.

[0230] A transistor with high reliability against light can be realized by using a metal oxide with a high content of element M as a semiconductor layer. By using this transistor in a transistor that needs to have high reliability against light, a semiconductor device with high reliability can be realized.

[0231] By increasing the content of element M, the oxygen vacancies (V O ) is formed. Therefore, by using a metal oxide with a high content of element M as a semiconductor layer, oxygen vacancies (V O ) is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation in the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0232] Alternatively, increasing the zinc content to produce a highly crystalline metal oxide can suppress the diffusion of impurities in the metal oxide. Therefore, using a metal oxide with a high zinc content as a semiconductor layer can suppress variations in the electrical characteristics of the transistor, thereby improving reliability.

[0233] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0234] The semiconductor layer may also have a stacked structure comprising two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may also have the same or substantially the same composition. By employing a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0235] The two or more metal oxide layers included in the semiconductor layer may have different compositions. For example, a stacked structure may suitably include a first metal oxide layer having an atomic ratio of In:M:Zn = 1:3:4 or a composition thereof, and a second metal oxide layer having an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof disposed on the first metal oxide layer. Furthermore, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure may include any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark).

[0236] Furthermore, the two or more metal oxide layers included in the semiconductor layer may have a stacked structure of a metal oxide layer that does not contain the element M and a metal oxide layer that contains the element M. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn = 4:0:1 [atomic ratio] or approximately thereabouts and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or approximately thereabouts provided on the first metal oxide layer may be suitably used. Note that a structure in which a metal oxide layer that does not contain the element M is stacked on a metal oxide layer that contains the element M may also be employed.

[0237] A crystalline metal oxide layer is preferably used as the semiconductor layer. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline structure, or a nanocrystalline (nc) structure can be used. Using a crystalline metal oxide layer as the semiconductor layer can reduce the defect state density in the semiconductor layer, thereby achieving a highly reliable semiconductor device.

[0238] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, using a metal oxide layer with low crystallinity can realize a transistor capable of passing a large current.

[0239] When depositing a metal oxide layer using a sputtering method, a higher substrate temperature (stage temperature) during formation results in a more crystalline metal oxide layer. Furthermore, a higher flow rate ratio of oxygen gas relative to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) results in a more crystalline metal oxide layer.

[0240] The semiconductor layer may also have a stacked structure of two or more metal oxide layers having different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may include a region having higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may include a region having lower crystallinity than the first metal oxide layer. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. For example, by using the same sputtering target and making the oxygen flow ratio different, a stacked structure of two or more metal oxide layers having different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other.

[0241] The thickness of semiconductor layer 108 and semiconductor layer 208 is preferably greater than 3 nm and less than 100 nm, more preferably greater than 5 nm and less than 100 nm, more preferably greater than 10 nm and less than 100 nm, more preferably greater than 10 nm and less than 70 nm, more preferably greater than 15 nm and less than 70 nm, more preferably greater than 15 nm and less than 50 nm, more preferably greater than 20 nm and less than 50 nm, more preferably greater than 20 nm and less than 40 nm, more preferably greater than 25 nm and less than 40 nm.

[0242] The substrate temperature during formation of the semiconductor layers 108 and 208 is preferably room temperature (25° C.) or higher and 200° C. or lower, more preferably room temperature or higher and 130° C. or lower. By adopting a substrate temperature within this range, warping or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0243] Here, oxygen vacancies that may be formed in the semiconductor layer will be described.

[0244] When an oxide semiconductor is used as a semiconductor layer, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies (V O ). In addition, sometimes hydrogen enters the defect in the oxygen vacancy (hereinafter referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes due to the bonding of a portion of hydrogen to the oxygen bonded to the metal atom, electrons as carriers are generated. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, because the hydrogen in the oxide semiconductor is easily moved due to heat, electric field, etc., when the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0245] VO H can be used as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, evaluation is sometimes performed based on carrier concentration rather than donor concentration. Therefore, in this specification, etc., as a parameter of an oxide semiconductor, instead of donor concentration, the carrier concentration in a state where no electric field is applied is sometimes used. In other words, the "carrier concentration" described in this specification, etc. may sometimes be referred to as the "donor concentration."

[0246] Therefore, when an oxide semiconductor is used as a semiconductor layer, it is preferable to minimize the V O H to make it high purity intrinsic or substantially high purity intrinsic. In order to obtain this V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities (e.g., water and hydrogen) in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to repair oxygen vacancies (V O ). By placing oxygen vacancies (V O ), V O Oxide semiconductors with sufficiently reduced H and impurities are used in the channel formation region of transistors to provide stable electrical characteristics. Note that oxygen may be supplied to the oxide semiconductor to repair oxygen vacancies (V O ) is recorded as oxidation treatment.

[0247] When an oxide semiconductor is used as the semiconductor layer, the carrier concentration of the oxide semiconductor in the region serving as the channel formation region is preferably 1×10 18 cm -3 Below, more preferably less than 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , more preferably less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the region serving as the channel formation region is not particularly limited, and can be set to, for example, 1×10 -9 cm -3 .

[0248] The higher the resistance of the channel formation region in the state where no channel is formed, the better. For example, the sheet resistance value of the channel formation region is preferably 1×10 9 Ω / □ or more, more preferably 5×10 9 Ω / □ or more, more preferably 1×10 10 Ω / □ or more.

[0249] Since the resistance of the channel formation region in the state where no channel is formed is as high as possible, there is no need to set an upper limit. However, when setting an upper limit, for example, the sheet resistance of the channel formation region is preferably 1×10 9 Ω / □ or more and 1×10 12 Ω / □ or less, more preferably 5×10 9 Ω / □ or more and 1×10 12 Ω / □ or less, more preferably 1×10 10 Ω / □ or more and 1×10 12 Ω / □ or less.

[0250] Compared to transistors using amorphous silicon as a semiconductor layer, transistors using oxide semiconductors as a semiconductor layer (hereinafter referred to as OS transistors) have a very high field-effect mobility. In addition, the leakage current between the source and drain of the OS transistor in the off state (also known as the off-state current) is extremely low, which can maintain the charge stored in the capacitor connected in series with the transistor for a long time. In addition, by using OS transistors in semiconductor devices, the power consumption of the semiconductor device can be reduced.

[0251] A semiconductor device according to one embodiment of the present invention can be used in a display device, for example. When increasing the brightness of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To this end, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because the source-drain withstand voltage of an OS transistor is higher than that of a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be increased, thereby improving the brightness of the light-emitting device. For example, when Figure 6A and Figure 6B When the semiconductor device 10 shown is used in a display device, a transistor 200 having a long channel length and a high source-drain voltage can be appropriately used as a driver transistor included in a pixel circuit. Alternatively, a transistor 100 having a short channel length can be used as a driver transistor included in a pixel circuit. In this case, the current flowing through the light-emitting device can be increased even if the source-drain voltage is not high.

[0252] When the transistor operates in the saturation region, the OS transistor can make the change in the source-drain current smaller in response to the change in the gate-source voltage than the Si transistor. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the current flowing between the source and the drain can be determined in detail according to the change in the gate-source voltage, so the amount of current flowing through the light-emitting device can be controlled. As a result, the number of grayscales of the pixel circuit can be increased. For example, when the Figure 6A and Figure 6B When the semiconductor device 10 shown is used in a display device, the transistor 200 having a long channel length and a high saturation characteristic can be suitably used as a driving transistor included in a pixel circuit.

[0253] Regarding the saturation characteristics of the current flowing when the transistor operates in the saturation region, compared to the Si transistor, the OS transistor can make a stable current (saturation current) flow even if the source-drain voltage is gradually increased. Therefore, by using the OS transistor as a driving transistor, a stable current can flow through the light-emitting device even if, for example, the current-voltage characteristics of the light-emitting device deviate. That is, when the OS transistor operates in the saturation region, even if the source-drain voltage is increased, the source-drain current remains almost unchanged, so the luminous brightness of the light-emitting device can be stabilized. For example, when the OS transistor is used as a driving transistor, a stable current can flow through the light-emitting device. Figure 6A and Figure 6B When the semiconductor device 10 shown is used in a display device, the transistor 200 having a long channel length and a high saturation characteristic can be suitably used as a driving transistor included in a pixel circuit.

[0254] As described above, by using an OS transistor as a drive transistor included in a pixel circuit, “suppression of black blur,” “increase in emission luminance,” “multi-gradation,” “suppression of emission luminance variation,” and the like can be achieved.

[0255] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits for flat-panel detectors of X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0256] [Insulation layer 110, insulation layer 110_1] An inorganic insulating material or an organic insulating material can be used as the insulating layer 110 (the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c). The insulating layer 110 may have a stacked-layer structure of an inorganic insulating material and an organic insulating material.

[0257] An inorganic insulating material can be used as appropriate for the insulating layer 110. As the inorganic insulating material, one or more of oxides, oxynitrides, oxynitrides, and nitrides can be used. As the insulating layer 110, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon oxynitride, and aluminum nitride can be used.

[0258] Note that in this specification and other documents, "oxynitride" refers to a material containing more oxygen than nitrogen. "Oxynitride" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0259] For example, oxygen and nitrogen content can be analyzed using secondary ion mass spectrometry (SIMS) or XPS. When the target element content is high (e.g., 0.5 atomic% or higher or 1 atomic% or higher), XPS analysis is preferred. On the other hand, when the target element content is low (e.g., 0.5 atomic% or lower or 1 atomic% or lower), SIMS analysis is preferred. When comparing elemental contents, a combined analysis using both SIMS and XPS is more preferred.

[0260] The insulating layer 110 may also have a stacked structure of two or more layers. Figure 6B Insulating layer 110 has a stacked structure comprising insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. The insulating layers 110a, 110b, and 110c can all use the materials described above for insulating layer 110. Note that insulating layers 110a, 110b, and 110c can be made of the same material or different materials. Insulating layers 110a, 110b, and 110c can also have a stacked structure of two or more layers.

[0261] The thickness of insulating layer 110b can be greater than that of insulating layer 110a. The thickness of insulating layer 110b can be greater than that of insulating layer 110c. The deposition rate of insulating layer 110b is preferably fast. In particular, when the thickness of insulating layer 110b is large, the deposition rate of insulating layer 110b is preferably fast. By increasing the deposition rate of insulating layer 110b, productivity can be improved. For example, increasing the power used during the formation of insulating layer 110b can increase the deposition rate.

[0262] The insulating layer 110b may also have a stacked structure of two or more layers. For example, when the insulating layer 110b is thick, the stress in the insulating layer 110b is high, sometimes causing the substrate to warp. By forming the insulating layer 110b in multiple layers, it is sometimes possible to suppress process problems caused by stress. Note that in cross-sectional transmission electron microscopy (TEM) images, etc., the boundaries between the layers constituting the insulating layer 110b are sometimes unclear.

[0263] The stress of the insulating layer 110b is preferably low. When the insulating layer 110b is thick, the stress of the insulating layer 110b is high, which may cause substrate warping. By reducing the stress of the insulating layer 110b, problems in the process caused by stress, such as substrate warping, can be suppressed.

[0264] The insulating layer 110a and the insulating layer 110c are used as barrier films to suppress the escape of gas from the insulating layer 110b. The insulating layer 110a and the insulating layer 110c are preferably made of a material in which gas does not diffuse easily. The insulating layer 110a and the insulating layer 110c preferably have a region with a higher film density than the insulating layer 110b. By increasing the film density of the insulating layer 110a and the insulating layer 110c, the barrier property against impurities (for example, water and hydrogen) can be improved. In addition, the film density of the insulating layer 110a and the insulating layer 110c can also be different. As the insulating layer 110a and the insulating layer 110c, for example, a material containing more nitrogen than the insulating layer 110b can be used. By increasing the nitrogen content of the insulating layer 110a and the insulating layer 110c, the barrier property against impurities can be improved. The nitrogen content of the insulating layer 110a and the insulating layer 110c can also be different.

[0265] The insulating layer 110a and the insulating layer 110c only need to have a thickness sufficient to serve as a barrier film for suppressing the release of gas from the insulating layer 110b, and may be thinner than the insulating layer 110b. The thicknesses of the insulating layer 110a and the insulating layer 110c may also be different. The deposition rate of the insulating layer 110a and the insulating layer 110c is preferably slower than the deposition rate of the insulating layer 110b. Note that by slowing down the deposition rate of the insulating layer 110a and the insulating layer 110c, the film density is increased, thereby improving the barrier property against impurities. Similarly, by increasing the substrate temperature during the deposition of the insulating layer 110a and the insulating layer 110c, the film density is increased, thereby improving the barrier property against impurities.

[0266] The film density can be evaluated, for example, using Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). In addition, the difference in film density can sometimes be evaluated using a cross-sectional TEM image. In TEM observation, when the film density is high, the transmitted electron (TE) image is dark (dark), and when the film density is low, the transmitted electron (TE) image is light (bright). Therefore, in the transmitted electron (TE) image, the insulating layer 110a and the insulating layer 110c sometimes appear as dark (dark) images compared to the insulating layer 110b. Note that even if the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c use the same material, the film density is different, so sometimes these boundaries can be observed with different contrast in the cross-sectional TEM image.

[0267] The difference in nitrogen content among the insulating layers 110a, 110b, and 110c can be confirmed using, for example, EDX. For example, when silicon nitride is used for the insulating layer 110a and silicon oxynitride is used for the insulating layer 110b, the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110a is higher than the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110b. When silicon nitride is used for the insulating layer 110c and silicon oxynitride is used for the insulating layer 110b, the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110c is higher than the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110b. Note that in EDX, the peak of a certain element refers to the point where the count of the element reaches a maximum value in a spectrum in which the horizontal axis represents the energy of the characteristic X-ray and the vertical axis represents the count (detection value) of the characteristic X-ray. Alternatively, the difference in nitrogen content can be confirmed using the count at the energy of the characteristic X-ray inherent to the element as the ratio of the nitrogen count to the silicon count. For example, silicon can be counted at 1.739 keV (Si-Kα), and nitrogen can be counted at 0.392 keV (N-Kα). The ratio of nitrogen counts to silicon counts in insulating layer 110a is higher than the ratio of nitrogen counts to silicon counts in insulating layer 110b. The ratio of nitrogen counts to silicon counts in insulating layer 110c is higher than the ratio of nitrogen counts to silicon counts in insulating layer 110b.

[0268] Insulating layer 110a and insulating layer 110c may have regions where the hydrogen concentration is higher than that of insulating layer 110b. The difference in hydrogen concentration among insulating layer 110a, insulating layer 110b, and insulating layer 110c can be evaluated using, for example, secondary ion mass spectrometry (SIMS).

[0269] Here, the insulating layer 110 (the insulating layer 110 a , the insulating layer 110 b , and the insulating layer 110 c ) will be specifically described, taking a structure in which a metal oxide is used as a semiconductor layer of a transistor as an example.

[0270] When an oxide semiconductor is used as the semiconductor layer, an inorganic insulating material can be appropriately used as the insulating layer 110 a , the insulating layer 110 b , and the insulating layer 110 c .

[0271] The insulating layer 110b is preferably made of oxide or oxynitride. A film that releases oxygen by heating is preferably used as the insulating layer 110b. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 110b.

[0272] Oxygen is released from the insulating layer 110b, and oxygen can be supplied from the insulating layer 110b to the semiconductor layer. By supplying oxygen from the insulating layer 110b to the semiconductor layer, especially to the channel formation region of the semiconductor layer, oxygen vacancies (V O ) and V OH, a transistor exhibiting excellent electrical characteristics and high reliability can be realized. The insulating layer 110b preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 110b, oxygen can be easily diffused into the insulating layer 110b, allowing efficient oxygen supply from the insulating layer 110b to the semiconductor layer. Note that other treatments for supplying oxygen to the semiconductor layer include heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.

[0273] Oxygen vacancies in the channel formation region of the transistor (V O ) and V O In particular, when the channel length is short, the oxygen vacancies (V O ) and V O H has a greater impact on the electrical characteristics and reliability of the transistor. For example, sometimes V O H diffuses from the source region or drain region into the channel formation region, increasing the carrier concentration in the channel formation region, causing the threshold voltage of the transistor to fluctuate or the reliability to decrease. The shorter the channel length, the lower the V O The greater the impact of H diffusion on the electrical characteristics and reliability of the transistor, the greater the effect. By supplying oxygen from the insulating layer 110b to the semiconductor layer, especially to the channel formation region of the semiconductor layer, oxygen vacancies (V O ) and V O H. Therefore, a transistor with a short channel length that exhibits good electrical characteristics and high reliability can be realized.

[0274] It is preferable that the amount of impurities (eg, water and hydrogen) released from the insulating layer 110b itself is small. Since the amount of impurities released from the insulating layer 110b is small, diffusion of the impurities into the semiconductor layer can be suppressed, thereby realizing a transistor with good electrical characteristics and high reliability.

[0275] The insulating layer 110b can appropriately use silicon oxide or silicon oxynitride formed by PECVD, for example. In this case, it is preferable to use a mixed gas of a silicon-containing gas and an oxygen-containing gas as the source gas. As the silicon-containing gas, for example, any one or more of silane, disilane, trisilane and fluorinated silane can be used. As the oxygen-containing gas, for example, any one or more of oxygen (O2), ozone (O3), nitrous oxide (N2O), nitric oxide (NO) and nitrogen dioxide (NO2) can be used. Note that by increasing the power when forming the insulating layer 110b, the amount of impurities (for example, water and hydrogen) released from the insulating layer 110b can be reduced.

[0276] The insulating layers 110a and 110c are preferably not easily permeable to oxygen. The insulating layers 110a and 110c function as barrier films that prevent oxygen from escaping from the insulating layer 110b. Furthermore, the insulating layers 110a and 110c are preferably not easily permeable to hydrogen. The insulating layers 110a and 110c function as barrier films that prevent hydrogen from diffusing from the outside of the transistor into the semiconductor layer. The film density of the insulating layers 110a and 110c is preferably high. Increasing the film density of the insulating layers 110a and 110c improves the barrier properties to oxygen and hydrogen. The film density of the insulating layers 110a and 110c is preferably higher than that of the insulating layer 110b. When silicon oxide or silicon oxynitride is used as the insulating layer 110b, silicon nitride, silicon oxynitride, or aluminum oxide, for example, can be appropriately used as the insulating layers 110a and 110c. Insulating layer 110a and insulating layer 110c preferably have a region containing a higher nitrogen content than insulating layer 110b. For example, insulating layer 110a and insulating layer 110c can be made of a material containing a higher nitrogen content than insulating layer 110b. Nitride or nitride oxide is preferably used as insulating layer 110a and insulating layer 110c. Silicon nitride or silicon oxynitride can be used as appropriate for insulating layer 110a and insulating layer 110c, for example.

[0277] When oxygen in the insulating layer 110b diffuses upward from a region of the insulating layer 110b that is not in contact with the semiconductor layer (for example, the semiconductor layer 108), the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer may be reduced. By providing the insulating layer 110c on the insulating layer 110b, it is possible to suppress the diffusion of oxygen in the insulating layer 110b from a region of the insulating layer 110b that is not in contact with the semiconductor layer to the upper side. Similarly, by providing the insulating layer 110a below the insulating layer 110b, it is possible to suppress the diffusion of oxygen in the insulating layer 110b from a region of the insulating layer 110b that is not in contact with the semiconductor layer to the lower side. Therefore, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer is increased, and thus the oxygen vacancies (V O ) and V O H. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0278] For example, sometimes the conductive layer 112a and the conductive layer 112b are oxidized due to oxygen in the insulating layer 110b in the transistor 100, so that the resistance of the conductive layer increases. In addition, sometimes the conductive layer 112a and the conductive layer 112b are oxidized due to oxygen in the insulating layer 110b, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer (semiconductor layer 108) is reduced. By providing the insulating layer 110a between the insulating layer 110b and the conductive layer 112a, the oxidation of the conductive layer 112a and the increase in resistance can be suppressed. Similarly, by providing the insulating layer 110c between the insulating layer 110b and the conductive layer 112b, the oxidation of the conductive layer 112b and the increase in resistance can be suppressed. At the same time, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer is increased, and the oxygen vacancies (V O ) and V O H, thereby achieving a transistor exhibiting good electrical characteristics and high reliability.

[0279] When hydrogen diffuses into the semiconductor layer, it reacts with oxygen atoms in the oxide semiconductor to form water, sometimes forming oxygen vacancies (V O ). Furthermore, V O H, sometimes the carrier concentration becomes high. By providing the insulating layer 110a and the insulating layer 110c, the oxygen vacancies (V O ) and V O H, thereby achieving a transistor exhibiting good electrical characteristics and high reliability.

[0280] The insulating layer 110a and the insulating layer 110c preferably have a thickness sufficient to function as a barrier film for oxygen and hydrogen. When the thickness of the insulating layer 110a and the insulating layer 110c is small, their function as a barrier film may be reduced. On the other hand, when the thickness of the insulating layer 110a and the insulating layer 110c is large, the region of the semiconductor layer (e.g., semiconductor layer 108) in contact with the insulating layer 110b becomes narrower, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer may be reduced. The thickness of the insulating layer 110a and the insulating layer 110c may also be thinner than that of the insulating layer 110b. The thickness of the insulating layer 110a and the insulating layer 110c is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 70 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 10 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, and more preferably 20 nm or more and 40 nm or less. By setting the thickness of the insulating layer 110a and the insulating layer 110c within the above range, the oxygen vacancies (V O ) and V O H, and thus a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0281] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layers 110a and 110c themselves is small. Since the amount of impurities released from the insulating layers 110a and 110c is small, diffusion of these impurities into the semiconductor layer can be suppressed, thereby achieving a transistor with good electrical characteristics and high reliability.

[0282] By reducing the release of impurities (e.g., water and hydrogen) from insulating layer 110a and insulating layer 110c, the semiconductor layer in contact with insulating layer 110a and the semiconductor layer in contact with insulating layer 110c can also be used as channel formation regions. Furthermore, when insulating layer 110a is made of a material that releases impurities (e.g., water and hydrogen), the semiconductor layer in contact with insulating layer 110a can be used as a source region or a drain region. The same applies to insulating layer 110c.

[0283] Since oxygen is supplied from the insulating layer 110b to the semiconductor layer, oxygen vacancies (V O ) and V O H is reduced. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0284] Oxygen may be released from the semiconductor layer due to heat applied in the process after forming the semiconductor layer. However, since oxygen is supplied from the insulating layer 110 to the semiconductor layer, oxygen vacancies (V O ) and V O H increases. Furthermore, the degree of freedom in the processing temperature can be increased in the steps after the semiconductor layer is formed. Specifically, the processing temperature can also be increased in the steps after the semiconductor layer is formed. As a result, a transistor with excellent electrical characteristics and high reliability can be realized.

[0285] Furthermore, one or more of the insulating layer 110a and the insulating layer 110c may not be provided. Furthermore, both the insulating layer 110a and the insulating layer 110c may not be provided.

[0286] The insulating layer 110_1 can use the same material as that used for the insulating layer 110b. Figure 6B The insulating layer 110_1 is shown as having a single-layer structure in the drawings, but one embodiment of the present invention is not limited thereto. The insulating layer 110_1 may have a stacked-layer structure of two or more layers.

[0287] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 202a, conductive layer 202b, conductive layer 204] The conductive layers 112a, 112b, 104, 202a, 202b, and 204, which serve as source, drain, or gate electrodes, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or alloys containing one or more of the foregoing metals. A low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be suitably used for the conductive layers 112a, 112b, 104, 202a, 202b, and 204. In particular, copper and aluminum are preferred due to their advantages in mass productivity.

[0288] A metal oxide film (also referred to as an oxide conductor) can be used for the conductive layers 112a, 112b, 104, 202a, 202b, and 204. Examples of the oxide conductor (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0289] Here, we will explain oxide conductors (OCs). For example, oxygen vacancies form in a metal oxide that exhibits semiconductor properties. Hydrogen is added to these oxygen vacancies, creating donor levels near the conduction band. This results in increased conductivity, making the metal oxide a conductor. Metal oxides that can function as conductors are called oxide conductors.

[0290] The conductive layers 112a, 112b, 104, 202a, 202b, and 204 may have a stacked-layer structure including a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. The use of a conductive film containing a metal or alloy can reduce wiring resistance.

[0291] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive layers 112a, 112b, 104, 202a, 202b, and 204. The use of a Cu-X alloy film allows processing using a wet etching process, thereby reducing manufacturing costs.

[0292] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 202b, and the conductive layer 204 can all use the same material or different materials.

[0293] Here, the conductive layers 112a, 112b, 202a, and 202b are specifically described by taking a structure in which metal oxides are used as the semiconductor layers 108 and 208 as an example.

[0294] When an oxide semiconductor is used as the semiconductor layer 108 and the semiconductor layer 208, the conductive layers 112a and 112b and the conductive layers 202a and 202b may be oxidized by oxygen in the semiconductor layers 108 and 208, thereby increasing the resistance. In addition, the conductive layers 112a and 112b and the conductive layers 202a and 202b may be oxidized by oxygen in the insulating layer 110b and the like, thereby increasing the resistance. In addition, the conductive layers 112a and 112b and the conductive layers 202a and 202b may be oxidized by oxygen in the semiconductor layers 108 and 208, thereby increasing the resistance. O Sometimes, the conductive layers 112a and 112b and the conductive layers 202a and 202b are oxidized by oxygen in the insulating layer 110b and the like, and the amount of oxygen supplied from the insulating layer 110b and the like to the semiconductor layers 108 and 208 is reduced.

[0295] In each of the transistor 100 and the transistor 200, sometimes V O H diffuses from the source and drain regions into the channel formation region, increasing the carrier concentration in the channel formation region, causing the threshold voltage of transistors 100 and 200 to fluctuate or reduce reliability. O The greater the impact of H diffusion on the electrical characteristics and reliability of the transistor. Therefore, as the conductive layers 112a and 112b having a region in contact with the semiconductor layer 108, and the conductive layers 202a and 202b having a region in contact with the semiconductor layer 208, it is preferable to use a material that is not easily oxidized. As the conductive layers 112a and 112b, and the conductive layers 202a and 202b, it is preferable to use an oxide conductor. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be used appropriately. As the conductive layers 112a and 112b, and the conductive layers 202a and 202b, a nitride conductor can also be used. As nitride conductors, tantalum nitride and titanium nitride can be cited. The conductive layers 112a and 112b, and the conductive layers 202a and 202b can also have a stacked structure of the above materials. Note that the conductive layers 112a and 112b can also use the same material or different materials. The conductive layer 202a and the conductive layer 202b may be made of the same material or different materials.

[0296] By using a material that is not easily oxidized for the conductive layers 112a and 112b and the conductive layers 202a and 202b, an increase in resistance due to oxidation of oxygen in the semiconductor layer 108, oxygen in the semiconductor layer 208, or oxygen in the insulating layer 110b and the like can be suppressed. In addition, oxygen vacancies (V O ) is suppressed while the amount of oxygen supplied from the insulating layer 110b and the like to the semiconductor layer 108 and the semiconductor layer 208 is increased. Therefore, the oxygen vacancies (V O ) and V O H, thereby achieving the transistor 100 and the transistor 200 having good electrical characteristics and high reliability.

[0297] As the conductive layer 112a serving as one of the source electrode and the drain electrode of the transistor 100 and the conductive layer 202a serving as one of the source electrode and the drain electrode of the transistor 200, one or more of an oxide conductor and a nitride conductor can be appropriately used. In addition, the conductive layer 112a and the conductive layer 202a can have a two-layer stacked structure, in which the above-mentioned materials can be used as the first layer, and a material lower than the first layer can be used as the second layer. For example, one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above-mentioned metals can be appropriately used for the second layer. Specifically, when the conductive layer 112a and the conductive layer 202a have a two-layer stacked structure, In-Sn-Si oxide (ITSO) can be appropriately used as the first layer, and tungsten can be appropriately used as the second layer.

[0298] Note that the structure of the conductive layers 112a and 202a can be determined based on the desired wiring resistance of the conductive layers 112a and 202a. For example, when the wiring (conductive layers 112a and 202a) is short and a high wiring resistance is required, the conductive layers 112a and 202a may have a single-layer structure using a material that is not easily oxidized. On the other hand, when the wiring (conductive layers 112a and 202a) is long and a low wiring resistance is required, a stacked structure of a material that is not easily oxidized and a low-resistance material is preferably used for the conductive layers 112a and 202a.

[0299] For example, in transistor 100, conductive layer 112a has a stacked-layer structure of a first conductive layer and a second conductive layer overlying the first conductive layer, with a portion of the second conductive layer removed to provide a region exposing the first conductive layer. Alternatively, a structure may be employed in which the first conductive layer is in contact with semiconductor layer 108 in this region. Similarly, in transistor 200, conductive layer 202a has a stacked-layer structure of a first conductive layer and a second conductive layer overlying the first conductive layer, with a portion of the second conductive layer removed to provide a region exposing the first conductive layer. Alternatively, a structure may be employed in which the first conductive layer is in contact with semiconductor layer 208 in this region. Note that the structures of conductive layer 112a and conductive layer 202a can also be applied to other conductive layers.

[0300] [Insulation layer 106] The insulating layer 106 serving as the gate insulating layer of the transistor 100 and the transistor 200 preferably has a low defect density. When the defect density of the insulating layer 106 is low, the transistor 100 and the transistor 200 can exhibit good electrical characteristics. Furthermore, the insulating layer 106 preferably has a high dielectric strength voltage. The high dielectric strength voltage of the insulating layer 106 can achieve highly reliable transistors 100 and 200.

[0301] The insulating layer 106 can be made of, for example, one or more of an insulating oxide, oxynitride, oxynitride, and nitride. The insulating layer 106 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 106 can be a single layer or a stacked layer. For example, the insulating layer 106 can have a stacked structure of oxides and nitrides.

[0302] Note that in a micro transistor, when the thickness of the gate insulating layer is thin, leakage current sometimes increases. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to achieve a lower voltage when the transistor is operating while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0303] It is preferable that a small amount of impurities (for example, water and hydrogen) be released from the insulating layer 106 itself. Since a small amount of impurities are released from the insulating layer 106, diffusion of impurities into the semiconductor layers 108 and 208 can be suppressed, thereby achieving the transistors 100 and 200 having good electrical characteristics and high reliability.

[0304] Since the insulating layer 106 is formed on the semiconductor layer 108 and the semiconductor layer 208, it is preferably formed under conditions that minimize damage to the semiconductor layers 108 and 208. For example, it is preferably formed under conditions with a sufficiently slow deposition speed (also referred to as a deposition rate). For example, when forming the insulating layer 106 using PECVD, forming the insulating layer under low power conditions can minimize damage to the semiconductor layers 108 and 208.

[0305] Here, the insulating layer 106 will be specifically described by taking a structure in which the semiconductor layer 108 and the semiconductor layer 208 are made of metal oxide as an example.

[0306] In order to improve the interface properties between the insulating layer 106 and the semiconductor layer 108, and between the insulating layer 106 and the semiconductor layer 208, an oxide or an oxynitride is preferably used on at least the side of the insulating layer 106 that contacts the semiconductor layer 108 and the semiconductor layer 208. For example, one or more of silicon oxide and silicon oxynitride can be suitably used as the insulating layer 106. Furthermore, a film that releases oxygen upon heating is more preferably used as the insulating layer 106.

[0307] Note that the insulating layer 106 may have a stacked-layer structure. The insulating layer 106 may have a stacked-layer structure of an oxide film in contact with the semiconductor layers 108 and 208, and a nitride film in contact with the conductive layers 104 and 204. For example, one or more of silicon oxide and silicon oxynitride can be suitably used as the oxide film. For example, silicon nitride can be suitably used as the nitride film.

[0308] [Substrate 102] While the material of the substrate 102 is not particularly limited, it must at least have heat resistance sufficient to withstand subsequent heat treatment. For example, the substrate 102 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate. Alternatively, a substrate having a semiconductor element provided thereon may be used as the substrate 102. Note that the semiconductor substrate and the insulating substrate may be circular or angular in shape.

[0309] A flexible substrate may be used as substrate 102, and transistors 100 and 200 may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between substrate 102 and transistors 100 and 200. The release layer may be used when a portion or all of a semiconductor device is fabricated on the release layer and then separated from substrate 102 and transferred to another substrate. In this case, transistors 100 and 200 may be transferred to a substrate with low heat resistance or a flexible substrate.

[0310] Notice, Figure 6B , etc., illustrate that in the transistor 100, the thickness of the conductive layer 112 a in the region in contact with the semiconductor layer 108 is equal to or substantially equal to the thickness of the region in contact with the semiconductor layer 108. However, one embodiment of the present invention is not limited to this. The thickness of the conductive layer 112 a in the region in contact with the semiconductor layer 108 may be thinner than the thickness of the region in contact with the semiconductor layer 108.

[0311] same, Figure 6B , etc., illustrate that in the transistor 200, the thickness of the conductive layer 202a in the region in contact with the semiconductor layer 208 is equal to or substantially equal to the thickness of the region in contact with the semiconductor layer 208. However, one embodiment of the present invention is not limited to this. The thickness of the conductive layer 202a in the region in contact with the semiconductor layer 208 may be thinner than the thickness of the region in contact with the semiconductor layer 208.

[0312] The above is the description of the components.

[0313] The following describes a configuration example of a semiconductor device having a partially different configuration from that of the aforementioned <Configuration Example 1>. The description of portions overlapping with those of the aforementioned <Configuration Example 1> may be omitted. In the following drawings, portions having the same functions as those of the aforementioned <Configuration Example 1> are hatched with the same hatching, and may not be assigned reference numerals.

[0314] <Structure Example 2> Figure 8A A plan view of the semiconductor device 10A is shown. Figure 8B Shown along Figure 8A A cross-sectional view along the dashed line A1-A2 is shown.

[0315] The semiconductor device 10A includes a transistor 100A and a transistor 200A. The difference between the transistor 100A and the transistor 100 included in the semiconductor device 10 shown in <Structural Example 1> is that the insulating layer sandwiched by the conductive layer 112a and the conductive layer 112b has a four-layer stacked structure, which includes, in addition to the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, an insulating layer 110e on the insulating layer 110c. In addition, the difference between the transistor 200A and the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> is that the insulating layer used as the insulating layer sandwiched by the conductive layer 202a and the conductive layer 202b has a five-layer stacked structure, which includes, in addition to the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, an insulating layer 110d on the insulating layer 110c, and an insulating layer 110e on the insulating layer 110d. Note that in Figure 8BIn the embodiment, the insulating layer 110a, the insulating layer 110c, and the insulating layer 110e may not be provided. The same applies to the other structural examples described in this specification.

[0316] In addition, if Figure 8B As shown, in transistor 100A, the end of the conductive layer 112b extends to the outside of the transistor 100 (the side opposite to the opening 143), and the end is located on a five-layer stack of insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d and insulating layer 110e.

[0317] In semiconductor device 10A, insulating layer 110d has the function of supplying oxygen to semiconductor layer 208. Therefore, insulating layer 110d can be formed using the same material as insulating layer 110b described above. Furthermore, insulating layer 110e has the function of suppressing the infiltration of impurities (e.g., water or hydrogen) from above insulating layer 110d into insulating layer 110d and preventing oxygen in insulating layer 110d from being released above insulating layer 110d. Therefore, insulating layer 110e can be formed using the same material as insulating layers 110a and 110c described above.

[0318] In the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1>, Figure 6B As shown, in the oxygen supplying insulating layer (i.e., insulating layer 110_1 and insulating layer 110b) sandwiched between conductive layer 202a and conductive layer 202b, the first insulating layer 110_1 is formed into an island shape, and a second insulating layer 110b is formed on the island-shaped insulating layer 110_1.

[0319] On the other hand, in the transistor 200A included in the semiconductor device 10A, as shown in FIG. Figure 8B As shown, in the insulating layers (i.e., insulating layers 110b and 110d) that supply oxygen to the conductive layers 202a and 202b, a structure is provided in which the second insulating layer 110d is formed in an island shape on the first insulating layer 110b formed on the substrate 102.

[0320] That is, the first insulating layer of the two insulating layers for supplying oxygen in the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> is processed into an island shape, and on the other hand, the second insulating layer of the two insulating layers for supplying oxygen in the transistor 200A included in the semiconductor device 10A is processed into an island shape.

[0321] Thus, in a semiconductor device according to one embodiment of the present invention, by processing any layer of the insulating layer (oxygen supplying insulating layer) in a stacked structure sandwiched between the source and drain electrodes of the vertical channel transistor into an island shape, the channel length of the vertical channel transistor can be adjusted. This allows the channel lengths of two or more transistors included in the semiconductor device to differ from each other. Furthermore, in Embodiment 2, details of an example method for manufacturing the semiconductor device 10 and semiconductor device 10A shown in <Structural Example 1> are described.

[0322] Regarding the transistors 100A and 200A included in the semiconductor device 10A, except for the above-mentioned differences, reference can be made to the description of the transistors 100 and 200 included in the semiconductor device 10 shown in <Structural Example 1>, and thus detailed description thereof is omitted.

[0323] The semiconductor device 10A can also enjoy the same effects as the semiconductor device 10 shown in <Structural Example 1>.

[0324] <Structure Example 3> Figure 9A A plan view of the semiconductor device 10B is shown. Figure 9B Shown along Figure 9A A cross-sectional view along the dashed line A1-A2 is shown.

[0325] Semiconductor device 10B includes transistor 100A and transistor 200B. The above description of transistor 100A can be referred to. Transistor 200B differs from transistor 200 included in semiconductor device 10 shown in <Structural Example 1> in that it has a six-layer stacked structure comprising an insulating layer 110a, an insulating layer 110_1 on insulating layer 110a, an insulating layer 110_1 on insulating layer 110_1, an insulating layer 110c on insulating layer 110b, an insulating layer 110d on insulating layer 110c, and an insulating layer 110e on insulating layer 110d, as an insulating layer sandwiched between conductive layers 202a and 202b.

[0326] In the transistor 200B included in the semiconductor device 10B, as shown in FIG. Figure 9B As shown, in the insulating layers (i.e., insulating layers 110_1, 110b, and 110d) that supply oxygen to the conductive layers 202a and 202b, the first insulating layer 110_1 is formed into an island shape, the second insulating layer 110b is formed on the island-shaped insulating layer 110_1, and a third insulating layer 110d formed into an island shape is formed on the insulating layer 110b.

[0327] That is, the transistor 200B included in the semiconductor device 10B can be said to be a combination of the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> (see Figure 6B ) and the transistor 200A included in the semiconductor device 10A shown in <Structural Example 2> (refer to Figure 8B Therefore, the transistor 200B included in the semiconductor device 10B includes three insulating layers (the insulating layer 110_1 , the insulating layer 110b , and the insulating layer 110d ) capable of supplying oxygen to the semiconductor layer 208 .

[0328] Regarding the transistor 200B included in the semiconductor device 10B, except for the above-mentioned differences, reference can be made to the description of the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> and the transistor 200A included in the semiconductor device 10A shown in <Structural Example 2>, and therefore detailed description thereof is omitted.

[0329] In the transistor 200B included in the semiconductor device 10B, the thickness of the insulating layer sandwiched between the source and drain electrodes is thicker and the channel length is longer than that of the transistor 200 included in the semiconductor device 10 and the transistor 200A included in the semiconductor device 10A. Therefore, the semiconductor device 10B is suitably used in circuits requiring high saturation performance and a high source-drain withstand voltage.

[0330] <Structure Example 4> Figure 10A A plan view of a semiconductor device 10C is shown. Figure 10B Shown along Figure 10A A cross-sectional view along the dashed line A1-A2 is shown.

[0331] Semiconductor device 10C includes transistor 100 and transistor 200C. The above description of transistor 100 can be referred to. Transistor 200C differs from transistor 200 included in semiconductor device 10 shown in <Structural Example 1> in that the insulating layer sandwiched between conductive layer 202a and conductive layer 202b has a three-layer stacked structure (insulating layer 110a, insulating layer 110b, and insulating layer 110c). In transistors 100 and 200C, insulating layer 110b is the only insulating layer that supplies oxygen to the semiconductor layer.

[0332] like Figure 10B As shown, the transistor 100 included in the semiconductor device 10C is provided on an island-shaped insulating layer 107 formed on a substrate 102. In the semiconductor device 10C, the insulating layer 110a is provided so as to cover a portion of the top surface of the substrate 102, the side surfaces of the insulating layer 107, a portion of the top surface and side surfaces of the conductive layer 112a, and a portion of the top surface and side surfaces of the conductive layer 202a.

[0333] In addition, if Figure 10B As shown, the conductive layer 112b serving as the other of the source electrode or the drain electrode of the transistor 100 and the conductive layer 202b serving as the other of the source electrode or the drain electrode of the transistor 200C included in the semiconductor device 10C are provided on the insulating layer 110c in a manner with substantially uniform height.

[0334] Therefore, the channel length of the transistor 100 included in the semiconductor device 10C (i.e., the thickness of the insulating layer 110a, the insulating layer 110b and the insulating layer 110c in the region sandwiched by the conductive layer 112a and the conductive layer 112b) is shorter than the channel length of the transistor 200C (i.e., the thickness of the insulating layer 110a, the insulating layer 110b and the insulating layer 110c in the region sandwiched by the conductive layer 202a and the conductive layer 202b) by the thickness of the insulating layer 107.

[0335] Thus, in the semiconductor device according to one embodiment of the present invention, by providing an island-shaped insulating layer on a substrate and forming a plurality of vertical channel transistors on the substrate having the island-shaped insulating layer, transistors with different channel lengths can be formed simultaneously. Note that details of an example method for manufacturing the semiconductor device 10C are described in Embodiment 2.

[0336] Regarding the transistor 200C included in the semiconductor device 10C, except for the above-mentioned differences, reference can be made to the description of the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1>, and thus detailed description thereof is omitted.

[0337] The semiconductor device 10C can also enjoy the same effects as the semiconductor device 10 shown in <Structural Example 1>.

[0338] <Structure Example 5> Figure 11A A plan view of a semiconductor device 10D is shown. Figure 11B Shown along Figure 11A A cross-sectional view along the dashed line A1-A2 is shown.

[0339] Semiconductor device 10D includes transistor 100 and transistor 200D. The above description of transistor 100 can be referred to. Transistor 200D differs from transistor 200 included in semiconductor device 10 shown in <Structural Example 1> in that the insulating layer sandwiched between conductive layer 202a and conductive layer 202b has a five-layer stacked structure (insulating layer 110a, insulating layer 110_1, insulating layer 110_2, insulating layer 110b, and insulating layer 110c).

[0340] like Figure 11BAs shown, the transistor 200D included in the semiconductor device 10D includes an insulating layer 110a between the conductive layer 202a and the conductive layer 202b, an insulating layer 110_1 formed in an island shape on the insulating layer 110a, an insulating layer 110_2 formed in an island shape covering the insulating layer 110_1, an insulating layer 110b formed on the insulating layer 110_2, and an insulating layer 110c formed on the insulating layer 110b.

[0341] In semiconductor device 10D, insulating layer 110_2 has the function of supplying oxygen to semiconductor layer 208. Therefore, insulating layer 110_2 can be formed using the same material as insulating layer 110_1 and insulating layer 110_2 described above. As a result, transistor 200D included in semiconductor device 10D includes three insulating layers (insulating layer 110_1, insulating layer 110_2, and insulating layer 110_1) that can supply oxygen to semiconductor layer 208.

[0342] Regarding the transistor 200D included in the semiconductor device 10D, except for the above-mentioned differences, reference can be made to the description of the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1>, and thus detailed description thereof is omitted.

[0343] In the transistor 200D included in the semiconductor device 10D, the thickness of the insulating layer sandwiched between the source and drain electrodes is thicker, and the channel length is longer, compared to the transistor 200 included in the semiconductor device 10. Therefore, the semiconductor device 10D is suitably used in circuits requiring high saturation performance and a high source-drain withstand voltage.

[0344] <Structure Example 6> Figure 12 A cross-sectional view showing a modified example of the semiconductor device 10 shown in <Structural Example 1>.

[0345] The semiconductor device 10 may have a structure including three or more vertical channel transistors having different channel lengths. Figure 12 The semiconductor device 10 is shown except Figure 6B The structure shown includes a transistor 300 in addition to the transistor 100 and the transistor 200 .

[0346] about Figure 12 For the transistor 100 and the transistor 200 included in the semiconductor device 10 shown, reference can be made to the above description.

[0347] Figure 12The transistor 300 included in the semiconductor device 10 shown includes a conductive layer 304, an insulating layer 106, a semiconductor layer 308, a conductive layer 302a, and a conductive layer 302b. The conductive layer 304 serves as a gate electrode. A portion of the insulating layer 106 serves as a gate insulating layer. The conductive layer 302a serves as one of a source electrode and a drain electrode, while the conductive layer 302b serves as the other. In the semiconductor layer 308, the entire region overlapping the gate electrode with the gate insulating layer between the source and drain electrodes serves as a channel formation region. Furthermore, in the semiconductor layer 308, the region in contact with the source electrode serves as a source region, and the region in contact with the drain electrode serves as a drain region.

[0348] The conductive layer 302a is provided in a region different from the conductive layer 112a and the conductive layer 202a on the substrate 102. The conductive layer 302a can be formed using the same material and process as those of the conductive layer 112a and the conductive layer 202a.

[0349] On conductive layer 302a are provided insulating layer 110a, insulating layer 210_1 on insulating layer 110a, insulating layer 210_2 on insulating layer 210_1, insulating layer 110b on insulating layer 210_2, and insulating layer 110c on insulating layer 110b. Conductive layer 302b is provided on insulating layer 110c. Insulating layers 110a, 210_1, 210_2, 110b, and 110c have regions sandwiched between conductive layer 302a and conductive layer 302b. Conductive layer 302a has regions overlapping with conductive layer 302b via insulating layers 110a, 210_1, 210_2, 110b, and 110c. Insulating layer 110a, insulating layer 210_1, insulating layer 210_2, insulating layer 110b, and insulating layer 110c have openings 341 in regions overlapping with conductive layer 302a. Conductive layer 302a is exposed in opening 341. Conductive layer 302b has openings 343 in regions overlapping with conductive layer 302a. Opening 343 is provided in a region overlapping with opening 341.

[0350] In transistor 300, the insulating layers that supply oxygen to semiconductor layer 308 include three layers: insulating layer 210_1, insulating layer 210_2, and insulating layer 110b. Therefore, insulating layer 210_1 and insulating layer 210_2 can be formed using the same materials as insulating layer 110b and insulating layer 110_1. Note that insulating layer 210_2 can be formed using the same process as insulating layer 110_1.

[0351] Semiconductor layer 308 is provided to cover openings 341 and 343. Semiconductor layer 308 has regions in contact with the top and side surfaces of conductive layer 302b, the side surfaces of insulating layer 110c, the side surfaces of insulating layer 110b, the side surfaces of insulating layer 210_2, the side surfaces of insulating layer 210_1, the side surfaces of insulating layer 110a, and the top surface of conductive layer 302a. Semiconductor layer 308 is electrically connected to conductive layer 302a through openings 341 and 343. Semiconductor layer 308 has a shape that extends along the top and side surfaces of conductive layer 302b, the side surfaces of insulating layer 110c, the side surfaces of insulating layer 110b, the side surfaces of insulating layer 210_2, the side surfaces of insulating layer 210_1, the side surfaces of insulating layer 110a, and the top surface of conductive layer 302a.

[0352] Note that the conductive layer 302b can be formed using the same material and process as the conductive layer 112b and the conductive layer 202b. In addition, the semiconductor layer 308 can be formed using the same material and process as the semiconductor layer 108 and the semiconductor layer 208.

[0353] The insulating layer 106, which serves as a gate insulating layer for the transistor 300, is provided to cover the openings 341 and 343 via the semiconductor layer 308. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the conductive layer 202b, the semiconductor layer 308, the conductive layer 302b, and the insulating layer 110c. The insulating layer 106 has a region in contact with the top surface of the semiconductor layer 108, the side surfaces of the conductive layer 112b, the top surface of the semiconductor layer 208, the side surfaces of the conductive layer 202b, the top surface of the semiconductor layer 308, the side surfaces of the conductive layer 302b, and the top surface of the insulating layer 110c. The insulating layer 106 has a shape that extends along the top surface of the insulating layer 110c, the side surfaces of the conductive layer 112b, the top surface of the semiconductor layer 108, the side surfaces of the conductive layer 202b, the top surface of the semiconductor layer 208, the side surfaces of the conductive layer 302b, and the top surface of the semiconductor layer 308.

[0354] The conductive layer 304 serving as the gate electrode of the transistor 300 is provided in contact with the top surface of the insulating layer 106. The conductive layer 304 has a region overlapping with the semiconductor layer 308 via the insulating layer 106. The conductive layer 304 has a shape along the top surface of the insulating layer 106 in this region.

[0355] Note that the conductive layer 304 can be formed using the same material and process as the conductive layer 104 and the conductive layer 204 .

[0356] like Figure 12 As in the semiconductor device 10 shown in FIG. 1 , when three transistors with different channel lengths are included, the output voltage is higher than when two transistors are included (see FIG. 1 ). Figure 6B), the types of characteristics of transistors included in one semiconductor device can be increased. Note that the number of transistors included in the semiconductor device 10 may be four or more.

[0357] <Structure Example 7> Figure 13 A cross-sectional view showing a modified example of the semiconductor device 10 shown in <Structural Example 1> which is different from <Structural Example 6>.

[0358] Figure 13 The semiconductor device 10 shown in the figure differs from the semiconductor device 10 shown in Structural Example 6 in that the transistor 300 does not include the insulating layer 210_2 , and the insulating layer 110_1 is provided in both the transistor 200 and the transistor 300 .

[0359] Specifically, in Figure 13 In the transistor 300 included in the semiconductor device 10 shown, the insulating layer 110_1 extends to one side of the transistor 300 and is provided not only on the conductive layer 202 a but also on the conductive layer 302 a and the insulating layer 210_1 .

[0360] <Structure Example 8> Figure 14 A cross-sectional view showing a modified example of the semiconductor device 10A shown in <Structural Example 2>.

[0361] Figure 14 The semiconductor device 10A is shown except Figure 8B The structure shown includes a transistor 300A in addition to the transistor 100A and the transistor 200A.

[0362] about Figure 14 For the transistor 100A and the transistor 200A included in the semiconductor device 10A shown, the above description can be referred to.

[0363] Figure 14 The transistor 300A included in the semiconductor device 10A shown in the figure is different from the transistor 300 included in the semiconductor device 10 shown in the <Structural Example 6> (see Figure 12 ) is that the number of insulating layers sandwiched between the conductive layer 302a and the conductive layer 302b is seven (insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, insulating layer 110e, insulating layer 110f, and insulating layer 110g). Note that in Figure 14 In the embodiment, the insulating layer 110a, the insulating layer 110c, the insulating layer 110e, and the insulating layer 110g may not be provided. The same applies to the other structural examples described in this specification.

[0364] exist Figure 14In the transistor 300A included in the semiconductor device 10A shown, the insulating layers 110b, 110d, and 110f have the function of supplying oxygen to the semiconductor layer 308. Therefore, the insulating layer 110f can be formed using the same material as the insulating layers 110b and 110d. Furthermore, the insulating layers 110a, 110c, 110e, and 110g have the functions of suppressing the infiltration of impurities (e.g., water and hydrogen) from outside the semiconductor device 10A into the insulating layers 110b, 110d, and 110f, and suppressing the release of oxygen from the insulating layers 110b, 110d, and 110f to the outside of the semiconductor device 10A. Therefore, the insulating layer 110g can be formed using the same material as the insulating layers 110a, 110c, and 110e.

[0365] like Figure 14 As shown in the semiconductor device 10A, by including three transistors with different channel lengths, the semiconductor device 10A can be realized in a manner different from that of the semiconductor device 10A including two transistors (see FIG. Figure 8B ), the former case can increase the variety of characteristics of the transistors included in one semiconductor device. Note that the number of transistors included in the semiconductor device 10A may be four or more.

[0366] <Structure Example 9> Figure 15 A cross-sectional view showing a modified example of the semiconductor device 10B shown in <Structural Example 3>.

[0367] Figure 15 The semiconductor device 10B is shown except Figure 9B The structure shown includes a transistor 300B in addition to the transistor 100A and the transistor 200B.

[0368] about Figure 15 For the transistor 100A and the transistor 200B included in the semiconductor device 10B shown, the above description can be referred to.

[0369] Figure 15 The transistor 300B included in the semiconductor device 10B shown in the embodiment is similar to the transistor 300 included in the semiconductor device 10 shown in the embodiment 6 (see Figure 12 ) is that the insulating layer sandwiched by the conductive layer 302a and the conductive layer 302b has a five-layer stacked structure (insulating layer 110a, insulating layer 210_1, insulating layer 110b, insulating layer 110c and insulating layer 110e).

[0370] exist Figure 15In the transistor 300B included in the semiconductor device 10B shown, the insulating layer 210_1 and the insulating layer 110b have the function of supplying oxygen to the semiconductor layer 308. Furthermore, the insulating layers 110a, 110c, and 110e have the functions of suppressing the infiltration of impurities (e.g., water and hydrogen) from outside the semiconductor device 10B into the insulating layer 210_1 and the insulating layer 110b, and suppressing the release of oxygen in the insulating layer 210_1 and the insulating layer 110b to the outside of the semiconductor device 10B.

[0371] Note that the insulating layer 210_1 can be formed using the same process as that of the insulating layer 110_1.

[0372] like Figure 15 As shown in the semiconductor device 10B, by including three transistors with different channel lengths, the semiconductor device 10B can be realized in a manner different from that of the semiconductor device 10B including two transistors (see FIG. Figure 9B ), the former case can increase the variety of characteristics of the transistors included in one semiconductor device. Note that the number of transistors included in the semiconductor device 10B may also be four or more.

[0373] <Structural Example 10> Figure 16 A cross-sectional view showing a modified example of the semiconductor device 10B shown in <Structural Example 3> which is different from <Structural Example 9>.

[0374] Figure 16 The semiconductor device 10B shown in the figure differs from the semiconductor device 10B shown in <Structural Example 9> in that the transistor 200B does not include the insulating layer 110_1 , and the insulating layer 210_1 is provided in both the transistor 200B and the transistor 300B.

[0375] Specifically, in Figure 16 In the transistor 200B included in the semiconductor device 10B shown, the insulating layer 210_1 extends to the side of the transistor 200B and is provided not only on the conductive layer 302 a but also on the conductive layer 202 a .

[0376] <Structural Example 11> Figure 17A A plan view of a semiconductor device 10E is shown. Figure 17B Shown along Figure 17A A cross-sectional view along the dashed line A1-A2 is shown.

[0377] The semiconductor device 10E includes a transistor 100E and a transistor 200E. The transistor 100E differs from the transistor 100 included in the semiconductor device 10 shown in <Structural Example 1> in that the conductive layer 112b, which serves as the other of the source electrode and the drain electrode, is in contact with the top surface of the semiconductor layer 108. Furthermore, the transistor 200E differs from the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> in that the conductive layer 202b, which serves as the other of the source electrode and the drain electrode, is in contact with the top surface of the semiconductor layer 208.

[0378] Thus, in a semiconductor device of one embodiment of the present invention, depending on the ease of manufacturing or the object for which the semiconductor device is used, the conductive layer used as the other of the source electrode and the drain electrode can contact the bottom surface of the semiconductor layer (the surface on the side of the insulating layer 110) or the top surface of the semiconductor layer.

[0379] Notice, Figure 17B The semiconductor device 10E includes transistors 100E and 200E in a structure in which the conductive layer serving as the other of the source and drain electrodes contacts the top surface of the semiconductor layer, but the present invention is not limited thereto. A semiconductor device according to one embodiment of the present invention may also have a structure in which the conductive layer serving as the other of the source and drain electrodes contacts the bottom surface (the surface facing the insulating layer 110 ) of the semiconductor layer in only some of the plurality of transistors included in the semiconductor device, and the conductive layer serving as the other of the source and drain electrodes contacts the top surface of the semiconductor layer in the remaining transistors.

[0380] Regarding the transistors 100E and 200E included in the semiconductor device 10E, reference can be made to the description of the transistors 100 and 200 included in the semiconductor device 10 shown in <Structural Example 1> except for the above-mentioned differences, and thus detailed description thereof is omitted.

[0381] <Structural Example 12> Figure 18A A plan view of a semiconductor device 10F is shown. Figure 18B Shown along Figure 18A A cross-sectional view along the dashed line A1-A2 is shown.

[0382] The semiconductor device 10F includes a transistor 100F and a transistor 200F. The transistor 100F differs from the transistor 100 included in the semiconductor device 10 shown in <Structural Example 1> in that the end of the conductive layer 112b serving as the other of the source electrode and the drain electrode on the side of the opening 143 is located outside the end of the opening 141. Furthermore, the transistor 200F differs from the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> in that the end of the conductive layer 202b serving as the other of the source electrode and the drain electrode on the side of the opening 243 is located outside the end of the opening 241.

[0383] Since the semiconductor device 10F has the above structure, when viewed from a planar perspective (see Figure 18A ) in the transistor 100F, the top end of the insulating layer 110 on the side of the opening 141 does not coincide with the bottom end of the conductive layer 112b on the side of the opening 143. Similarly, in the transistor 200F, the top end of the insulating layer 110 and the insulating layer 110_1 on the side of the opening 241 does not coincide with the bottom end of the conductive layer 202b on the side of the opening 243. In addition, when viewed from a cross-section (see Figure 18B ), in the transistor 100F, a step is generated between the top surface end of the insulating layer 110 on the opening 141 side and the bottom surface end of the conductive layer 112b on the opening 143 side. Similarly, in the transistor 200F, a step is generated between the top surface end of the insulating layer 110 and the insulating layer 110_1 on the opening 241 side and the bottom surface end of the conductive layer 202b on the opening 243 side.

[0384] Therefore, compared with the transistor 100 having no step structure (see Figure 6B ), the transistor 100F can increase the area of ​​the surface where the semiconductor layer 108 is formed. Similarly, compared with the transistor 200 having a structure without a step (see Figure 6B ), the transistor 200F can increase the area of ​​the surface on which the semiconductor layer 208 is formed. Therefore, it can be said that the transistor included in the semiconductor device 10F has higher coverage of the surface on which the semiconductor layer is formed than the transistor included in the semiconductor device 10 shown in <Structural Example 1>.

[0385] Notice, Figure 18B Although the semiconductor device 10F includes transistors 100F and 200F, each having a step between the top edge of the insulating layer 110 and the bottom edge of the conductive layer serving as the other of the source electrode and the drain electrode, the present invention is not limited thereto. In a semiconductor device according to one embodiment of the present invention, only some of the plurality of transistors included in the semiconductor device may have a step between the top edge of the insulating layer 110 and the bottom edge of the conductive layer serving as the other of the source electrode and the drain electrode.

[0386] Regarding the transistors 100F and 200F included in the semiconductor device 10F, reference can be made to the description of the transistors 100 and 200 included in the semiconductor device 10 shown in <Structural Example 1> except for the above-mentioned differences, and thus detailed description thereof is omitted.

[0387] <Structural Example 13> Figure 19A A plan view of a semiconductor device 10G is shown. Figure 19B Shown along Figure 19A A cross-sectional view along the dashed line A1-A2 is shown.

[0388] Semiconductor device 10G includes transistor 100F and transistor 200G. The above description can be referred to for transistor 100F. Transistor 200G differs from transistor 200F included in semiconductor device 10F described in Structural Example 12 in that the taper angle of the side surfaces of insulating layers 110a and 110_1 on the side of opening 241 is different from the taper angle of the side surfaces of insulating layers 110b and 110c on the side of opening 241.

[0389] Specifically, in the transistor 200F included in the semiconductor device 10F shown in <Structural Example 12>, the taper angles of the side surfaces of the insulating layers 110a, 110_1, 110b, and 110c on the side of the opening 241 are substantially the same. In contrast, in the transistor 200G included in the semiconductor device 10G, the taper angles of the side surfaces of the insulating layers 110a and 110_1 on the side of the opening 241 are smaller than the taper angles of the side surfaces of the insulating layers 110b and 110c on the side of the opening 241.

[0390] Thus, compared to the transistor 200F included in the semiconductor device 10F shown in <Structural Example 12>, the transistor 200G included in the semiconductor device 10G can improve coverage of the formed surface of the semiconductor layer 208. Furthermore, when the taper angles of the side surfaces of the insulating layers 110a, 110_1, 110b, and 110c on the side of the openings 241 are substantially the same, as in the transistor 200F, the openings 241 can be formed collectively, thereby simplifying the manufacturing process of the transistor 200F compared to the manufacturing process of the transistor 200G.

[0391] Notice, Figure 19BThe structure shown is such that the taper angle of the side surface of insulating layer 110a and insulating layer 110_1 on the side of opening 241 is smaller than the taper angle of the side surface of insulating layer 110b and insulating layer 110c on the side of opening 241, but the present invention is not limited to this. In one embodiment of the present invention, the taper angle of the side surface of insulating layer 110a and insulating layer 110_1 on the side of opening 241 may be larger than the taper angle of the side surface of insulating layer 110b and insulating layer 110c on the side of opening 241.

[0392] Regarding the transistor 200G included in the semiconductor device 10G, except for the above-mentioned differences, reference can be made to the description of the transistor 200F included in the semiconductor device 10F shown in <Structural Example 12>, and thus detailed description thereof is omitted.

[0393] <Structural Example 14> Figure 20A A plan view of the semiconductor device 10H is shown. Figure 20B Shown along Figure 20A A cross-sectional view along the dashed line A1-A2 is shown.

[0394] Semiconductor device 10H includes transistor 100F and transistor 200H. Regarding transistor 100F, the above description can be referred to. Transistor 200H differs from transistor 200F included in semiconductor device 10F described in Structural Example 12 in that the side surfaces of insulating layers 110a and 110_1 on the side of opening 241 are located inward of the side surfaces of insulating layers 110b and 110c on the side of opening 241.

[0395] Thus, the transistor 200F included in the semiconductor device 10F shown in <Structural Example 12> (see Figure 18B ), the transistor 200H can increase the area of ​​the surface on which the semiconductor layer 208 is formed. Therefore, it can be said that the coverage of the surface on which the semiconductor layer 208 is formed by the transistor 200H is higher than that of the transistor 200F.

[0396] Regarding the transistor 200H included in the semiconductor device 10H, except for the above-mentioned differences, reference can be made to the description of the transistor 200F included in the semiconductor device 10F shown in <Structural Example 12>, and thus detailed description thereof is omitted.

[0397] <Structural Example 15> Figure 21A A plan view of the semiconductor device 10I is shown. Figure 21B Shown along Figure 21A A cross-sectional view along the dashed line A1-A2 is shown.

[0398] The semiconductor device 10I includes a transistor 100I and a transistor 200I. The transistors 100I and 200I included in the semiconductor device 10I differ from the transistors 100 and 200 included in the semiconductor device 10 shown in <Structural Example 1> in the arrangement of source and drain electrodes and the sizes of the openings 141 and 241.

[0399] Specifically, in the transistor 100 included in the semiconductor device 10 shown in <Structural Example 1>, when viewed from a plane (refer to Figure 6A ), the conductive layer 112a serving as one of the source electrode and the drain electrode and the conductive layer 112b serving as the other of the source electrode and the drain electrode are provided so as to overlap with each other and are each provided so as to cover the opening 141. In addition, the opening 141 is provided so as to be included in the interior of the semiconductor layer 108 when viewed from a planar perspective. Similarly, in the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1>, when viewed from a planar perspective (refer to Figure 6A ), the conductive layer 202a serving as one of the source electrode and the drain electrode and the conductive layer 202b serving as the other of the source electrode and the drain electrode are provided so as to overlap with each other and are each provided so as to cover the opening 241. In addition, the opening 241 is provided so as to be embedded in the interior of the semiconductor layer 208 when viewed from a planar perspective.

[0400] On the other hand, in the transistor 100I included in the semiconductor device 10I, when viewed from a planar perspective (see Figure 21A ), the conductive layer 112a and the conductive layer 112b are arranged with a gap therebetween. In addition, when viewed from a plane, the opening 141 extends beyond the interior of the semiconductor layer 108, and the length of the opening 141 in the Y direction is longer than that of the semiconductor layer 108. Similarly, in the transistor 200I included in the semiconductor device 10I, when viewed from a plane (refer to Figure 21A ), the conductive layer 202a and the conductive layer 202b are arranged with a gap therebetween. In addition, when viewed from a planar perspective, the opening 241 extends beyond the interior of the semiconductor layer 208, and the length of the opening 241 in the Y direction is longer than that of the semiconductor layer 208.

[0401] In the case where the transistor included in the semiconductor device 10I has the above-mentioned structure, similar to the transistors included in the semiconductor devices shown in <Structural Example 1> to <Structural Example 14>, transistors with different channel lengths can be formed by making the thickness of the insulating layer sandwiched by the source electrode and the drain electrode different within the substrate surface.

[0402] <Structural Example 16> Figure 22A A plan view of a semiconductor device 10J is shown. Figure 22B Shown along Figure 22AA cross-sectional view along the dashed line A1-A2 is shown.

[0403] The semiconductor device 10J includes transistors 100J and 200J. The transistors 100J and 200J included in the semiconductor device 10J differ from the transistors 100I and 200I included in the semiconductor device 10I shown in <Structural Example 15> in the size of the conductive layer used as one of the source electrode and the drain electrode.

[0404] Specifically, in the transistor 100I included in the semiconductor device 10I, when viewed from a planar perspective (see Figure 21A ), the conductive layer 112a serving as one of the source electrode and the drain electrode has only a region overlapping with the A1 side of the opening 141. In addition, when viewed from a planar perspective, the conductive layer 112a and the conductive layer 112b serving as the other of the source electrode and the drain electrode are provided with a gap therebetween. Similarly, in the transistor 200I included in the semiconductor device 10I, when viewed from a planar perspective (refer to Figure 21A ), the conductive layer 202a serving as one of the source electrode and the drain electrode has a region overlapping only with the A1 side of the opening 241. In addition, when viewed from a planar perspective, the conductive layer 202a and the conductive layer 202b serving as the other of the source electrode and the drain electrode are provided with a space therebetween.

[0405] In contrast, in transistor 100J included in semiconductor device 10J, conductive layer 112a is provided so as to have a region overlapping with conductive layer 112b when viewed from above, and its length in the X direction is longer than that of conductive layer 112a included in transistor 100I. Similarly, in transistor 200J included in semiconductor device 10J, conductive layer 202a is provided so as to have a region overlapping with conductive layer 202b when viewed from above, and its length in the X direction is longer than that of conductive layer 202a included in transistor 200I.

[0406] Regarding the transistor 100J and the transistor 200J included in the semiconductor device 10J, except for the above-mentioned differences, reference can be made to the description of the transistor 100I and the transistor 200I included in the semiconductor device 10I shown in <Structural Example 15>, and thus detailed description thereof is omitted.

[0407] <Structural Example 17> Figure 23A A plan view of the semiconductor device 10K is shown. Figure 23B Shown along Figure 23A A cross-sectional view along the dashed line A1-A2 is shown.

[0408] The semiconductor device 10K includes a transistor 100K and a transistor 200K. The transistors 100K and 200K included in the semiconductor device 10K differ from the transistors 100I and 200I included in the semiconductor device 10I shown in Structural Example 15 in that the source electrode and the drain electrode are provided on the insulating layer 110 so that their heights are substantially uniform, and an island-shaped conductive layer is provided below the semiconductor layer 108 and the semiconductor layer 208 (on the substrate 102 side).

[0409] Specifically, transistor 100K included in semiconductor device 10K includes an island-shaped conductive layer 112c on substrate 102. Furthermore, conductive layers 112b_1 and 112b_2 are formed on insulating layer 110c, with insulating layers 110a, 110b, and 110c interposed therebetween. In transistor 100K, conductive layer 112b_1 serves as one of a source electrode and a drain electrode. Conductive layer 112b_2 serves as the other of the source and drain electrodes. Conductive layer 112c is an independent conductive layer that is not electrically connected to other conductive layers. Hereinafter, this conductive layer will also be referred to as a floating electrode.

[0410] Furthermore, transistor 200K included in semiconductor device 10K includes an island-shaped conductive layer 202c in a region separate from conductive layer 112c on substrate 102. Furthermore, conductive layers 202b_1 and 202b_2 are provided on insulating layer 110c, with insulating layers 110a, 110_1, 110b, and 110c interposed therebetween. In transistor 200K, conductive layer 202b_1 functions as one of a source electrode and a drain electrode. Conductive layer 202b_2 functions as the other of the source electrode and the drain electrode. Conductive layer 202c is an independent conductive layer (floating electrode) that is not electrically connected to other conductive layers.

[0411] In the transistor 100K included in the semiconductor device 10K, the conductive layer 112b_1 corresponds to the conductive layer 112a in the transistor 100I included in the semiconductor device 10I shown in <Structural Example 15>. Furthermore, in the transistor 100K included in the semiconductor device 10K, the conductive layer 112b_2 corresponds to the conductive layer 112b in the transistor 100I included in the semiconductor device 10I shown in <Structural Example 15>. Similarly, in the transistor 200K included in the semiconductor device 10K, the conductive layer 202b_1 corresponds to the conductive layer 202a in the transistor 200I included in the semiconductor device 10I shown in <Structural Example 15>. Furthermore, in the transistor 200K included in the semiconductor device 10K, the conductive layer 202b_2 corresponds to the conductive layer 202b in the transistor 200I included in the semiconductor device 10I shown in <Structural Example 15>.

[0412] Regarding the transistors 100K and 200K included in the semiconductor device 10K, reference can be made to the description of the transistors 100I and 200I included in the semiconductor device 10I shown in <Structural Example 15> except for the above-mentioned differences, and thus detailed description thereof is omitted.

[0413] Here, refer to Figure 24A and Figure 24B The channel length and channel width of the transistor 100K will be described. Figure 24A is a plan view of transistor 100K. Figure 24B yes Figure 23B An enlarged view of transistor 100K is shown.

[0414] The following is omitted Figure 7A and Figure 7B The description of the channel length and channel width of the transistor 100 overlaps with that described in .

[0415] Note that the description of the channel length and channel width of the transistor 100K shown below can also be applied to the transistor 200K having the same structure as the transistor 100K.

[0416] In semiconductor layer 108, a region in contact with conductive layer 112b_1 functions as one of a source region and a drain region, while a region in contact with conductive layer 112b_2 functions as the other of the source region and the drain region. Furthermore, as described above, conductive layer 112c functions as a floating electrode. Therefore, in semiconductor layer 108, both the region between conductive layer 112b_1 and conductive layer 112c, and the region between conductive layer 112b_2 and conductive layer 112c, function as channel formation regions.

[0417] That is, the transistor 100K has two channel formation regions in which a floating electrode is held between a source electrode and a drain electrode. Figure 24C 100K is a circuit diagram corresponding to transistor 100K. Figure 24C As shown in FIG. 1 , the transistor 100K has a structure equivalent to two transistors connected in series via the conductive layer 112 c .

[0418] The channel length of the transistor 100K refers to the distance between the source region and the floating electrode and the distance between the drain region and the floating electrode. Figure 24BIn the figure, the double-dashed arrows indicate the channel length L100_1 and the channel length L100_2 of the transistor 100K. The channel length L100_1 refers to the distance between the end of the region where the semiconductor layer 108 contacts the conductive layer 112b_1 and the end of the region where the semiconductor layer 108 contacts the conductive layer 112c, as viewed in a cross section. The channel length L100_2 refers to the distance between the end of the region where the semiconductor layer 108 contacts the conductive layer 112b_2 and the end of the region where the semiconductor layer 108 contacts the conductive layer 112c, as viewed in a cross section.

[0419] The channel width of the transistor 100K refers to the length of the channel formation region in the direction perpendicular to the channel length direction. In other words, it can also refer to the length of the source region or the length of the drain region in the direction perpendicular to the channel length direction. In other words, the channel width refers to the length of the region where the semiconductor layer 108 contacts the conductive layer 112b_1 and the length of the region where the semiconductor layer 108 contacts the conductive layer 112b_2 in the direction perpendicular to the channel length direction. Figure 24A In the figure, solid double arrows indicate channel widths W100_1 and W100_2 of transistor 100K, respectively. Channel width W100_1 is the channel width in the channel formation region between conductive layer 112b_1 and conductive layer 112c, while channel width W100_2 is the channel width in the channel formation region between conductive layer 112b_2 and conductive layer 112c. Channel width W100_1 refers to the length in the Y direction of the region where conductive layer 112b_1 overlaps with semiconductor layer 108 when viewed from a planar perspective. Channel width W100_2 refers to the length in the Y direction of the region where conductive layer 112b_2 overlaps with semiconductor layer 108 when viewed from a planar perspective.

[0420] <Structural Example 18> Figure 25A A plan view of the semiconductor device 10L is shown. Figure 25B Shown along Figure 25A A cross-sectional view along the dashed line A1-A2 is shown.

[0421] Semiconductor device 10L includes transistor 100L and transistor 200L. Transistor 100L differs from transistor 100K included in semiconductor device 10K shown in Structural Example 17 in that the end of conductive layer 112b_1, which serves as one of the source and drain electrodes, on the side of opening 141, and the end of conductive layer 112b_2, which serves as the other of the source and drain electrodes, on the side of opening 141, are both located outside the end of insulating layer 110c on the side of opening 141. Furthermore, transistor 200L differs from transistor 200K included in semiconductor device 10K shown in Structural Example 17 in that the end of conductive layer 202b_1, which serves as one of the source and drain electrodes, on the side of opening 241, and the end of conductive layer 202b_2, which serves as the other of the source and drain electrodes, on the side of opening 241, are both located outside the end of insulating layer 110c on the side of opening 241.

[0422] Since the semiconductor device 10L has the above structure, when viewed from a plane (see Figure 25A ) in the transistor 100L, the top surface end of the insulating layer 110 on the side of the opening 141 does not coincide with the bottom surface end of the conductive layer 112b_1 on the side of the opening 141, and the top surface end of the insulating layer 110 on the side of the opening 141 does not coincide with the bottom surface end of the conductive layer 112b_2 on the side of the opening 141. Similarly, when viewed from a planar perspective (see Figure 25A ) in the transistor 200L, the top end of the insulating layer 110 and the insulating layer 110_1 on the side of the opening 241 does not coincide with the bottom end of the conductive layer 202b_1 on the side of the opening 241, and the top end of the insulating layer 110 and the insulating layer 110_1 on the side of the opening 241 does not coincide with the bottom end of the conductive layer 202b_2 on the side of the opening 241. In addition, when viewed from a cross-section (see Figure 25B ). In transistor 100L having a configuration similar to FIG1 , a step is formed between the top surface end of insulating layer 110 on the side of opening 141 and the bottom surface end of conductive layer 112b_1 on the side of opening 141. Furthermore, a step is formed between the top surface end of insulating layer 110 on the side of opening 141 and the bottom surface end of conductive layer 112b_2 on the side of opening 141. Similarly, in transistor 200L, a step is formed between the top surface end of insulating layer 110 and insulating layer 110_1 on the side of opening 241 and the bottom surface end of conductive layer 202b_1 on the side of opening 241. Furthermore, a step is formed between the top surface end of insulating layer 110 and insulating layer 110_1 on the side of opening 241 and the bottom surface end of conductive layer 202b_2 on the side of opening 241.

[0423] Therefore, compared with the transistor 100K having a structure without a step (see Figure 23B) compared to the transistor 100L, the area of ​​the surface where the semiconductor layer 108 is formed can be increased. Similarly, compared to the transistor 200K having a structure without a step (see Figure 23B ), the transistor 200L can increase the area of ​​the surface on which the semiconductor layer 208 is formed. Therefore, it can be said that the transistor included in the semiconductor device 10L has a higher coverage of the surface on which the semiconductor layer is formed than the transistor included in the semiconductor device 10K shown in <Structural Example 17>.

[0424] Notice, Figure 25B While the semiconductor device 10L includes transistors 100L and 200L, both transistors 100L and 200L have a step between the top edge of the insulating layer 110 and the bottom edge of the conductive layer serving as the source and drain electrodes, the present invention is not limited thereto. In a semiconductor device according to one embodiment of the present invention, only some of the plurality of transistors included in the semiconductor device may have a step between the top edge of the insulating layer 110 and the bottom edge of the conductive layer serving as the source and drain electrodes.

[0425] Regarding the transistors 100L and 200L included in the semiconductor device 10L, reference can be made to the description of the transistors 100K and 200K included in the semiconductor device 10 shown in <Structural Example 17> except for the above-mentioned differences, and thus detailed description thereof is omitted.

[0426] <Structural Example 19> Figure 26A A plan view of a semiconductor device 10M is shown. Figure 26B Shown along Figure 26A A cross-sectional view along the dashed line A1-A2 is shown.

[0427] The semiconductor device 10M includes a transistor 100M and a transistor 200M. Figure 26A ), the transistor 100M differs from the transistor 100L included in the semiconductor device 10L shown in <Structural Example 18> in that the conductive layer 112c serving as a floating electrode is provided with a gap between the conductive layer 112b_1 and the conductive layer 112b_2 serving as the source or drain electrode. Furthermore, when viewed from above, the transistor 200M differs from the transistor 200L included in the semiconductor device 10L shown in <Structural Example 18> in that the conductive layer 202c serving as a floating electrode is provided with a gap between the conductive layer 202b_1 and the conductive layer 202b_2 serving as the source or drain electrode.

[0428] As described above, by reducing the in-plane size of the floating electrode of the transistor included in the semiconductor device 10M, the in-plane area occupied by the transistor can be reduced, and the semiconductor device including the transistor can be miniaturized.

[0429] Regarding the transistors 100M and 200M included in the semiconductor device 10M, except for the above-mentioned differences, reference can be made to the description of the transistors 100L and 200L included in the semiconductor device 10L shown in <Structural Example 18>, and thus detailed description thereof is omitted.

[0430] <Structure Example 20> Figure 27A A plan view of the semiconductor device 10N is shown. Figure 27B Shown along Figure 27A A cross-sectional view along the dashed line A1-A2 is shown.

[0431] The semiconductor device 10N includes a transistor 100N and a transistor 200N. The transistor 100N differs from the transistor 100K included in the semiconductor device 10K shown in Structural Example 17 in that the conductive layers 112b_1 and 112b_2, which function as source and drain electrodes, are in contact with the top surface of the semiconductor layer 108. Furthermore, the transistor 200N differs from the transistor 200K included in the semiconductor device 10K shown in Structural Example 17 in that the conductive layers 202b_1 and 202b_2, which function as source and drain electrodes, are in contact with the top surface of the semiconductor layer 208.

[0432] Thus, in a semiconductor device of one embodiment of the present invention, depending on the ease of manufacturing or the object for which the semiconductor device is used, the conductive layer used as the source electrode or the drain electrode can have a structure in which the conductive layer contacts the bottom surface of the semiconductor layer (the surface on the side of the insulating layer 110), or can have a structure in which the conductive layer contacts the top surface of the semiconductor layer.

[0433] Notice, Figure 27B While the semiconductor device 10N includes transistors 100N and 200N, the conductive layer serving as the source or drain electrode of the semiconductor device 10N is shown as being in contact with the top surface of the semiconductor layer, the present invention is not limited thereto. In a semiconductor device according to one embodiment of the present invention, only some of the transistors included in the semiconductor device may have a structure in which the conductive layer serving as the source or drain electrode is in contact with the bottom surface (the surface facing the insulating layer 110 ) of the semiconductor layer, while the conductive layer serving as the source or drain electrode of the remaining transistors is in contact with the top surface of the semiconductor layer.

[0434] Regarding the transistors 100N and 200N included in the semiconductor device 10N, except for the above-mentioned differences, reference can be made to the description of the transistors 100K and 200K included in the semiconductor device 10K shown in <Structural Example 17>, and thus detailed description thereof is omitted.

[0435] <Structural Example 21> Figure 28A A plan view of the semiconductor device 100 is shown. Figure 28B Shown along Figure 28A A cross-sectional view along the dashed line A1-A2 is shown.

[0436] The semiconductor device 100 includes a transistor 1000 and a transistor 2000. When viewed from a planar perspective (see Figure 28A ), the transistor 100O differs from the transistor 100N included in the semiconductor device 10N shown in <Structural Example 20> in that the conductive layer 112c serving as a floating electrode is provided with a gap between the conductive layer 112b_1 and the conductive layer 112b_2 serving as the source or drain electrode. Furthermore, when viewed from above, the transistor 200O differs from the transistor 200N included in the semiconductor device 10N shown in <Structural Example 20> in that the conductive layer 202c serving as a floating electrode is provided with a gap between the conductive layer 202b_1 and the conductive layer 202b_2 serving as the source or drain electrode.

[0437] As described above, by reducing the size of the floating electrode in the transistor within the substrate plane included in the semiconductor device 100, the area occupied by the transistor within the substrate plane can be reduced. In addition, the semiconductor device including the transistor can be miniaturized.

[0438] Regarding the transistors 100O and 200O included in the semiconductor device 10O, except for the above-mentioned differences, reference can be made to the description of the transistors 100N and 200N included in the semiconductor device 10N shown in <Structural Example 20>, and thus detailed description thereof is omitted.

[0439] <Structural Example 22> Figure 29A and Figure 29B The transistor 100K included in the semiconductor device 10K shown in <Structural Example 17> is shown (see Figure 23B ) is a cross-sectional view of a deformation example. In addition, Figure 29C Shown corresponding to Figure 29A and Figure 29B The circuit diagram of transistor 100K is shown.

[0440] Note that the following description can also be applied to the transistor 200K included in the semiconductor device 10K shown in <Structural Example 17> (see Figure 23B ).

[0441] Figure 29A The transistor 100K shown in the figure is composed of two transistors: a transistor 100K_1 and a transistor 100K_2.

[0442] Transistor 100K_1 includes a conductive layer 112c_1 arranged in an island shape on a substrate 102, a conductive layer 112b_1 and a conductive layer 112b_2 arranged on the conductive layer 112c_1 with an insulating layer 110 (insulating layer 110a, insulating layer 110b and insulating layer 110c) separated therefrom, a semiconductor layer 108 having an area in contact with the top surface of the conductive layer 112c_1, the top surface of the conductive layer 112b_1 and the top surface of the conductive layer 112b_2, an insulating layer 106 on the semiconductor layer 108 and a conductive layer 104 on the insulating layer 106.

[0443] In transistor 100K_1, conductive layer 112c_1 functions as a floating electrode. Conductive layer 112b_1 functions as one of a source electrode and a drain electrode. Conductive layer 112b_2 functions as the other of the source and drain electrodes. In semiconductor layer 108, the region between conductive layer 112b_1 and conductive layer 112c_1, and the region between conductive layer 112b_2 and conductive layer 112c_1, function as a channel formation region. Insulating layer 106 functions as a gate insulating layer. Conductive layer 104 functions as a gate electrode.

[0444] Transistor 100K_2 includes a conductive layer 112c_2 arranged in an island shape on a substrate 102, a conductive layer 112b_2 and a conductive layer 112b_3 arranged on the conductive layer 112c_2 via an insulating layer 110 (insulating layer 110a, insulating layer 110b and insulating layer 110c), a semiconductor layer 108 having an area in contact with the top surface of the conductive layer 112c_2, the top surface of the conductive layer 112b_2 and the top surface of the conductive layer 112b_3, an insulating layer 106 on the semiconductor layer 108 and a conductive layer 104 on the insulating layer 106.

[0445] In transistor 100K_2, conductive layer 112c_2 serves as a floating electrode. Conductive layer 112b_2 serves as one of a source electrode and a drain electrode. Conductive layer 112b_3 serves as the other of the source electrode and the drain electrode. In semiconductor layer 108, the region between conductive layer 112b_2 and conductive layer 112c_2, and the region between conductive layer 112b_3 and conductive layer 112c_2, serve as channel formation regions. Insulating layer 106 serves as a gate insulating layer. Conductive layer 104 serves as a gate electrode.

[0446] Since the transistor 100K has the above-described structure, it is not necessary to form a semiconductor layer, a gate insulating layer, and a gate electrode separately for each transistor, and thus the number of steps can be reduced.

[0447] Figure 29B Shown with Figure 29A Cross-sectional views of various modified examples of the transistor 100K.

[0448] Figure 29B The transistor 100K is shown with Figure 29A The transistor 100K shown is different in that the transistor 100K_2 constituting the transistor 100K is used as an insulating layer sandwiched by the conductive layer 112c_2, the conductive layer 112b_2, and the conductive layer 112b_3, including the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c) and the insulating layer 110_1.

[0449] exist Figure 29B In the transistor 100K shown, of the transistors 100K_1 and 100K_2 that constitute the transistor 100K, the channel length of the transistor 100K_2 is longer than the channel length of the transistor 100K_1 by the thickness of the insulating layer 110_1. Thus, in the transistor 100K according to one embodiment of the present invention, the channel lengths of the plurality of transistors constituting the transistor 100K may differ from one another.

[0450] in addition, Figure 29A and Figure 29B The transistor 100K is shown as Figure 29C As shown in the circuit diagram, the structure is equivalent to a structure in which four transistors are connected in series via the conductive layer 112c_1, the conductive layer 112b_2, and the conductive layer 112c_2. In addition, these four transistors share the semiconductor layer 108 having a channel formation region, the insulating layer 106 serving as a gate insulating layer, and the conductive layer 104 serving as a gate electrode.

[0451] <Structural Example 23> Figure 30A and Figure 30B A cross-sectional view of a modified example of the transistor 100K shown in <Structural Example 22> is shown. Figure 30C Shown corresponding to Figure 30A and Figure 30B The circuit diagram of transistor 100K is shown.

[0452] Figure 30A The transistor 100K is shown with Figure 29A The transistor 100K shown is different in that the transistor 100K_1 and the transistor 100K_2 constituting the transistor 100K include different semiconductor layers.

[0453] Specifically, the transistor 100K_1 includes the semiconductor layer 108_1 as a semiconductor layer forming a channel, and the transistor 100K_2 includes the semiconductor layer 108_2 as a semiconductor layer forming a channel.

[0454] By configuring the transistors 100K_1 and 100K_2 to have the above structure, a portion of the conductive layer 112 b_2 (specifically, a region that does not overlap with the semiconductor layer 108_1 and the semiconductor layer 108_2 ) can be used as a floating electrode.

[0455] exist Figure 30A The transistor 100K shown in FIG. 1 is similar to the transistor 100K shown in FIG. 1 , except for the differences described above. Figure 29A The contents described in the transistor 100K are shown.

[0456] Figure 30B Show composition Figure 30A The example of the transistor 100K shown in FIG. 1 is an example in which the channel lengths of the transistor 100K_1 and the transistor 100K_2 are different from each other. For details, please refer to Figure 29B The contents described in the transistor 100K are shown.

[0457] <Structure Example 24> Figure 31A and Figure 31B 1 and 2 show cross-sectional views of modified examples of the transistor 100K shown in <Structural Example 22> and <Structural Example 23>. Figure 31C Shown corresponding to Figure 31A and Figure 31B The circuit diagram of transistor 100K is shown.

[0458] Figure 31A The transistor 100K is shown with Figure 29A The transistor 100K shown is different in that the transistor 100K_1 and the transistor 100K_2 constituting the transistor 100K do not include the conductive layer 112 b_2 .

[0459] By making the transistor 100K have the above structure, in the semiconductor layer 108, the region between the conductive layer 112b_1 and the conductive layer 112c_1, the region between the conductive layer 112c_1 and the conductive layer 112c_2, and the region between the conductive layer 112b_3 and the conductive layer 112c_2 can be used as a channel formation region. Figure 31A The transistor 100K is shown as Figure 31CAs shown in the circuit diagram, the structure is equivalent to a structure in which three transistors are connected in series via the conductive layer 112c_1 and the conductive layer 112c_2. In addition, the three transistors share the semiconductor layer 108 having a channel formation region, the insulating layer 106 serving as a gate insulating layer, and the conductive layer 104 serving as a gate electrode.

[0460] exist Figure 31A The transistor 100K shown in FIG. 1 is similar to the transistor 100K shown in FIG. 1 , except for the differences described above. Figure 29A The contents described in the transistor 100K are shown.

[0461] Figure 31B Show composition Figure 31A The transistor 100K_1 and the transistor 100K_2 of the transistor 100K are different in channel length. Figure 29B The contents described in the transistor 100K are shown.

[0462] <Structural Example 25> Figure 32A A plan view of the semiconductor device 10P is shown. Figure 32B Shown along Figure 32A A cross-sectional view along the dashed line A1-A2 is shown.

[0463] The semiconductor device 10P includes the transistor 100 (see FIG. 1 ) included in the semiconductor device 10 shown in <Structural Example 1>. Figure 6A and Figure 6B ) and the transistor 200I included in the semiconductor device 10I shown in <Structural Example 15> (refer to Figure 21A and Figure 21B ).

[0464] Regarding the transistor 100 and the transistor 200I included in the semiconductor device 10P, reference can be made to the description of the transistor 100 included in the semiconductor device 10 shown in <Structural Example 1> and the description of the transistor 200I included in the semiconductor device 10I shown in <Structural Example 15>, respectively, and thus detailed descriptions thereof are omitted.

[0465] As in the semiconductor device 10P, a semiconductor device according to one embodiment of the present invention may include two transistors having different configurations of source and drain electrodes and different shapes of openings formed in the insulating layer 110, etc. This makes it possible to implement a semiconductor device having both the advantages of the transistor 100 and the advantages of the transistor 200I.

[0466] <Structural Example 26> Figure 33A A plan view of the semiconductor device 10Q is shown. Figure 33B Shown along Figure 33AA cross-sectional view along the dashed line A1-A2 is shown.

[0467] The semiconductor device 10Q includes the transistor 100I (see FIG. 10A ) included in the semiconductor device 10I shown in <Structural Example 15>. Figure 21A and Figure 21B ) and the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1> (refer to Figure 6A and Figure 6B ).

[0468] Regarding the transistor 100I and the transistor 200 included in the semiconductor device 10Q, reference can be made to the description of the transistor 100I included in the semiconductor device 10I shown in <Structural Example 15> and the description of the transistor 200 included in the semiconductor device 10 shown in <Structural Example 1>, respectively, and thus detailed descriptions thereof are omitted.

[0469] As in the semiconductor device 10Q, a semiconductor device according to one embodiment of the present invention may include two transistors having different configurations of source and drain electrodes and shapes of openings formed in the insulating layer 110, etc. This allows for a semiconductor device having both the advantages of the transistor 100I and the advantages of the transistor 200.

[0470] <Structure Example 27> Figure 34A A plan view of the semiconductor device 10R is shown. Figure 34B Shown along Figure 34A A cross-sectional view along the dashed line A1-A2 is shown.

[0471] The semiconductor device 10R includes the transistor 100 (see FIG. 1 ) included in the semiconductor device 10 shown in <Structural Example 1>. Figure 6A and Figure 6B ) and the transistor 200K included in the semiconductor device 10K shown in <Structural Example 17> (refer to Figure 23A and Figure 23B ).

[0472] Regarding the transistor 100 and the transistor 200K included in the semiconductor device 10R, reference can be made to the description of the transistor 100 included in the semiconductor device 10 shown in <Structural Example 1> and the description of the transistor 200K included in the semiconductor device 10K shown in <Structural Example 17>, respectively, and thus detailed descriptions thereof are omitted.

[0473] As in the semiconductor device 10R, a semiconductor device according to one embodiment of the present invention may include two transistors having different configurations of source and drain electrodes and shapes of openings formed in the insulating layer 110, etc. This makes it possible to implement a semiconductor device having both the advantages of the transistor 100 and the advantages of the transistor 200K.

[0474] <Structure Example Including Multiple Transistors> Figure 35A Abstract shows Figure 2C A circuit diagram of part of the components shown in FIG. Figure 35A The circuit diagram shown shows a transistor 51 , a transistor 52 , a wiring 41 , a wiring 43 , and a wiring 45 .

[0475] Note that when the semiconductor device 10 (see Figure 6A and Figure 6B ) as an example, Figure 35A The transistor 51 in FIG. 1 is equivalent to the transistor 100 . Figure 35A The transistor 52 in FIG. 1 is equivalent to the transistor 200. The conductive layer 104 included in the transistor 100 is used as Figure 35A The conductive layer 112a included in the transistor 100 is used as Figure 35A The conductive layer 202b included in the transistor 200 is used as Figure 35A Therefore, for ease of understanding, Figure 35B 、 Figure 36A and Figure 37 In the plan view shown, a wiring corresponding to wiring 41 is shown as conductive layer 104, a wiring corresponding to wiring 43 is shown as conductive layer 112a, and a wiring corresponding to wiring 45 is shown as conductive layer 202b.

[0476] Figure 35B Shown available for Figure 35A The conductive layer 104 and the conductive layer 202b are each a wiring extending in the Y direction. In addition, the conductive layer 112a is a wiring extending in the X direction and intersects with each of the conductive layer 104 and the conductive layer 202b. Figure 35C corresponds to Figure 35B The cross-sectional view of the dotted line E1-E2 is shown. Figure 35D corresponds to Figure 35B A cross-sectional view along the dashed line E3-E4 is shown.

[0477] The conductive layer 112a and the conductive layer 202b are highly complementary and identical wirings, and the conductive layer 202b is located above the conductive layer 112a. An insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c) is disposed between the conductive layers 112a and 202b.

[0478] The wiring of conductive layer 202b and conductive layer 104 are arranged at different heights, with conductive layer 104 positioned above conductive layer 202b. For example, conductive layer 104 includes a region that is arranged at a height higher than conductive layer 202b by the thickness of insulating layer 106. Furthermore, conductive layer 104 and conductive layer 202b are arranged parallel or substantially parallel when viewed in plan.

[0479] The conductive layer 112a can be used as one of a source electrode and a drain electrode of the transistor 51. The semiconductor layer 108 of the transistor 51 has a region overlapping with the conductive layer 112a. The semiconductor layer 108 is provided in contact with the top surface of the conductive layer 112a.

[0480] The conductive layer 104 can function as a gate electrode of the transistor 51 .

[0481] An insulating layer 106 is provided between the semiconductor layer 108 and the conductive layer 104. The insulating layer 106 serves as a gate insulating layer of the transistor 51.

[0482] The conductive layer 202b can function as one of a source electrode and a drain electrode of the transistor 52. The semiconductor layer 208 of the transistor 52 is provided in contact with the top surface of the conductive layer 202a functioning as the other of the source electrode and the drain electrode of the transistor 52. The conductive layer 204 functions as a gate electrode of the transistor 52.

[0483] The insulating layer 106 is provided with an opening 91. The conductive layer 204 is preferably in contact with the top surface of the conductive layer 112b in a region overlapping with the opening 91.

[0484] As mentioned above, in Figure 35B and Figure 35C In the example of the structure shown, the transistor 51 and the transistor 52 can each refer to Figure 6A and Figure 6B The transistors 100 and 200 are described in detail. For the components of the transistors 51 and 52, for example, reference can be made to the description of the corresponding components in the transistors 100 and 200.

[0485] like Figure 35D As shown, in the region where the conductive layer 112 a intersects the conductive layer 202 b , the insulating layer 110 is disposed on the conductive layer 112 a , and the conductive layer 202 b is disposed on the insulating layer 110 .

[0486] <Structure Example Including Pixel Circuit> Figure 36A It is shown that Figure 2C FIG. 4 is a plan view showing an example of the structure of the pixel circuit 40A, the wiring 41, the wiring 43, and the wiring 45. Figure 36B corresponds to Figure 36ANote that, as described above, when the semiconductor device 10 (see FIG. 1 ) shown in <Structural Example 1> Figure 6A and Figure 6B ) as an example, the wiring 41 in the pixel circuit 40A corresponds to the conductive layer 104, the wiring 43 in the pixel circuit 40A corresponds to the conductive layer 112a, and the wiring 45 in the pixel circuit 40A corresponds to the conductive layer 202b.

[0487] Note that in Figure 36A In the plan views and the like described later, a portion of the components such as the conductive layer electrically connected to the light emitting element 60 is omitted. Figure 36A In the plan views and the like described later, some components of the display device, such as a substrate and an insulating layer, are omitted.

[0488] Note that the shapes of conductive layers, semiconductor layers, etc. may be simplified in plan views. Also, for the sake of simplicity, the configuration of components may differ between plan views, perspective views, and cross-sectional views. Consequently, the size, configuration, and shape of components may differ between plan views and cross-sectional views. Furthermore, the size, configuration, and shape of components may differ between perspective views and cross-sectional views.

[0489] Conductive layer 104 and conductive layer 202b are each a wiring extending in the Y direction. Conductive layer 112a is a wiring extending in the X direction, and conductive layer 112a intersects each of conductive layer 104 and conductive layer 202b.

[0490] Conductive layer 112a and conductive layer 202b have wiring at different heights, with conductive layer 202b positioned above conductive layer 112a. Insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c) is provided between conductive layer 112a and conductive layer 202b.

[0491] The wiring heights of conductive layer 202b and conductive layer 104 differ, with conductive layer 104 positioned above conductive layer 202b. For example, conductive layer 104 includes a region positioned at a height higher than conductive layer 202b by the thickness of insulating layer 106. Furthermore, conductive layer 104 and conductive layer 202b are arranged parallel or substantially parallel. The space S1 between conductive layer 104 and conductive layer 202b is smaller than the wiring width L1 of conductive layer 104 and smaller than the wiring width L2 of conductive layer 202b. The difference in height between conductive layer 104 and conductive layer 202b allows for the arrangement of conductive layer 104 and conductive layer 202b to be minimized.

[0492] The conductive layer 112a can be used as one of the source electrode and the drain electrode of the transistor 51. The semiconductor layer 108 of the transistor 51 has a region overlapping with the conductive layer 112a. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. In addition, the conductive layer 112b has an opening 143 at a position overlapping with the opening 141. The semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143 and to have a region inside the opening 141 and the opening 143. The semiconductor layer 108 is provided so as to be in contact with the top surface of the conductive layer 112a. In addition, the semiconductor layer 108 has the following regions: a region within the opening 143 of the conductive layer 112b that serves as the other of the source electrode and the drain electrode of the transistor 51; and a region provided so as to be in contact with the top surface of the conductive layer 112b.

[0493] The conductive layer 104 can function as a gate electrode of the transistor 51. The conductive layer 104 has a relatively large wiring width in a region overlapping with the semiconductor layer 108 of the transistor 51. Alternatively, the conductive layer 104 may be represented as having a branch in the region overlapping with the semiconductor layer 108 of the transistor 51.

[0494] An insulating layer 106 is provided between the semiconductor layer 108 and the conductive layer 104. The insulating layer 106 serves as a gate insulating layer of the transistor 51.

[0495] The conductive layer 202 b can function as one of a source electrode and a drain electrode of the transistor 52. The semiconductor layer 208 of the transistor 52 is provided in contact with the top surface of the conductive layer 202 a, which functions as the other of the source electrode and the drain electrode of the transistor 52. The conductive layer 204 functions as a gate electrode of the transistor 52 and one electrode of the capacitor 57.

[0496] The conductive layer 312 is used as the other electrode of the capacitor 57 .

[0497] The conductive layer 104 and the conductive layer 204 preferably have regions with the same height. Furthermore, the conductive layer 104 and the conductive layer 204 may, for example, comprise the same material. Furthermore, when the conductive layer 104 has a laminated structure, the conductive layer 204 may also, for example, have the same laminated structure. The conductive layer 104 and the conductive layer 204 may, for example, be formed by processing the same conductive film. Here, the height of the wiring, conductive layer, semiconductor layer, insulating layer, etc. included in the display device may, for example, be the distance from a reference plane. As the reference plane, for example, the surface of a substrate, a flat region of a film disposed on a substrate, etc. may be used. As the reference plane, for example, the surface of a substrate, a flat region of a film disposed on a substrate, etc. may be used.

[0498] The conductive layer 112a and the conductive layer 202a preferably have highly aligned regions. The conductive layer 112a and the conductive layer 202a may, for example, be made of the same material. If the conductive layer 112a has a stacked-layer structure, the conductive layer 202a may also have the same stacked-layer structure. The conductive layer 112a and the conductive layer 202a may be formed by processing the same conductive film.

[0499] The conductive layers 202b, 112b, and 312 preferably have regions with identical heights. The conductive layers 202b, 112b, and 312 may, for example, be made of the same material. If the conductive layer 202b has a stacked-layer structure, the conductive layers 112b and 312 may also have the same stacked-layer structure. The conductive layers 202b, 112b, and 312 may be formed by processing the same conductive film.

[0500] Conductive layer 312 has a region that is embedded in an opening of insulating layer 110. Conductive layer 312 preferably contacts conductive layer 202a in this region. Alternatively, a plug may be provided in the opening of insulating layer 110, and conductive layer 312 and conductive layer 202a may be electrically connected via the plug.

[0501] Furthermore, conductive layer 204 has a region provided so as to fit into an opening of insulating layer 106. Conductive layer 204 preferably contacts conductive layer 112b in this region. Alternatively, a plug may be provided in the opening of insulating layer 106, and conductive layer 204 and conductive layer 112b may be electrically connected via the plug.

[0502] An insulating layer 106 is provided between the semiconductor layer 208 and the conductive layer 204 and between the conductive layer 312 and the conductive layer 204. The insulating layer 106 serves as a gate insulating layer of the transistor 52 and a dielectric layer of the capacitor 57.

[0503] When a light-emitting element is provided above the capacitor 57 , the pixel electrode of the light-emitting element may be provided in contact with the region 82 on the top surface of the conductive layer 312 , for example.

[0504] Figure 37 Shows that the row and column directions are Figure 36A The structural configuration shown is an example of multiple configurations. Figure 37 In FIG. 3 , a pixel electrode 311 electrically connected to the light emitting element 60 is indicated by a two-dot chain line. The pixel electrode 311 is provided so as to be in contact with the region 82 on the top surface of the conductive layer 312, for example.

[0505] Figure 38A and Figure 38B yes Figure 6A and Figure 6B The semiconductor device 10 shown is a modified example of the transistor 100 included in the embodiment. Figure 38A A plan view of transistor 100 is shown. Figure 38B Shown along Figure 38A A cross-sectional view along the dashed line B1-B2 is shown.

[0506] Figure 38A and Figure 38B An example is shown in which the transistor 100 has two openings 141 and 143 , which are arranged in the X direction.

[0507] exist Figure 38A and Figure 38B In FIG, the two openings 141 are respectively recorded as opening 141_1 and opening 141_2 to distinguish them, and the two openings 143 are respectively recorded as opening 143_1 and opening 143_2 to distinguish them. Figure 38A and Figure 38B An example is shown in which different semiconductor layers 108 are provided inside the openings 141_1 and 143_1 and inside the openings 141_2 and 143_2 , and these two semiconductor layers 108 are respectively described as semiconductor layer 108_1 and semiconductor layer 108_2 to distinguish them. The same description is applied to the following drawings.

[0508] Figure 39A yes Figure 38A In the modified example of the structure shown, a common semiconductor layer 108 is provided inside the opening 141_1 and the opening 143_1 and inside the opening 141_2 and the opening 143_2. Figure 39A An example is shown in which the transistor 100 includes two openings 141 , two openings 143 , and one semiconductor layer 108 . Figure 39B yes Figure 39A A cross-sectional view along the dashed line B1-B2 is shown.

[0509] exist Figure 39A and Figure 39B In the structure shown, for example, when the semiconductor layer 108 is formed by photolithography and etching, Figure 38A and Figure 38B Compared with the structure shown in FIG. 1 , the position alignment accuracy of the photomask can be reduced. Thus, the transistor 100 can be easily manufactured. On the other hand, in Figure 38A and Figure 38B In the structure shown in FIG. 1 , since the surface area of ​​the semiconductor layer 108 having a higher resistance than the conductive layer 112b can be reduced, Figure 39A and Figure 39B The on-state current of the transistor 100 can be increased compared to the structure shown in FIG. Figures 40A to 42B In the structure shown, there may be only one semiconductor layer 108 .

[0510] Figure 40A yes Figure 38A The modified example of the structure shown here shows an example in which two openings 141 and 143 are arranged in the Y direction. Figure 40B yes Figure 40A A modified example of the structure shown in FIG. shows an example in which a single opening 141 and opening 143 is provided to the right of two openings 141 and opening 143 arranged in the Y direction. Here, the two openings 141 and opening 143 arranged in the Y direction are arranged in the first row, and the single opening 141 and opening 143 is arranged in the second row. In this case, for example, the center of the openings 141 and opening 143 in the second row can be located between the center of the openings 141 and opening 143 on the upper side of the first row in the Y direction and the center of the openings 141 and opening 143 on the lower side of the first row.

[0511] Figure 40C yes Figure 40A A modified example of the structure shown in FIG. shows an example in which one opening 141 and one opening 143 are provided to the left and right of two openings 141 and 143 arranged in the Y direction, respectively. Here, one opening 141 and one opening 143 are provided in the first and third rows, and two openings 141 and 143 arranged in the Y direction are provided in the second row. In this case, for example, the centers of the openings 141 and 143 in the first row and the centers of the openings 141 and 143 in the third row are located in the Y direction between the centers of the openings 141 and 143 on the upper side of the second row and the centers of the openings 141 and 143 on the lower side of the second row.

[0512] Figure 41A yes Figure 38A The modified example of the structure shown shows an example in which four openings 141 and four openings 143 are arranged in a matrix of two rows and two columns. Figure 41B yes Figure 41A In the example of a variation of the structure shown, one opening 141 and one opening 143 are provided below two openings 141 and 143 arranged in the X direction. Here, the two openings 141 and 143 arranged in the X direction are provided in the first row, and one opening 141 and one opening 143 are provided in the second row. In this case, for example, the center of the openings 141 and 143 in the second row may be located between the center of the openings 141 and 143 on the left side of the first row and the center of the openings 141 and 143 on the right side of the first row in the X direction.

[0513] Figure 41C yes Figure 41A The modified example of the structure shown in FIG. 1 is a diagram showing a structure in which the two openings 141 and 143 on the lower side are aligned with the Figure 41A Compared to the right side. Figure 41C In the structure shown, the four openings 141 and the opening 143 are arranged in a zigzag shape.

[0514] Figure 42A yes Figure 38A The modified example of the structure shown shows an example in which nine openings 141 and nine openings 143 are arranged in a matrix of three rows and three columns. Figure 42B yes Figure 42A The modified example of the structure shown in FIG. 1 shows an example in which the number of openings 141 and 143 provided in the central row is two. Figure 42B In the example shown, the upper row of openings 141 and openings 143 and the middle row of openings 141 and openings 143 are arranged in a zigzag pattern. Figure 42B In the example shown, the openings 141 and 143 in the lower row and the openings 141 and 143 in the middle row are arranged in a zigzag shape.

[0515] By increasing the number of openings 141 and 143 provided in transistor 100, the total length of the outer peripheries of openings 141 and 143 when viewed from a planar perspective can sometimes be increased. As described above, the channel width of transistor 100 can be equal to the length of the outer periphery of opening 143 when viewed from a planar perspective, for example. Thus, by providing a plurality of openings 141 and 143 in transistor 100, the channel width of transistor 100 can sometimes be increased. On the other hand, by reducing the number of openings 141 and 143 provided in transistor 100, it can sometimes be easier to manufacture transistor 100 and miniaturize transistor 100.

[0516] Notice, Figures 38A to 42B The structure shown is as follows Figure 6A and Figure 6B The transistor 100 of the transistors included in the semiconductor device 10 shown in the figure is used as a modified example for description, but the invention is not limited thereto. Figure 6A and Figure 6B The semiconductor device 10 shown includes a transistor 200 .

[0517] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0518] (Implementation Method 2) In this embodiment, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described with reference to the drawings.

[0519] <Manufacturing Method Example 1> Below, refer to Figures 43A to 46C illustrate Figure 6B1 and 2. The manufacturing method of the semiconductor device 10 shown in FIG. Each figure shows a cross-sectional view taken along the dashed line A1-A2.

[0520] Note that thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and ALD. Examples of CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD. Furthermore, one thermal CVD method includes metal organic chemical vapor deposition (MOCVD).

[0521] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and blade coating.

[0522] When processing thin films constituting semiconductor devices, photolithography or the like can be used. Alternatively, thin films can be processed using nanoimprinting, sandblasting, lift-off, or the like. Furthermore, island-shaped thin films can be directly formed using a deposition method using a shadow mask such as a metal mask.

[0523] Photolithography typically involves two methods. One involves forming a resist mask on the film to be processed, processing the film by etching, etc., and then removing the resist mask. The other involves forming a photosensitive film, then exposing it to light and developing it, processing the film into the desired shape.

[0524] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, exposure can also be performed using liquid immersion exposure technology. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-Violet) light or X-rays can also be used. In addition, an electron beam can also be used instead of the light used for exposure. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0525] As a method for etching the thin film, for example, dry etching, wet etching, or sand blasting can be used.

[0526] [Formation of Conductive Layer 112a and Conductive Layer 202a] A conductive film 112af (which becomes the conductive layer 112a and the conductive layer 202a) is formed over the substrate 102. Figure 43A ) The conductive film 112af can be formed by, for example, sputtering as appropriate.

[0527] Next, a resist mask (not shown) is formed on the conductive film 112af by a photolithography process, and then the conductive film 112af is processed to form the conductive layer 112a and the conductive layer 202a ( Figure 43B The conductive film 112 af can be processed by either a wet etching method or a dry etching method, or both. Thus, the conductive layer 112 a serving as one of the source electrode and the drain electrode of the transistor 100 and the conductive layer 202 a serving as one of the source electrode and the drain electrode of the transistor 200 are formed.

[0528] [Formation of Insulating Layer 110 a , Insulating Layer 110_1 , Insulating Layer 110 b , and Insulating Layer 110 c ] Next, an insulating film 110_1f (which becomes the insulating layer 110a and the insulating layer 110_1) is formed in this order over the substrate 102, the conductive layer 112a, and the conductive layer 202a. Figure 43C ).

[0529] The insulating layer 110a and the insulating film 110_1f can be formed using a PECVD method. After forming the insulating layer 110a, the insulating film 110_1f is preferably formed continuously in a vacuum, without exposing the surface of the insulating layer 110a to the atmosphere. By continuously forming the insulating layer 110a and the insulating film 110_1f, the adhesion of atmospheric impurities to the surface of the insulating layer 110a can be suppressed. Examples of such impurities include water and organic matter.

[0530] The substrate temperature during formation of the insulating layer 110a and the insulating film 110_1f is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and even more preferably 350°C to 400°C. By setting the substrate temperature during formation of the insulating layer 110a and the insulating film 110_1f within the above range, the release of impurities (e.g., water and hydrogen) from the insulating layer 110a and the insulating film 110_1f themselves can be reduced, thereby suppressing the diffusion of impurities into semiconductor layers to be formed later. Consequently, a transistor exhibiting excellent electrical characteristics and high reliability can be realized.

[0531] Note that since the insulating layer 110a and the insulating film 110_1f are formed first and then the semiconductor layer 108 and the semiconductor layer 208 are formed, there is no concern that oxygen will be released from the semiconductor layer 108 and the semiconductor layer 208 due to heat applied when forming the insulating layer 110a and the insulating film 110_1f.

[0532] Alternatively, heat treatment may be performed after forming the insulating layer 110a and the insulating film 110_1f. The heat treatment can remove water and hydrogen from the surfaces and the inner layers of the insulating layer 110a and the insulating film 110_1f.

[0533] The heat treatment temperature is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Clean dry air (CDA) can also be used as a nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen, oxygen, and the like in this atmosphere is preferably as low as possible. A high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferably used as this atmosphere. Using an atmosphere with minimal hydrogen, water, and the like content minimizes absorption of hydrogen, water, and the like by the insulating layer 110a and the insulating film 110_1f. This heat treatment can be performed, for example, in an oven or a rapid thermal annealing (RTA) apparatus. Using an RTA apparatus can shorten the heat treatment time.

[0534] Next, a resist mask (not shown) is formed on the insulating film 110_1f by a photolithography process so as to have a region overlapping with the conductive layer 202a, and then the insulating film 110_1f is processed, thereby forming the insulating layer 110_1 ( Figure 44A The insulating layer 110_1 is formed in an island shape on the insulating layer 110a so as to have a region overlapping with the conductive layer 202a. The insulating film 110_1f can be processed by either or both wet etching and dry etching.

[0535] Next, an insulating layer 110b and an insulating layer 110c are sequentially formed on the insulating layer 110a and the insulating layer 110_1 ( Figure 44B ).

[0536] The insulating layers 110b and 110c can be formed using a PECVD method. After forming the insulating layer 110b, the insulating layer 110c is preferably formed continuously in a vacuum, without exposing the surface of the insulating layer 110b to the atmosphere. By continuously forming the insulating layers 110b and 110c, the adhesion of atmospheric impurities to the surface of the insulating layer 110b can be suppressed. Examples of such impurities include water and organic matter.

[0537] The substrate temperature when forming the insulating layer 110 b and the insulating layer 110 c can be the same as the substrate temperature when forming the insulating layer 110 a and the insulating film 110_1 f described above.

[0538] Alternatively, after forming the insulating layer 110b, a treatment for supplying oxygen to the insulating layer 110b may be performed. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. may be supplied to the insulating layer 110b using ion doping, ion implantation, plasma treatment, or the like. Alternatively, after forming a film that inhibits oxygen detachment on the insulating layer 110b, oxygen may be added to the insulating layer 110b through the film. Preferably, the film is removed after supplying oxygen. As the film that inhibits oxygen detachment, a conductive film or semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten may be used. Alternatively, the insulating layer 110c may be formed after performing the above-mentioned treatment.

[0539] Alternatively, heat treatment may be performed after forming the insulating layer 110b and the insulating layer 110c. This heat treatment may employ the same conditions as those for the heat treatment that can be performed after forming the insulating layer 110a and the insulating film 110_1f.

[0540] [Formation of Conductive Film 112bf] Next, a conductive film 112bf (which will become the conductive layer 112b and the conductive layer 202b) is formed on the insulating layer 110c. Figure 44C ) The conductive film 112bf can be formed by, for example, sputtering as appropriate.

[0541] [Formation of Conductive Layer 112B and Conductive Layer 202B] Next, the conductive film 112bf is processed to form a conductive layer 112B in a region overlapping with the conductive layer 112a, and a conductive layer 202B in a region overlapping with the conductive layer 202a. Figure 45A The conductive layer 112B and the conductive layer 202B can be formed by one or both of a wet etching method and a dry etching method. For example, the conductive layer 112B and the conductive layer 202B can be formed by a wet etching method as appropriate.

[0542] [Formation of Openings 141, 143, 241, and 243] Next, a portion of the conductive layer 112B and a portion of the conductive layer 202B are removed to form a conductive layer 112b having an opening 143 and a conductive layer 202b having an opening 243, respectively. Figure 45B The openings 143 and 243 can be formed by wet etching or dry etching, or both. For example, the openings 143 and 243 can be formed by wet etching as appropriate.

[0543] Next, the insulating layer (insulating layer 110a, insulating layer 110b, and insulating layer 110c) in the region overlapping with the opening 143 and the insulating layer (insulating layer 110a, insulating layer 110_1, insulating layer 110b, and insulating layer 110c) in the region overlapping with the opening 243 are removed to form the opening 141 and the opening 241 ( Figure 45B Openings 141 and 241 can be formed using either or both wet etching and dry etching. For example, dry etching can be used as appropriate for the formation of openings 141 and 241. This formation exposes conductive layer 112a in opening 141, and exposes conductive layer 202a in opening 241.

[0544] The opening 141 can be formed, for example, using a resist mask (not shown) used to form the opening 143. Specifically, a resist mask can be formed on the conductive film 112bf, and the conductive film 112bf can be removed using the resist mask to form the opening 143. The insulating layers 110a, 110b, and 110c can then be removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0545] Similarly, the opening 241 can be formed using, for example, a resist mask (not shown) used to form the opening 243. Specifically, a resist mask can be formed on the conductive film 112bf, and the conductive film 112bf can be removed using the resist mask to form the opening 243. The insulating layer 110a, the insulating layer 110_1, the insulating layer 110b, and the insulating layer 110c can be removed using the resist mask to form the opening 241. The opening 241 can also be formed using a resist mask different from the resist mask used to form the opening 243.

[0546] [Formation of Semiconductor Layer 108 and Semiconductor Layer 208] Next, a metal oxide film 108f is formed so as to cover the opening 143, the opening 141, the opening 243, and the opening 241. Figure 45CThe metal oxide film 108f has a region in contact with the top surface and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110c, the side surfaces of the insulating layer 110b, the side surfaces of the insulating layer 110a, and the top surface of the conductive layer 112a through the openings 143 and 141. Furthermore, the metal oxide film 108f has a region in contact with the top surface and side surfaces of the conductive layer 202b, the side surfaces of the insulating layer 110c, the side surfaces of the insulating layer 110b, the side surfaces of the insulating layer 110_1, the side surfaces of the insulating layer 110a, and the top surface of the conductive layer 202a through the openings 243 and 241.

[0547] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0548] The metal oxide film 108f is preferably a dense film with as few defects as possible. The metal oxide film 108f is preferably a high-purity film with as few impurities as possible containing hydrogen. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0549] When forming the metal oxide film 108f, an oxygen gas is preferably used. By using an oxygen gas when forming the metal oxide film 108f, oxygen can be appropriately supplied to the insulating layer 110b and the insulating layer 110_1. For example, when an oxide is used for the insulating layer 110b and the insulating layer 110_1, oxygen can be appropriately supplied to the insulating layer 110b and the insulating layer 110_1.

[0550] By supplying oxygen to the insulating layer 110 b and the insulating layer 110_1 , oxygen will be supplied to the semiconductor layer 108 and the semiconductor layer 208 in a subsequent step, thereby reducing oxygen vacancies (V O ) and V O H.

[0551] When depositing the metal oxide film 108f, oxygen gas and an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may also be mixed. Note that the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas when depositing the metal oxide film 108f (oxygen flow ratio), the higher the crystallinity of the metal oxide film 108f can be, and a transistor with high reliability can be achieved. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film 108f, thereby achieving a transistor w...

Claims

1. A semiconductor device comprising: a first transistor; as well as The second transistor, The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer and a first insulating layer. The second conductive layer is disposed on the first conductive layer, The first semiconductor layer is in contact with the top surface of the first conductive layer and the second conductive layer, The first insulating layer contacts the top surface of the first semiconductor layer. The third conductive layer is disposed on the first insulating layer in a manner of having a region overlapping with the first semiconductor layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer and the first insulating layer, The fifth conductive layer is disposed on the fourth conductive layer, The second semiconductor layer is in contact with the top surface of the fourth conductive layer and the fifth conductive layer, The first insulating layer contacts the top surface of the second semiconductor layer. The sixth conductive layer is disposed on the first insulating layer in a manner of having a region overlapping with the second semiconductor layer. A second insulating layer is provided between the first conductive layer and the second conductive layer and between the fourth conductive layer and the fifth conductive layer. Furthermore, a thickness of the second insulating layer between the first conductive layer and the second conductive layer and a thickness of the second insulating layer between the fourth conductive layer and the fifth conductive layer are different from each other.

2. The semiconductor device according to claim 1, The first semiconductor layer and the second semiconductor layer both contain metal oxide.

3. The semiconductor device according to claim 1 or 2, The second insulating layer includes a third insulating layer and a fourth insulating layer, The third insulating layer is arranged in an island shape on the fourth conductive layer, And the fourth insulating layer is disposed on the first conductive layer and the third insulating layer.

4. The semiconductor device according to claim 1 or 2, The second insulating layer includes a third insulating layer and a fourth insulating layer, The third insulating layer is disposed on the first conductive layer and the fourth conductive layer. And the fourth insulating layer is provided on the third insulating layer in a manner of having an opening in a region overlapping with the first conductive layer.

5. The semiconductor device according to claim 1 or 2, The second insulating layer includes a third insulating layer and a fourth insulating layer, The third insulating layer is configured in an island shape. The first conductive layer is disposed on the third insulating layer, And the fourth insulating layer is disposed on the first conductive layer and the fourth conductive layer.

6. A method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive film; Processing the first conductive film to form a first conductive layer and a second conductive layer; forming a first insulating film on the first conductive layer and the second conductive layer; Processing the first insulating film to form a first insulating layer overlapping the second conductive layer; forming a second insulating layer on the first conductive layer, the second conductive layer and the first insulating layer; forming a second conductive film on the second insulating layer; Processing the second conductive film to form a third conductive layer overlapping the first conductive layer and a fourth conductive layer overlapping the second conductive layer; removing a portion of the third conductive layer and the fourth conductive layer to form a fifth conductive layer having a first opening and a sixth conductive layer having a second opening, respectively; Removing the second insulating layer in a region overlapping with the first opening and the first insulating layer and the second insulating layer in a region overlapping with the second opening to form a third opening and a fourth opening respectively; a metal oxide film covering the first opening, the second opening, the third opening, and the fourth opening and contacting a top surface of the first conductive layer, a top surface of the second conductive layer, a top surface and a side surface of the fifth conductive layer, a top surface and a side surface of the sixth conductive layer, a side surface of the first insulating layer, and a side surface of the second insulating layer; Processing the metal oxide film into an island shape to form a first semiconductor layer in contact with the top surface of the first conductive layer, the side surface of the second insulating layer, and the top surface and side surface of the fifth conductive layer, and a second semiconductor layer in contact with the top surface of the second conductive layer, the side surface of the first insulating layer, the side surface of the second insulating layer, and the top surface and side surface of the sixth conductive layer; forming a third insulating layer on the first semiconductor layer, the second semiconductor layer, the fifth conductive layer, the sixth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; as well as The third conductive film is processed to form a seventh conductive layer overlapping the first conductive layer and the first semiconductor layer and an eighth conductive layer overlapping the second conductive layer and the second semiconductor layer.

7. A method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive film; Processing the first conductive film to form a first conductive layer and a second conductive layer; forming a first insulating layer on the first conductive layer and the second conductive layer and a first insulating film on the first insulating layer; processing the first insulating film to form a second insulating layer having a first opening in a region overlapping the first conductive layer; forming a second conductive film on the first insulating layer and the second insulating layer, Processing the second conductive film to form a third conductive layer overlapping the first conductive layer and a fourth conductive layer overlapping the second conductive layer; removing a portion of the third conductive layer and the fourth conductive layer to form a fifth conductive layer having a second opening and a sixth conductive layer having a third opening, respectively; Removing the first insulating layer in a region overlapping with the second opening and the first insulating layer and the second insulating layer in a region overlapping with the third opening to form a fourth opening and a fifth opening respectively; a metal oxide film covering the second opening, the third opening, the fourth opening, and the fifth opening to form a contact with a top surface of the first conductive layer, a top surface of the second conductive layer, a top surface and a side surface of the fifth conductive layer, a top surface and a side surface of the sixth conductive layer, a side surface of the first insulating layer, and a side surface of the second insulating layer; Processing the metal oxide film into an island shape to form a first semiconductor layer in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the top surface and side surface of the fifth conductive layer, and a second semiconductor layer in contact with the top surface of the second conductive layer, the side surface of the first insulating layer, the side surface of the second insulating layer, and the top surface and side surface of the sixth conductive layer; forming a third insulating layer on the first semiconductor layer, the second semiconductor layer, the fifth conductive layer, the sixth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; as well as The third conductive film is processed to form a seventh conductive layer overlapping the first conductive layer and the first semiconductor layer and an eighth conductive layer overlapping the second conductive layer and the second semiconductor layer.

8. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating film; Processing the first insulating film to form a first insulating layer; forming a first conductive film on the first insulating layer; Processing the first conductive film to form a first conductive layer on the first insulating layer and a second conductive layer on a region different from the first insulating layer; forming a second insulating film on the first insulating layer, the first conductive layer, and the second conductive layer; Processing the second insulating film to form a second insulating layer with a flat or substantially flat surface; forming a second conductive film on the second insulating layer; Processing the second conductive film to form a third conductive layer overlapping the first conductive layer and a fourth conductive layer overlapping the second conductive layer; removing a portion of the third conductive layer and the fourth conductive layer to form a fifth conductive layer having a first opening and a sixth conductive layer having a second opening, respectively; Removing the second insulating layer in a region overlapping with the first opening and the second insulating layer in a region overlapping with the second opening to form a third opening and a fourth opening respectively; A metal oxide film is formed covering the first opening, the second opening, the third opening, and the fourth opening to contact the top surface of the first conductive layer, the top surface of the second conductive layer, the top surface and the side surface of the fifth conductive layer, the top surface and the side surface of the sixth conductive layer, and the side surface of the second insulating layer; Processing the metal oxide film into an island shape to form a first semiconductor layer in contact with the top surface of the first conductive layer, the side surface of the second insulating layer, and the top surface and side surface of the fifth conductive layer, and a second semiconductor layer in contact with the top surface of the second conductive layer, the side surface of the second insulating layer, and the top surface and side surface of the sixth conductive layer; forming a third insulating layer on the first semiconductor layer, the second semiconductor layer, the fifth conductive layer, the sixth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; as well as The third conductive film is processed to form a seventh conductive layer overlapping the first conductive layer and the first semiconductor layer and an eighth conductive layer overlapping the second conductive layer and the second semiconductor layer.

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