A method for applying partial erasure voltage to a liquid crystal writing device, a writing film, and a device.

Abstract

This invention belongs to the field of liquid crystal writing technology, specifically disclosing a method for applying partial erasure voltage, a writing film, and a device for a liquid crystal writing device. The liquid crystal writing device includes a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer arranged sequentially from top to bottom. The first and second conductive layers are respectively divided into multiple mutually insulated conductive regions. The method includes: setting three voltages satisfying: first voltage V1 > second voltage V2 > third voltage V3; applying the first voltage V1 to the conductive region on the first conductive layer covering the target erasure area, and applying the third voltage V3 to other conductive regions on the first conductive layer; applying the third voltage V3 to the conductive region on the second conductive layer covering the target erasure area, and applying the second voltage V2 to other conductive regions on the second conductive layer; thereby erasing the written content at the corresponding position of the target erasure area, while the written content in other areas remains unchanged. This invention greatly simplifies the complexity of the voltage circuit and reduces production and maintenance costs.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal writing technology, and in particular to a method for applying partial erasure voltage to a liquid crystal writing device, a writing film, and a device. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Currently available liquid crystal writing films work by utilizing the bistable properties of liquid crystals to display and / or erase written content on the liquid crystal writing surface. For example, using cholesteric liquid crystal as the writing film, pressure applied to the liquid crystal writing surface records the writing pressure trajectory of the writing pen, thereby displaying the corresponding written content; applying an electric field causes a change in the structure of the cholesteric liquid crystal, causing the writing pressure trajectory on the liquid crystal writing surface to disappear, thus achieving erasure.

[0004] Existing technologies disclose techniques for achieving partial erasure by applying an auxiliary voltage. These techniques divide two conductive layers into several conductive regions, and apply a predetermined voltage to each conductive region to achieve partial erasure. For example, existing technologies disclose the following two voltage application schemes:

[0005] The first approach is to apply voltage A to the conductive layer region on the first conductive layer covering the local erasure area, apply voltage B to the conductive layer region on the first conductive layer covering the local erasure area, and apply a compensation voltage C to the other conductive regions on the first and second conductive layers, thereby achieving local erasure.

[0006] The second approach is to apply voltage A to the conductive layer region on the first conductive layer covering the partial erasure area, voltage B to the conductive layer region on the first conductive layer covering the partial erasure area, a compensation voltage C to the other conductive regions on the first conductive layer, and a compensation voltage D to the other conductive regions on the second conductive layer, thereby achieving partial erasure.

[0007] Compared to the first approach, the second approach requires four different voltages to achieve partial erasure, which increases the product's design cost and maintenance difficulty to some extent.

[0008] Furthermore, both of the above solutions require the use of voltage driving devices to achieve different voltage outputs. For example, existing technology discloses a system using a VFD driver chip to achieve partial erase voltage control, where the voltage required for partial erasure is output on each conductive layer via the VFD driver chip. However, the VFD driver chip is a two-to-one chip, which can only output a zero voltage and another non-zero voltage. In both of the above solutions, there is a situation where at least one conductive layer has both applied voltages that are not zero. Therefore, it is not possible to directly output the required voltage using the VFD driver chip. Instead, it is necessary to use components such as optocouplers and isolation transformers to output the required voltage. This results in a more complex circuit structure, increased production costs, and a correspondingly higher product failure rate. Summary of the Invention

[0009] To address the aforementioned issues, this invention proposes a method and system for applying partial erasure voltage to a liquid crystal writing device. By employing a reasonable voltage application method, a relatively ideal partial erasure effect can be achieved using as little erasure voltage as possible. Furthermore, it simplifies the structure of the driving circuit and reduces production costs.

[0010] In some implementations, the following technical solutions are adopted:

[0011] A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions, the method comprising:

[0012] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0013] A first voltage V1 is applied to the conductive area covering the target erasure area on the first conductive layer, and a third voltage V3 is applied to other conductive areas of the first conductive layer;

[0014] A third voltage V3 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0015] The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0016] |V1-V3|>Vst;

[0017] |V3-V2| <Vst;

[0018] |V1-V2| <Vst;

[0019] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0020] This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

[0021] As an optional approach, firstly, a second voltage V2 is applied to the conductive area covering the target erasure area on the first conductive layer, and a third voltage V3 is applied to other conductive areas on the first conductive layer.

[0022] A third voltage V3 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0023] Then, the voltage of the conductive area covering the target erasure area on the first conductive layer is adjusted to the first voltage V1.

[0024] In other embodiments, the following technical solutions are adopted:

[0025] A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions, the method comprising:

[0026] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0027] A first voltage V1 is applied to the conductive area covering the target erasure area on the second conductive layer, and a third voltage V3 is applied to other conductive areas of the second conductive layer;

[0028] A third voltage V3 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0029] The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0030] |V1-V3|>Vst;

[0031] |V3-V2| <Vst;

[0032] |V1-V2| <Vst;

[0033] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0034] This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

[0035] As an optional approach, firstly, a second voltage V2 is applied to the conductive area covering the target erasure area on the second conductive layer, and a third voltage V3 is applied to other conductive areas on the second conductive layer.

[0036] A third voltage V3 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0037] Then, the voltage of the conductive area covering the target erasure area on the second conductive layer is adjusted to the first voltage V1.

[0038] As an optional solution, the first voltage V1, the second voltage V2, and the third voltage V3 further satisfy:

[0039] 0.3*|V1-V3|≤|V2-V3|≤ 0.7*|V1-V3|.

[0040] Furthermore, using the third voltage V3 as a reference zero potential, the VFD driver chip is used to output the voltage required by each conductive region on the first conductive layer and / or the second conductive layer.

[0041] As an optional solution, the voltages applied to the first and second conductive layers are interchanged according to a set time rule to prevent liquid crystal passivation.

[0042] As an optional solution, the first conductive layer and the second conductive layer are each divided into multiple parallel strip-shaped conductive regions, and the strip-shaped conductive regions on the first conductive layer and the strip-shaped conductive regions on the second conductive layer are spatially perpendicular to each other.

[0043] In other embodiments, the following technical solutions are adopted:

[0044] An apparatus for implementing the above-described method for applying a partial erasure voltage to a liquid crystal writing device includes:

[0045] A voltage generating circuit that generates at least two voltages required for erasure;

[0046] An X-direction voltage selection circuit connected to a voltage generation circuit, wherein the X-direction voltage selection circuit selects at least one voltage output from the circuit generated by the voltage generation circuit;

[0047] The X-direction VFD driver chip is connected to the X-direction voltage selection circuit. The output voltage of the X-direction voltage selection circuit is input to the X-direction VFD driver chip, and the X-direction VFD driver chip applies the required voltage to each conductive region in the X-direction.

[0048] A Y-direction voltage selection circuit connected to a voltage generation circuit, wherein the Y-direction voltage selection circuit selects at least one voltage output from the circuit generated by the voltage generation circuit;

[0049] The Y-direction VFD driver chip is connected to the Y-direction voltage selection circuit. The output voltage of the Y-direction voltage selection circuit is input to the Y-direction VFD driver chip, and the Y-direction VFD driver chip applies the required voltage to each conductive region in the Y direction.

[0050] The main controller is connected to the voltage generation circuit, the X-direction voltage selection circuit, the X-direction VFD drive chip, the Y-direction voltage selection circuit, and the Y-direction VFD drive chip, respectively.

[0051] In other embodiments, the following technical solutions are adopted:

[0052] A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions, the method comprising:

[0053] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0054] A third voltage V3 is applied to the conductive area covering the target erasure area on the first conductive layer, and a first voltage V1 is applied to the other conductive areas of the first conductive layer;

[0055] A first voltage V1 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0056] The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0057] |V1-V3|>Vst;

[0058] |V2-V3| <Vst;

[0059] |V2-V1| <Vst;

[0060] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0061] This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

[0062] As an optional approach, firstly, a second voltage V2 is applied to the conductive area covering the target erasure area on the first conductive layer, and a first voltage V1 is applied to other conductive areas on the first conductive layer.

[0063] A first voltage V1 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0064] Then, the voltage of the conductive area covering the target erasure area on the first conductive layer is adjusted to the third voltage V3.

[0065] In other embodiments, the following technical solutions are adopted:

[0066] A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions, the method comprising:

[0067] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0068] A third voltage V3 is applied to the conductive area covering the target erasure area on the second conductive layer, and a first voltage V1 is applied to the other conductive areas of the second conductive layer;

[0069] A first voltage V1 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0070] The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0071] |V1-V3|>Vst;

[0072] |V2-V3| <Vst;

[0073] |V2-V1| <Vst;

[0074] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0075] This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

[0076] As an optional approach, firstly, a second voltage V2 is applied to the conductive area covering the target erasure area on the second conductive layer, and a first voltage V1 is applied to other conductive areas on the second conductive layer.

[0077] A first voltage V1 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0078] Then, the voltage of the conductive area covering the target erasure area on the second conductive layer is adjusted to the third voltage V3.

[0079] As an optional solution, the first voltage V1, the second voltage V2, and the third voltage V3 further satisfy:

[0080] 0.3*|V3-V1| ≤|V2-V1|≤0.7*|V3-V1|.

[0081] Furthermore, when the first voltage V1, the second voltage V2, and the third voltage V3 simultaneously meet the following requirements:

[0082] V1 > 0; V2 < 0; V3 < 0;

[0083] Use an STN liquid crystal driver chip to output the voltage required for each conductive region on the first conductive layer and / or the second conductive layer.

[0084] As an optional solution, the voltages applied to the first and second conductive layers are interchanged according to a set time rule to prevent liquid crystal passivation.

[0085] As an optional solution, the first conductive layer and the second conductive layer are each divided into multiple parallel strip-shaped conductive regions, and the strip-shaped conductive regions on the first conductive layer and the strip-shaped conductive regions on the second conductive layer are spatially perpendicular to each other.

[0086] In other embodiments, the following technical solutions are adopted:

[0087] An apparatus for implementing the above-described method for applying a partial erasure voltage to a liquid crystal writing device includes:

[0088] A negative voltage generating circuit that generates at least one negative voltage as required.

[0089] A voltage generating circuit connected to the negative voltage generating circuit generates at least two voltages based on the negative voltage and inputs them to the X-direction STN liquid crystal driving chip and the Y-direction STN liquid crystal driving chip, respectively.

[0090] The X-direction STN liquid crystal driver chip applies the required voltage to each conductive region in the X direction;

[0091] The Y-direction STN liquid crystal driver chip applies the required voltage to each conductive region in the Y direction.

[0092] The main controller is connected to the negative pressure generation circuit, the voltage generation circuit, the X-direction STN LCD driver chip, and the Y-direction STN LCD driver chip, respectively.

[0093] In other embodiments, the following technical solutions are adopted:

[0094] A liquid crystal writing film includes a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions; it also includes: using the above-mentioned liquid crystal writing device local erasing voltage application method to achieve local erasing.

[0095] In other embodiments, the following technical solutions are adopted:

[0096] A liquid crystal writing device includes the liquid crystal writing film described above.

[0097] Compared with the prior art, the beneficial effects of the present invention are:

[0098] (1) When performing partial erasure, the present invention can ensure that the voltage difference between the upper and lower conductive layers corresponding to the non-erasure area is zero in the row (or column) where the target erasure area is located by reasonably setting the voltage required to be applied to the target erasure area and the non-erasure area. Therefore, these areas will not be affected by the magnitude of the erasure voltage. Even if the erasure voltage is not set properly, the writing content in these areas will not become lighter or disappear due to the influence of the erasure voltage.

[0099] (2) When performing partial erasure, the present invention applies two different voltages to the first conductive layer and the second conductive layer respectively, and one of the voltages applied to the upper and lower conductive layers is the same; therefore, the present invention only requires three voltages to achieve partial erasure, which simplifies the design cost and maintenance difficulty of the product.

[0100] (3) The present invention can achieve that there is a zero voltage in both the voltage applied to the first conductive layer and the second conductive layer. Under the premise that the applied voltage is positive, both conductive layers can directly output the zero voltage and the other voltage through the VFD driver chip. At this time, the required voltage can be directly output by the VFD driver chip without the need to connect additional auxiliary components such as optocouplers and isolation transformers. This greatly simplifies the complexity of the voltage circuit and reduces production and maintenance costs.

[0101] Other features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0102] Figure 1This is a schematic diagram of a partial erasure voltage application method for a liquid crystal writing device in Embodiment 1 of the present invention;

[0103] Figure 2 This is a schematic diagram of the steady voltage increase process in Embodiment 1 of the present invention;

[0104] Figure 3 This is a schematic diagram of the voltage driving circuit structure of the VFD driving chip used in Embodiment 1 of the present invention;

[0105] Figure 4 This is a schematic diagram of the X-direction voltage selection circuit structure in Embodiment 1 of the present invention;

[0106] Figure 5 This is another schematic diagram of the partial erasure voltage application method of the liquid crystal writing device in Embodiment 1 of the present invention;

[0107] Figure 6 This is a schematic diagram of a specific voltage application method in Embodiment 1 of the present invention;

[0108] Figure 7 This is a schematic diagram of a partial erasure voltage application method for a liquid crystal writing device in Embodiment 2 of the present invention;

[0109] Figure 8 This is a schematic diagram of the voltage driving circuit structure of the STN liquid crystal driving chip used in Embodiment 2 of the present invention;

[0110] Figure 9 for Figure 8 A schematic diagram of the voltage application method corresponding to the circuit in the middle;

[0111] Figure 10 This is a schematic diagram of a specific voltage application method in Embodiment 2 of the present invention. Detailed Implementation

[0112] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0113] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0114] Example 1

[0115] In one or more embodiments, a method for applying a partial erasure voltage to a liquid crystal writing device is disclosed. The liquid crystal writing device includes a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom. The first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions.

[0116] As a specific example, this embodiment illustrates that the first conductive layer is divided into multiple mutually insulated and parallel longitudinal strip-shaped conductive regions (Y-direction conductive regions), and the second conductive layer is divided into multiple mutually insulated and parallel transverse strip-shaped conductive regions (X-direction conductive regions). Of course, the specific shape of the conductive regions can be set according to actual needs. For example, the second conductive layer can be divided into longitudinal conductive regions, and the first conductive layer into transverse conductive regions; or, the conductive regions can be set into strip shapes or U-shapes, etc.

[0117] The specific method for applying the local erasure voltage in this embodiment is as follows:

[0118] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0119] A first voltage V1 is applied to the conductive area covering the target erasure area on the first conductive layer, and a third voltage V3 is applied to other conductive areas of the first conductive layer;

[0120] A third voltage V3 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0121] Among them, the first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0122] |V1-V3|>Vst;

[0123] |V3-V2| <Vst;

[0124] |V1-V2| <Vst;

[0125] Vst is the erase-start voltage of cholesteric liquid crystal, which is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state.

[0126] This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

[0127] As a preferred embodiment, the first voltage V1, the second voltage V2, and the third voltage V3 further satisfy the following:

[0128] 0.3*|V1-V3|≤|V2-V3|≤ 0.7*|V1-V3|.

[0129] It should be noted that due to measurement errors or the influence of the electrical properties of the measured object itself (such as resistance, parasitic capacitance, etc.), the above range may have an error within ±10%. Voltage values ​​within the above error range are still within the protection scope of this patent, and the same applies to the following.

[0130] This results in a significant difference between the voltage difference between the upper and lower conductive layers in the target erasure area and the voltage difference between the upper and lower conductive layers in the non-erasure area, allowing for a wider range of erase voltage options and facilitating the selection of the optimal erase voltage to improve the erasure speed.

[0131] In this embodiment, it is assumed that the first voltage V1 is 2Va, the second voltage V2 is Va, and the third voltage V3 is 0; Va > 0; at this time, it satisfies: |2Va| > Vst; and |Va| < Vst.

[0132] At this time, combined Figure 1 The specific method for applying the voltage is as follows:

[0133] A voltage of 2Va is applied to the conductive area covering the target erasure area on the first conductive layer, and a zero voltage is applied to the other conductive areas on the first conductive layer; a zero voltage is applied to the conductive area covering the target erasure area on the second conductive layer, and a voltage Va is applied to the other conductive areas on the second conductive layer.

[0134] In this way, the voltage difference between the upper and lower conductive layers of the entire liquid crystal writing film satisfies the following conditions: the voltage difference between the upper and lower conductive layers corresponding to the target erasure area is 2Va; in the row containing the target erasure area, the voltage difference in other areas besides the target erasure area is 0; and the voltage difference in the remaining areas is Va or -Va. At this time, only the written content corresponding to the target erasure area with a voltage difference of 2Va is erased, and the voltage difference in other areas of the row containing the target erasure area is 0, so the corresponding written content is completely unaffected by the erasure voltage.

[0135] In some implementations, due to the limited energy of the output current of the driving circuit and the influence of the capacitance effect of the liquid crystal writing film, it is difficult for the voltage applied during the boost or buck process to reach the set target voltage value in a short time. Therefore, during the boost or buck process, the entire strip-shaped conductive area covering the target erasure area may become lighter or disappear due to the influence of the erasure voltage.

[0136] To avoid the aforementioned problems, as an optional solution, this embodiment employs a steady voltage increase or decrease during the voltage increase or decrease process to reduce the impact of the capacitance effect of the liquid crystal writing film; and during the steady voltage increase process, the written content will not fade or disappear due to the influence of the erasure voltage; combined with Figure 2 The specific process is as follows:

[0137] The explanation will still be based on the assumption that the first voltage V1 is 2Va, the second voltage V2 is Va, and the third voltage V3 is 0.

[0138] First, apply Va to the conductive area covering the target erasure area on the first conductive layer, and apply zero voltage to the other conductive areas on the first conductive layer; apply zero voltage to the conductive area covering the target erasure area on the second conductive layer, and apply Va to the other conductive areas on the second conductive layer; at this time, none of the areas are erased.

[0139] Then, the voltage of the conductive area covering the target erasure area on the first conductive layer is adjusted to a first voltage of 2Va, at which point the written content of the target erasure area is erased.

[0140] By increasing the erasure voltage corresponding to the target erasure area to the target voltage value through the above two processes, the influence of the capacitance effect of the liquid crystal writing film is reduced, and the writing content corresponding to areas other than the target erasure area is avoided from being affected during the voltage application process.

[0141] As a preferred example, considering that the VFD driver chip can only directly output two voltages, one of which is zero voltage; and the solution in this embodiment, by reasonably selecting the voltage, can satisfy the following: both voltages applied to the conductive layers contain one zero voltage, that is: one of the two voltages applied to the first conductive layer is zero voltage; and one of the two voltages applied to the second conductive layer is zero voltage. Therefore, the voltage for partial erasure in this embodiment can be directly output by the VFD driver chip.

[0142] The following explanation uses the example of applying a voltage to each X-direction conductive region on the second conductive layer:

[0143] Figure 3 A schematic diagram of the voltage driving circuit using a VFD driver chip corresponding to the second conductive layer is given, specifically including:

[0144] A voltage generation circuit is used to generate at least two voltages required for erasure.

[0145] An X-direction voltage selection circuit connected to a voltage generation circuit selects at least one voltage output from the voltage generated by the voltage generation circuit.

[0146] The X-direction VFD driver chip is connected to the X-direction voltage selection circuit. The output voltage of the X-direction voltage selection circuit is input to the X-direction VFD driver chip, and the X-direction VFD driver chip applies the required voltage to each conductive region in the X-direction.

[0147] A Y-direction voltage selection circuit connected to a voltage generation circuit selects at least one voltage output from the voltage generated by the voltage generation circuit.

[0148] The Y-direction VFD driver chip is connected to the Y-direction voltage selection circuit. The output voltage of the Y-direction voltage selection circuit is input to the Y-direction VFD driver chip, and the Y-direction VFD driver chip applies the required voltage to each conductive region in the Y direction.

[0149] The main controller is connected to the voltage generation circuit, the X-direction voltage selection circuit, the X-direction VFD drive chip, the Y-direction voltage selection circuit, and the Y-direction VFD drive chip, respectively.

[0150] Combination Figure 3 The specific working principle is as follows: The MCU outputs two PWM signals to the voltage generation circuit. The voltage generation circuit generates two voltages, Va and 2Va, respectively, through the two PWM signals. The MCU then outputs an enable signal to the X-direction voltage selection circuit. If the enable signal is 1, the X-direction voltage selection circuit outputs 2Va; if the enable signal is 0, the voltage selection circuit outputs Va. As a specific example, the structure of the X-direction voltage selection circuit is as follows: Figure 4 As shown, the output of the Xs enable signal is controlled by the MCU. When Xs=1, transistors Q1 and Q2 are turned on, and the output of the voltage selection circuit is X. VH =2Va; When Xs=0, diode D1 conducts, and the output of the voltage selection circuit is X VH =Va. Output X of the voltage selection circuit VH The signal is transmitted to the X-direction VFD driver chip, which, under the control of the MCU, outputs voltage X to different X-direction conductive regions on the second conductive layer. VH Or 0.

[0151] In this embodiment, the voltage generation circuit, voltage selection circuit, and VFD driver chip are all implemented using existing structures. For example, the specific model of the VFD driver chip can be PT6392. Of course, in addition to the VFD driver chip, other chips with similar functions that can output zero voltage and positive voltage and meet actual driving requirements can also be used.

[0152] The voltage driving circuit structure and principle corresponding to the first conductive layer are the same as those described above, and will not be repeated here.

[0153] This embodiment can directly output the voltage required for partial erasure through the VFD driver chip, without the need for other additional electronic components, which greatly simplifies the circuit structure, reduces maintenance difficulty, and saves production costs.

[0154] As an optional example, in the various examples above, the voltages applied to the first conductive layer and the second conductive layer are interchanged according to a set time rule, so that the electric field formed on the entire liquid crystal writing film has the same magnitude but opposite direction, in order to avoid the polarization phenomenon of liquid crystal caused by applying an electric field in the same direction to the liquid crystal writing film for a long time.

[0155] Figure 5 A schematic diagram of a partial erase voltage application method is given as another example of voltage loading. In this example, it is assumed that the first voltage V1 is 0, the second voltage V2 is -Va, and the third voltage V3 is -2 Va, where Va > 0. The corresponding voltage application method is as follows:

[0156] Zero voltage is applied to the conductive area covering the target erasure area on the first conductive layer, and -2Va is applied to the other conductive areas on the first conductive layer; -2Va is applied to the conductive area covering the target erasure area on the second conductive layer, and -Va is applied to the other conductive areas on the second conductive layer.

[0157] This example can also use the steady boost and voltage swapping process described above, which will not be detailed here.

[0158] As a more concrete example, Figure 6 A specific voltage application strategy is given, namely: first voltage = 5V, second voltage = 0V, and third voltage = -5V.

[0159] A first voltage of 5V is applied to the conductive area covering the target erasure area on the first conductive layer, and a third voltage of -5V is applied to the other conductive areas of the first conductive layer;

[0160] A third voltage of -5V is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage of 0V is applied to other conductive areas on the second conductive layer.

[0161] At this point, only the writing in the target erasure area is completely erased, while the writing in other areas remains unchanged.

[0162] This voltage application method reduces the amount of voltage required for local erasure, while ensuring that the voltage difference between other areas in the same row as the target erasure area is zero, so that the corresponding written content is completely unaffected by the erasure voltage.

[0163] Example 2

[0164] In one or more embodiments, a method for applying a partial erasure voltage to a liquid crystal writing device is disclosed. The implementation process and principle of this embodiment are completely identical to those in Embodiment 1, and will not be described in detail again; the only difference is that the voltages applied to the first conductive layer and the second conductive layer are interchanged, i.e.:

[0165] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0166] A first voltage V1 is applied to the conductive area covering the target erasure area on the second conductive layer, and a third voltage V3 is applied to other conductive areas of the second conductive layer;

[0167] A third voltage V3 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0168] The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0169] |V1-V3|>Vst;

[0170] |V3-V2| <Vst;

[0171] |V1-V2| <Vst;

[0172] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0173] This allows for the erasure of written content at the corresponding location within the target erasure area.

[0174] In a preferred embodiment, firstly, a second voltage V2 is applied to the conductive area covering the target erasure area on the second conductive layer, and a third voltage V3 is applied to other conductive areas on the second conductive layer; then, the third voltage V3 is applied to the conductive area covering the target erasure area on the first conductive layer, and the second voltage V2 is applied to other conductive areas on the first conductive layer.

[0175] Then, the voltage of the conductive area covering the target erasure area on the second conductive layer is adjusted to the first voltage V1.

[0176] The specific implementation effect is exactly the same as in Example 1, and will not be described in detail again.

[0177] Example 3

[0178] In one or more embodiments, a method for applying a partial erasure voltage to a liquid crystal writing device is disclosed. The structure of the liquid crystal writing device is exactly the same as that in Embodiment 1, and will not be described in detail here.

[0179] The specific method for applying the local erasure voltage in this embodiment is as follows:

[0180] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0181] A third voltage V3 is applied to the conductive area covering the target erasure area on the first conductive layer, and a first voltage V1 is applied to the other conductive areas of the first conductive layer;

[0182] A first voltage V1 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0183] Among them, the first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0184] |V1-V3|>Vst;

[0185] |V2-V3| <Vst;

[0186] |V2-V1| <Vst;

[0187] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0188] This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

[0189] As a preferred embodiment, the first voltage V1, the second voltage V2, and the third voltage V3 further satisfy the following:

[0190] 0.3*|V3-V1| ≤|V2-V1| ≤0.7*|V3-V1|.

[0191] In this embodiment, it is assumed that the first voltage V1 is 0, the second voltage V2 is -Va, and the third voltage V3 is -2Va; Va>0; at this time, it satisfies: |-2Va|>Vst; and |-Va|<Vst.

[0192] At this time, combined Figure 7 The specific method for applying the voltage is as follows:

[0193] -2Va is applied to the conductive area covering the target erasure area on the first conductive layer, and zero voltage is applied to the other conductive areas on the first conductive layer; zero voltage is applied to the conductive area covering the target erasure area on the second conductive layer, and -Va is applied to the other conductive areas on the second conductive layer.

[0194] In this way, the voltage difference between the upper and lower conductive layers of the entire liquid crystal writing film satisfies the following conditions: the voltage difference between the upper and lower conductive layers corresponding to the target erasure area is -2Va; in the row containing the target erasure area, the voltage difference in other areas besides the target erasure area is 0; and the voltage difference in the remaining areas is Va or -Va. At this time, only the written content corresponding to the target erasure area with a voltage difference of 2Va is erased, and the voltage difference in other areas of the row containing the target erasure area is 0, so the corresponding written content is completely unaffected by the erasure voltage.

[0195] Similarly, to avoid the influence of the capacitance effect of the liquid crystal writing film, this embodiment also adopts a steady voltage boost or steady voltage buck method to reduce the impact of the liquid crystal writing film capacitance effect; the specific process is as follows:

[0196] First, a second voltage V2 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a first voltage V1 is applied to other conductive areas on the first conductive layer.

[0197] A first voltage V1 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer.

[0198] Then, the voltage of the conductive area covering the target erasure area on the first conductive layer is adjusted to the third voltage V3.

[0199] The specific effects are the same as in Example 1, and will not be described in detail again.

[0200] As a preferred example, considering that the STN liquid crystal driver chip can directly output negative voltage, when the first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy: V1 > 0; V2 < 0; V3 < 0, the STN liquid crystal driver chip can be used to directly output the voltage required by each conductive region on the first and second conductive layers.

[0201] The voltage drive circuit structure using STN LCD driver chips is as follows: Figure 8 As shown, it specifically includes:

[0202] A negative voltage generating circuit is used to generate at least one negative voltage.

[0203] A voltage generating circuit connected to the negative voltage generating circuit generates at least two voltages based on the generated negative voltage, and inputs them to the STN liquid crystal driver chip in the X direction and the STN liquid crystal driver chip in the Y direction, respectively.

[0204] The X-direction STN liquid crystal driver chip applies the required voltage to each conductive region in the X direction;

[0205] The Y-direction STN liquid crystal driver chip applies the required voltage to each conductive region in the Y direction.

[0206] The main controller is connected to the negative pressure generation circuit, the voltage generation circuit, the X-direction STN LCD driver chip, and the Y-direction STN LCD driver chip, respectively.

[0207] Combination Figure 8 The specific working process of the voltage driving circuit using the STN LCD driver chip is as follows: The negative voltage generation circuit is controlled by the MCU to output a negative voltage V. EE negative voltage V EE The input is sent to the voltage generation circuit. The MCU sends an enable signal to the voltage generation circuit. When the enable signal is 1, the voltage generation circuit can output a negative voltage V. E1 and negative voltage V E2 Then, according to actual needs, the negative voltage V E1 V input to the STN LCD driver chip in the X direction 12 and V 34 The V0 pin of the X-direction STN LCD driver chip is connected to the power supply Vcc. At this point, the MCU can control the X-direction STN LCD driver chip to output Vcc and V... E1 Two voltages are applied to different X-direction conductive regions on the second conductive layer; a negative voltage V is applied. E2 V input to the STN LCD driver chip in the Y direction 12 and V 34 The V0 pin of the Y-direction STN LCD driver chip is connected to the power supply Vcc. At this point, the MCU can control the Y-direction STN LCD driver chip to output Vcc and V... E2 Two voltages are applied to different Y-direction conductive regions on the first conductive layer.

[0208] In this embodiment, the negative voltage generation circuit, voltage generation circuit, and STN liquid crystal driver chip are all implemented using existing structures. For example, the STN liquid crystal driver chip can be an SDN8008. Of course, in addition to the STN liquid crystal driver chip, chips with similar performance and negative voltage output functions can also be used.

[0209] Assuming that Vcc and V are related according to voltage magnitude E1 and V E2 The order is as follows: Vcc > V E1 >V E2 And Vcc > 0, V E1 <0, V E2 <0; if the following conditions are met:

[0210] |V e2 -Vcc|>Vst; and|V e2 -Ve1 | <Vst; |Vcc-V e1 | <Vst.

[0211] This allows for localized erasure.

[0212] Combination Figure 9 The specific voltage application method is as follows:

[0213] Apply V to the conductive area covering the target erasure area on the first conductive layer. e2 Vcc is applied to other conductive areas of the first conductive layer; Vcc is applied to the conductive areas on the second conductive layer that cover the target erasure area, and V is applied to other conductive areas on the second conductive layer. e1 .

[0214] As a preferred option, the above voltage can be further satisfied as follows:

[0215] 0.3*|V e2 - Vcc|≤|Vcc -V e1 |≤ 0.7*|V e2 - Vcc|.

[0216] In this embodiment, the preferred value is 0.5*|V e2 - Vcc |= | Vcc -V e1 |, that is, Vcc-V e1= V e1- V e2 .

[0217] This embodiment can directly output the voltage required for partial erasure using the STN liquid crystal driver chip, without the need for other additional electronic components, which greatly simplifies the circuit structure, reduces maintenance difficulty, and saves production costs.

[0218] As a more concrete example, Figure 10 A specific voltage application strategy is given, namely: first voltage = 5V, second voltage = 0V, and third voltage = -5V.

[0219] A third voltage of -5V is applied to the conductive area covering the target erasure area on the first conductive layer, and a first voltage of 5V is applied to the other conductive areas of the first conductive layer.

[0220] A first voltage of 5V is applied to the conductive area covering the target erasure area on the second conductive layer, and a second voltage of 0V is applied to other conductive areas on the second conductive layer.

[0221] At this point, only the writing in the target erasure area is completely erased, while the writing in other areas remains unchanged.

[0222] As a preferred example, the voltages applied to the first and second conductive layers are interchanged according to a set time rule, so that the electric field formed on the entire liquid crystal writing film has the same magnitude but opposite direction, in order to avoid the polarization phenomenon of liquid crystal caused by applying an electric field in the same direction to the liquid crystal writing film for a long time.

[0223] Example 4

[0224] In one or more embodiments, a method for applying a partial erasure voltage to a liquid crystal writing device is disclosed. The implementation process and principle of this embodiment are completely identical to those in Embodiment 3, and will not be described in detail again; the only difference is that the voltages applied to the first conductive layer and the second conductive layer are interchanged, i.e.:

[0225] Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3;

[0226] A third voltage V3 is applied to the conductive area covering the target erasure area on the second conductive layer, and a first voltage V1 is applied to the other conductive areas of the second conductive layer;

[0227] A first voltage V1 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0228] The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy:

[0229] |V1-V3|>Vst;

[0230] |V2-V3| <Vst;

[0231] |V2-V1| <Vst;

[0232] Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state;

[0233] This allows for the erasure of written content at the corresponding location within the target erasure area.

[0234] In a preferred embodiment, firstly, a second voltage V2 is applied to the conductive area covering the target erasure area on the second conductive layer, and a first voltage V1 is applied to other conductive areas on the second conductive layer;

[0235] A first voltage V1 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer.

[0236] Then, the voltage of the conductive area covering the target erasure area on the second conductive layer is adjusted to the third voltage V3.

[0237] The specific effect is the same as in Example 3.

[0238] Example 5

[0239] In one or more embodiments, a liquid crystal writing film is disclosed, comprising a first conductive layer, a cholesteric liquid crystal layer and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into a plurality of mutually insulated conductive regions.

[0240] In this embodiment, the writing film adopts any one of the partial erasure voltage application methods of the liquid crystal writing device in Embodiments 1 to 4 to achieve partial erasure.

[0241] The liquid crystal writing film of this embodiment can be applied to liquid crystal products such as blackboards, drawing boards, and writing boards to simplify circuit structures and reduce production costs.

[0242] Example 6

[0243] In one or more embodiments, a liquid crystal writing device is disclosed, including the liquid crystal writing film described in Embodiment 5.

[0244] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions, characterized in that the method... include: Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3; A first voltage V1 is applied to the conductive area covering the target erasure area on the first conductive layer, and a third voltage V3 is applied to other conductive areas of the first conductive layer; A third voltage V3 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer. The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy: |V1-V3|>Vst; |V3-V2| <Vst; |V1-V2| <Vst; Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state; This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

2. The method for applying a partial erasure voltage to a liquid crystal writing device as described in claim 1, characterized in that, First, a second voltage V2 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a third voltage V3 is applied to other conductive areas on the first conductive layer. A third voltage V3 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer. Then, the voltage of the conductive area covering the target erasure area on the first conductive layer is adjusted to the first voltage V1.

3. A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into multiple mutually insulated conductive regions, characterized in that the method... include: Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3; A first voltage V1 is applied to the conductive area covering the target erasure area on the second conductive layer, and a third voltage V3 is applied to other conductive areas of the second conductive layer; A third voltage V3 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer. The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy: |V1-V3|>Vst; |V3-V2| <Vst; |V1-V2| <Vst; Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state; This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

4. The method for applying a partial erasure voltage to a liquid crystal writing device as described in claim 3, characterized in that, First, a second voltage V2 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a third voltage V3 is applied to other conductive areas on the second conductive layer. A third voltage V3 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer. Then, the voltage of the conductive area covering the target erasure area on the second conductive layer is adjusted to the first voltage V1.

5. A method for applying a partial erasure voltage to a liquid crystal writing device as described in any one of claims 1-4, characterized in that, The first voltage V1, the second voltage V2, and the third voltage V3 further satisfy: 0.3*|V1-V3|≤|V2-V3|≤ 0.7*|V1-V3|.

6. The method for applying a partial erasure voltage to a liquid crystal writing device as described in claim 5, characterized in that, Using the third voltage V3 as a reference zero potential, the VFD driver chip outputs the voltage required by each conductive region on the first conductive layer and / or the second conductive layer.

7. A method for applying a partial erasure voltage to a liquid crystal writing device as described in any one of claims 1-4, characterized in that, The voltages applied to the first and second conductive layers are interchanged according to a set time rule to prevent liquid crystal passivation.

8. A method for applying a partial erasure voltage to a liquid crystal writing device as described in any one of claims 1-4, characterized in that, The first conductive layer and the second conductive layer are each divided into multiple parallel strip-shaped conductive regions, and the strip-shaped conductive regions on the first conductive layer and the strip-shaped conductive regions on the second conductive layer are spatially perpendicular to each other.

9. An apparatus for implementing the partial erasure voltage application method of the liquid crystal writing device according to any one of claims 1-4, characterized in that, include: A voltage generating circuit that generates at least two voltages required for erasure; An X-direction voltage selection circuit connected to a voltage generation circuit, wherein the X-direction voltage selection circuit selects at least one voltage output from the circuit generated by the voltage generation circuit; The X-direction VFD driver chip is connected to the X-direction voltage selection circuit. The output voltage of the X-direction voltage selection circuit is input to the X-direction VFD driver chip, and the X-direction VFD driver chip applies the required voltage to each conductive region in the X-direction. A Y-direction voltage selection circuit connected to a voltage generation circuit, wherein the Y-direction voltage selection circuit selects at least one voltage output from the circuit generated by the voltage generation circuit; The Y-direction VFD driver chip is connected to the Y-direction voltage selection circuit. The output voltage of the Y-direction voltage selection circuit is input to the Y-direction VFD driver chip, and the Y-direction VFD driver chip applies the required voltage to each conductive region in the Y direction. The main controller is connected to the voltage generation circuit, the X-direction voltage selection circuit, the X-direction VFD drive chip, the Y-direction voltage selection circuit, and the Y-direction VFD drive chip, respectively.

10. A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into a plurality of mutually insulated conductive regions, characterized in that the method... include: Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3; A third voltage V3 is applied to the conductive area covering the target erasure area on the first conductive layer, and a first voltage V1 is applied to the other conductive areas of the first conductive layer; A first voltage V1 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer. The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy: |V1-V3|>Vst; |V2-V3| <Vst; |V2-V1| <Vst; Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state; This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

11. The method for applying a partial erasure voltage to a liquid crystal writing device as described in claim 10, characterized in that, First, a second voltage V2 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a first voltage V1 is applied to other conductive areas on the first conductive layer. A first voltage V1 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the second conductive layer. Then, the voltage of the conductive area covering the target erasure area on the first conductive layer is adjusted to the third voltage V3.

12. A method for applying a partial erasure voltage to a liquid crystal writing device, the liquid crystal writing device comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into a plurality of mutually insulated conductive regions, characterized in that the method... include: Set three voltages that satisfy the following condition: first voltage V1 > second voltage V2 > third voltage V3; A third voltage V3 is applied to the conductive area covering the target erasure area on the second conductive layer, and a first voltage V1 is applied to the other conductive areas of the second conductive layer; A first voltage V1 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer. The first voltage V1, the second voltage V2, and the third voltage V3 simultaneously satisfy: |V1-V3|>Vst; |V2-V3| <Vst; |V2-V1| <Vst; Wherein, Vst is the erasure initiation voltage of the cholesteric liquid crystal, and the erasure initiation voltage is the voltage that enables some liquid crystal molecules to begin changing from the planar state to the focal conic state; This allows for the erasure of written content at the corresponding location within the target erasure area, while leaving written content in other areas unchanged.

13. The method for applying a partial erasure voltage to a liquid crystal writing device as described in claim 12, characterized in that, First, a second voltage V2 is applied to the conductive area on the second conductive layer that covers the target erasure area, and a first voltage V1 is applied to other conductive areas on the second conductive layer. A first voltage V1 is applied to the conductive area on the first conductive layer that covers the target erasure area, and a second voltage V2 is applied to other conductive areas on the first conductive layer. Then, the voltage of the conductive area covering the target erasure area on the second conductive layer is adjusted to the third voltage V3.

14. A method for applying a partial erasure voltage to a liquid crystal writing device as described in any one of claims 10-13, characterized in that, The first voltage V1, the second voltage V2, and the third voltage V3 further satisfy: 0.3*|V3-V1| ≤|V2-V1|≤0.7*|V3-V1|.

15. The method for applying a partial erasure voltage to a liquid crystal writing device as described in claim 14, characterized in that, When the first voltage V1, the second voltage V2, and the third voltage V3 simultaneously meet the following requirements: V1 > 0; V2 < 0; V3 < 0; Use an STN liquid crystal driver chip to output the voltage required for each conductive region on the first conductive layer and / or the second conductive layer.

16. A method for applying a partial erasure voltage to a liquid crystal writing device as described in any one of claims 10-13, characterized in that, The voltages applied to the first and second conductive layers are interchanged according to a set time rule to prevent liquid crystal passivation.

17. A method for applying a partial erasure voltage to a liquid crystal writing device as described in any one of claims 10-13, characterized in that, The first conductive layer and the second conductive layer are each divided into multiple parallel strip-shaped conductive regions, and the strip-shaped conductive regions on the first conductive layer and the strip-shaped conductive regions on the second conductive layer are spatially perpendicular to each other.

18. An apparatus for implementing the partial erasure voltage application method of the liquid crystal writing device according to any one of claims 10-13, characterized in that, include: A negative voltage generating circuit that generates at least one negative voltage as required. A voltage generating circuit connected to the negative voltage generating circuit generates at least two voltages based on the negative voltage and inputs them to the X-direction STN liquid crystal driving chip and the Y-direction STN liquid crystal driving chip, respectively. The X-direction STN liquid crystal driver chip applies the required voltage to each conductive region in the X direction. The Y-direction STN liquid crystal driver chip applies the required voltage to each conductive region in the Y direction. The main controller is connected to the negative pressure generation circuit, the voltage generation circuit, the X-direction STN LCD driver chip, and the Y-direction STN LCD driver chip, respectively.

19. A liquid crystal writing film, comprising a first conductive layer, a cholesteric liquid crystal layer, and a second conductive layer disposed sequentially from top to bottom, wherein the first conductive layer and the second conductive layer are respectively divided into a plurality of mutually insulated conductive regions; characterized in that, It also includes: using the partial erasure voltage application method of the liquid crystal writing device according to any one of claims 1-8 or 10-17 to achieve partial erasure.

20. A liquid crystal writing device, characterized in that, Includes the liquid crystal writing film as described in claim 19.

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