Voltage regulator circuit, method for regulating voltage and power transmission system

Abstract

The invention relates to a voltage regulator circuit, a method for regulating voltage and a power transmission system. A voltage regulator is described for high power transfer applications, including notebook computers, supercomputers, and electric vehicles. The voltage regulator is configured with multi-phase current and constant on-time (COT) control. In response to a dynamic load, the voltage regulator may be configured with adaptive on-time control of subshoots in the output voltage signal. The multi-phase current source may be configured with an adjustable current sharing gain to provide a democratic current balancing approach. Methods of operating the voltage regulator may be compatible with analog, digital, and hybrid implementations.

Description

Technical Field

[0001] The present specification relates to a voltage regulator circuit in a power delivery system for industrial and automotive core applications. More particularly, the present specification relates to a voltage regulator circuit including a multi-phase current source system with constant on-time control. Background Art

[0002] Power converters may be used, for example, in automotive systems to convert a high voltage (e.g., 400V) supplied by an electric vehicle (EV) battery to a lower voltage (e.g., 12V or 5V) for powering auxiliary devices such as sensors, dashboard electronics, multimedia systems, power windows, LED lighting, etc. Known power converters may not have features that are well suited for certain applications. Summary of the invention

[0003] In some aspects, the technology described herein relates to a circuit comprising: a multi-phase current source, the multi-phase current source comprising: a first current loop, the first current loop configured to drive a first inductor with a first drive signal at a first switching frequency; a second current loop, the second current loop configured to drive a second inductor with a second drive signal at a second switching frequency; and a voltage loop, the voltage loop comprising a constant on-time (COT) control stage, the COT control stage configured to provide a control signal having a leading edge modulation based on a voltage error and a trailing edge modulation based on a current sharing error.

[0004] In some aspects, the techniques described herein relate to a circuit in which pulse width modulated (PWM) drive signals are out of phase with each other in a multi-phase application.

[0005] In some aspects, the techniques described herein relate to a circuit configured as a buck voltage regulator circuit in which an output voltage is less than an input voltage.

[0006] In some aspects, the technology described herein relates to a circuit in which an input voltage is in a range of about 5V to about 21V, and an output voltage is in a range of about 0.2V to about 3.3V.

[0007] In some aspects, the techniques described herein relate to a circuit configured as a boost voltage regulator circuit in which an output voltage is greater than an input voltage.

[0008] In some aspects, the techniques described herein relate to a circuit in which an output voltage signal is configured to achieve a zero undershoot response in a drooping system when a multiphase current source is coupled to a dynamic load.

[0009] In some aspects, the techniques described herein relate to a circuit wherein the multiphase current source further includes a non-hosted current sharing loop configured to provide trailing edge current error correction.

[0010] In some aspects, the techniques described herein relate to a circuit in which a COT control stage includes an integrator.

[0011] In some aspects, the techniques described herein relate to a circuit in which a COT control stage includes a trigger ramp.

[0012] In some aspects, the techniques described herein relate to a circuit in which a COT control stage is configured to provide control pulses that are out of phase with each other.

[0013] In some aspects, the techniques described herein relate to a circuit in which a current sharing loop gain of the circuit is dynamically adjustable based on an error signal level.

[0014] In some aspects, the techniques described herein relate to a circuit in which a current sharing loop gain of the circuit is a portion of a Ton ramp.

[0015] In some aspects, the techniques described herein relate to a circuit in which the current sharing loop gain of the circuit is adjustable by changing the height of the Ton ramp.

[0016] In some aspects, the technology described herein relates to a circuit wherein the circuit occupies an area less than about 25 mm2.

[0017] In some aspects, the technology described herein relates to a method of regulating voltage, the method comprising: performing DC to DC voltage conversion in a circuit coupled to a dynamic load; providing an output current from a multi-phase current source; changing a pulse frequency in response to a change in load current; changing a pulse width in response to a change in load current to provide adaptive on-time control; increasing the output current at a high speed to match the load current; and transmitting an output voltage signal with zero undershoot.

[0018] In some aspects, the technology described herein relates to a method in which responding to a change in load current includes supplying output current in incremental steps.

[0019] In some aspects, the techniques described herein relate to a method in which providing an output current includes use of a masterless current balancing process.

[0020] In some aspects, the techniques described herein relate to a method that is compatible with analog, digital, and hybrid implementations.

[0021] In some aspects, the technology described herein relates to a system comprising: a power delivery circuit configured to deliver power to a dynamic load, the power delivery circuit comprising: a voltage regulator having an input voltage, an output voltage, and an output capacitor; and a constant on-time (COT) control stage configured to provide a variable on-time in response to changes in the dynamic load.

[0022] In some aspects, the techniques described herein relate to a system in which a voltage regulator is configured to provide a regulated output voltage signal with zero undershoot.

[0023] In some aspects, the techniques described herein relate to a system in which an output voltage signal remains stable when the output capacitance is less than 1 mF.

[0024] In some aspects, the techniques described herein relate to a system that also includes a multi-phase current source system configured with adjustable current sharing gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 and Figure 2 is a high-level circuit schematic depicting a buck converter circuit according to a specific implementation of the present disclosure.

[0026] Figure 3 It is a specific implementation according to the present disclosure. Figure 2 0048] A timing diagram of the response of the buck converter circuit shown in FIG. 1 to a boost in dynamic load current.

[0027] Figure 4 is a detailed circuit schematic of a buck converter circuit according to a specific implementation of the present disclosure, featuring variable frequency leading edge constant on-time (COT) control.

[0028] Figure 5 It is a specific implementation according to the present disclosure. Figure 4 0048] A timing diagram of the response of the buck converter circuit shown in FIG. 1 to a boost in dynamic load current.

[0029] Figure 6 is a detailed circuit schematic of a buck converter circuit including variable frequency dual-edge COT control according to a specific implementation of the present disclosure.

[0030] Figure 7 It is a specific implementation according to the present disclosure. Figure 6 0048] A timing diagram of the response of the buck converter circuit shown in FIG. 1 to a boost in dynamic load current.

[0031] Figure 8is a detailed circuit schematic diagram illustrating a multi-phase buck converter circuit with variable on-time (COT) control and current balancing according to a specific implementation of the present disclosure.

[0032] Fig. 9 is a circuit diagram of a current sharing loop according to a specific implementation of the present disclosure.

[0033] Fig.10 is a high-level system block diagram of a frequency modulated constant current system according to a specific implementation of the present disclosure, where COT control is modulated as a current sharing error.

[0034] Fig.11 According to the specific implementation of the present disclosure, Figure 8 Two-phase timing diagram of the multiphase buck converter circuit shown in .

[0035] Fig.12 It is a specific implementation according to the present disclosure. Figure 8 00480 FIG. 10 is a timing diagram of the current sharing error correction response of the multiphase buck converter circuit shown in FIG.

[0036] Fig.13 is a flow chart illustrating a method of operating a buck converter circuit according to a specific implementation of the present disclosure.

[0037] Fig.14A , Fig. 14B , Fig.15A and Fig. 15B is a series of graphs illustrating simulation results of characteristics of a buck converter circuit according to a specific implementation of the present disclosure.

[0038] When with Figure 1 When reading together, the various aspects of the present disclosure are best understood from the following detailed description. It should be noted that various features are not necessarily drawn to scale. For clarity of discussion, the sizes of various features can be increased or reduced arbitrarily. In the accompanying drawings, the same reference symbols can indicate the same and / or similar parts (elements, structures, etc.) in different views. The accompanying drawings generally illustrate various specific implementations discussed in the present disclosure by way of example and not limitation. The reference symbols shown in one accompanying drawing may not be repeated for the same and / or similar elements in the related views. The reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for the context between the related views. In addition, not all similar elements in the accompanying drawings are specifically referenced with reference symbols when multiple instances of the element are shown. DETAILED DESCRIPTION

[0039] At least some of the power converter embodiments described herein are configured to solve various problems of known power converters. For example, the power converter described herein can be configured to use current balancing to solve hot spot problems that may occur at certain currents and voltages in some applications. For example, in a high power transmission circuit suitable for electric vehicles (EV) or industrial applications, when the output voltage is reduced by a power converter (e.g., a DC-DC power converter), the output current increases. This may result in the presence of relatively large currents (e.g., approximately 30 amps per phase to approximately 40 amps per phase), which may generate hot spots in some circuits. The embodiments herein can avoid hot spots by maintaining current balance throughout the circuit. In addition, the voltage regulator of the high power transmission circuit can be used to maintain a stable output voltage, for example, an output voltage within a narrow range, for example, with a variation of less than about + / -10%.

[0040] At least some of the power converter implementations described herein can also be used to meet the strictly regulated load power transmission requirements of high-performance microprocessor systems. For example, the power converter implementation herein can be configured to support the high load requirements of high-performance central processing units with low power budgets and / or lower (e.g., minimum) cost compact solutions. In order to support high conversion rate loads, multi-phase operation can be used in some implementations, where all phases are synchronized for fast turn-on to maximize load speed under the condition of minimum undershoot output voltage dynamic response. The power converter described herein may include design considerations for fast dynamic response, smaller (e.g., minimum) output voltage interference, tight current balance and / or stability of the voltage regulator under minimum output capacitance.

[0041] At least some of the power converters described herein implement constant on-time (COT) control, which is used in voltage regulator module (VRM) applications for high bandwidth capability and natural frequency scaling in light load applications. Compared to the power converters described herein, some known systems with COT and minimum off-time have a limited inductor current increment and a constant on-time relative to T. on The disadvantage of large dynamic undershoot and overshoot caused by the load release timing of the cycle. To overcome this defect, T on Adaptive nonlinear expansion circuits introduce variable on-time and off-time control. However, these circuits increase complexity and have strict timing requirements.

[0042] In addition, at least some of the power converters described herein can be used in multi-phase applications. In some known systems, current balancing can be achieved by having a reference current for all phases to track as a current mode control control system or by a dedicated parallel current sharing loop. These methods add complex compensation networks, resulting in voltage undershoot response and the response to fast dynamic loads may be slow, with respect to other parallel loops The bandwidth is limited. The multi-phase COT control method may lack a simple high-speed current balancing method to maintain strict current balance during dynamic loads without increasing power, complexity and cost.

[0043] At least some of the power converter implementations described herein have the above advantages, but also address the above deficiencies in known systems with a simple, low-cost adaptive COT control method. The methods described herein extend single-edge COT control to dual-edge adaptive COT control with no master current balancing. In some implementations, these techniques result in a zero voltage undershoot response at minimum output load capacitance, a less complex (e.g., minimal) compensation network, and / or a fast current balancing technique with built-in dynamic gain adjustment.

[0044] There are at least three types of power converters that can implement the above solution, namely, buck converters, boost converters, and buck-boost converters. The accompanying drawings shown and described herein are specifically implemented for buck converters only by way of example. Any of the specific implementations described herein in connection with the buck converter may also be included in any type of power converter, for example, a boost converter or a buck-boost converter. A buck converter is a DC-DC power converter in which the output voltage is less than the input voltage. A buck converter may also be referred to as a buck converter. A boost converter is a DC-DC power converter in which the output voltage is greater than the input voltage. A boost converter may also be referred to as a boost converter. A DC-DC power converter may also be referred to as a voltage regulator, and one type of DC-DC power converter may be a switching regulator that efficiently regulates power by operating a transistor as a switch. In industrial applications, a power converter may be used to convert a high voltage into a lower voltage for use in a microprocessor-based system (e.g., a mobile computing device such as a notebook computer or a tablet computer).

[0045] Figure 1 is a high-level schematic circuit diagram of a voltage regulator according to some specific implementations of the present disclosure. Specifically, Figure 1 FIG. 1 shows a step-down buck converter circuit 100 according to some specific implementations of the present disclosure. The buck converter circuit 100 is a switching voltage regulator circuit in which V in Exceed V out, in some automotive or industrial implementations, V in can be in the range of about 100V to about 500V and V out can be in the range of about 5V to about 15V. In some computing implementations, V in can be in the range of about 5V to about 21V and V out The buck converter circuit 100 includes a power switch S, an inductor L, and a diode D as basic elements for transferring energy from the input to the output. The power switch S can be considered as a driver stage 112, which can be implemented as one or more metal oxide semiconductor field effect transistors (MOSFETs), for example. When the power switch S is closed, energy is stored in the inductor L. When the power switch S is open, the energy is transferred to the output through the variable load capacitor C. out The dynamic load represented by is released from the inductor L. Therefore, the inductor current is controlled by the frequency of activating the MOSFET and the on-time that the switch S is closed. In some implementations, the switch S can be operated according to a control stage 110 that supplies a control signal 120 (e.g., a timing signal or a clock signal) to the switch S.

[0046] The following are shown and described in various figures with varying details and / or complexity. Figure 1 For example, a more detailed version of the control stage 110 is shown in Figure 2 , Figure 4 , Figure 6 and Figure 8 110a, 110b, 110c, and 110d, respectively. Likewise, the following are shown and described in different details and / or complexities in various figures. Figure 1 For example, a more detailed version of the driver stage 112 is presented in Figure 2 , Figure 4 , Figure 6 and Figure 8 In the figure, they are respectively shown as driver stage 112a, driver stage 112b, driver stage 112c and driver stage 112d.

[0047] Figure 2 is a high-level schematic circuit diagram of a voltage regulator according to some specific implementations of the present disclosure. Specifically, Figure 2 Some specific implementations according to the present disclosure include Figure 1 The example buck converter circuit 200 includes some elements of a voltage regulator as shown in FIG. The example buck converter circuit 200 includes a control stage 110 a, a diode D, an inductor L, and a load capacitor C. out The power switch S is implemented as a driver stage 112a. Figure 2 As shown in FIG. 1 , the driver stage 112 a includes a first MOSFET M1 and a second MOSFET M2. The MOSFETs of the power switch S are all operated, for example, driven, by a pulse control signal 220 generated in the control stage 110 a. The pulse control signal 220 is implemented as a pulse signal output of a pulse generator 230 to reduce the input voltage to a lower output voltage.

[0048] Various control topologies may be used to generate the pulse drive control signal 220, including voltage mode control, current mode control, and / or constant on-time (COT) control. Figure 2 The example control stage 110a shown in FIG. 1 is a high-level illustration of COT control, where a pulse drive control signal 220 replaces a fixed frequency clock. The COT pulse generator can be triggered to generate pulses with a variable frequency depending on the load. In some implementations, the COT pulse generator can be triggered to generate pulses with a variable width, i.e., with a variable on-time and off-time depending on the load.

[0049] Figure 3 is a timing diagram illustrating a COT control scheme 300 according to some specific implementations of the present disclosure. The COT control scheme 300 may be applied to Figure 2 2 to generate the pulse drive control signal 220. In some implementations, the COT control scheme 300 can be applied to the control stage of a boost converter circuit. The timing diagram shows the response of the dynamic load current I through the load capacitor Cout to the control stage 110a of the buck converter circuit 200 shown in FIG. load , the time-varying pulse signal 220 and the inductor current I through the inductor L L (At least in Figure 2 ).

[0050] Figure 3 At least one of the important advantages of COT control is shown. Figure 3 As shown in FIG. 3 , in the COT control scheme 300 , when the load current I load When time t0 suddenly increases, the frequency of the pulse drive control signal 220 can be temporarily increased to meet the demand for a higher output current transmitted to the inductor. L Rise to I load The delay between the high values ​​of Figure 3 The control stage 110a can be configured to increase the output current in incremental steps to match the load current within a specified or predetermined time delay.

[0051] Figure 4is a high-level schematic circuit diagram of an example buck converter circuit 400 according to some implementations of the present disclosure. The buck converter circuit 400 is Figure 1 The buck converter circuit 400 is a variant of the voltage regulator implementation shown in FIG. out and drive control signal 420. In the exemplary buck converter circuit 400, the drive control signal 420 to the driver stage 112b is a leading single edge modulated COT pulse. The single edge COT control uses at least one inner current control loop I_LOOP and one outer voltage loop V_LOOP. Figure 4 In the example implementation shown in FIG. 1 , the control stage 110 b includes a leading edge control stage 470 and a COT control stage 450 . The leading edge control stage 470 is configured with a leading edge comparator 440 having an inductor current signal Ri*I L (I1_Loop) and the regulated voltage error signal V error As input, the COT control stage 450 includes a T on Comparator 430, which has a COT ramp signal V ramp and a fixed threshold voltage V th as input.

[0052] Figure 5 is a timing diagram illustrating a single edge modulated COT control scheme 500 according to some specific implementations of the present disclosure. The COT control scheme 500 may be applied to Figure 4 The COT control stage 110b of the buck converter circuit 400 shown in FIG. 1 is used to control the voltage from the leading edge comparator 440 and T on The COT pulse output signal of the comparator 430 generates the drive control signal 420. error In contrast, the COT pulse has an inductor current signal I L The variable frequency leading edge modulation 510 is generated. With a fixed threshold voltage V th In comparison, from T on The COT pulse output signal of the comparator 430 is at least composed of the voltage ramp signal V ramp generate.

[0053] Figure 6 is a detailed schematic circuit diagram of an example buck converter circuit 600 according to some specific implementations of the present disclosure. The buck converter circuit 600 is Figure 1 The buck converter circuit 600 is a variant of the voltage regulator implementation shown in FIG. outand drive control signal 620. In the example buck converter circuit 600, the drive control signal 620 to the driver stage 112c is a dual-edge modulated COT pulse. The dual-edge COT control uses two inner current loops I1_LOOP and I2_LOOP and one outer voltage loop V_LOOP. Figure 6 In the example implementation shown in FIG. 1 , the control stage 110 c includes a leading edge control stage 650 and a trailing edge control stage 670. The leading edge control stage 650 is configured with a leading edge comparator 630 having a trigger ramp signal V trigger and the regulated error signal V generated by the error amplifier HV error as input.

[0054] In some implementations, the trigger ramp signal V trigger It can be a single-ended or differential trigger ramp signal. Trigger ramp signal V trigger It can be an analog generated signal or a digital signal, for example, a signal using a digital counter method. In some implementations, the trailing edge control stage 670 can be configured with a trailing edge comparator 640 having a voltage ramp V ramp and the threshold voltage V added to the valley inductor current information (I2_Loop) th In some implementations, V is generated by adding the inductor current information (I1_Loop) during the off time to the COT ramp signal Sr. ramp .

[0055] Figure 7 7 is a timing diagram illustrating a dual-edge modulated COT control scheme 700 according to some specific implementations of the present disclosure. The dual-edge modulated COT control scheme 700 can be applied to the control stage 110c of the buck converter circuit 600 to generate a COT drive control signal 620 in a single-phase configuration. The generated COT pulse is a variable frequency pulse with dual edge modulation (e.g., leading edge modulation 710 and trailing edge modulation 720). By triggering the ramp signal V trigger The regulated voltage error signal V error The leading edge modulation 710 is generated by comparing the voltage ramp signal V in the trailing edge comparator 640. In some implementations, the trailing edge modulation 720 is based on the current sharing error. ramp and valley current information RiI L Added T on Threshold voltage signal V th The comparison is performed to generate the trailing edge modulation 720. The dual edge modulated COT control scheme 700 may have a variable on time (trailing edge for valley current error correction) and / or a variable off time (leading edge for voltage error correction).

[0056] In some implementations, the output voltage V OUT The corresponding temporary drop in the inductor current signal I L Thus, controlling the frequency of the pulse drive control signal 620 also controls the output voltage. In some existing control systems, the falling output voltage may also exhibit undershoot. Proper control of the pulse drive control signal 620 can potentially reduce or eliminate the voltage undershoot. Thus, the advantage of COT control is the ability to maintain stability and high bandwidth capability as well as the frequency scaling inherent in light load applications.

[0057] As mentioned above, some disadvantages of COT control include the limited inductor current increment and the on The large dynamic undershoot and overshoot in the output current caused by the load release timing of the cycle. These aspects are Figure 3 The inductor current I in the upper frame L The sawtooth curve is shown. The existing solution to these shortcomings introduces variable on-time control and off-time control using an on-time adaptive nonlinear expansion circuit. However, this circuit increases complexity and has strict timing requirements.

[0058] therefore, Figure 6 and Figure 7 The disclosure of the invention relates to a scalable control method for extending the COT on-time during dynamic loads. Figure 6 and Figure 7 , in addition to variable frequency, the enhanced COT provides a modulated on-time instead of a fixed on-time, with a new built-in fast-response current balancing method.

[0059] Figure 8 is a detailed schematic circuit diagram of an example buck converter circuit 800 according to some specific implementations of the present disclosure. The buck converter circuit 800 is Figure 1 The buck converter circuit 800 includes a first driver stage 112d-1 having a drive switch S1 and a second driver stage 112d-2 having a drive switch S2, for respectively driving the load capacitors C out and the resistive load R L The two inductors L1 and L2 are energized and discharged. The buck converter circuit 800 is also implemented with a control stage 110d featuring a multi-phase design and dual-edge COT control. The multi-phase current source provides an output current I having a first current component IL1 and a second current component IL2 that are out of phase with each other. outBuck converter circuit 800 provides a compact footprint solution. In some implementations, the footprint can be less than about 5 mm×5 mm or 25 mm. 2 .

[0060] The structure of the buck converter circuit 800 includes a voltage loop 805, a first current loop 840, and a second current loop 845, which define a frequency-modulated multiphase current source system to provide current balance as described below. The first current loop 840 regulates the first current component IL1 by driving the first inductor L1 with a first drive signal 820A at a first switching frequency. The second current loop 845 regulates the second current component IL2 by driving the second inductor L2 with a second drive signal 820B at a second switching frequency. The switching frequency can range from about 20kHz in a discontinuous conduction mode to about 2MHz in a continuous conduction mode. In some specific implementations, the second drive signal 820B is out of phase with the first drive signal 820A.

[0061] The voltage loop 805 of the buck converter circuit 800 is implemented with a leading edge COT control stage 810. The leading edge COT control stage 810 generates a pulse control signal or trigger pulse 832. The trigger pulse 832 is divided into a first trigger pulse 834 and a second trigger pulse 836 that are 180 degrees out of phase. The first trigger pulse 834 activates the driver switch S1 with the COT pulse D1 of the drive signal 820A to operate the first inductor L1. In parallel, the second trigger pulse 836 activates the driver S2 with the COT pulse D2 of the drive signal 820B to operate the second inductor L2. The sum of the multi-phase currents (e.g., the first current component IL1 and the second current component IL2) is I out .

[0062] The trigger pulse 832 can be generated by comparing the trigger ramp signal 838 with the voltage error signal 839 at the COT control stage 110d ( Figure 8 The trigger pulse 832 is phase-managed into a first trigger pulse 834 and a second trigger pulse 836 to generate a rising COT pulse D1 of the drive signal 820A and a rising COT pulse D2 of the drive signal 820B in leading edge modulation.

[0063] The reset ramp signals 880 and 885 determine the falling COT pulse D1 and the falling COT pulse D2 in the trailing edge modulation. In some implementations, the voltage error signal 859 includes iSum information 920 for a constant output impedance falling response. In some implementations, the voltage error signal 859 also includes an integrator that eliminates the output offset generated by the trigger ramp signal 838. The integrator can be an amplifier analog block or a digital filter approach.

[0064] In addition, in some specific implementations, the first current component IL1 can be added to the first T on The ramp cs_ramp1 is used to add the second current component IL2 (eg, the second current of phase 2) to the second T via the second current loop 865. on Ramp cs_ramp2. In some implementations, at least one of the current loops 860 and 865 is configured as a masterless current sharing loop that provides trailing edge current error correction. The current loops 860 and 865 can be used to tune the currents, thereby balancing the current values, so that hot spots (e.g., circuit hot spots as described above) can be avoided. In some implementations, the current loops 860 and 865 can be used to tune the phase current errors relative to the average current reference I2, thereby balancing the currents using a masterless approach.

[0065] Fig. 9 9 is a schematic circuit diagram 900 showing the generation of an average valley value I2 as a current sharing reference at 910 according to some specific implementations of the present disclosure. The average valley value I2 is Figure 8 8 is shown as an input for generating a reset ramp signal 880 in the first current loop 840. The currents IL1 and IL2 are added at 920. The average value (1 / 2) of the resulting currents is then provided as a current sharing reference, where the valley in the resulting current signal is the trigger point.

[0066] Fig.10 is a simplified schematic circuit diagram of a frequency-controlled multiphase current source system 1000 according to some specific implementations of the present disclosure. The frequency-controlled multiphase current source system 1000 corresponds to Figure 6 The single-phase buck converter circuit 600 and Figure 8 The multiphase buck converter circuit 800 shown in FIG. 1 is a multiphase current source system 1000 controlled by frequency, wherein the loop frequency Af is modulated by the voltage error. In the multiphase current source system 1000 controlled by frequency, T on The current balance error is used for modulation. Therefore, T on is based on the error signal level. In addition, in the frequency controlled multi-phase current source system 1000, the phase current tracks the system reference current I2.

[0067] Fig.11 FIG. 8 is a diagram showing a buck converter circuit 800 ( Figure 8 1100 is a timing diagram of the enhanced COT control scheme 1100. Fig.11 shows multiphase COT control in a two-phase application. on ) is provided by starting with a trigger ramp having a voltage error. In some implementations, the trigger ramp has a slope S=N*Vout , where N is the number of phases and V out is the regulated output voltage. In some implementations, the voltage with a slope of s=fsw*V in *A th The Ton ramp generates a fixed on-time pulse width modulation (PWM) trailing edge, where fsw is the switching frequency and V in is the input supply voltage, and A th is a scaling element. In some implementations, the start relative to the threshold includes valley average current information (I2) of all phases in parallel, where the switching period T sw is given by the inverse of the switching frequency fsw, 1 / fsw, and A th By 1 / A i (the inverse of the current sharing loop gain) is given by A th The parameter is used to adjust the current sharing loop gain (A i ) without affecting the circuit operating frequency T on Ramp height and slope scaling elements. On-time ramp T on Slope = V id *A th +I2–I phase , where V id is the target reference voltage and I phase is the current per phase. In some implementations, the current sharing decision can be based on the per-phase current valley and average valley current sharing reference information. In some implementations, the method provides high bandwidth and better noise suppression while maintaining loop response speed without adding a low-pass filter.

[0068] Fig.11 Shows Figure 8 The multiphase current source system is configured with adjustable current sharing gain. Using dual edge modulation, T on is adaptive, thus overcoming the fixed on-time limitation of existing COT control schemes. Using this method, T on Including current, V in and V out In some implementations, the adjustable current sharing gain is a simple current sharing gain tuning method that changes T on The height of the ramp is provided without adding complexity or additional resources to the COT system to provide dynamically adjustable gain without a main current sharing loop.

[0069] Fig.12 FIG. 8 is a diagram showing a buck converter circuit 800 ( FIG. 10 ) for current balance error correction according to some specific implementations of the present disclosure. Figure 81200). Current balance errors may be caused by mismatches in the impedance paths across the parallel phases. In some implementations, the T on The value is modulated using the phase current error. In some specific implementations, the I2 current feedforward provides a valley reference current I2 for each of the parallel phase currents. ref The average current is given by I avg =(I ph1 +I ph2 ) / 2. Current error correction can be performed so that I ph1 With a smaller T on and larger phase current and I ph2 With a larger T on and smaller phase current. When I phase Close to I2 ref The highest current gain occurs when the system returns to the nominal operating point quickly, while the I2 reference is further away. Ph This dynamic gain adjustment provides additional stability and damping to the phase current sharing response while quickly converging to the current reference I2, avoiding overshoot and ringing in the system response.

[0070] Fig.13 FIG. 8 is a diagram illustrating a method for operating a DC to DC converter or voltage regulator (eg, a buck converter circuit 800 (at least in Figure 8 A flowchart of method 1300 is shown in FIG. Figures 1 to 12 In some specific implementations described, operations 1302 to 1312 of method 1300 may be performed to gradually reduce a high input voltage to a low output voltage. The operations of method 1300 may be performed in a different order, or not performed, depending on the specific application. It should be noted that method 1300 may not be the only way to operate buck converter circuit 800. Therefore, it should be understood that additional processes may be provided before, during, or after method 1300, and some of these additional processes may be briefly described herein.

[0071] At 1302, method 1300 includes performing DC to DC voltage conversion in a voltage regulator circuit coupled to a dynamic load (eg, using buck converter circuit 800) according to some implementations of the present disclosure. In some implementations, the input voltage can be about 10 to about 100 times greater than the output voltage.

[0072] At 1304, method 1300 includes providing output currents (eg, I in voltage loop 805) from multiphase current sources (eg, IL1 from first current loop 840 and IL2 from current loop 845) according to some implementations of the present disclosure. out ).

[0073] At 1306, method 1300 includes, in accordance with some implementations of the present disclosure, responding to a load current (eg, I Load ) changes by changing the pulse frequency (eg, the frequency of the trigger pulse 832 generated in the control stage 110d). Increasing the pulse frequency can reduce the delay time before the output current matches the load current.

[0074] At 1308, according to some implementations of the present disclosure, method 1300 includes changing a pulse width (e.g., a width of the trigger pulse 832 generated in the control stage 110d) to provide adaptive on-time control. Changing the pulse width corresponds to changing (e.g., extending) the on-time T on .

[0075] At 1310, according to some implementations of the present disclosure, the method 1300 includes providing an output current I out With load current I Load match.

[0076] At 1312, method 1300 includes transmitting an output voltage (eg, V out ).

[0077] FIG. 14A to FIG. 14B and FIG. 15A to FIG. 15B Simulation results generated by a piecewise linear system simulation (SIMPLIS) model simulation of at least a buck converter circuit 800 are shown, according to some implementations of the present disclosure. Fig.14A and Fig. 14B 1 shows simulation results corresponding to a buck converter circuit 800 with extended on-time and current sharing error correction performance. More specifically, Fig.14A and Fig. 14B A series of graphs 1410 to 1470 are shown for a 5V input voltage and a 0.9V output voltage, in response to a load current boost of 144 amperes in a four-phase system. In this simulation, the output capacitance is 1.5 mF and the drop resistance is 1.1 mΩ. However, when the output capacitance is less than 1 mF, the output voltage signal remains stable. The dynamic load current 1410 suddenly begins to increase at time step t1, and by time step t2, the buck converter circuit 800 has adjusted so that the output current I out Increases in incremental steps to essentially match the load current Iload , and the voltage error 1460 has dissipated.

[0078] Fig.14A The top panel of 1400 shows the relationship between phase current IPh1, phase current IPh2, phase current IPh3, phase current IPh4, load current, and output current. Pulse wave modulation (PWM) pulse graphs 1420, 1430, 1440, and 1450 show high frequency voltage pulses during the two second dynamic response duration between t1 and t2, and then return to a frequency of one pulse per time step. The PWM pulse graphs also show the variable pulse width (T on ), thereby providing adaptive on-time control. The phase current increases rapidly and reaches a steady state with minimal error by time step t2. This occurs by rapidly extending the PWM on-time and increasing operating frequency 1510, operating frequency 1520, operating frequency 1530 and operating frequency 1540 in stable dynamic and static current sharing performance. When the load current stabilizes at time step t2, the PWM pulse width becomes uniform again. The phase 1 PWM signal has a different operating frequency and Ton response (1440) than the other phases because its current IPh1 lags behind the other parallel phases at the initial load step. The current sharing loop increases the phase 1 frequency faster until the current sharing loop catches up with the other phase currents in the system. Graph 1480 shows the Ton ramp in response to a dynamic load, with the minimum slope at the IPh information and the peak slope at the Vid+I2 current reference. As the output current rises, for 1.1mR*I Load In the falling response, the output voltage 1470 drops from 0.9V to 0.76V, where the zero undershoot response shows another advantage of the system.

[0079] Fig.15A and Fig. 15B The output voltage disturbance and current sharing correction in response to phase shedding are shown. Fig.15A and Fig. 15B It shows excellent current sharing, good stability and minimal output disturbance during phase increase from four-phase operation to single-phase operation.

[0080] As described above, various implementations of a multi-phase buck inverter circuit with COT control can improve performance by shortening the response time to dynamic load changes, providing variable on-time in the control signal, and balancing current by adding a current sharing loop.

[0081] It should be understood that in the foregoing description, when an element such as a layer, a region or a substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, an element shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings.

[0082] As used in this specification, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, at the top, at the bottom, etc.) are intended to cover different orientations of the device in use or operation, except for the orientations shown in the drawings. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

[0083] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor device processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0084] Although certain features of the described implementations have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. For example, features shown with respect to one implementation may also be included in other implementations where appropriate. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

Claims

1. A voltage regulator circuit, comprising: A multi-phase current source, the multi-phase current source comprising: a first current loop configured to drive a first inductor with a first drive signal at a first switching frequency; a second current loop configured to drive a second inductor with a second drive signal at a second switching frequency; and A voltage loop includes a constant on-time (COT) control stage configured to provide a control signal having a leading edge modulation based on a voltage error and a trailing edge modulation based on a current sharing error.

2. The voltage regulator circuit according to claim 1, wherein: The first driving signal and the second driving signal are pulse width modulation (PWM) driving signals, and the first driving signal is out of phase with the second driving signal.

3. The voltage regulator circuit according to claim 2, wherein: The output voltage signal is configured to have a zero undershoot response when the multi-phase current source is coupled to a dynamic load.

4. The voltage regulator circuit according to claim 1, wherein: The COT control stage includes an integrator.

5. The voltage regulator circuit according to claim 1, wherein: The COT control stage includes a trigger ramp signal.

6. The voltage regulator circuit according to claim 1, wherein: The COT control stage is configured to provide trigger pulses that are out of phase with each other.

7. The voltage regulator circuit according to claim 1, wherein: At least one of the first current loop and the second current loop of the multi-phase current source is implemented as a non-maintained current sharing loop configured to provide trailing edge current error correction.

8. The voltage regulator circuit according to claim 7, wherein: The gain of the non-hosted current sharing loop is dynamically adjustable based on the error signal level.

9. The voltage regulator circuit according to claim 7, wherein: The gain of the masterless current sharing loop is T on Part of a slope.

10. The voltage regulator circuit according to claim 9, wherein: The gain of the non-main current sharing loop is obtained by varying the T on The height of the ramp is adjustable.

11. The voltage regulator circuit of claim 1, the voltage regulator circuit being configured as a buck voltage regulator circuit, wherein an output voltage is less than an input voltage.

12. The voltage regulator circuit according to claim 11, wherein: The input voltage is in the range of 5V to 21V, and the output voltage is in the range of 0.2V to 3.3V. 13 . The voltage regulator circuit of claim 1 , configured as a boost voltage regulator circuit, wherein the output voltage is greater than the input voltage.

14. The voltage regulator circuit of claim 1, wherein the voltage regulator circuit occupies an area less than 25 mm 2 .

15. A method for regulating voltage, the method comprising: performing DC to DC voltage conversion in a multiphase current source coupled to a dynamic load; outputting current from the multi-phase current source; varying a pulse frequency in response to a change in a load current of the dynamic load; varying pulse width in response to said change in said load current to provide adaptive on-time control; increasing the output current to match the load current; as well as Generates an output voltage signal with zero undershoot.

16. The method of claim 15, wherein responding to changes in the load current comprises supplying the output current in incremental steps.

17. The method of claim 15, wherein providing the output current comprises use of no main current balancing process.

18. The method of claim 15, wherein the method is compatible with analog implementations, digital implementations, and hybrid implementations.

19. A power transmission system comprising: A power transmission circuit, the power transmission circuit being configured to transmit power to a dynamic load, the power transmission circuit comprising: a voltage regulator having an input voltage, an output voltage, and an output capacitor; and A constant on-time (COT) control stage is configured to provide a variable on-time in response to changes in the dynamic load.

20. The power transmission system of claim 19, wherein: The voltage regulator is configured to provide an output voltage signal having zero undershoot.

21. The power transmission system of claim 20, wherein when the output capacitance is less than 1 mF, the output voltage signal remains stable.

22. The power transmission system of claim 19, further comprising a multi-phase current source system configured with an adjustable current sharing gain.

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