Semiconductor system for reducing delay and power consumption and method of operating same

Abstract

A semiconductor system for reducing idle power when a particular block is idle and a method of operating the same are provided. In one embodiment, a semiconductor system includes a first block including a plurality of intellectual property (IP) blocks, each IP block configured to generate activity information, and a first control logic configured to determine an activity state of each of the plurality of IP blocks based on the activity information, and in response to the activity state of each of the plurality of IP blocks being an idle state, generate an active state of each of the plurality of IP blocks. A power gating operation is performed on the first block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0153096 filed in the Korean Intellectual Property Office on November 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments relate to a semiconductor system and / or an operating method thereof, and more particularly, to a semiconductor system and / or an operating method thereof for reducing idle power when a specific block is idle. Background Art

[0004] The semiconductor system may include one or more blocks, and the block may include or be included in one or more intellectual property (IP) blocks, a clock management unit (CMU), and a power management unit (PMU). When a specific block is idle, the idle power of the block can be reduced by performing a power-off operation of the IP block (such as stopping the clock signal from the CMU to the IP block).

[0005] However, because the power-off operation is controlled by an operating system (OS), when a specific block is in a short idle state of tens of milliseconds (ms) or less, the power-off operation may not be performed on the specific block due to a latency problem. Therefore, a technology that solves or improves the latency problem and performs a power-off operation on a block in a short idle state is needed or desired. Summary of the invention

[0006] Various example embodiments provide a semiconductor system for effectively reducing power consumption of a specific block when the specific block is idle, and an operating method thereof.

[0007] According to various example embodiments, a semiconductor system is provided, the semiconductor system including: a first block including a plurality of intellectual property (IP) blocks, each IP block being configured to generate active information, and a first control logic configured to determine an active state of each of the plurality of IP blocks based on the active information, and in response to the active states of the plurality of IP blocks being all idle states, perform a power gating operation on the first block.

[0008] Alternatively or additionally, according to some example embodiments, there is provided an operating method of a semiconductor system including a plurality of blocks, comprising: determining an activity state of each of a plurality of IP blocks included in a first block among the plurality of blocks, performing a power gating operation on the first block when the activity states of the plurality of IP blocks are all idle states, and performing a wake-up operation on the first block based on a wake-up request received by a second block among the plurality of blocks.

[0009] Alternatively or additionally, there is provided an operating method of a semiconductor system including a plurality of blocks, comprising: determining an activity state of each of a plurality of IP blocks included in a first block among the plurality of blocks, in response to the activity states of the plurality of IP blocks being all idle states, determining data to be sent from a second block among the plurality of blocks to the first block through data communication, in response to the absence of data to be sent through data communication, stopping the data communication, performing a power gating operation on the first block after the data communication is stopped, and performing a wake-up operation on the first block based on a wake-up request received by the second block. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] In order to more fully understand the drawings referenced in the detailed description of the inventive concepts, a brief description of each drawing is provided.

[0012] Figure 1 is a block diagram illustrating a semiconductor system according to some example embodiments;

[0013] Figure 2 is a block diagram illustrating a semiconductor system according to some example embodiments;

[0014] Figure 3 is a flowchart illustrating an operating method of a semiconductor system according to some example embodiments;

[0015] Figure 4 is a flowchart illustrating a power on / power off method of a semiconductor system according to some example embodiments;

[0016] Figure 5 is a block diagram illustrating a semiconductor system according to some example embodiments;

[0017] Fig. 6A and Figure 6B is a graph illustrating a stall mode operation of a semiconductor system according to some example embodiments;

[0018] Figure 7 is a block diagram illustrating a semiconductor system according to some example embodiments;

[0019] Fig. 8A and Figure 8B is a graph for explaining a stop mode operation of a semiconductor system according to some example embodiments;

[0020] Fig. 9 is a block diagram illustrating an electronic device according to some example embodiments; and

[0021] Fig.10 is a block diagram illustrating an electronic device according to some example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a block diagram illustrating a semiconductor system 1 a according to some example embodiments.

[0024] refer to Figure 1 , the semiconductor system 1a may be implemented as or include or be included in a personal computer (PC) and / or a mobile device; however, the example embodiments are not limited thereto. For example, the mobile device may be implemented as or include or be included in one or more of a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, or an e-book. But not limited thereto.

[0025] The semiconductor system 1a may refer to a semiconductor device, and the semiconductor system 1a may be implemented as or include an integrated circuit (IC), a mainboard, a system on a chip (SoC), a microprocessor, an application processor (AP), a mobile AP, a chipset, or a collection of semiconductor chips, but is not limited thereto.

[0026] The semiconductor system 1a may include a first block 100a. Although it is shown that the semiconductor system 1a includes the first block 100a, the semiconductor system 1a may actually include a plurality of blocks (not shown).

[0027] The first block 100a may include a first control logic 110a and a plurality of intellectual property (IP) blocks 120a. The plurality of IP blocks 120a are functional blocks that perform specific functions, and each may include, for example, one or more of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a communication processor (CP), a digital signal processor (DSP), a video module (e.g., a camera interface, a joint photo expert group (JPEG) processor, a video processor, a mixer, etc.), a 3-dimensional graphics core, an audio system, or a driver. At least one of the plurality of IP blocks 120a may include at least one core that executes instructions, but example embodiments are not limited thereto. Each IP block in the IP block 121a may include a separate IP block, such as IP 1, IP 2, ... IPn; each separate IP may communicate with one or more other IPs; in some example embodiments, separate IPs may be routed to each other; example embodiments are not limited thereto.

[0028] The first control logic 110a may determine the activity state of each of the plurality of IP blocks 120a based on the activity information. In some example embodiments, each of the plurality of IP blocks 120a may be configured to generate activity information, and the first control logic 110a may determine whether the activity state of each of the plurality of IP blocks 120a is idle or non-idle based on the activity information received from the plurality of IP blocks 120a. For example, when the activity state of the first IP block 121a of the plurality of IP blocks 120a is idle, the first IP block 121a may generate activity information of a first level (e.g., a low level). When the activity state of the first IP block 121a is an operating state, the first IP block 121a may generate activity information of a second level (e.g., a high level). The first control logic 110a may receive activity information from the first IP block 121a, and when the received activity information is the activity information of the first level, it may be determined that the state of the first IP block 121a is an idle state, and when the received activity information is the activity information of the second level, it may be determined that the state of the first IP block 121a is an operating state (e.g., a non-idle state).

[0029] The first control logic 110a may perform a power gating operation on the first block 100a based on the activity state of each IP block in the plurality of IP blocks 120a. The power gating operation may be or may include an operation of blocking the power supply voltage applied to the first block 100a so as to reduce the power consumption of the first block 100a (e.g., power consumption due to leakage current). In some example embodiments, when the activity states of the plurality of IP blocks 120a are all idle states, the first control logic 110a may determine the first block 100a as an idle block, and may perform a power gating operation on the first block 100a. For example, when the activity information of each IP block in the plurality of IP blocks 120a is the activity information of the first level, as a power gating operation on the first block 100a, the first control logic 110a may block the power supply voltage applied to each IP block in the plurality of IP blocks 120a. For example, when activity information of a first IP block 121a among the plurality of IP blocks 120a is activity information of the second level, the first control logic 110a may determine that the first block 100a is not an idle block and may not perform a power gating operation on the first block 100a.

[0030] The first control logic 110a may be implemented as hardware, and the first control logic 110a may perform a power gating operation on an idle block without intervention of software (e.g., without intervention of an operating system (OS)). The power gating operation performed by the first control logic 110a is faster than the power gating operation performed by the OS, and thus, the latency of the power gating operation may be reduced. Therefore, the first control logic 110a may perform a power-off operation (e.g., a power gating operation on an idle block) even on a block in an idle state for a short duration (e.g., tens of ms or less), and thus, power consumption in an idle state may be reduced, and thus, power consumption of the semiconductor system 1a may be reduced.

[0031] In some example embodiments, when the activity states of the plurality of IP blocks 120a remain all in an idle state for more than a threshold time, the first control logic 110a may determine the first block 100a as an idle block, and may perform a power gating operation on the first block 100a. For example, when the activity information of each of the plurality of IP blocks 120a is the activity information of the first level, the first control logic 110a may determine whether each of the received activity information is maintained at the first level for more than a threshold time as the activity information, and then as a power gating operation on the first block 100a, the power supply voltage applied to each of the plurality of IP blocks 120a may be blocked. When the first block 100a remains idle for less than a specific time, the power consumed by the first control logic 110a in performing a power-on operation of applying the blocked power supply voltage again after performing the power gating operation on the first block 100a may be greater than the idle power consumed by the first block 100a. The threshold time may be or may be based on the above-mentioned specific time, and when the first block 100a remains idle for more than the threshold time, the first control logic 110a may perform a power gating operation on the first block 100a, and thus, power consumption may be effectively managed.

[0032] Figure 2 is a block diagram illustrating a semiconductor system 1 b according to some example embodiments.

[0033] refer to Figure 2 , the semiconductor system 1b may include a first block 100b, a second block 200b, a main PMU 300b, and a power management integrated circuit (PMIC) 400b. Although the semiconductor system 1b is shown to include the first block 100b, the second block 200b, the main PMU 300b, and the PMIC 400b, the semiconductor system 1b may actually include a plurality of blocks, such as a plurality of blocks (not shown).

[0034] The first block 100b may include a first control logic 110b, a plurality of IP blocks 120b, a second control logic 130b, a first bus 140b, and a memory 150b. The second block 200b may include a second bus 210b. Although the second block 200b is shown to include the second bus 210b, the second block 200b may also include a plurality of components, such as the same components as those of the first block 100b. The first control logic 110b and the plurality of IP blocks 120b may be respectively Figure 1 The first control logic 110a and the plurality of IP blocks 120a are shown in FIG. Figure 1 Those related redundant descriptions.

[0035] The first control logic 110b may send a power control signal to the second control logic 130b. The second control logic 130b may generate a clock signal based on the power control signal and perform a clock gating operation on the first block 100b. The clock gating operation may be an operation that reduces the power consumption (e.g., switching power consumption) of a specific circuit by not supplying a clock signal to the specific circuit when the operation of the specific circuit is not needed or performed. In some example embodiments, when the active states of the plurality of IP blocks 120b are all idle states, the first control logic 110b may determine that the first block 100b is an idle block and may send a power control signal to the second control logic 130b. The second control logic 130b may perform a clock gating operation on each of the plurality of IP blocks 120b based on the received power control signal. For example, the second control logic 130b may supply a clock signal to each of the plurality of IP blocks 120b, and may not supply a clock signal to each of the plurality of IP blocks 120b after receiving the power control signal.

[0036] In some example embodiments, the first control logic 110b and the second control logic 130b may operate in a handshake method of exchanging power control requests and power control confirmations as power control signals. For example, when it is determined that the first block 100b is an idle block, the first control logic 110b may send a power control request to the second control logic 130b. When a clock gating operation is performed on each of the multiple IP blocks 120b, the second control logic 130b may send a power control acceptance to the first control logic 110b in response to the power control request req, and when a clock gating operation is not performed on each of the multiple IP blocks 120b, a power control rejection is sent to the first control logic 110b.

[0037] The first bus 140b and the second bus 210b may each be implemented as (or may include or be included in) one or more of an Advanced Microcontroller Bus Architecture (AMBA), an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced Extensible Interface (AXI), an Advanced System Bus (ASB), an AXI Coherence Extension (ACE), or a combination thereof, but is not limited thereto. In some example embodiments, the first control logic 110b may perform a power gating operation on the first bus 140b.

[0038] The first block 100b may exchange data with the second block 200b through the first bus 140b and the second bus 210b. In some example embodiments, the first bus 140b may perform data communication with the second bus 210b, and through the data communication, the first block 100b may exchange data with the second block 200b.

[0039] The memory 150b is or includes a storage location for storing data and may be electrically connected to each of the plurality of IP blocks. For example, the memory 150b may be electrically connected to each of the plurality of IP blocks 120b. The memory 150b may include one or more of a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM) or a non-volatile memory such as a phase change RAM (PRAM), a resistive RAM (ReRAM), and a magnetic RAM (MRAM) flash memory. Although in Figure 2 1 and 2 show that the memory 150b is provided within the first block 100b, but the memory 150b is not limited thereto and may be provided separately outside the first block 100b. In some example embodiments, the first control logic 110b may perform a power gating operation on the memory 150b.

[0040] The main PMU 300b may control the power supply voltage applied to each of the plurality of blocks included in the semiconductor system 1b, and may perform a power gating auxiliary operation on each of the plurality of blocks. In some example embodiments, the main PMU 300b may perform a power gating auxiliary operation on the first block 100b by communicating with the first control logic 110b. For example, the main PMU 300b may be implemented by software or at least partially by software, and when the first control logic 110b does not perform a power gating operation on the first block 100b in an idle state, the main PMU 300b may perform a power gating operation on the first block 100b. In some example embodiments, when the first control logic 110b and the main PMU 300b do not perform a power gating operation on the first block 100b in an idle state, the main PMU 300b may transmit power gating operation failure information to a CPU (not shown). For example, when the first control logic 110b and the main PMU 300b do not perform a power gating operation on the first block 100b in an idle state, the semiconductor system 1b may not operate normally, and in this case, the main PMU 300b may transmit power gating operation failure information as error information to the main CPU (not shown). The semiconductor system 1b may quickly perform a power-off operation (e.g., a power gating operation on the idle block) on the idle block by hardware (e.g., the first control logic 110b), and when the hardware does not operate normally, the power-off operation (e.g., a power gating operation on the idle block) may be performed on the idle block additionally or alternatively by software (e.g., the main PMU 300b), and therefore, the power consumption of the semiconductor system 1b may be effectively reduced.

[0041] The PMIC 400b may generate a power supply voltage by the control of the PMU, and provide the generated power supply voltage to each of the plurality of blocks. In some example embodiments, the PMIC 400b may generate a power supply voltage by the control of the first control logic 110b, and provide the generated power supply voltage to the first block 100b. For example, the PMIC 400b may provide a power supply voltage to each of the plurality of IP blocks 120b. In some example embodiments, the PMIC 400b may block the power supply voltage to the first block 100b by the control of the first control logic 110b. For example, the first control logic 110b may determine the first block 100b as an idle block, and may perform a power gating operation of controlling the PMIC 400b to block the power supply voltage applied to the first block 100b.

[0042] Figure 3 1 is a flow chart illustrating an operating method 10 of a semiconductor system according to some example embodiments. Figure 3 As shown, the operating method 10 of the semiconductor system may include a plurality of operations S311 to S323 .

[0043] refer to Figure 2 and Figure 3 , it may be determined in operation S311 whether to perform a power-off operation. In some example embodiments, the first control logic 110b may determine the activity state of each of the plurality of IP blocks 120b based on the activity information. For example, each of the plurality of IP blocks 120b may be configured to generate activity information, and the first control logic 110b may determine whether the activity state of each of the plurality of IP blocks 120b is an idle state based on the activity information received from the plurality of IP blocks 120b, or alternatively, determine whether at least one of the plurality of IP blocks 120b is not in an idle state. In some example embodiments, the first control logic 110b may determine whether to perform a power-off operation on the first block 100b based on the activity state of each of the plurality of IP blocks 120b. For example, when the activity states of the plurality of IP blocks 120b are all idle states, the first control logic 110b may determine that the first block 100b is an idle block, and may perform a power-off operation on the first block 100b in an idle state. For example, when the activity information of the first IP block 121b among the multiple IP blocks 120b is activity information of the second level (e.g., logic high), the first control logic 110b can determine the first block 100b as an operating block, and therefore, the power-off operation may not be performed on the first block 100b in the operating state.

[0044] When it is determined in operation S311 that the power-off operation is performed, in operation S312, it may be determined whether the power-off operation is completed. In some example embodiments, the first control logic 110b may control the power supply voltage applied to the first block 100b, and the power-off operation may include a power gating operation of reducing the power consumption of the first block 100b (e.g., power consumption due to leakage current) by blocking the power supply voltage applied to the first block 100b in an idle state. The first control logic 110b may determine whether the power-off operation has been completed by determining whether the power gating operation has been completed for the first block 100b in an idle state.

[0045] When the power-off operation is not completed in operation S312, power-off operation failure information may be transmitted to the master PMU 300b in operation S313. In some example embodiments, when the first control logic 110b does not perform a power gating operation on the first block 100b in an idle state, the first control logic 110b may transmit the power-off operation failure information to the master PMU 300b.

[0046] When the power-off operation failure information is received, in operation S321, the master PMU 300b may determine whether the power-off operation has been completed. In some example embodiments, the master PMU 300b may control a power supply voltage applied to each of a plurality of blocks included in the semiconductor system 1b, and perform a power gating auxiliary operation on each of the plurality of blocks. After receiving the power-off operation failure information, the master PMU 300b may perform a power gating operation on the first block 100b in an idle state, and determine whether the power-off operation has been completed based on whether the power gating operation has been completed.

[0047] When the power-off operation is not completed in operation S321, power-off operation failure information may be transmitted to the main CPU (not shown) in operation S322. In some example embodiments, when the first control logic 110b and the main PMU 300b do not perform a power gating operation on the first block 100b in an idle state, the main PMU 300b may transmit the power-off operation failure information to the main CPU (not shown). For example, when the first control logic 110b and the main PMU 300b do not perform a power-off operation (e.g., a power gating operation) on the first block 100b in an idle state, the semiconductor system 1b may not operate normally, and in this case, the main PMU 300b may transmit the power-off operation failure information to the main CPU (not shown) as error information.

[0048] When the power-off operation is completed in operation S312 or operation S321, the first block 100b may maintain the power-off state in operation S314. In some example embodiments, the first control logic 110b or the main PMU 300b may perform a power gating operation on the first block 100b in the idle state. The first block 100b that has completed the power gating operation may be in a state where the power supply voltage is blocked. Therefore, the first block 100b may maintain the power-off state and the idle power may be reduced, and thus, the power consumption of the semiconductor system 1b may be reduced. In addition, the semiconductor system 1b may quickly perform a power-off operation (e.g., a power gating operation on the idle block) on the idle block by hardware (e.g., the first control logic 110b), and when the hardware does not operate normally, the power-off operation (e.g., the power gating operation on the idle block) may be performed on the idle block by software (e.g., the main PMU 300b) alternatively or additionally, and thus, the power consumption of the semiconductor system 1b may be effectively reduced.

[0049] In operation S315, it may be determined whether to perform a power-on operation. In some example embodiments, the first control logic 110b may determine whether to perform a power-on operation on the first block 100b in a power-off state. For example, the first control logic 110b may receive a wake-up request from the outside (e.g., the second block 200b), and determine whether to perform a power-on operation based on the wake-up request.

[0050] When it is determined not to perform the power-on operation in operation S315, the power-off state may be maintained in operation S314. In some example embodiments, the first control logic 110b may not perform the power-on operation on the first block 100b, and the first block 100b may maintain the power-off state.

[0051] When it is determined in operation S315 that the power-on operation is performed, it may be determined in operation S316 whether the power-on operation has been completed. In some example embodiments, the first control logic 110b may control the power supply voltage applied to the first block 100b, and the power-on operation may include a wake-up operation to maintain the first block 100b in an operating state by applying the blocked power supply voltage to the first block 100b. The first control logic 110b may determine whether the power-on operation has been completed based on whether the wake-up operation on the first block 100b has been completed.

[0052] When the power-on operation is not completed in operation S316, power-on operation failure information may be transmitted to the master PMU 300b in operation S317. In some example embodiments, when the first control logic 110b does not perform a wake-up operation on the first block 100b, the first control logic 110b may transmit the power-on operation failure information to the master PMU 300b.

[0053] When the power-on operation failure information is received, the master PMU 300b may determine whether the power-on operation has been completed in operation S323. In some example embodiments, the master PMU 300b may control a power supply voltage applied to each of a plurality of blocks included in the semiconductor system 1b, and perform a wake-up operation on each of the plurality of blocks. After receiving the power-on operation failure information, the master PMU 300b may perform a wake-up operation on the first block 100b, and may determine whether the power-on operation has been completed based on whether the wake-up operation has been completed.

[0054] When the power-off operation is not completed in operation S323, power-on operation failure information may be transmitted to the main CPU (not shown) in operation S322. In some example embodiments, when the first control logic 110b and the main PMU 300b do not perform a wake-up operation on the first block 100b, the main PMU 300b may transmit the power-on operation failure information to the main CPU (not shown). For example, when the first control logic 110b and the main PMU 300b do not perform a power-on operation (e.g., a wake-up operation) on the first block 100b, the semiconductor system 1b may not operate normally, and in this case, the main PMU 300b may transmit the power-on operation failure information to the main CPU (not shown) as error information.

[0055] When the power-on operation is completed in operation S316 or operation S323, the first block 100b may maintain the power-on state in operation S318. In some example embodiments, the first control logic 110b or the main PMU 300b may perform a wake-up operation on the first block 100b, and the first block 100b that has performed the wake-up operation may maintain the power-on state. In addition, when the power-off operation is not performed in operation S311, the first block 100b may maintain the power-on state in operation S318.

[0056] Figure 4 2 is a flow chart illustrating a power-on / power-off method 20 of a semiconductor system according to some example embodiments. Figure 4 As shown, the power on / off method 20 of the semiconductor system may include a plurality of operations S410 to S490 .

[0057] refer to Figure 2 and Figure 4, the block may maintain a power-on state in operation S410, and with respect to the block maintaining the power-on state, an activity state of each of the plurality of IP blocks included in the block may be determined in operation S420. In some example embodiments, the first control logic 110b may receive activity information of each of the plurality of IP blocks 120b from the plurality of IP blocks 120b included in the first block 100b in the power-on state. The first control logic 110b may determine whether the activity state of the plurality of IP blocks 120b is an idle state based on the received activity information. For example, each of the plurality of IP blocks 120b may be configured to generate activity information, and when the activity information received from each of the plurality of IP blocks 120b is activity information of a first level (e.g., logic "0"), the first control logic 110b may determine that the activity state of the plurality of IP blocks 120b is an idle state. For example, when activity information of the first IP block 121b among the plurality of IP blocks 120b is activity information of the second level (eg, logic '1'), the first control logic 110b may determine that the activity state of the plurality of IP blocks 120b is not the idle state.

[0058] When it is determined in operation S420 that the activity states of the plurality of IP blocks 120 b are not (or not all) the idle state, in operation S410 , the first control logic 110 b may maintain the first block 100 b in the powered-on state.

[0059] When it is determined in operation S420 that the activity states of the plurality of IP blocks 120b are idle states, it may be determined in operation S430 whether the activity states of the plurality of IP blocks 120b are all maintained in the idle state for more than a threshold time. In some example embodiments, when the activity states of the plurality of IP blocks 120b are all maintained in the idle state for more than a threshold time, the first control logic 110b may determine that the first block 100b is an idle block, and when at least one of the activity states of the plurality of IP blocks 120b is maintained in the idle state for less than a threshold time, it is determined that the first block 100b is an active block. In some example embodiments, the first control logic 110b may further include an idle counter (not shown) that determines whether the activity states of the plurality of IP blocks 120b are all maintained in the idle state for more than a threshold time.

[0060] When it is determined in operation S430 that the first block 100b is an idle block, in operation S450, the first control logic 110b may perform a power control operation on the second control logic 130b. The power control operation may be an operation of controlling the second control logic 130b to perform a clock gating operation by a power control signal. In some example embodiments, the first control logic 110b and the second control logic 130b may operate in a handshake method of exchanging a power control request req and a power control confirmation ack as a power control signal. For example, when it is determined that the first block 100b is an idle block, the first control logic 110b may send a power control request req to the second control logic 130b. When a clock gating operation is performed on each of the multiple IP blocks 120b, the second control logic 130b may send a power control acceptance to the first control logic 110b in response to the power control request req, and when a clock gating operation is not performed on each of the multiple IP blocks 120b, a power control rejection is sent to the first control logic 110b.

[0061] In operation S460, it may be determined whether to perform a power-off operation. In some example embodiments, the first control logic 110b may perform a power-off operation on the first block 100b upon receiving a power control accept, and may stop the power-off operation on the first block 100b upon receiving a power control reject.

[0062] In operation S470, a clock gating operation may be performed on all the plurality of IP blocks 120b. In some example embodiments, the second control logic 130b may perform a clock gating operation to reduce power consumption (e.g., switching power consumption) of the first block 100b by not supplying a clock signal to the first block 100b after sending a power control acceptance to the first control logic 110b.

[0063] In operation S480, a retention operation may be performed. The retention operation may be or may include an operation of saving data stored in the plurality of IP blocks 120b in the memory 150b before the power gating operation. In some example embodiments, the first control logic 110b may perform a retention operation on each of the plurality of IP blocks 120b after the clock gating operation performed by the second control logic 130b is completed.

[0064] In operation S490, a power gating operation may be performed on the block. In some example embodiments, the first control logic 110b may perform a power gating operation on the first block 100b after performing a retaining operation on each of the plurality of IP blocks 120b.

[0065] In operation S440, the power-off operation may be stopped and a wake-up operation may be performed. In some example embodiments, the first control logic 110b may receive a wake-up request from an idle counter when at least one of the active states of the plurality of IP blocks 120b remains in an idle state for less than a threshold time, and based on the received wake-up request, determine again whether all of the active states of the plurality of IP blocks 120b remain in an idle state for more than a threshold time again, or perform a wake-up operation to allow the first block 100b to remain in a powered-on state. In some example embodiments, the first control logic 110b may perform a wake-up operation to allow the first block 100b to remain in a powered-on state when a power control rejection is received from the second control logic 130b or a wake-up request is received from the outside (e.g., the second block 200b). Refer to FIG. 10A for details. Figures 5 to 8B Various embodiments of receiving a wake-up request from an external source are described.

[0066] In some example embodiments, operations S410 to S460 may be referred to as a power-off operation stop possible period. For example, the first control logic 110b may receive a wake-up request while performing a power-off operation, and may stop the power-off operation based on the received wake-up request.

[0067] Figure 5 is a block diagram illustrating a semiconductor system 1c according to some example embodiments.

[0068] refer to Figure 5 , the semiconductor system 1c may include a first block 100c and a second block 200c. Although the semiconductor system 1c is shown to include the first block 100c and the second block 200c, the semiconductor system 1c may actually include a plurality of blocks, such as a plurality of blocks (not shown). The first block 100c and the second block 200c may be respectively Figure 2 The first block 100b and the second block 200b are shown in FIG. Figure 2 Those redundant descriptions.

[0069] The first control logic 110c may send a low power interface (LPI) signal to the first bus 140c and receive a low power interface (LPI) signal from the first bus 140c, and may perform a power-off operation on the first bus 140c based on the LPI signal. The first bus 140c may send a power-down signal to the second bus 210c and receive a power-down signal from the second bus 210c, and the second bus 210c may operate in a stop mode based on the power-down signal. The first bus 140c may perform data communication with the second bus 210c, and the first block 100c may exchange data with the second block 200c through data communication. The second bus 210c may operate in a stop mode and / or a normal mode, and the normal mode may be or correspond to a mode in which the data communication between the first bus 140c and the second bus 210c is maintained. The stop mode may be or correspond to a mode in which the data communication between the first bus 140c and the second bus 210c is stopped.

[0070] In some example embodiments, when a power-off operation is performed on the first block 100c, the first control logic 110c may send an LPI request to the first bus 140c. When the LPI request is received, the first bus 140c may send a power-off notification to the second bus 210c. When the power-off notification is sent, the second bus 210c may send a power-off acceptance or a power-off rejection to the first bus 140c based on whether there is data to be transmitted to the first bus 140c through data communication, and determine whether to operate in the stop mode. The first bus 140c may send an LPI acceptance or an LPI rejection to the first control logic 110c based on the received power-off signal. The first control logic 110c may determine whether to perform a power gating operation on the first bus 140c based on the received LPI signal. Reference is made below to Fig. 6A and Figure 6B Embodiments related to an LPI signal and a power-down signal are described.

[0071] Fig. 6A and Figure 6B 30a and 30b are first and second graphs for explaining a stop mode operation of a semiconductor system 1c according to some example embodiments.

[0072] refer to Figure 5 and Fig. 6A, the first graph 30a may be a graph such as a timing diagram for explaining a stop mode of the semiconductor system 1c in a process of performing a power-on operation after performing a power-off operation on the first block 100c. In some example embodiments, the first period T1 may be a period in which the second bus 210c operates in a normal mode. The normal mode may be a mode in which data may be exchanged through data communication between the first bus 140c and the second bus 210c. For example, the first control logic 110c may receive activity information of each of the plurality of IP blocks 120c from the plurality of IP blocks 120c included in the first block 100c in a power-on state, and based on the received activity information, it may be determined whether the activity states of the plurality of IP blocks 120c are all idle states. When the activity states of the plurality of IP blocks 120c are all idle states, the first control logic 110c may determine that the first block 100c is an idle block, and may send an LPI request to the first bus 140c by changing the LPI request. For example, the LPI request is raised from a first level (e.g., logic "0") to a second level (e.g., logic "1"). When receiving the LPI request of the second level, the first bus 140c may transmit the power-down notification to the second bus 210c by raising the power-down notification from the first level to the second level.

[0073] In some example embodiments, the second period T2 may be a period in which the second bus 210c operates in the stop mode. For example, when receiving a power-off notification of the second level, the second bus 210c may determine whether there is data to be sent to the first bus 140c. When there is no data to be sent to the first bus 140c (e.g., time t1), the second bus 210c may send a power-off acceptance to the first bus 140c by changing (e.g., raising) the power-off acceptance from the first level to the second level, and may operate in the stop mode. Because the second bus 210c operates in the stop mode, data communication between the first bus 140c and the second bus 210c may be stopped. When receiving a power-off confirmation of the second level, the first bus 140c may send an LPI confirmation to the first control logic 110c by raising the LPI confirmation from the first level to the second level. When receiving the LPI acceptance of the second level, the first control logic 110c may perform a power gating operation on the first block 100c including the first bus 140c, and the first block 100c may be in a power-off state. When there is data to be sent from the second bus 210c to the first bus 140c after performing a power-off operation on the first block 100c (e.g., time t2), the second bus 210c may send a wake-up request to the first control logic 110c by changing or raising the wake-up request from the first level to the second level. When receiving the wake-up request of the second level, the first control logic 110c may send the LPI request to the first bus 140c by changing the LPI request (e.g., lowering the LPI request from the second level to the first level), and perform a power-on operation (e.g., a wake-up operation) on the first block 100c. When receiving the LPI request of the first level, the first bus 140c may send a power-off notification to the second bus 210c by changing or lowering the power-off notification from the second level to the first level. When receiving the power-off notification of the first level, the second bus 210c can send the power-off acceptance to the first bus 140c by changing the power-off acceptance (e.g., lowering the power-off acceptance from the second level to the first level). In some example embodiments, the changing level may correspond to a lowering level and an increasing level; example embodiments are not limited thereto; for example, in some cases, a logic low level may be used instead of a logic high level, and a logic high level may be used instead of a logic high level.

[0074] In some example embodiments, the third period T3 may be a period in which the second bus 210c operates in the normal mode after the stop mode. For example, the first bus 140c may send the LPI acceptance to the first control logic 110c by changing or lowering the LPI acceptance from the second level to the first level. When the first control logic 110c receives the LPI acceptance of the first level, the second bus 210c may operate in the normal mode, and the data communication between the first bus 140c and the second bus 210c may be restored. Therefore, valid data may be sent from the second bus 210c to the first bus 140c.

[0075] When the state of a specific block is in a power-off state, an error may occur when data is transmitted from another block to the specific block in the power-off state. The semiconductor system 1c can allow another block capable of performing data communication with the block in the power-off state to operate in a stop mode and stop data communication until the power-off state is converted to the power-on state, and thus prevent an error from occurring in the semiconductor system 1c.

[0076] Further references Figure 6B , the second graph 30b may be a graph for explaining a process of stopping a power-off operation and a stop mode while performing a power-off operation on a first block 100c of the semiconductor system 1c. In some example embodiments, when there is data to be transmitted to a block on which a power-off operation is performed during a stop mode entry process, the semiconductor system 1c may stop the stop mode and the power-off operation. For example, when the activity states of the plurality of IP blocks 120c are all idle states, the first control logic 110c may determine that the first block 100c is an idle block, and send an LPI request to the first bus 140c by changing or raising the LPI request from a first level to a second level. When receiving the LPI request of the second level, the first bus 140c may send a power-off notification to the second bus 210c by changing or raising the power-off notification from a first level to a second level. When there is data to be sent to the first bus 140c (e.g., time t3), the second bus 210c may send a wake-up request to the first control logic 110c by changing or raising the wake-up request from the first level to the second level, and then send a power-down rejection to the first bus 140c by changing or raising the power-down rejection from the first level to the second level. At this time, the second bus 210c does not operate in the stop mode and may remain in the normal mode. When receiving the second level of power-down rejection, the first bus 140c may send an LPI rejection to the first control logic 110c by changing or raising the LPI rejection from the first level to the second level. When receiving the second level of LPI rejection, the first control logic 110c may stop the power-off operation of the first block 100c, and the state of the first block 100c may remain in the power-on state.

[0077] Figure 7 is a block diagram illustrating a semiconductor system 1d according to some example embodiments.

[0078] refer to Figure 7 , the semiconductor system 1d may include a first block 100d and a second block 200d. Although the semiconductor system 1d is shown to include the first block 100d and the second block 200d, the semiconductor system 1d may actually include a plurality of blocks, such as a plurality of blocks (not shown). The first block 100d and the second block 200d may be respectively Figure 2 The first block 100b and the second block 200b are shown in FIG. Figure 2 Those redundant descriptions.

[0079] The clock gating controller 220d included in the second block 200d may receive a clock signal from the second control logic 130d, and may send an LPI signal to and receive an LPI signal from the second control logic 130d. The first bus 140d may perform data communication through the second bus 210d and the clock gating controller 220d. The clock gating controller 220d may operate in a stop mode or a normal mode, and the normal mode may be a mode in which data communication between the first bus 140d and the second bus 210d is maintained. The stop mode may be a mode in which data communication between the first bus 140d and the second bus 210d is stopped.

[0080] In some example embodiments, the second control logic 130d may transmit the clock signal CLK to the clock gating controller 220d, and when the first control logic 110d performs a power-off operation on the first block 100d, the second control logic 130d may transmit an LPI request to the clock gating controller 220d. When the LPI request is received, the clock gating controller 220d may transmit an LPI acceptance or an LPI rejection to the second control logic 130d based on whether there is data to be transmitted to the first bus 140d through data communication. The second control logic 130d may control whether the clock gating controller 220d operates in a normal mode or a stop mode based on the LPI signal received through the clock gating operation on the clock gating controller 220d. Referring to FIG. 1 below, Fig. 8A and Figure 8B Embodiments related to LPI signals are described.

[0081] Fig. 8A and Figure 8B 4 are third and fourth graphs 40a and 40b for explaining a stop mode of a semiconductor system 1d according to some example embodiments.

[0082] refer to Figure 7 and Fig. 8A , the third graph 40a is a graph for explaining the stop mode of the semiconductor system 1d in the process of performing a power-on operation after performing a power-off operation on the first block 100d. In some example embodiments, the fourth period T4 may be a period in which the clock gating controller 220d operates in a normal mode. For example, the first control logic 110d may receive activity information of each of the plurality of IP blocks 120d from the plurality of IP blocks 120d included in the first block 100d in a power-on state, and based on the received activity information, it may be determined whether the activity states of the plurality of IP blocks 120d are all idle states. When the activity states of the plurality of IP blocks 120d are all idle states, the first control logic 110d may perform a power control operation on the second control logic 130d. The power control operation may be an operation of controlling the second control logic 130d to perform a clock gating operation by a power control signal. After receiving the power control request as the power control signal from the first control logic 110d, the second control logic 130d may send an LPI request to the clock gating controller 220d by changing or raising the LPI request from a first level (e.g., logic “0”) to a second level (e.g., logic “1”).

[0083] In some example embodiments, the fifth period T5 may be a period in which the clock gating controller 220d operates in the stop mode. For example, upon receiving the LPI request of the second level, the clock gating controller 220d may determine whether there is data to be sent to the first bus 140d. When there is no data to be sent to the first bus 140d (e.g., time t4), the clock gating controller 220d may send the LPI acceptance to the second control logic 130d by changing or raising the LPI acceptance from the first level to the second level. The second control logic 130d may perform a clock gating operation of stopping the supply of the clock signal CLK to the clock gating controller 220d based on the LPI acceptance of the second level, and therefore, the clock gating controller 220d may operate in the stop mode. Because the clock gating controller 220 operates in the stop mode, data communication between the first bus 140c and the second bus 210c may be stopped. When the clock gating controller 220d enters the stop mode, the first control logic 110d may perform a power-off operation on the first block 100d, and the first block 100d may be in a power-off state. When there is data to be transmitted to the first bus 140d after the power-off operation is performed on the first block 100d (for example, time t5), the second bus 210d may send a wake-up request to the first control logic 110d by changing or raising the wake-up request from the first level to the second level, and the second control logic 130d may send an LPI request to the clock gating controller 220d by changing or lowering the LPI request from the second level to the first level. When receiving the LPI request of the first level, the clock gating controller 220d may send an LPI acceptance to the second control logic 130d by changing or lowering the LPI acceptance from the second level to the first level.

[0084] In some example embodiments, the sixth period T6 may be a period in which the clock gating controller 220d operates in a normal mode after the stop mode. For example, when receiving the LPI acceptance of the first level, the second control logic 130d may send the clock signal CLK to the clock gating controller 220d. Therefore, valid data may be transmitted from the second bus 210d to the first bus 140d through the clock gating controller 220d.

[0085] When the state of a specific block is in a power-off state, an error may occur when data is transmitted from another block to the specific block in the power-off state. The semiconductor system 1d can allow another block capable of performing data communication with the block in the power-off state to operate in a stop mode and stop data communication until the power-off state is converted to the power-on state, thereby preventing an error from occurring in the semiconductor system 1d.

[0086] Further references Figure 8B, the fourth graph 40b may be a graph for explaining a process of stopping a power-off operation and a stop mode while performing a power-off operation on a first block 100d of the semiconductor system 1d. In some example embodiments, when there is data to be transmitted to a block on which a power-off operation is performed during a stop mode entry process, the semiconductor system 1d may stop the stop mode and the power-off operation. For example, when the activity states of the plurality of IP blocks 120d are all idle states, the first control logic 110d may determine the first block 100d as an idle block, and the second control logic 110d may perform a power control operation on the second control logic 130d. After receiving a power control request as a power control signal from the first control logic 110d, the second control logic 130d may send an LPI request to the clock gating controller 220d by changing or raising the LPI request from a first level (e.g., logic '0') to a second level (e.g., logic '1'). When there is data to be transmitted to the first bus 140d after the clock gating controller 220d receives the LPI request of the second level (for example, time t6), the second bus 210d may transmit the wake-up request to the first control logic 110d by changing or raising the wake-up request from the first level to the second level, and the clock gating controller 220d may transmit the LPI rejection to the second control logic 130d by changing or raising the LPI rejection from the first level to the second level. When the LPI rejection of the second level is received, the second control logic 130d may not perform the clock gating operation on the clock gating controller 220d, and the clock gating controller 220d may remain in the normal mode. When the wake-up request of the second level is received, the first control logic 110d may stop the power-off operation on the first block 100d, and the state of the first block 100d may maintain the power-on state.

[0087] Fig. 9 is a block diagram illustrating an electronic device 2 according to some example embodiments.

[0088] refer to Fig. 9 , the electronic device 2 may be implemented as or include or be included in one or more handheld devices such as a mobile phone, a smart phone, a tablet PC, a PDA, an EDA, a digital still camera, a digital video camera, a PMP, a PND, a handheld game console, or an e-book.

[0089] The electronic device 2 may include the SoC 1000 , an external memory 1850 , a display device 1550 , and a PMIC 1950 .

[0090] SoC 1000 may include a CPU 1100, a clock management unit (CMU) 1200, a GPU 1300, a timer 1400, a display controller 1500, a random access memory (RAM) 1600, a read-only memory (ROM) 1700, a memory controller 1800, a PMU 1910, and a bus 1050. In addition to the components shown, SoC 1000 may also include other components. For example, electronic device 2 may also include a display device 1550, an external memory 1850, and a PMIC 1950. PMIC 1950 may be implemented outside SoC 1000. However, SoC 1000 is not limited thereto, and may include a PMU capable of performing the functions of PMIC 1950.

[0091] The CPU 1100 may also be referred to as a processor, and may process or execute a program and / or data stored in the external memory 1850. For example, the CPU 1100 may process or execute a program and / or data in response to an operation clock signal output from the CMU 1200.

[0092] The CPU 1100 may be implemented as a multi-core processor. A multi-core processor may be a computing component having two or more independent physical processors (referred to as "cores"), and each processor may read and execute program instructions. Programs and / or data stored in the ROM 1700, RAM 1600, and / or external memory 1850 may be loaded into a memory (not shown) of the CPU 1100 as needed.

[0093] The CMU 1200 may generate an operation clock signal. The CMU 1200 may include a clock signal generating device such as a phase locked loop (PLL), a delay locked loop (DLL), or a crystal oscillator.

[0094] The operation clock signal may be supplied to the GPU 1300. The operation clock signal may be supplied to other components (eg, the CPU 1100 or the memory controller 1800, etc.). The CMU 1200 may change the frequency of the operation clock signal.

[0095] The GPU 1300 may convert data read from the external memory 1850 by the memory controller 1800 into a signal suitable for the display device 1550 .

[0096] The timer 1400 may output a count value indicating time based on the operation clock signal output from the CMU 1200 .

[0097] The display device 1550 may display an image signal output from the display controller 1500. For example, the display device 1550 may be implemented as (or include or be included in) one or more of a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, or a flexible display. The display controller 1500 may control the operation of the display device 1550.

[0098] The RAM 1600 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory may be temporarily stored in the RAM 1600 by the control of the CPU 1100 or according to the boot code stored in the ROM 1700. The RAM 1600 may be implemented as or include a DRAM and / or an SRAM.

[0099] The ROM 1700 may store permanent programs and / or data. The ROM 1700 may be implemented as or include an erasable programmable read-only memory (EPROM) and / or an electrically erasable programmable read-only memory (EEPROM).

[0100] The memory controller 1800 may communicate with the external memory 1850 through an interface. The memory controller 1800 may control all operations of the external memory 1850 and control data exchange between the host and the external memory 1850. For example, the memory controller 1800 may write data to the external memory 1850 or read data from the external memory 1850 at the request of the host. Here, the host may be a master device such as the CPU 1100, the GPU 1300, or the display controller 1500.

[0101] The external memory 1850 is a storage medium for storing data, and may store an OS, various programs, and / or various data. The external memory 1850 may be, for example, a DRAM, but is not limited thereto. For example, the external memory 1850 may be or may include a non-volatile memory device (e.g., one or more of a flash memory, a PRAM, an MRAM, an RRAM, or a FeRAM device). Alternatively or additionally, the external memory 1850 may be an internal memory provided inside the SoC 1000. In addition, the external memory 1850 may be or include one or more of a flash memory, an embedded multimedia card (eMMC), or a universal flash storage (UFS).

[0102] The PMU 1910 may control the voltage required for each device connected to the SoC 1000 to operate. In some example embodiments, the SoC 1000 may include a plurality of blocks (e.g., the CPU 1100, the GPU 1300, or the bus 1050), and the PMU 1910 may perform a power-on / power-off operation on each of the plurality of blocks. The PMU 1910 may be used in conjunction with the above Figure 2 1300 or bus 1050 is the same as the first control logic 110b described in . For example, PMU 1910 can be implemented as hardware. PMU 1910 can determine whether the state of CPU 1100, GPU 1300 or bus 1050 is an idle state, and when it is determined that the state of CPU 1100, GPU 1300 or bus 1050 is an idle state, a power gating operation is performed on CPU 1100, GPU 1300 or bus 1050. The power gating operation performed by PMU 1910 on multiple blocks can be a faster operation than the power gating operation performed by OS, and the latency of the power gating operation can be reduced. Therefore, PMU 1910 can even perform a power-off operation (e.g., a power gating operation on an idle block) on a block in a short idle state of tens of ms or less, and therefore, the idle power can be reduced, and the power consumption of the semiconductor system can be reduced.

[0103] The CPU 1100 , the CMU 1200 , the GPU 1300 , the timer 1400 , the display controller 1500 , the RAM 1600 , the ROM 1700 , the memory controller 1800 , the power control circuit 1900 , and the PMU 1910 may communicate with one another via the bus 1050 .

[0104] Fig.10 is a block diagram illustrating an electronic device 3 according to some example embodiments.

[0105] refer to Fig.10 , the electronic device 3 can be implemented as a PC, a data server or a portable electronic device.

[0106] The electronic device 3 may include a SoC 2000 , a camera module 2100 , a display 2200 , a power supply 2300 , an input / output (I / O) port 2400 , a memory 2500 , a storage 2600 , an external memory 2700 , and a network device 2800 .

[0107] SoC 2000 may include a plurality of blocks (e.g., Fig. 9 The CPU 1100, GPU 1300 or bus 1050 (not shown), and each of the plurality of blocks may include the same Figure 2The same circuit (not shown) as the first control logic 110b described in . For example, the circuit (not shown) included in each of the multiple blocks can be implemented as hardware, and it can be determined whether the state of each of the multiple blocks (not shown) is an idle state. When the state of each of the multiple blocks (not shown) is an idle state, the circuit (not shown) can perform a power gating operation on each of the multiple blocks (not shown). The power gating operation of the circuit (not shown) on each of the multiple blocks can be a faster operation than the power gating operation of the OS, and the latency of the power gating operation can be reduced. Therefore, the circuit (not shown) can even perform a power-off operation (e.g., a power gating operation on an idle block) on a block in a short idle state of tens of ms or less, and therefore, the idle power can be reduced, and the power consumption of the semiconductor system can be reduced.

[0108] The camera module 2100 may be a module capable of converting an optical image into an electrical image. Therefore, the electrical image output from the camera module 2100 may be stored in the storage 2600, the memory 2500, or the external memory 2700. In addition, the electrical image output from the camera module 2100 may be displayed through the display 2200.

[0109] The display 2200 may display data output from the storage 2600, the memory 2500, the I / O port 2400, the external memory 2700, or the network device 2800. The display 2200 may be Fig. 9 Display device 1550 shown in .

[0110] The power supply 2300 may supply an operating voltage to at least one of the components. Fig. 9 The PMIC 1950 shown in FIG.

[0111] The I / O port 2400 may be a port capable of transmitting data to the electronic device 1 or transmitting data output from the electronic device 2 to an external device. For example, the I / O port 2400 may include a port for connecting a pointing device such as a computer mouse, a port for connecting a printer, or a port for connecting a USB drive.

[0112] The memory 2500 may be implemented as a volatile memory or a nonvolatile memory. According to some example embodiments, a memory controller capable of controlling a data access operation (such as a read operation, a write operation (or a program operation), or an erase operation) to the memory 2500 may be integrated or embedded in the SoC 2000. According to another embodiment, the memory controller may be implemented between the SoC 2000 and the memory 2500.

[0113] The storage device 2600 may be implemented as or may include a hard disk drive and / or a solid state drive (SSD).

[0114] The external memory 2700 may be implemented as or may include a secure digital (SD) card and / or a multimedia card (MMC). According to some example embodiments, the external memory 2700 may be a subscriber identity module (SIM) card or a universal subscriber identity module (USIM) card.

[0115] The network device 2800 may be a device capable of connecting the electronic device 3 to a wired network and / or a wireless network.

[0116] refer to Fig.10 Any or all of the elements described may be used with reference to Fig.10 For example, any element may communicate with any or all other elements described. Figure 1 Any or all other elements in the system may perform unidirectional and / or bidirectional and / or broadcast communication to transmit and / or exchange and / or receive information, such as but not limited to data and / or commands, in a serial and / or parallel manner via a wireless and / or wired bus (not shown). The information may be in various formats encoded, such as in analog format and / or in digital format.

[0117] Any of the elements and / or functional blocks disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include an electrical component such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include an electrical component such as a logic gate, which includes at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0118] Although various inventive concepts have been specifically shown and described with reference to embodiments thereof, it will be appreciated that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. The example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

Claims

1. A semiconductor system, comprising: a plurality of blocks, including a first block; as well as a controller configured to control the plurality of blocks, Wherein, the first block includes: a plurality of intellectual property IP blocks, each IP block being configured to generate activity information, and The first control logic is configured to determine an activity state of each of the plurality of IP blocks based on the activity information, and in response to the activity states of the plurality of IP blocks being all idle states, perform a power gating operation on the first block.

2. The semiconductor system according to claim 1, wherein: The first control logic is configured to perform the power gating operation in response to the active states of the plurality of IP blocks all remaining in the idle state for more than a threshold time.

3. The semiconductor system according to claim 1, wherein The plurality of blocks further includes a second block, the second block including a second bus, The first block further includes a first bus configured to perform data communication with the second bus, and The second bus is configured to operate in a stop mode in which, in response to the absence of data to be transmitted to the first bus through data communication after receiving a power-off notification through the first bus, the data communication is stopped.

4. The semiconductor system according to claim 3, wherein The first control logic is configured to send a low power interface (LPI) request to the first bus based on the activity status, The first bus is configured to send the power loss notification to the second bus after receiving the LPI request, and The second bus is configured to operate in the stop mode in response to an absence of data to be sent to the first bus through the data communication after receiving the power-off notification.

5. The semiconductor system according to claim 4, wherein The second bus is configured to, when operating in the stop mode, send a wake-up request to the first control logic in response to the presence of data to be sent to the first bus through the data communication, and The first control logic is configured to perform a wake-up operation on the first block based on the wake-up request.

6. The semiconductor system according to claim 4, wherein The second bus is configured to send a power-down rejection to the first bus in response to the presence of data to be sent to the first bus through the data communication after receiving the power-down notification, The first bus is configured to send an LPI rejection to the first control logic based on the power loss rejection, and The first control logic is configured to perform a wake-up operation on the first block based on the LPI rejection.

7. The semiconductor system according to claim 1, wherein The first control logic is configured to generate a power control signal in response to the active state of the plurality of IP blocks being in the idle state, and The first block also includes second control logic configured to perform a clock gating operation on each of the plurality of IP blocks based on the power control signal.

8. The semiconductor system according to claim 7, further comprising: The second block includes the second bus and clock gating controller, Wherein, the first block further includes a first bus, the first bus being configured to perform data communication with the second bus through the clock gating controller, and The second control logic is configured to send a clock signal to the clock gating controller and perform a clock gating operation on the clock gating controller.

9. The semiconductor system according to claim 8, wherein The clock gating controller is configured to send an LPI acceptance to the second control logic in response to the absence of data to be sent to the first bus through the data communication after receiving a low power interface LPI request generated based on the power control signal from the second control logic, and The second control logic is configured to perform the clock gating operation based on the LPI acceptance.

10. The semiconductor system according to claim 9, wherein The second bus is configured to send a wake-up request to the first control logic in response to the presence of data to be sent to the first bus via the data communication, The clock gating controller is configured to send an LPI rejection to the second control logic in response to the presence of data to be sent to the first bus through the data communication after receiving the LPI request, The second control logic is configured to supply a clock signal to the clock gating controller based on the LPI rejection, and The first control logic is configured to perform a wake-up operation on the first block based on the wake-up request.

11. The semiconductor system according to claim 1, wherein: The controller is configured to perform a power gating assist operation on the first block by communicating with the first control logic.

12. An operating method of a semiconductor system, the semiconductor system comprising a plurality of blocks, the operating method comprising: determining an activity status of each IP block of a plurality of intellectual property IP blocks included in a first block of the plurality of blocks; In response to the activity states of the plurality of IP blocks being all in an idle state, performing a power-off operation on the first block; as well as A wake-up operation is performed on the first block based on a wake-up request received by a second block among the plurality of blocks.

13. The operating method according to claim 12, wherein: The performing of the power-off operation includes performing the power-off operation in response to the active states of the plurality of IP blocks all remaining in the idle state for more than a threshold time.

14. The operating method according to claim 12, wherein The performing of the power-off operation includes, operating by the second block in a stop mode in which, in response to an absence of data to be sent from the second block to the first block via data communication, the data communication is stopped; and The power-off operation is performed on the first block after the second block operates in the stop mode.

15. The operating method according to claim 14, wherein The performing of the power-off operation includes, In response to the presence of data to be transmitted from the second block to the first block through the data communication, transmitting the wake-up request by the second block; and The power-off operation on the first block is stopped based on the wake-up request.

16. The operating method according to claim 14, wherein The performing of the power-off operation includes, In response to the absence of data to be transmitted from the second block to the first block through the data communication, performing a clock gating operation on a clock gating controller included in the second block; and A power gating operation is performed on the first block after the clock gating operation.

17. The operating method according to claim 16, wherein The performing of the power-off operation includes In response to the presence of data to be sent from the second block to the first block through the data communication, sending the wake-up request by the second block to the first block; and The power-off operation on the first block is stopped based on the wake-up request.

18. An operating method of a semiconductor system, the semiconductor system comprising a plurality of blocks, the operating method comprising: determining an activity status of each IP block of a plurality of intellectual property IP blocks included in a first block among the plurality of blocks; In response to the activity states of the plurality of IP blocks being all idle states, determining data to be sent from a second block among the plurality of blocks to the first block through data communication; cessation of the data communication in response to the absence of data to be sent via the data communication; After the data communication is stopped, performing a power-off operation on the first block; as well as A wake-up operation is performed on the first block based on the wake-up request received by the second block.

19. The operating method according to claim 18, wherein The performing of the power-off operation includes sending, by the second block, the wake-up request in response to the presence of data to be sent through the data communication after the data communication is stopped; and Power gating operation is stopped based on the wake-up request.

20. The operating method according to claim 18, wherein: The determining of the data to be sent through the data communication includes determining the data to be sent through the data communication in response to the activity states of the plurality of IP blocks all remaining in the idle state for more than a threshold time.

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