DDD5 client PMIC power-on sequence and state transition

Abstract

The invention relates to a DDR5 client PMIC power-on sequence and state transition. An apparatus includes a plurality of registers and a host interface including a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry into a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing a signal having a first level to the enable pin. The apparatus may be configured to exit the low power state in response to providing the signal having a second level to the enable pin. After exiting the low power state, the device may enter an idle state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a state of a plurality of voltage regulators.

Description

[0001] Description of the case

[0002] This application is a divisional application of the Chinese invention patent application with application number 202010600630.8 filed on June 28, 2020 and named “DDR5 Client PMIC Power-On Sequence and State Transition”.

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application is related to U.S. Provisional Application No. 62 / 868,019 filed on June 28, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0005] The present invention relates generally to computer memory and, more particularly, to methods and / or apparatus for implementing DDR5 client PMIC power-up sequences and state transitions. Background Art

[0006] Consumers are seeking to reduce the power consumption of computing devices. As computing devices become more portable, power consumption becomes increasingly important to ensure long battery life. In particular, portable computing devices such as laptops, notebooks, and netbooks have stringent current requirements in certain states. Each component of a computing device needs to be optimized to reduce power consumption.

[0007] DDR5 SODIMM / UDIMM implements various power states to minimize power consumption. A power state (or P-state) is a voltage-frequency pair that sets the speed and power consumption of a component. When operating at a lower voltage, power consumption may be lower. Generally, power consumption is lower when operating at a higher P-state.

[0008] A power management integrated circuit (PMIC) can control the power state of a DDR5 SODIMM / UDIMM. However, in order to maintain a small package size for the power management integrated circuit, the number of available pins is limited. DDR5 client PMICs and SODIMM / UDIMMs have only one pin for controlling the power state. Conventional PMICs for DDR5 client PMICs and SODIMM / UDIMMs do not allow for seamless transitions from specific power states (i.e., P1 state and P3a state) without requiring additional pins.

[0009] It is desirable to implement DDR5 client PMIC power-on sequence and state transitions. Summary of the invention

[0010] The present invention relates to a device, which includes a plurality of registers and a host interface including a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry into a low power state. One of the plurality of pins may be an enable pin. The device may be configured to enter a low power state in response to setting the power state entry register to a first value and providing a signal having a first level to the enable pin. The device may be configured to exit the low power state in response to providing a signal having a second level to the enable pin. After exiting the low power state, the device may enter an idle state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control the state of a plurality of regulators. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the invention will become apparent from the following detailed description and appended claims and accompanying drawings.

[0012] Figure 1 is a diagram illustrating an example embodiment of an unbuffered memory module.

[0013] Figure 2 It's a picture. Figure 1 Block diagram of the memory module.

[0014] Figure 3 is a diagram illustrating an example embodiment of a buffer memory module.

[0015] Figure 4 It's a picture. Figure 3 Block diagram of the memory module.

[0016] Figure 5 is a diagram illustrating a pinout diagram of a power management integrated circuit.

[0017] Figure 6 is a diagram illustrating the I2C interface between the host memory controller and the memory module. 2 C / I 3 C bus diagram.

[0018] Figure 7 is a state diagram illustrating entry and exit of a static power state.

[0019] Figure 8 is a timing diagram illustrating the power-up sequence when the VR_EN pin is high after VIN_BULK ramps up and there is no bus command.

[0020] Fig. 9 is a timing diagram illustrating the power-up sequence when the VR_EN pin is high before VIN_BULK ramps up and there is no bus command.

[0021] Fig.10 is a timing diagram illustrating the power-up sequence when the VR_EN pin is high and there is no bus command during the VIN_BULK ramp-up period.

[0022] Fig.11 is a timing diagram illustrating a power-up sequence for a PMIC with a bus command.

[0023] Fig.12 is a timing diagram illustrating the power-down sequence in the programming mode of operation when the VR_EN pin is high and the low power status register is at a low value.

[0024] Fig.13 is a timing diagram illustrating the power-down sequence in the programming mode of operation when the VR_EN pin is low and the low power status register is at a low value.

[0025] Fig.14 is a timing diagram illustrating the power-down sequence when the VR_EN pin is high and the low power status register is at a high value in the programming mode of operation.

[0026] Fig.15 is a timing diagram illustrating the power-down sequence when the VR_EN pin is low and the low power status register is at a high value in the programming mode of operation.

[0027] Fig.16 is a timing diagram illustrating the power-down sequence in the safe operating mode when the VR_EN pin is high and the low power status register is at a low value.

[0028] Fig.17 is a timing diagram illustrating a disable or enable command on the bus during a safe operating mode.

[0029] Fig.18 is a timing diagram illustrating the power-down sequence in the safe operating mode when the VR_EN pin is high and the low power status register is at a high or low value.

[0030] Fig.19 is a timing diagram illustrating a power-down sequence using the VR_EN pin in safe operating mode with the low power status register at a high value. DETAILED DESCRIPTION

[0031] Embodiments of the present invention include providing a DDR5 client PMIC power-on sequence and state transitions that can (i) seamlessly transition from a low-power P1 state to an idle P3a state, (ii) use existing pins for PMIC circuitry, (iii) use a VR_EN pin and register control to enter or exit a low-power state, (iv) support a safe operating mode and a programmable operating mode, (v) support a bidirectional PWR_GOOD pin or an output-only PWR-GOOD pin, (vi) support a VR Disable command through a VR_EN pin or a VR Disable command on an I2C / I3C bus, (vii) be implemented as part of a DDR5 unbuffered memory module, (viii) be implemented as a buffered memory module, (ix) be implemented as part of a registered double data rate fifth generation memory module, and / or (x) be implemented as one or more integrated circuits.

[0032] Embodiments of the present invention may be configured to be implemented in a double data rate fifth generation (DDR5) random access memory (RAM) module. Low power hardware and / or hardware for mobile devices may have a limited power budget. Power states (e.g., P-states) may be implemented to limit power consumption under specific operating conditions. Embodiments of the present invention may be configured to control power states (e.g., entry and exit) of DDR5 memory and operate according to the strict current requirements of various P-states.

[0033] Embodiments of the present invention may be configured to enable seamless transitions from the P1 state to the P3a state. Transitioning between P-states may reduce power consumption (e.g., helping to meet laptop power requirements). In an example, a static power state (e.g., P-state P1) may have a current requirement of approximately 25 μA, while an idle state (e.g., P-state P3a) may have a current requirement of approximately 100 μA. Embodiments of the present invention may be configured to utilize pre-existing pins (e.g., pins that already have existing functions) to transition between the P1 state and the P3a state. Reusing pins may ensure that the present invention can meet package size requirements and / or reduce layout complexity. Only one pin (e.g., the VR_EN pin) may be used to control the power state. In an example, the I 2 The VR_EN pin or the VR enable command on the C / I3C bus turns on the output rail.

[0034] In one example, embodiments of the present invention may be implemented in an unbuffered dual in-line memory module (UDIMM). For example, for a notebook computer, embodiments of the present invention may be implemented in a small outline dual in-line memory module (SODIMM). In an example, a DDR5 SODIMM may include a pin (e.g., VR_EN) for controlling the power state. In another example, embodiments of the present invention may be implemented in a registered dual in-line memory module (RDIMM). The type of memory module implemented may vary depending on the design criteria of a particular implementation.

[0035] Embodiments of the present invention may be configured to support a safe mode of operation and / or a programmable mode of operation. Embodiments of the present invention may support bidirectional operation on a pin (e.g., PWR_GOOD) and / or output-only operation on the PWR_GOOD pin. Embodiments of the present invention may be configured to support a VR Disable command using a VR_EN pin and / or a VRDisable command on an I2C / I3C bus.

[0036] Reference Figure 1 , a diagram illustrating an example embodiment of an unbuffered memory module is shown. In various embodiments, the memory system includes a plurality of circuits 50a-50n. The circuits 50a-50n may be implemented as memory modules (or boards). In an example, the circuits 50a-50n may be implemented as dual in-line memory modules (DIMMs). In some embodiments, the circuits 50a-50n may be implemented as double data rate fifth generation (DDR5) SDRAM modules.

[0037] In various embodiments, the circuits 50a-50n may include a plurality of blocks (or circuits) 72a-72n, a block (or circuit) 100, and / or various other blocks, circuits, pins, connectors, and / or traces. The circuits 72a-72n may implement memory devices. In an example, the circuits 72a-72n may be implemented as synchronous dynamic random access memory (SDRAM) devices (or chips, or modules). The circuit 100 may be implemented as a power management integrated circuit (PMIC). In an example, the PMIC 100 may comply with the JEDEC DDR5 specification. The type, arrangement, and / or number of components of the memory modules 50a-50n may be changed to meet the design criteria of a particular implementation.

[0038] Memory modules 50a-50n are shown connected to block (or circuit) 20. Circuit 20 may implement a memory controller (e.g., a host controller). Circuit 20 may be located in another device, such as a computing engine. Various connectors (or pins or traces) 60 may be implemented to connect memory modules 50a-50n to memory controller 20. In some embodiments, connectors (or pins or traces) 60 may be a 288-pin configuration. In an example, memory controller 20 may be a component of a computer motherboard (or mainboard). In another example, memory controller 20 may be a component of a microprocessor. In yet another example, memory controller 20 may be a component of a central processing unit (CPU).

[0039] In an example, some connectors (or pins or traces) 60 can be part of the memory modules 50a-50n, and some connectors (or pins or traces) 60 can be part of the motherboard and / or the memory controller 20. The memory modules 50a-50n can be connected to the computer motherboard (e.g., through pins, traces and / or connectors 60) to transfer data between the components of the computing device and the memory modules 50a-50n. In some embodiments implementing UDIMM, the connectors (or pins or traces) 60 can implement a 64-bit bus or a 72-bit bus. In an example, the memory controller 20 can be implemented on the north bridge of the motherboard and / or implemented as a component of a microprocessor (e.g., Intel CPU, AMD CPU, ARM CPU, etc.). The implementation of the memory controller 20 can vary according to the design criteria of the specific implementation.

[0040] In various embodiments, the circuits 50a-50n may be implemented as DDR5 SDRAM memory modules. In an example, the circuits 50a-50n may have a memory module density of 128 gigabytes (GB), 512 GB, 1 terabyte (TB), or more per module. In an embodiment implementing a DDR5 standard SDRAM memory module, the circuits 50a-50n may operate at a frequency of 1.2-3.2 gigahertz (GHz) and / or higher.

[0041] In an embodiment implementing a DDR5 standard SDRAM memory module, the circuits 50a-50n may have a data rate range of 3.2GT / s to 4.6GT / s. In an example embodiment implementing a DDR5 SDRAM memory module, the circuits 50a-50n may operate at a data rate of up to 8GT / s. The operating parameters of the memory modules 50a-50n may vary according to the design criteria of a particular implementation.

[0042] In an example, the memory modules 50a-50n may be implemented according to a fifth generation (DDR5) standard (e.g., a standard currently being developed by JEDEC). References to the DDR5 standard may refer to the latest operational version and / or draft version of the DDR5 specification published by JEDEC and / or distributed to committee members in March 2019. Appropriate portions of the DDR5 standard are incorporated herein by reference in their entirety. The JEDEC specification may refer to a DDR5 SDRAM specification and / or a specification for a next generation DDR SDRAM (e.g., DDR6).

[0043] Reference Figure 2 , showing the diagram Figure 1 1 is a block diagram of a memory module 50a of FIG. 1. Memory module 50a may be representative of memory modules 50b-50n. Memory module 50a is shown in communication with memory controller 20. Memory controller 20 is shown as part of block (or circuit) 10. Circuit 10 may be a motherboard (or mainboard) or other electronic component or computing engine or host device that communicates with memory module 50a.

[0044] The memory module 50a may include one or more blocks (or circuits) 80a-80n and / or the PMIC 100. The circuits 80a-80n may implement the data paths of the memory module 50a. In the example shown, the memory module 50a may include five data paths (e.g., 80a-80e) on one side of the memory module 50a and four data paths (e.g., 80k-80n) on the other side of the memory module 50a. The circuits 82a-82n may be implemented as memory channels, respectively. Each memory channel 82a-82n may include a plurality of blocks (or circuits) 84a-84n. The circuits 84a-84n may be implemented as random access memory (RAM) chips. For example, the RAM chips 84a-84n may implement volatile memories such as dynamic RAM (DRAM). The RAM chips 84a-84n may be SDRAM devices 72a-72n (e.g., the chips 84a-84n may include one or more of the circuits 72a-72n located within one of the memory channels 82a-82n). In some embodiments, the RAM chips 84a-84n may be physically located on both sides (e.g., the front and back sides) of the circuit board of the memory modules 50a-50n. The storage capacity on the memory module 50a may vary depending on the design criteria of the particular implementation.

[0045] The memory controller 20 may generate a clock signal (e.g., CLK), a plurality of control signals (e.g., ADDR / CMD), and / or a plurality of commands. The signal CLK and / or the signal ADDR / CMD may be presented to the memory channels 82a-82n. In one example, the signals ADDR / CMD and CLK may be transmitted on the common bus 52 and the common bus 54, respectively. The command may be presented to the PMIC 100 via the bus 90. The data bus 30 may be connected between the memory controller 20 and the data paths 80a-80n. The bus 30 may include traces, pins, and / or connections between the memory controller 20 and the memory channels 82a-82n. The memory controller 20 may generate and / or receive data signals (e.g., DQa-DQn) and data strobe signals (e.g., DQSa-DQSn) that may be presented / received from the data bus 30. A portion of the signals DQa-DQn and DQSa-DQSn may be presented to the corresponding data paths 80a-80n. For example, signals DQa-DQn may be DQ signals defined in the JEDEC specification, and signals DQSa-DQSn may be DQS signals defined in the JEDEC specification. In the example shown, each signal DQa-DQn may have a corresponding signal DQSa-DQSn, but in some embodiments, one DQS signal may select multiple (e.g., four) DQ signals.

[0046] The bus 90 may be implemented as a host interface bus. The host interface bus 90 may be bidirectional. The host interface bus 90 may be configured to transmit commands and / or other data to other components of the PMIC 100 and / or the memory module 50a. In some embodiments, the host interface bus 90 may implement I 2 In some embodiments, the host interface bus 90 may implement the I3C protocol. The protocol implemented by the host interface 90 may vary depending on the design criteria of a particular implementation.

[0047] Reference Figure 3 , a diagram illustrating an example embodiment of a buffer memory module is shown. Figure 3 The buffer memory module shown includes a Figure 1 A similar implementation is shown for the unbuffered memory modules.

[0048] In various embodiments, the circuits 50a-50n may include SDRAM devices 72a-72n, PMIC 100, multiple blocks (or circuits) 70a-70n, blocks (or circuits) 74, and / or various other blocks, circuits, pins, connectors, and / or traces. The circuits 70a-70n may be configured as data buffers. The circuit 74 may be implemented as a registered clock driver (RCD). In another example, the RCD circuit 74 may be implemented as an RCD circuit that complies with a JEDEC specification (e.g., a DDR5 standard). For example, in an embodiment where the circuit 50a-50n is implemented as a DDR5-compatible SDRAM module, the memory module 50a-50n may include a circuit 72a-72n arranged in a row of ten SDRAM devices (or chips, or modules), the circuit 70a-70n may be arranged in a row corresponding to the circuit 72a-72n, the RCD circuit 74 may be positioned so that the circuit 72a-72n is a group of five on either side of the two sides of the RCD circuit 74, and the power management integrated circuit 100 may comply with the JEDEC DDR5 specification. In an embodiment where a DDR5 standard SDRAM memory module is implemented, there may be 5 memory modules on each side of the RCD 74. In some embodiments, the connector (or pin or trace) 60 may implement an 80-bit bus. The number, type, and / or arrangement of the components of the circuit 50a-50n may vary according to the design criteria of a particular implementation.

[0049] Reference Figure 4 , showing the diagram Figure 31. A block diagram of a memory module of a memory module 50a. The memory module 50a may include data paths 80a-80n, an RCD circuit 74, and / or a PMIC 100. For example, the data path 80a may include a memory channel 82a and / or a data buffer 70a. The data paths 80b-80n may have similar implementations. In the example shown, the memory module 50a may include five data paths (e.g., 80a-80e) on one side of the RCD 74, and five data paths (e.g., 80j-80n) on the other side of the RCD 74. The RCD circuit 74 may be configured to communicate with the memory controller 20, the data buffers 70a-70n, the memory channels 82a-82n, and / or the PMIC 100. The RCD circuit 74 may decode instructions (e.g., control words) received from the memory controller 20. The signal CLK and / or the signal ADDR / CMD may be presented to the RCD circuit 74. For example, the RCD circuit 74 may receive a register command word (RCW). In another example, the RCD circuit 74 may receive a buffer control word (BCW). The RCD circuit 74 may be configured to train the DRAM chips 84a-84n, the data buffers 70a-70n, and / or command and address lines between the RCD circuit 74 and the memory controller 20. For example, the RCW may flow from the memory controller 20 to the RCD circuit 74. The RCW may be used to configure the RCD circuit 74.

[0050] The RCD circuit 74 can be used in both LRDIMM and RDIMM configurations. The RCD circuit 74 can implement a 32-bit 1:2 command / address register. For example, the RCD circuit 74 can have two sets (e.g., A and B) of command / address outputs. The RCD circuit 74 can support a high-speed bus (e.g., a BCOM bus between the RCD circuit 74 and the data buffers 70a-70n). The RCD circuit 74 can implement automatic impedance calibration. The RCD circuit 74 can implement command / address parity checking. The RCD circuit 74 can control register RCW readback. In an example, the RCD circuit 74 can implement a serial communication bus (e.g., a 1 MHz integrated circuit (I 2 C) bus, etc.). However, other types of management bus protocols (e.g., sideband interface, etc.) may be implemented to meet the design criteria of a particular implementation. In some embodiments, the RCD circuit 74 may implement a 12.5 MHz integrated circuit (I 3 C) bus. The input to the RCD circuit 74 can be pseudo-differential by using external and / or internal reference voltages. The clock output, command / address output, control output and / or data buffer control output of the RCD circuit 74 can be enabled in groups and driven independently with different strengths.

[0051] The RCD circuit 74 may receive a signal CLK and / or a signal ADDR / CMD from the memory controller 20. Various digital logic components of the RCD circuit 74 may be used to generate a signal based on the signal CLK and / or the signal ADDR / CMD and / or other signals (e.g., RCW). The RCD circuit 74 may also be configured to generate a signal (e.g., CLK') and a signal (e.g., ADDR' / CMD'). The signal CLK' and / or the signal ADDR' / CMD' may be presented to each memory channel 82a-82n. In one example, the signal ADDR' / CMD' and CLK' may be sent on the common bus 52 and the common bus 54, respectively. In another example, the RCD circuit 74 may implement a single ADDR / CMD input and two ADDR' / CMD' outputs to support a 1:2 command / address architecture. The RCD circuit 74 may generate one or more signals (e.g., DBC). The signal DBC may be presented to the data buffer 70a-70n. The signal DBC may implement a data buffer control signal. Signal DBC may be sent on a common bus 56 (eg, a data buffer control bus).

[0052] The data buffers 70a-70n may be configured to receive commands and data from the bus 56. The data buffers 70a-70n may be configured to generate data to / receive data from the bus 30. The bus 30 may include traces, pins, and / or connections between the memory controller 20 and the data buffers 70a-70n. The bus 58 may carry data between each data buffer 70a-70n and the corresponding memory channel 82a-82n. The data buffers 70a-70n may be configured to buffer data on the buses 30 and 58 for write operations (e.g., data transmission from the memory controller 20 to the corresponding memory channel 82a-82n). The data buffers 70a-70n may be configured to buffer data on the buses 30 and 58 for read operations (e.g., data transmission from the corresponding memory channel 82a-82n to the memory controller 20).

[0053] Data buffers 70a-70n can exchange data with DRAM chips 84a-84n in smaller units (e.g., 4-bit half bytes for x4 DRAM; or, 8-bit bytes for x8 DRAM). In various embodiments, DRAM chips 84a-84n can be arranged into multiple groups (e.g., two groups). For implementations of two groups / two DRAM chips (e.g., 84a-84b), each group can include a single DRAM chip (e.g., 84a or 84b). Each DRAM chip 84a-84b can be connected to the corresponding data buffer 70a-70n via the upper half byte and the lower half byte or byte. For implementations of two groups / four DRAM chips (e.g., 84a-84d), each group can include two DRAM chips (e.g., 84a-84b or 84c-84d). The first group can be connected to the corresponding data buffer 70a-70n via the upper half byte. Another group can be connected to the corresponding data buffer 70a-70n via the lower half byte. For an embodiment of two groups / eight DRAM chips (e.g., 84a-84h), each group may include four DRAM chips 84a-84h. One group of four DRAM chips (e.g., 84a-84d) may be connected to corresponding data buffers 70a-70n via upper nibbles. Another group of four DRAM chips (e.g., 84e-84h) may be connected to corresponding data buffers 70a-70n via lower nibbles. Other numbers of groups, other numbers of DRAM chips, and other data unit sizes may be implemented to meet the design criteria of a particular embodiment.

[0054] An interface 102 is shown. The interface 102 can be configured to enable communication between the RCD circuit 74 and the PMIC 100. For example, the interface 102 can implement a register clock driver / power management integrated circuit interface (e.g., an RCD-PMIC interface). The interface 102 can include one or more signals and / or connections. Some signals and / or connections implemented by the interface 102 can be unidirectional. Some signals and / or connections implemented by the interface 102 can be bidirectional. The interface 102 can be enabled by the host memory controller 20. In one example, the memory controller 20 can enable the interface 102 using the signal ADDR / CMD. In another example, the memory controller 20 can enable the interface 102 for the PMIC 100 by presenting an enable command. In some embodiments, the bus 90 can communicate with the RCD 74.

[0055] Reference Figure 5, a diagram illustrating a pinout diagram of a power management integrated circuit is shown. A top view of a microchip package of the PMIC 100 is shown. In an example, the microchip package of the PMIC 100 may be implemented as a quad flat no-lead (QFN) package. For example, the dimensions of the QFN package of the PMIC 100 may be approximately 4 mm x 3 mm. The amount of space available to the PMIC 100 on the circuits 50 a-50 n may be limited.

[0056] A plurality of pins for the PMIC 100 are shown. The PMIC 100 may be implemented with 28 pins (e.g., pin1-pin28). Since the amount of space available to the PMIC 100 may be limited, the size of the PMIC 100 may be limited to a particular specification. The pinout of the PMIC 100 may be implemented according to a design standard in accordance with the JEDEC DDR5 specification. In some embodiments, the pinout of the PMIC 100 may be predefined according to the JEDEC DDR5 specification. For example, due to size limitations, it may not be possible to add more pins to the PMIC 100.

[0057] Typically, pins pin1-pin28 may have predefined functionality, respectively. One or more of the pins pin1-pin28 of the PMIC 100 may be a host interface. The PMIC 100 may be configured to use the available pins pin1-pin28 to implement entry and / or exit of the P1 state and the P3a state. The PMIC 100 may be configured to add additional functionality to one or more of the pins pin1-pin28 while enabling the predefined functionality of each pin pin1-pin28.

[0058] In the example shown, pins pin 2, pin 6, and pin 20 can respectively transmit signals (e.g., VIN_BULK_A, VIN_BULK_B, and VIN_BULK_C, which can be collectively signal VIN_BULK). Pin pin 13 can transmit a signal (e.g., VOUT_1.8V). Pin pin 15 can transmit a signal (e.g., VOUT_1.0V). Pin pin 3 can transmit a signal (e.g., SWA). Pin pin 5 can transmit a signal (e.g., SWB). Pin pin 19 can transmit a signal (e.g., SWC). Pin pin 9 can transmit a signal (e.g., PID). Pin pin 23 can transmit a signal (e.g., GSI_n). Pin pin 25 can transmit a signal (e.g., PWR_GOOD). Pin pin 27 can transmit a signal (e.g., VR_EN). The pinout of PMIC 100 can vary according to the design criteria of a particular implementation and / or according to the DDR5 standard JEDEC specification.

[0059] The PMIC 100 may include blocks (or circuits) 102a-102n. The circuits 102a-102n may implement registers, respectively. Each register 102a-102n may include a location. In an example, a location 104 is shown in register 102i. Register 102i may be a power state entry register. The PMIC 100 may also include blocks (or circuits) 106a-106n. The circuits 106a-106n may implement regulators, respectively. The PMIC 100 may include other components (not shown). The number, type, and / or arrangement of the components of the PMIC 100 may vary according to the design criteria of a particular implementation.

[0060] The registers 102a-102n may be configured to provide volatile storage. The registers 102a-102n may have attributes that may be read-only, read / write, write-only, or reserved. A subset of the registers 102a-102n may include an area accessible by the host controller 20. For example, the host controller 20 may be configured to read and write from a subset of the registers 102a-102n. The subset of the registers 102a-102n may enable a DIMM vendor (e.g., a vendor of circuits 50a-50n) to program the PMIC 100. The subset of the registers 102a-102n may be a PMIC vendor (e.g., a vendor of the PMIC 100) specific area. The registers 102a-102n may be configured to provide various functions of the PMIC 100 (e.g., error logs, status information (real-time and periodic), shielding, power state entry, current thresholds, voltage settings, temperature readings, power measurements, etc.). The functionality of registers 102a-102n may vary depending on the design criteria of a particular implementation.

[0061] Registers 102a-102n may be 8-bit registers. In an example, registers 102a-102n may include 8 storage locations (or register values). Register value 104 may be a representative example of one of the register values ​​(or storage locations) of registers 102a-102n. In the example shown, register 102i may be an R1A register, and register value 104 may be an R1A[4] value (e.g., bit 4 of bits 0:7 of register R1A). The value stored in register value 104 may be configured to enable additional functionality of one or more pins of pins pin1-pin28. Register value 104 may be configured to enable a low power (e.g., static) state for PMIC 100. Register value 104 may be configured to control entry and / or exit from a low power state and an idle power state.

[0062] The register 102i may be one of a subset of registers 102a-102n accessible by the host controller 20. The register value 104 may be a read / write value (e.g., the host controller 20 may read from or write to the register value 104). The register value 104 may be a PMIC static state entry enable value (e.g., QUIESCENT_STATE_EN). In an example, when the register value 104 has a low (e.g., logic 0) value, the static state may be disabled. In an example, when the register value 104 has a high (e.g., logic 1) value, the static state may be enabled.

[0063] Regulators 106a-106n may include switching regulators and / or low dropout (LDO) regulators. In an example, regulator 106a may be a SWA regulator, regulator 106b may be a SWB regulator, and regulator 106c may be a SWC regulator. Regulators 106a-106c may be switch node output buck regulators connected to a power inductor. In another example, regulator 106d may be a 1.8V LDO regulator, and regulator 106e may be a 1.0V LDO regulator. The number and / or type of regulators implemented may vary according to the design criteria of a particular implementation.

[0064] Signal VIN_BULK may be a 5V input power supply to PMIC 100 for one or more of regulators 106a-106n. In an example, signal VIN_BULK_A may be an input power supply for SWA regulator 106a, signal VIN_BULK_B may be an input power supply for SWB regulator 106b, and signal VIN_BULK_C may be an input power supply for SWC regulator 106c. Signal VOUT_1.8V may be a 1.8V output of LDO regulator 106d. Signal VOUT_1.0V may be a 1.0V output of LDO regulator 106e. Signal SWA may be an output of SWA regulator 106a, signal SWB may be an output of switching regulator 106b, and signal SWC may be an output of switching regulator 106c. Signal PID may receive a 5V input power supply for I 2 The signal GSI_n may provide an overall status interrupt output. The signal GSI_n may be an open drain output configured to transmit an event to the host controller 20.

[0065] The signal PWR_GOOD may be an open drain output configured to indicate the power state of the PMIC 100. For example, when VIN_BULK and all enabled regulators 106a-106n remain within the tolerance threshold as configured by the corresponding registers 102a-102n, the signal PWR_GOOD may be asserted high. In an example, when VIN_BULK is below a threshold or when any of the enabled regulators 106a-106n exceeds the tolerance threshold, the signal PWR_GOOD may be asserted low. The signal PWR_GOOD may be configured as an I / O. For example, in a low power operating state, pin 25 of the signal PWR_GOOD may be used as an I / O. In another example, only pin 25 for the signal PWR_GOOD may be output.

[0066] Signal VR_EN may be a PMIC enable input signal. In an example, when signal VR_EN is asserted high, PMIC 100 may turn on one of voltage regulators 106a-106n. In an example, when signal VR_EN is asserted low, PMIC 100 may turn off one of voltage regulators 106a-106n. pin27 may be an enable pin for a host interface of PMIC 100. Enable pin pin27 may be an input configured to control the state of one or more of voltage regulators 106a-106n.

[0067] When the mask bit of the register 102a-102n is not set, the PMIC 100 can assert the output signal GSI_n and the signal PWR_GOOD when any event occurs. In an example, various events may cause the PMIC 100 to generate a VRDisable command internally (e.g., the voltage of the signal VIN_BULK is too high or too low, the voltage of the signal SWA-SWC is too high or too low, critical temperature, etc.). For events that do not trigger the VR Disable command, the PMIC 100 can operate normally. The host controller 20 can be configured to read the registers 102a-102n as status registers to determine and / or isolate the cause of the assertion of the signal GSI_n or the signal PWR_GOOD. The PMIC 100 can keep the signal GSI_n or the signal PWR_GOOD asserted until the host controller 20 clears or masks the appropriate registers 102a-102n.

[0068] In some embodiments, in the low power (e.g., static) P1 state, the current of VIN_BULK can be about 25 μA (VIN_BULK is 5V). All circuits in PMIC 100, including all regulators 106a-106n, can be turned off. Signal VR_EN can be set to a static low or static high state. Signal GSI_n can be pulled high. I2 C or I3C interface, and the bus can be pulled high. The signal PID can be pulled high or low.

[0069] In some embodiments, in the idle power P3a state, the current of VIN_BULK can be about 100 μA (VIN_BULK is 5V). All outputs and / or LDO regulators 106a-106n can be turned on at 0A output load. Signal VR_EN can be set to a static low or static high state. Signal GSI_n can be pulled high. I 2 C or I3C interface, and the bus can be pulled high. The signal PID can be pulled high or low.

[0070] The PMIC 100 may be configured to operate in a secure operating mode or a programmable operating mode. Whether the PMIC 100 operates in a secure operating mode or a programmable operating mode may be determined by one of the values ​​of the registers 102a-102n. In an example, one of the register values ​​for one of the registers 102a-102n (e.g., register value R2F[2]) may be used to determine in which operating mode the PMIC 100 functions. After registering a VR Enable command provided by the host controller 20 (e.g., using the signal VR_EN at pin 27 or at I 2 C / I3C bus), the operating mode of the PMIC 100 can be selected.

[0071] In the programmable operation mode, when the host controller 20 issues a VR Enable command (eg, using the signal VR_EN or I 2 C / I3C bus), the PMIC 100 can be configured to allow modification of any register 102a-102n based on commands provided by the host controller 20. The host controller 20 can modify any register 102a-102n that is part of the host subset of registers 102a-102n. The PMIC 100 can operate in response to programming of the registers 102a-102n by the host controller 20.

[0072] In the secure operating mode, the PMIC 100 may be configured to not allow the host controller 20 to modify some of the registers 102a-102n (e.g., secure registers). For example, in the secure operating mode, some of the registers 102a-102n may be modified by the host 20, while some of the registers 102a-102n may not allow the host 20 to modify them. The PMIC 100 may be configured to ignore requests corresponding to some of the registers 102a-102n from the host controller 20. For example, when the PMIC 100 operates in the secure operating mode, registers R15-R2F, registers R32-R34, registers R40-R6F, and / or registers R70-RFF (e.g., secure registers) of the registers 102a-102n may not be modified. Generally, although the PMIC 100 may write-protect some of the registers 102a-102n in the secure operating mode, there may be no restrictions on read operations on the registers 102a-102n in the secure operating mode (or programmable operating mode).

[0073] When the PMIC 100 has entered the secure operating mode, the host controller 20 may reboot the PMIC 100 to enable writing to the secure registers. The reboot of the PMIC 100 may be to completely remove the signal VIN_BULK to the PMIC 100 (e.g., no input to pins pin2, pin6, and pin20). The secure operating mode may be entered only after the host controller 20 has provided a VR Enable command. For example, when the PMIC 100 is powered up (e.g., corresponding to the secure operating mode), the register R2F[2] may default to zero, but the PMIC 100 may allow the host controller 20 to modify any register 102a-102n (from the host subset) before providing the VR Enable command.

[0074] Some of the registers 102a-102n may store threshold values. In an example, one or more of the registers 102a-102n may store threshold voltages for the signal SWA, the signal SWB, and / or the signal SWC. The PMIC 100 may actively monitor the output voltage on each regulator 106a-106n that is enabled. In a programming mode of operation, when the PMIC 100 detects that any switching regulator (e.g., regulator 106a-106c) has an overvoltage condition, the PMIC 100 may generate a VR Disable command, disable the switching regulator 106a-106c, update the registers 102a-102n, assert the signal GSI_n, and assert the signal PWR_GOOD (the LDO regulators 106d-106e may remain active). The PMIC 100 may enable the host controller 20 to access the registers 102a-102n to determine the cause of the overvoltage condition and clear the appropriate registers. Once the host controller 20 clears the appropriate registers and issues a VR_Enable command, the switching regulators 106a-106n may be re-enabled by the host controller 20. In the safe operating mode, when the PMIC 100 detects that any of the switching regulators 106a-106c has an overvoltage condition, the PMIC 100 may respond similarly to the programmed operating mode, but the host controller 20 may cause the PMIC 100 to reboot.

[0075] Reference Figure 6 , which shows an I2C interface between the host memory controller 20 and the memory modules 50a-50h. 2 C / I3C bus. A system bus 350 is shown. The system bus 350 can implement I 2 C or I3C protocol. In one example, the system bus 350 may utilize a combination of Figure 2 The host interface bus 90 is shown to be responsive. In general, the system bus 350 can communicate with eight DIMMs (eg, memory modules 50a-50h) per bus.

[0076] The memory modules 50a-50h may include corresponding hubs 200a-200h and / or multiple devices 352a-352n, respectively. The hubs 200a-200h may implement serial presence detection (SPD) hubs. Each SPD hub 200a-200h may enable the memory controller 20 to access information about the memory modules 50a-50h. For example, each SPD hub 200a-200h may provide access to a certain number of memories installed, timing to be used, etc. In one example, the SPD hubs 200a-200h may use I 2In another example, the SPD hubs 200a-200h may communicate using the I3C protocol. The SPD hubs 200a-200n may be configured to present the enable command from the host memory controller 20 to the PMIC 100.

[0077] In the example shown, the SPD hub 200a and slave devices 352a-352d are shown as representative examples corresponding to the memory module 50a. In the example, the slave devices 352a-352d can be the PMIC 100, the RCD 74, and two temperature sensors. A portion 350' of the system bus 350 is shown on the memory module 50a, which communicates between the SPD hub 200a and the slave devices 352a-352d. In some embodiments, the system bus 350 can communicate with at least five devices of each memory module 50a-50h (e.g., to receive power measurement readouts, the status of the PMIC 100, temperature readouts, the status of the SPD, and / or the status of the RCD 74).

[0078] In an example of a system bus 350 implementing the I3C protocol (e.g., operating at 12.5 MHz), the total amount of time used for a basic periodic read (e.g., excluding packet error checking (PEC), IBI checking, and / or software overhead) can be approximately 464 μs. For example, using only the system bus 350, the PMIC current / power read time can be approximately 128 μs (e.g., 8*16) when there is one PMIC per DIMM, and 256 μs (e.g., 2*8*16) when there are two PMICs per DIMM. In another example, using only the system bus 350, the PMIC overall status read time can be approximately 128 μs (e.g., 8*16) when there is one PMIC per DIMM, and 256 μs (e.g., 2*8*16) when there are two PMICs per DIMM. In yet another example, using only the system bus 350, the temperature sensor (TS) readout time may be 128 μs (e.g., 8*2*8) when each DIMM has two temperature sensors, and 48 μs (8*6) when each DIMM has 1 SPD TS. In yet another example, using only the system bus 350, the SPD readout time may be approximately 80 μs when each DIMM has 1 SPD (e.g., in addition to the SPD TS, two registers (MR48 and MR52) may also be read). In addition, using only the system bus 350 may also include the RCD readout time. In another example, using I 2 C-bus protocol (e.g., running at 1 MHz), the total time for a basic cycle read may be approximately 5.5 ms.

[0079] The PMIC 100 may be configured to provide real-time measured power and / or current consumption for each rail (e.g., on each regulator module). In an example, the memory controller 20 may access the power data and utilize this information to adjust access patterns for the DRAM modules 72a-72n. The system bus 350 may be configured to enable the memory controller 20 to access the power data (e.g., via I 2 C / I3C protocol).

[0080] At power-up, by default, the PMIC 100 can 2 C operating mode. 2 In I C operating mode, the maximum operating speed of PMIC 100 may be limited to 1 MHz, in-band interrupts may not be supported, resetting bus 350 may not be supported, parity checking may not be supported (except for supported CCC), and packet error checking may not be supported. PMIC 100 may be in I 2 The PMIC 100 may operate in the I3C mode until the host 20 provides a command to enter the I3C mode of operation. In an example, the host 20 may issue a SETAASA CCC command to initiate the I3C mode of operation. In the I3C mode of operation, the PMIC 100 may have a maximum operating speed of up to 12.5 MHz, may support in-band interrupts, may support resetting the bus 350, may enable parity checking by default, and may support (but disable by default) packet error checking.

[0081] Reference Figure 7 , a state diagram illustrating entering and exiting a static power state is shown. A state diagram 380 is shown. State diagram 380 may include power states 382-392. Power state 382 may be a P0 state. Power state 384 may be a P2_B power state. Power state 386 may be a P3 (or P3a) power state. Power state 388 may be a P1 power state. State 390 may be a P2_A1 power state. Power state 392 may be a P2_A2 power state. Power states 382-392 may be power states in which the PMIC 100 may be configured to operate. The PMIC 100 may include other power states (not shown). The number and / or type of power states implemented by the PMIC 100 may vary depending on the design criteria of a particular implementation.

[0082] In the P0 power state 382, ​​the signal VIN_BULK may be inactive and the PWR_GOOD signal may be a logic low value. For example, there may be no input to pins pin2, pin6, and pin20. The P0 power state 382 may be a restart of the PMIC 100. The PMIC 100 may move from the P0 power state 382 to the P2_B power state 384.

[0083] In the P2_B power state 384, all switching regulators 106a-106c may be off and all LDO regulators 106d-106e may be on. In the P2_B power state 384, the signal PWR_GOOD may be a logic low value and the signal VR_EN may be a logic low value (or a high impedance state). In the P2_B power state 384, the register value R32[7] may be zero. The P2_B power state 384 may be a transition state from the P0 power state 382 and / or the P1 power state 388 prior to a VR Enable command. When the signal VR_EN transitions to high or the VR Enable command is on at I 2 C / I3C bus 90, P2_B power state 384 may move to P3 power state 386.

[0084] In the P3 power state 386, all switching regulators 106a-106c may be on. In an example, the P3 power state 386 may be a voltage regulation mode of operation and / or a VIN_BULK link monitoring mode of operation. In the P3 power state 386, the register value R32[7] may be 1. In an example, in the P3 power state 386, the PMIC 100 may have a current of approximately 100 μA at 5V VIN_BULK.

[0085] In the P3 power state 386, if the VR_EN pin transitions from high to low, the R32[5] register is set to 0 and the register value 104 is set to 0, the signal PWR_GOOD may be low and the PMIC 100 may move to the P2_A1 power state 390. In the P3 power state 386, if the VR_EN pin transitions from high to low, the R32[5] register is set to 0 and the register value 104 is set to 1, the signal PWR_GOOD may be low and the PMIC 100 may move to the P1 power state 388. In the P3 power state 386, if the VR_EN pin transitions from high to low and the R32[5] register is set to 1, the PMIC 100 may be in an improper configuration (e.g., using both the signal VR_EN and the signal PWR_GOOD as I / O types may be inappropriate because the VR_EN pin can turn the output rail on or off only when the signal PWR_GOOD is configured as an I / O, and the signal PWR_GOOD may be connected to GND if the signal PWR_GOOD is configured as an I / O). In the P3 power state 386, if the VR_EN pin transitions from low to high, the signal PWR_GOOD may be in a high impedance state and the PMIC 100 may move to stay in the P3 power state 386 (e.g., assuming the PMIC 100 is configured as an I / O type via I 2The VR Enable command on the C / I3C bus 90 enters the P3 power state 386).

[0086] In P3 power state 386, if the VR Enable command is in I 2 C / I3C bus 90, the R2F[2] register is set to 1 and the register value 104 is set to 0, the signal PWR_GOOD may be in a high impedance state and the PMIC 100 may move to the P2_A1 power state 390. In the P3 power state 386, if the VR Enable command is issued during I 2 On the C / I3C bus 90, the R2F[2] register is set to 1 and the register value 104 is set to 1, the signal PWR_GOOD may be in a high impedance state and the PMIC 100 may move to the P1 power state 388. In the P3 power state 386, if the VR Enable command is issued on the I 2 On the C / I3C bus 90, the R2F[2] register is set to 0, the signal PWR_GOOD may be in a high impedance state and the PMIC 100 may remain in the P3 power state 386. In the P3 power state 386, if the VR disable command is issued on the I 2 C / I3C bus 90, signal PWR_GOOD may be in a high impedance state and PMIC 100 may remain in P3 power state 386 (eg, assuming PMIC 100 enters P3 power state 386, VR_EN pin transitions high).

[0087] In the P3 power state 386, if the signal PWR_GOOD is input low and the R32[5] register is set to 0, the signal PWR_GOOD may be in a high impedance state and the PMIC 100 remains in the P3 power state 386 (e.g., (the PWR_GOOD I / O type may be configured as output only, the PWR_GOOD input may be low, but internally, the output signal PWR_GOOD may be in a high impedance state). In the P3 power state 386, if the signal PWR_GOOD is input low and the R32[5] register is set to 1, the signal PWR_GOOD may be low and the PMIC 100 remains in the P2_A1 power state 390.

[0088] In the P3 power state 386, if there is an internal VR Disable event and the R2F[2] register is set to 0, the signal PWR_GOOD may be low, the PMIC 100 may move to the P2_A1 power state 390, and the PMIC 100 may need to be restarted. In the P3 power state 386, if there is an internal VR Disable event and the R2F[2] register is set to 1, the signal PWR_GOOD may be low, the PMIC 100 may move to the P2_A1 power state 390, and the PMIC 100 may not need to be restarted (e.g., assuming that the event no longer exists and the status register is cleared, the PMIC 100 can re-enable the output regulators 106a-106n using the VR Enable command). In the P3 power state 386, if the signal VIN_BULK is invalid, the PMIC 100 may move to the P0 power state 382.

[0089] In the P1 power state 388, the register value 104 may be set to 1. The P1 power state 388 may only be entered from the P3 power state 386. In the P1 power state 388, if the VR_EN pin transitions from low to high and the register value 104 is set to 1, the signal PWR_GOOD may be in a high impedance state, a restart may not be required and the PMIC 100 may move to the P3 power state 386. In the P1 power state 388, if the VR Enable or VR Disable command is set at I 2 C / I3C bus 90 and register value 104 is set to 1, signal PWR_GOOD may not change and PMIC 100 may remain in P1 power state 388. In one example, in P1 power state 388, at 5V VIN_BULK, PMIC 100 may have a current of approximately 25 μA. For example, in P1 power state 388, PMIC 100 may consume less power than in P3 power state 386.

[0090] The P2_A1 power state 390 may be a no fault event state. After a VR Enable command, the P2_A1 power state 390 may transition from the P3 power state 386. In the P2_A1 power state 390, all switching regulators 106a-106c may be off. In the P2_A1 power state 390, all LDO regulators 106e-106f may be on. In the P2_A1 power state 390, the signal PWR_GOOD may be low or high, the input signal VR_EN may be low or high, and the register R32[7] may be set to 0.

[0091] In the P2_A1 power state 390, if the VR_EN pin transitions from high to low, there may be no change (e.g., the PMIC 100 may already be in the P2_A1 power state 390 and the VR_EN pin may not have any meaning). In the P2_A1 power state 390, if the VR_EN pin transitions from low to high, and register R32[5] is set to 1, the PMIC 100 may be in an improper configuration. In the P2_A1 power state 390, if the VR_EN pin transitions from low to high, register R32[5] is set to 0, and register value 104 is set to 0, signal PWR_GOOD may be in a high impedance state and the PMIC 100 may move to the P3 power state 386. In general, the P2_A1 power state 390 may not be entered if there is no event (e.g., register value 104 is set to 1).

[0092] In P2_A1 power state 390, if the VR Disable command is on I 2 C / I3C bus 90, there may be no change (e.g., PMIC 100 is already in P2_A1 power state 390 via VR_EN pin, VR Disable command may have no effect). In P2_A1 power state 390, if VR Enable command is on I3C bus 90, then there may be no change (e.g., PMIC 100 is already in P2_A1 power state 390 via VR_EN pin, VR Disable command may have no effect). 2 C / I3C bus 90, and register R2F[2] is set to 0, then there may be no change. In P2_A1 power state 390, if the VR Enable command is on I 2 C / I3C bus 90, and register R2F[2] is set to 1, signal PWR_GOOD may be in a high impedance state and PMIC 100 may move to P3 power state 386, and a restart may not be required.

[0093] In the P2_A1 power state 390, if there is an internal VR Disable event and register R2F[2] is set to 0, the signal PWR_GOOD may be set low, a restart may be required, and the PMIC 100 may move to the P2_A2 power state 392. In the P2_A1 power state 390, if there is an internal VR Disable event and register R2F[2] is set to 1, the signal PWR_GOOD may be set low, a restart may not be required, and the PMIC 100 may move to the P2_A2 power state 392 (e.g., assuming that the event no longer exists and the status registers are cleared, the PMIC 100 may re-enable the output regulators 106a-106n using the VR Enable command, and, if there is a thermal shutdown, the PMIC 100 may need to restart regardless of the settings of the registers 102a-102n). In the power state P2_A1, if the signal VIN_BULK is not valid, the PMIC 100 may move to the P0 power state 382.

[0094] The P2_A2 power state 392 may be a fault event state. After a VR Enable command, the P2_A2 power state 392 may transition from the P3 power state 386. In the P2_A2 power state 392, all switching regulators 106a-106c may be off. In the P2_A2 power state 392, all LDO regulators 106e-106f may be on. In the P2_A2 power state 392, the signal PWR_GOOD output may be low, the input signal VR_EN may be low or high, and the register R32[7] may be set to 0.

[0095] In the P2_A2 power state 392, if the VR_EN pin transitions from high to low, there may be no change (e.g., the PMIC 100 may already be in the P2_A2 power state 392 and the VR_EN pin may not have any meaning). In the P2_A2 power state 392, if the VR_EN pin transitions from low to high and the register R2F[2] is set to 0, the signal PWR_GOOD may be set to low, the PMIC 100 may need to be restarted and the PMIC 100 may remain in the P2_A2 power state 392. In the P2_A2 power state 392, if the VR_EN pin transitions from low to high, the register R2F[2] is set to 1 and the register value 104 is set to 0, the signal PWR_GOOD may be in a high impedance state, a restart may not be required, and the PMIC 100 may move to the P3 power state 386. In the P2_A2 power state 392, if the VR_EN pin transitions from low to high, register R2F[2] is set to 1, register R32[5] is set to 0, and register value 104 is set to 0, then signal PWR_GOOD may be in a high impedance state, a restart may not be required and the PMIC 100 may move to the P3 power state 386. In the P2_A2 power state 392, if the VR_EN pin transitions from low to high, register R2F[2] is set to 1, register R32[5] is set to 1, and register value 104 is set to 0, then the PMIC 100 may be in an improper configuration.

[0096] In P2_A2 power state 392, if the VR Enable command is on I 2 C / I3C bus 90 and register R2F[2] is set to 0, signal PWR_GOOD may be set low, a reboot may be required, and PMIC 100 may remain in P2_A2 power state 392. In P2_A2 power state 392, if the VR Enable command is issued on I 2 On the C / I3C bus 90, register R2F[2] is set to 1 and register value 104 is set to 0, signal PWR_GOOD may be in a high impedance state, a restart may not be required, and the PMIC 100 may move to the P3 power state 386. In the P2_A2 power state 392, if the VR Enable command is issued on the I 2 On the C / I3C bus 90 , register R2F[2] is set to 1 and register value 104 is set to 1, then signal PWR_GOOD may be in a high impedance state, a restart may not be required and the PMIC 100 may move to the P3 power state 386 .

[0097] In the P2_A2 power state 392, if an internal VR Disable event occurs and register R2F[2] is set to 0, there may be no change and a reboot may be required. In the P2_A2 power state 392, if an internal VRDisable event occurs and register R2F[2] is set to 1, there may be no change and a reboot may not be required. In the P2_A2 power state 392, if the signal VIN_BULK is not active, the PMIC 100 may move to the P0 power state 382.

[0098] The P1 power state 388 may be a static power state. In the static power state 388, the signal VIN_BULK may be nominally 5V and may require a current of 25μA. In the static power state 388, all circuits in the PMIC 100, including the switching regulators 106a-106c and the LDO regulators 106d-106e, may be off. In the static power state 388, the signal VR_EN may be at a static low level or high level. In the static power state 388, I 2 C / I3C interface access (e.g., access to bus 90 can be disabled) and can be pulled high, and signal PID can be at a static low or high level. Static power state 388 is applicable only when register value 104 is set to a logic 1 (or high) value. When PMIC 100 enters static power state 388, PMIC 100 can store the settings of register bits R32[5], R2F[2] and register value 104 in non-volatile memory as long as signal VIN_BULK is valid. In an example, the non-volatile memory can be accessed via host controller 20. When PMIC 100 is in a programming operation mode and in static power state 388, pin 25 of signal PWR_GOOD can be configured to have bidirectional operation.

[0099] The P3 / P3a power state 386 may be an idle power state. In the idle power state 386, the signal VIN_BULK may be nominally 5V and may require a current of 100μA. In the idle power state 386, all circuits in the PMIC 100, including the switching regulators 106a-106c and the LDO regulators 106d-106e, may be on at a 0A load. In the idle power state 386, the signal VR_EN may be at a static low or high level. In the idle power state 386, the I 2C / I3C interface access (e.g., access to bus 90 may be enabled) and may be pulled high, and signal PID may be at a static low or high level. Idle power state 386 is applicable only when register value 104 is set to a logic 0 (or low) value. P3a power state may be the same as P3 power state, but the load on all switching output regulators 106a-106c and LDO regulators 106d-106e is 0A. For example, in static power state 388, PMIC 100 may consume less power than when in idle power state 386.

[0100] Register 102i may be a power state entry register. Power state entry register 102i may be an R1A register. Power state entry register R1A may include 8 bits (e.g., eight storage locations). One of the storage locations (e.g., R1A[4]) may be a register value 104. The R1A register may be configured to control entry into a static (e.g., low) P1 power state 388.

[0101] Bit [0] of register R1A may be a VOUT_1.0V_POWER_GOOD_THRESHOLD_VOLTAGE storage location that may provide a VOUT_1.0V LDO output threshold voltage for a power good state. In an example, a value of 0 of bit [0] of register R1A may be -10% of the setting of register R51[2:1], and a value of 1 may be -15% of the setting of register R51[2:1].

[0102] Bit [1] of register R1A may be an OUTPUT_POWER_SELECT storage location (e.g., applicable only when register RIB [6] is set to 1), which may provide a switch output power selection. In an example, a value of 0 of bit [1] of register R1A may report the individual power of each rail on R0C, R0E, and R0F, and a value of 1 may report the total power of each rail in R0C.

[0103] Bit [2] of register R1A may be a VOUT_1.8_POWER_GOOD_THRESHOLD_VOLTAGE storage location that may provide an LDO output threshold voltage for a power good state. In an example, a value of 0 of bit [2] of register R1A may indicate a voltage of 1.6V, and a value of 1 may be reserved. Bit [3] of register R1A may be reserved.

[0104] Bit [4] of register R1A may be register value 104. Register value 104 may be a QUIESCENT_STATE_EN storage location that may provide an enable bit for entering static power state 388. Register value 104 must be configured prior to issuing a VR Enable command. In an example, a value of 0 for register value 104 disables static power state 388, while a value of 1 may enable static power state 388 (e.g., a VR Disable command (e.g., only in programmable mode, the VR_EN pin transitioning to low or register R32[7] being set to 0) may cause the PMIC 100 to enter static power state 388).

[0105] Bit [5] of register R1A may be a VIN_BULK_POWER_GOOD_THRESHOLD_VOLTAGE storage location that may provide a VIN_BULK input power (falling) threshold voltage for a power good state. In an example, a value of 0 of bit [5] of register R1A may indicate a voltage of 4.0 V, and a value of 1 of bit [5] of register R1A may indicate a voltage of 3.75 V. Bits [6:7] of register R1A may be reserved.

[0106] The default value of the bits of register R1A may be 0. In an example, by default, the register value 104 may be a value of 0. With the register value 104 value of 0, the PMIC 100 may disable the static power state 388 (e.g., the PMIC 100 may not enter the static power state 388). The register value 104 may be changed to a value of 1 to enable the static power state 388. The register value 104 may be changed by a command from the host controller 20. In one example, the command from the host controller 20 to change the register value 104 may be a transition of the signal VR_EN. In another example, the command from the host controller 20 to change the register value 104 may be a VR Enable command or a VR Disable command on the bus 90.

[0107] In some embodiments, a host controller interface (e.g., pins pin1-pin28) for PMIC 100 may be defined by the DDR5 specification. Each of the pins pin1-pin28 may have a specific function. The signal VR_EN may have a predefined functionality. The PMIC 100 may add the predefined functionality of pin pin28. For example, the PMIC 100 may reuse pin pin28 and register value 104 to control entry into and exit from a static power state 388. The PMIC 100 may be configured to work within the requirements of the DDR5 specification (and later generation versions) to add the functionality of a static power state 388. The combination of pin pin28 for the signal VR_EN and register value 104 for controlling entry into and exit from a static power state 388 may enable the PMIC 100 to control the state of the regulators 106a-106n without increasing the number of pins pin1-pin28 of the host controller interface of the PMIC 100.

[0108] Reference Figure 8 , a timing diagram illustrating a power-up sequence when the VR_EN pin is high and there is no bus command after VIN_BULK ramps up is shown. A timing diagram 420 is shown. The timing diagram 420 may include waveforms 422-438. Waveform 422 may represent the signal VIN_BULK. Waveform 424 may represent the signal VOUT_1.8V. Waveform 426 may represent the signal VOUT_1.0V. Waveform 428 may represent the I 2 C / I3C bus 90. Waveform 430 may represent signal VR_EN. Waveform 432 may represent signal SWC. Waveform 434 may represent signal SWB. Waveform 436 may represent signal SWA. Waveform 438 may represent signal PWR_GOOD.

[0109] Vertical lines 440-450 are shown. Vertical lines 440-450 may correspond to specific timing and / or responses performed by PMIC 100. In an example, vertical line 440 may represent a sequence of events and / or actions. Vertical line 440 may correspond to a transition of VIN_BULK waveform 422 from low to high. Vertical line 442 may correspond to a transition of VOUT_1.8V waveform 424 from low to high. The time between line 440 and line 442 may be t1.8V_READY. Vertical line 444 may correspond to a transition of VOUT_1.0V waveform 426 from low to high. The time between line 442 and line 444 may be t1.0V_READY.

[0110] Line 448 may correspond to the transition of VR_EN waveform 430 from low to high. Line 446 may precede line 448. The time between line 442 and line 446 may be tMANAGEMENT_READY. The time between line 440 and line 448 may be tVIN_BULK_TO_VR_ENABLE. 2 There may be no VR Enable command on C / I3C bus 90.

[0111] At time 448, SWC waveform 432 may transition from low to high, then SWB waveform 434 may transition from low to high, then SWA waveform 436 may transition from low to high, then PWR_GOOD waveform 438 may transition from low to high. For example, changing VR_EN waveform 430 (e.g., providing an input) may change the state of regulators 106a-106n. Prior to time 440, PWR_GOOD waveform 438 may be in an indeterminate state 452. Line 450 may correspond to the transition of the PWR_GOOD waveform from low to high. The time between line 448 and line 450 may be tPMIC_PWR_GOOD_OUT.

[0112] Signal VIN_BULK (e.g., signal VIN_BULK_A, signal VIN_BULK_B, and signal VIN_BULK_C) can be one input power supply for PMIC 100. The input power supply can be received from a host platform (e.g., host controller 20). The VIN_BULK power supply can be used by PMIC 100 for all three switching output regulators 106a-106c and two LDO output regulators 106d-106e. Signal VOUT_1.8V (e.g., LDO output) can be separate and independent from signal SWC (e.g., a switching output that can be used for a DRAM VPP rail). Signal VOUT_1.0V (e.g., LDO output) can be separate and independent from signal SWA or SWB.

[0113] When the PMIC 100 is powered on, the VIN_BULK supply may reach a minimum threshold voltage of approximately 4.25V before being detected as valid to the PMIC 100. After the VIN_BULK supply reaches the minimum threshold voltage, the PMIC 100 may update register R08[7] when signal VIN_BULK falls below the threshold setting in bit [5] of register R1A.

[0114] Once the VIN_BULK supply is valid (e.g., at time 440), the PWR_GOOD waveform 438 may transition from the indeterminate state 452 to a low value, and the PMIC 100 may drive the VOUT_1.8V waveform 424 high (e.g., within t1.8V_READY) and the VOUT_1.0V waveform 426 high (e.g., within t1.0V_READY). The PMIC 100 may only drive the signal PWR_GOOD low when the VIN_BULK waveform 422 reaches the minimum threshold voltage. The PWR_GOOD waveform 438 may be pulled up (e.g., from 1.8V to 3.3V) on the platform or on the host controller 20. The pull-up voltage of the waveform PWR_GOOD 438 may be used only after the signal VIN_BULK is valid and stable. The PMIC 100 may enable I 2 C / I3C bus 90 interface function. The host 20 may not attempt to access registers 102a-102n until the tMANAGEMENT_READY timing requirement is met.

[0115] During power-up, the host 20 may ramp up the VIN_BULK waveform 422, keep the VIN_BULK waveform 422 stable for a minimum time period of tVIN_VULK_TO_VR_ENABLE, and keep the VR_EN pin statically low or high. Generally, there may be no timing relationship requirements for the VR_EN waveform 430 as long as the VR_EN waveform 430 is maintained at a static level (low or high). During the ramp-up of the VIN_BULK waveform 422, if the VR_EN waveform 430 is maintained low, the VR_EN waveform 430 may only transition to high once. Once high, the VR_EN waveform 430 is not allowed to transition to low during the ramp-up of the VIN_BULK waveform 422. If the VR_EN waveform 430 is maintained high or transitions high during the ramp-up of the VIN_BULK waveform 422, the PMIC 100 may turn on the output rail. If VR_EN waveform 430 is held low during the ramp-up of VIN_BULK waveform 422, host 20 may assert signal VR_EN high to turn on the PMIC 100 output rail. 2 C / I3C bus 90 sets register R32[7] to 1 to issue a VR Enable command to turn on the PMIC 100 output rail. Figure 8-12 The example power-up initialization sequence shown may be a representative example. A specific ramp-up sequence may be configured via registers 102a-102n corresponding to the power-up sequence configuration.

[0116] When registering the VR Enable command in I 2 After registering the signal VR_EN high on the C / I3C bus 90, the PMIC 100 may perform a number of steps within a time tPMIC_PWR_GOOD_OUT. The PMIC 100 may check whether the power good state of the VIN_BULK waveform 422 is valid. The PMIC 100 may power up using a power-up sequence configuration (e.g., described by register R40 and / or register R42) and internal registers 102a-102n as programmed in the DIMM vendor memory space registers. The PMIC 100 may then power up all enabled output switching regulators 106a-106c in preparation for normal operation. The PMIC 100 may then update a status register (e.g., R08) and float the PWR_GOOD waveform 438 within a time tPMIC_PWR_GOOD_OUT. If the PWR_GOOD waveform 438 is not floating within the time tPMIC_PWR_GOOD_OUT, the host 20 may access the status register of the PMIC 100 to obtain detailed information. After the VR Enable command, until the time tPMIC_PWR_GOOD_OUT expires, the PMIC 100 may not confirm the I 2 C / I3C bus 90.

[0117] Reference Fig. 9 , a timing diagram illustrating a power-up sequence when the VR_EN pin is high and there is no bus command before VIN_BULK ramps up is shown. A timing diagram 480 is shown. The timing diagram 480 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0118] Vertical lines 482-490 are shown. Vertical lines 482-490 may correspond to specific timing and / or responses by PMIC 100. Vertical line 482 may correspond to a transition of VIN_BULK waveform 422 from low to high. Vertical line 484 may correspond to a transition of VOUT_1.8V waveform 424 from low to high. The time between line 482 and line 484 may be 11.8V_READY. Vertical line 486 may correspond to a transition of VOUT_1.V waveform 426 from low to high. The time between line 484 and line 486 may be t1.0V_READY.

[0119] The transition of VR_EN waveform 430 from low to high may occur before time 482 (e.g., before the ramp-up of VIN_BULK waveform 422). Line 488 may be after line 486. The time between line 484 and line 488 may be tMANAGEMENT_READY. Line 490 may correspond to the transition of PWR_GOOD waveform 438 from low to high (and after the transition of SWC waveform 432 from low to high, the transition of SWB waveform 434 from low to high, and the transition of SWA waveform 436 from low to high). PWR_GOOD waveform 438 may be in an indeterminate state 492 before time 482 (e.g., before VIN_BULK ramps up). The time between time 482 and time 490 may be tVIN_BULK_TO_PWR_GOOD_OUT. 2 There may be no VR Enable command on C / I3C bus 90.

[0120] Reference Fig.10 , shows a timing diagram illustrating a power-up sequence when the VR_EN pin is high and there is no bus command during the VIN_BULK ramp-up period. A timing diagram 520 is shown. The timing diagram 520 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0121] Vertical lines 522-530 are shown. Vertical lines 522-530 may correspond to specific timing and / or responses by PMIC 100. Vertical line 522 may correspond to a transition of VIN_BULK waveform 422 from low to high. Vertical line 524 may correspond to a transition of VOUT_1.8V waveform 424 from low to high. The time between line 522 and line 524 may be t1.8V_READY. Vertical line 526 may correspond to a transition of VOUT_1.0V waveform 426 from low to high. The time between line 524 and line 526 may be t1.0V_READY.

[0122] The transition of VR_EN waveform 430 from low to high may occur at time 522 (e.g., during the ramp-up of VIN_BULK waveform 422). Line 528 may be after line 526. The time between line 524 and line 528 may be tMANAGEMENT_READY. Line 530 may correspond to the transition of PWR_GOOD waveform 438 from low to high (and after the transition of SWC waveform 432 from low to high, the transition of SWB waveform 434 from low to high, and the transition of SWA waveform 436 from low to high). PWR_GOOD waveform 438 may be in an indeterminate state 532 before time 522 (e.g., before VIN_BULK ramps up). The time between time 522 and time 530 may be tVIN_BULK_TO_PWR_GOOD_OUT. I 2 There may be no VR Enable command on C / I3C bus 90.

[0123] Reference Fig.11 , shows a timing diagram illustrating a power-up sequence for a PMIC in the presence of a bus command. A timing diagram 580 is shown. The timing diagram 580 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0124] Vertical lines 582-592 are shown. Vertical lines 582-592 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 582 may correspond to a transition of the VIN_BULK waveform 422 from low to high. Vertical line 584 may correspond to a transition of the VOUT_1.8V waveform 424 from low to high. The time between line 582 and line 584 may be t1.8V_READY. Vertical line 586 may correspond to a transition of the VOUT_1.0V waveform 426 from low to high. The time between line 584 and line 586 may be t1.0V_READY.

[0125] Line 588 may be after line 586. The time between line 584 and line 588 may be tMANAGEMENT_READY. Line 590 may correspond to I 24C bus 90. The VR Enable command 596 may be asserted after the ramp-up of the VIN_BULK waveform 422. After the VR Enable command 596, the transition of the SWC waveform 432 may be from low to high, the transition of the SWB waveform 434 may be from low to high, and the transition of the SWA waveform 436 may be from low to high. The PWR_GOOD waveform 438 may transition from low to high after the VR Enable command 596 and after the transition of the waveforms 432-436 at time 592. The PWR_GOOD waveform 438 may be in an indeterminate state 594 before time 582 (e.g., before the VIN_BULK ramps up). The time between time 582 and time 590 may be tVIN_BULK_TO_VR_ENABLE. The time between time 590 and time 592 may be tPMIC_PWR_GOOD_OUT. A portion 598 of the VR_EN waveform 430 is shown after the VR Enable command 596. After the VR Enable command 596 , the VR_EN pin going high may have no effect on the operation of the PMIC 100 .

[0126] Reference Fig.12 , shows a timing diagram illustrating a power-down sequence when the VR_EN pin is high and the low power status register is at a low value in the programming mode of operation. A timing diagram 620 is shown. The timing diagram 620 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0127] Vertical lines 622-632 are shown. Vertical lines 622-632 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 622 may correspond to a transition of the VIN_BULK waveform 422 from low to high. Vertical line 624 may correspond to a transition of the VOUT_1.8V waveform 424 from low to high. The time between line 622 and line 624 may be t1.8V_READY. Vertical line 626 may correspond to a transition of the VOUT_1.0V waveform 426 from low to high. The time between line 624 and line 626 may be t1.0V_READY.

[0128] Line 628 may be after line 586. The time between line 624 and line 628 may be tMANAGEMENT_READY. Vertical line 630 may correspond to the transition of VR_EN waveform 430 from low to high. After the ramp-up of VIN_BULK waveform 422, VR_EN waveform 430 may transition to high. After time 630, SWC waveform 432 may transition from low to high, SWB waveform 434 may transition from low to high, and SWA waveform 436 may transition from low to high. PWR_GOOD waveform 438 may transition from low to high after time 630 and the transition of waveforms 432-436 at line 632. PWR_GOOD waveform 438 is in an indeterminate state 634 before time 622 (e.g., before VIN_BULK ramps up). The time between time 622 and time 630 may be tVIN_BULK_TO_VR_ENABLE. The time between time 630 and time 632 may be tPMIC_PWR_GOOD_OUT. After the VR_EN waveform 430 is asserted high at time 630, a VR Enable command 636 is shown. The VR Enable command 636 may have no effect on the operation of the PMIC 100 after the signal VR_EN pin is asserted.

[0129] Reference Fig.13 , a timing diagram illustrating a power-down sequence when the VR_EN pin is low and the low power status register is at a low value in the programming mode of operation is shown. A timing diagram 650 is shown. The timing diagram 650 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0130] Vertical lines 652-654 are shown. Vertical lines 652-654 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 652 may correspond to a transition of the VR_EN waveform 430 from high to low. Vertical line 654 may correspond to a transition of the VR_EN waveform 430 from low to high.

[0131] VIN_BULK waveform 422, VOUT_1.8V waveform 424, and VOUT_V1.0V waveform 426 may each be a high value. There may be no VR Disable command on bus 90. Register value 104 may be set to zero.

[0132] After the time 652 at which the VR_EN waveform 430 transitions to low, the PWR_GOOD waveform 438 may transition to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. For example, changing the VR_EN waveform 430 (e.g., providing an input) may change the state of the regulators 106a-106n. After the time 654, when the VR_EN waveform 430 transitions back to high, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, then the SWA waveform 436 may transition from low to high, and then the PWR_GOOD waveform 438 may transition from low to high. For example, changing the VR_EN waveform 430 (e.g., providing an input) may change the state of the regulators 106a-106n. After the time 654, when the VR_EN waveform 430 transitions back to high, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, then the SWA waveform 436 may transition from low to high, and then the PWR_GOOD waveform 438 may transition from low to high.

[0133] Regardless of how the voltage regulators 106a-106n are turned on (e.g., using the signal VR_EN or VR Enable command on the bus 90), the voltage regulators 106a-106n may be powered down based on the operating mode (e.g., programmable mode or safe mode) of the PMIC 100. In the programmable operating mode, when the register value 104 is set to 0, the PMIC 100 may enable the host 20 to power down any or all of the voltage regulators 106a-106n using three different methods.

[0134] In one approach, when the PMIC 100 is in a programmable operating mode and the register value 104 is set to 0, the host 20 can use a VR Disable command (e.g., setting register R32[7] to 0 or transitioning signal VR_EN to low) to power down the voltage regulators 106a-106n. The PMIC 100 can perform one or more power-down sequences according to the configuration (e.g., as defined by register R58 and / or defined by register R5A) to maintain the voltage relationship as configured in the registers 102a-102n.

[0135] In one example, the PMIC 100 may control the signal PWR_GOOD by providing a VR Disable command using the VR_EN pin (e.g., setting the signal VR_EN to low). The PMIC 100 may then assert the signal PWR_GOOD to low. The host 20 may re-enable the output regulators 106a-106n by asserting the signal VR_EN to high. After the timing parameter tPMIC_PWR_GOOD_OUT is met, the PMIC 100 may perform one or more power-up sequences according to the registers 102a-102n and float the signal PWR_GOOD. The PMIC 100 may not need to be restarted.

[0136] In another example, the PMIC 100 may control the signal PWR_GOOD by providing a VR Disable command via the host 20 using the bus 90 (e.g., setting the register value R32[7] to 0). Since there may not be a fault condition (e.g., the VRDisable command may be an intentional command from the host 20), the PMIC 100 may leave the signal PWR_GOOD floating. The host 20 may re-enable the regulators 106a-106n by issuing a VR Enable command on the bus 90 (e.g., setting the register value R32[7] to 1). The PMIC 100 may perform one or more power-up sequences according to the registers 102a-102n and continue to float the signal PWR_GOOD until time tPMIC_PWR_GOOD_OUT. The PMIC 100 may then assume normal control of the signal PWR_GOOD (e.g., as combined with Fig.14 shown).

[0137] Generally, it may not be allowed to use the signal VR_EN and the VR Enable (or VR Disable) command simultaneously on the bus 90. For example, if the signal VR_EN first transitions to low, then the signal PWR_GOOD will transition to low and remain low even if there are subsequent commands on the bus 90.

[0138] In another method for controlling power down of the voltage regulators 106a-106n, the PMIC 100 may configure one or more bits of the registers 102a-102n (e.g., bits [6, 4:3] of register R2F) in any particular sequence desired by the host controller 20. The PMIC 100 may not perform the power down sequence without an instruction from the host 20. The PMIC 100 may leave the signal PWR_GOOD floating because the power down may be an intentional command of the host 20 (e.g., not a fault condition). The host 20 may re-enable any voltage regulators 106a-106n that have been disabled by configuring one or more bits of the registers 102a-102n (e.g., bits [6, 4:3] of register R2F) in any particular sequence desired by the host 20.

[0139] In another method for controlling power down of the voltage regulators 106a-106n, the registers 102a-102n (e.g., register R32[5] is set to 1) may drive the signal PWR_GOOD low. The PMIC 100 may perform one or more power down sequences according to the registers 102a-102n to maintain the voltage relationship as configured by the registers 102a-102n and drive the signal PWR_GOOD low. The PMIC 100 may retain the contents of all registers 102a-102n (e.g., including the MTP error log register). The host 20 may re-enable the voltage regulators 106a-106n by issuing a VR Enable command on the bus 90, and after the tPMIC_PWR_GOOD timing parameter is met, the PMIC 100 may perform one or more power up sequences and float the signal PWR_GOOD. The PMIC 100 may not need to be restarted.

[0140] The PMIC 100 may be configured to generate an internal VRDisable command at any time in response to one or more events. The PMIC 100 may perform one or more power-off sequences according to the registers 102a-102n to maintain the voltage relationship as configured in the registers 102a-102n. The PMIC 100 may then assert the signal PWR_GOOD to low. The host 20 may re-enable the regulators 106a-106n using the VR Enable command (via the signal VR_EN or bus 90), and the PMIC 100 may float the PWR_GOOD signal. The PMIC 100 may not need to be restarted.

[0141] Reference Fig.14 , a timing diagram illustrating a power-down sequence when the VR_EN pin is high and the low power status register is at a high value in the programming operation mode is shown. A timing diagram 680 is shown. The timing diagram 680 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0142] Vertical lines 682-684 are shown. Vertical lines 682-684 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 682 may correspond to a VR Disable command on the bus 90. Vertical line 684 may correspond to a VR Enable command on the bus 90.

[0143] VIN_BULK waveform 422, VOUT_1.8V waveform 424, and VOUT_V1.0V waveform 426 may each be at a high value. VR_EN waveform 430 may be held at a static high value. Register value 104 may be set to zero.

[0144] After time 682 when VR Disable command 686 is provided on bus 90, SWA waveform 436 may transition from high to low, then SWB waveform 434 may transition from high to low, then SWC waveform 432 may transition from high to low. After time 684, when VR Enable command 688 is provided on bus 90, SWC waveform 432 may transition from low to high, then SWB waveform 434 may transition from low to high, then SWA waveform 436 may transition from low to high (e.g., switching regulators 106a-106c may be powered back on). PWR_GOOD waveform 438 may be maintained high regardless of VR Disable command 686 and VR Enable command 688.

[0145] Reference Fig.15 , shows a timing diagram illustrating a power-down sequence when the VR_EN pin is low and the low power status register is at a high value in the programming mode of operation. A timing diagram 720 is shown. The timing diagram 720 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0146] Vertical lines 722-724 are shown. Vertical lines 722-724 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 722 may correspond to a transition of the VR_EN waveform 430 from high to low. Vertical line 724 may correspond to a transition of the VR_EN waveform 430 from low to high.

[0147] VIN_BULK waveform 422, VOUT_1.8V waveform 424, and VOUT_V1.0V waveform 426 may each be a high value. There may be no VR Disable command on bus 90. Register value 104 may be set to 1.

[0148] After the VR_EN waveform 430 transitions to low time 722, the PWR_GOOD waveform 438 may transition from high to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. After the SWC waveform 432 transitions from high to low, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from high to low, and the VIN_BULK waveform 422 may remain high.

[0149] At time 724, VR_EN waveform 430 may transition from low to high. After time 724, when VR_EN waveform 430 transitions back high, VOUT_1.8V waveform 424 may transition from low to high, and then VOUT_1.0V waveform 426 may transition from low to high. Next, SWC waveform 432 may transition from low to high, and then SWB waveform 434 may transition from low to high, and then SWA waveform 436 may transition from low to high, and then PWR_GOOD waveform 438 may transition from low to high.

[0150] Regardless of how the voltage regulators 106a-106n are turned on (e.g., using the signal VR_EN or VR Enable command on the bus 90), the voltage regulators 106a-106n may be powered down based on the operating mode (e.g., programmable mode or safe mode) of the PMIC 100. In the programmable operating mode, when the register value 104 is set to 1, the PMIC 100 may enable the host 20 to power down any or all of the voltage regulators 106a-106n using three different methods.

[0151] In one approach, when the PMIC 100 is in a programmable operating mode and the register value 104 is set to 1, the host 20 can use a VR Disable command (e.g., setting register R32[7] to 0 or transitioning signal VR_EN to low) to power down the voltage regulators 106a-106n. The PMIC 100 can perform one or more power-down sequences according to the configuration (e.g., as defined by register R58 and / or defined by register R5A) to maintain the voltage relationship as configured in registers 102a-102n. The PMIC 100 can enter a static P1 power state 388.

[0152] In one example, the PMIC 100 may control the signal PWR_GOOD by providing a VR Disable command using the VR_EN pin (e.g., setting the signal VR_EN to low). The PMIC 100 may then assert the signal PWR_GOOD to low. The host 20 may re-enable the output regulators 106a-106n by asserting the signal VR_EN to high. The PMIC 100 may exit the static P1 power state 388 (e.g., move to the idle P3 power state 386). As shown in the timing diagram 720, after the timing parameter tPMIC_PWR_GOOD_OUT plus the additional timing parameters are satisfied, the PMIC 100 may perform one or more power-up sequences according to the registers 102a-102n and float the signal PWR_GOOD. The PMIC 100 may not need to be restarted.

[0153] In another example, the PMIC 100 may control the signal PWR_GOOD by providing a VR Disable command via the host 20 using bus 90 (e.g., setting register value R32[7] to 0). Since there may not be a fault condition (e.g., the VRDisable command may be an intentional command from the host 20), the PMIC 100 may leave the signal PWR_GOOD floating. The PMIC 100 may exit the static P1 power state 388 only if the signal VR_EN transitions high. The host 20 may re-enable the regulators 106a-106n by asserting the signal VR_EN high. The PMIC 100 may then perform one or more power-up sequences according to the registers 102a-102n and continue to float the signal PWR_GOOD until time tPMIC_PWR_GOOD_OUT plus additional timing parameters. The PMIC 100 may then assume normal control of the signal PWR_GOOD (e.g., as combined with Fig.16 shown).

[0154] Generally, it may not be allowed to use the signal VR_EN and the VR Enable (or VR Disable) command simultaneously on the bus 90. For example, if the signal VR_EN first transitions to low, then the signal PWR_GOOD will transition to low and remain low even if there are subsequent commands on the bus 90.

[0155] In another method for controlling power down of the voltage regulators 106a-106n, the PMIC 100 may configure one or more bits of the registers 102a-102n (e.g., configuring bits [6,4:3] of register R2F to 0) in any particular sequence desired by the host controller 20. The PMIC 100 may not execute the power down sequence without an instruction from the host 20. The PMIC 100 may leave the signal PWR_GOOD floating because the power down may be an intentional command by the host 20 (e.g., not a fault condition). The host 20 may re-enable any voltage regulators 106a-106n that have been disabled by configuring one or more bits of the registers 102a-102n (e.g., configuring bits [6,4:3] of register R2F to 1) in any particular sequence desired by the host 20. This may be combined with Fig.16 to illustrate the behavior of the signal PWR_GOOD.

[0156] In another method for controlling power down of the voltage regulators 106a-106n, the registers 102a-102n (e.g., register R32[5] is set to 1) may drive the signal PWR_GOOD low. The PMIC 100 may perform one or more power down sequences according to the registers 102a-102n to maintain the voltage relationship as configured by the registers 102a-102n and drive the signal PWR_GOOD low. The PMIC 100 may retain the contents of all registers 102a-102n (e.g., including the MTP error log register). The PMIC 100 may not enter the static P1 power state 388. The host 20 may re-enable the voltage regulators 106a-106n by issuing a VREnable command on the bus 90 (e.g., setting register R32[7] to 1), and, after the tPMIC_PWR_GOOD timing parameter is met, the PMIC 100 may perform one or more power up sequences and float the signal PWR_GOOD. The PMIC 100 may not need to be restarted.

[0157] The PMIC 100 may be configured to generate an internal VRDisable command at any time in response to one or more events. The PMIC 100 may perform one or more power-off sequences according to registers 102a-102n (e.g., register R58 and register R5A) to maintain the voltage relationship as configured in registers 102a-102n. The PMIC 100 may not enter the static P1 power state 388. The PMIC 100 may then assert the signal PWR_GOOD to low. The host 20 may re-enable the regulators 106a-106n using the VREnable command (via signal VR_EN or bus 90), and the PMIC 100 may float the PWR_GOOD signal. The PMIC 100 may not need to be restarted.

[0158] Reference Fig.16 , a timing diagram illustrating a power-down sequence in a safe operating mode when the VR_EN pin is high and the low power status register is at a low value is shown. A timing diagram 780 is shown. The timing diagram 780 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0159] A vertical line 782 is shown. The vertical line 782 may correspond to a particular timing and / or response by the PMIC 100. The vertical line 782 may correspond to a VR Disable command generated by the host 20 on the bus 90.

[0160] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. The VR_EN waveform 430 may not transition before time 782. The register value 104 may be set to 1.

[0161] Before and after time 782 of the VR Disable command 784 on the bus 90, the PWR_GOOD waveform 438 may remain high. After time 782, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. After the SWC waveform 432 transitions from high to low, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from high to low, and the VIN_BULK waveform 422 may remain high. After time 782, the state of the VR_EN waveform 430 may have no effect.

[0162] After time 782, the PMIC 100 may be in the static P1 power state 388. After time 782, a transition 786 of the VR_EN waveform 430 is shown. The transition 786 may be the VR_EN waveform 430 going from low to high. When the VR_EN waveform 430 transitions from low to high, the PMIC 100 may exit the static P1 power state. After transition 786, the VOUT_1.8V waveform 424 may transition from low to high, and then the VOUT_1.0V waveform 426 may transition from low to high. Next, the SWC waveform 432 may transition from low to high, and then the SWB waveform 434 may transition from low to high, and then the SWA waveform 436 may transition from low to high. The PWR_GOOD waveform 438 may remain static high.

[0163] Reference Fig.17 , a timing diagram illustrating a disable or enable command on a bus during a safe operating mode is shown. A timing diagram 830 is shown. The timing diagram 830 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0164] Vertical lines 832-834 are shown. Vertical lines 832-834 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 832 may correspond to a transition of the VR_EN waveform 430 from high to low. Vertical line 834 may correspond to a transition of the VR_EN waveform 430 from low to high.

[0165] VIN_BULK waveform 422, VOUT_1.8V waveform 424, and VOUT_V1.0V waveform 426 may each be a high value. There may be no VR Disable command on bus 90. Register value 104 may be set to zero.

[0166] After the time 832 at which the VR_EN waveform 430 transitions to low, the PWR_GOOD waveform 438 may transition from high to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. When the VR_EN waveform 430 transitions from high to low, the host 20 providing a VR Enable command or a VR Disable command on the bus 90 may have no effect on the operation of the PMIC 100.

[0167] At time 834, VR_EN waveform 430 may transition from low to high. After time 834, when VR_EN waveform 430 transitions back to high, SWC waveform 432 may transition from low to high, then SWB waveform 434 may transition from low to high, then SWA waveform 436 may transition from low to high, then PWR_GOOD waveform 438 may transition from low to high. VIN_BULK waveform 422, VOUT_1.8V waveform 424, and VOUT_V1.0V waveform 426 may each be a high value.

[0168] Regardless of how the voltage regulators 106a-106n are turned on (e.g., using the signal VR_EN or VR Enable command on the bus 90), the voltage regulators 106a-106n may be powered down based on the operating mode (e.g., programmable mode or safe mode) of the PMIC 100. In the safe operating mode, when the register value 104 is set to 0, the PMIC 100 may enable the host 20 to power down any or all of the voltage regulators 106a-106n using two different methods.

[0169] In one approach, when the PMIC 100 is in a safe operating mode and the register value 104 is set to 0, the host 20 may provide a VR Disable command by transitioning the signal VR_EN to low. The PMIC 100 may then assert the signal PWR_GOOD to low. The PMIC 100 may perform one or more power-down sequences according to the registers 102a-102n (e.g., register R58 and register R5A) to maintain the voltage relationship as configured by the registers 102a-102n. The host 20 may re-enable the output regulators 106a-106n by asserting the signal VR_EN to high. After the timing parameter tPMIC_PWR_GOOD_OUT is met, the PMIC 100 may perform one or more power-up sequences according to the registers 102a-102n and float the signal PWR_GOOD. The PMIC 100 may not need to be restarted. A VR Disable command or VR Enable command on bus 90 (e.g., register value R32[7] is set to 0 or 1) may have no effect on PMIC 100. Configuring one or more bits (e.g., register value R2F[6,4:3]) to 0 may have no effect on PMIC 100 (e.g., in conjunction with Fig.18 shown).

[0170] In another approach, when the PMIC 100 is in a safe operating mode and the register value 104 is set to 0, the regulators 106a-106n may be powered down by setting the register value R32[5] to 1, which may drive the signal PWR_GOOD low. The PMIC 100 may perform one or more of the power down sequences based on the registers 102a-102n (e.g., register R58 and / or register R5A) to maintain the voltage relationship as configured in the registers 102a-102n. The PMIC 100 may drive the signal PWR_GOOD low and only unlock the register R32. The PMIC 100 may allow the host 20 to issue a VR Enable command. The PMIC 100 may retain the contents of all registers 102a-102n (e.g., including the MTP error log register). In the safe operating mode, the PMIC 100 may keep all write protection registers locked (except R32[7]). The host 20 may re-enable the voltage regulators 106a-106n by issuing a VR Enable command on the bus 90, and after the tPMIC_PWR_GOOD timing parameter is satisfied, the PMIC 100 may perform one or more power-up sequences and float the signal PWR_GOOD. After the host 20 issues the VR Enable command, the PMIC 100 may re-lock the register R32. The PMIC 100 may not need to be restarted to re-enable the output voltage regulators 106a-106n.

[0171] The PMIC 100 may be configured to generate an internal VRDisable command at any time in response to one or more events. The PMIC 100 may perform one or more power-down sequences according to the registers 102a-102n to maintain the voltage relationship as configured in the registers 102a-102n. The PMIC 100 may then assert the signal PWR_GOOD to low. In the safe operating mode, the PMIC 100 may need to be restarted. The VR Enable command (e.g., provided by the bus 90 or provided by the signal VR_EN) may have no effect on the PMIC 100, and the PMIC 100 may maintain the signal PWR_GOOD to low.

[0172] Reference Fig.18 , a timing diagram illustrating a power-down sequence when the VR_EN pin is high and the low power status register is at a high or low value in a safe operating mode is shown. A timing diagram 880 is shown. The timing diagram 880 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0173] A vertical line 882 is shown. The vertical line 882 may correspond to a particular timing and / or response by the PMIC 100. The vertical line 882 may correspond to a VR Disable command on the bus 90.

[0174] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may be high values, respectively. The VR_EN waveform 430 may be a static high value. Since the VR_EN waveform 430 is held high, the VR Disable command 884 or the VR Enable command on the bus 90 may have no effect on the PMIC 100. The register value 104 may be set to 0 or 1. The SWC waveform 432, the SWB waveform 434, and the SWA waveform 436 may be on and switchable. The signal PWR_GOOD may be held high.

[0175] Reference Fig.19 , a timing diagram illustrating a power-down sequence using the VR_EN pin in a safe operating mode while the low power status register is at a high value is shown. A timing diagram 930 is shown. The timing diagram 930 may include waveforms 422-438. The waveforms 422-438 may be similar to the combination of Figure 8 Waveforms 422-438 are shown.

[0176] Vertical lines 932-934 are shown. Vertical lines 932-934 may correspond to specific timing and / or responses by the PMIC 100. Vertical line 932 may correspond to a transition of the VR_EN waveform 430 from high to low. Vertical line 934 may correspond to a transition of the VR_EN waveform 430 from low to high.

[0177] VIN_BULK waveform 422, VOUT_1.8V waveform 424, and VOUT_V1.0V waveform 426 may each be a high value. SWC waveform 432, SWB waveform 434, SWA waveform 436, and PWR_GOOD waveform 438 may each be a high value. A VRDisable command or VR Enable command on bus 90 may have no effect. Register value 104 may be set to 1.

[0178] After the VR_EN waveform 430 transitions to low at time 932, the PWR_GOOD waveform 438 may transition from high to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. After the SWC waveform 432 transitions to low, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from high to low.

[0179] At time 934, VR_EN waveform 430 may transition from low to high. After time 934, when VR_EN waveform 430 transitions back high, VOUT_1.8V waveform 424 and VOUT_1.V waveform 426 may transition from low to high. Next, SWC waveform 432 may transition from low to high, then SWB waveform 434 may transition from low to high, then SWA waveform 436 may transition from low to high, then PWR_GOOD waveform 438 may transition from low to high.

[0180] Regardless of how the voltage regulators 106a-106n are turned on (e.g., using the signal VR_EN or VR Enable command on the bus 90), the voltage regulators 106a-106n may be powered down based on the operating mode (e.g., programmable mode or safe mode) of the PMIC 100. In the safe operating mode, when the register value 104 is set to 1, the PMIC 100 may enable the host 20 to power down any one or all of the voltage regulators 106a-106n using two different methods.

[0181] In one approach, when the PMIC 100 is in a safe operating mode and the register value 104 is set to 1, the host 20 may provide a VR Disable command by transitioning the signal VR_EN to low. The PMIC 100 may then assert the signal PWR_GOOD to low. The PMIC 100 may perform one or more power down sequences according to the registers 102a-102n (e.g., register R58 and register R5A) to maintain the voltage relationships as configured by the registers 102a-102n. The PMIC 100 may then enter the static P1 power state 388.

[0182] The host 20 may re-enable the output regulators 106a-106n by asserting signal VR_EN high. The PMIC 100 may exit the static P1 power state 388 and move to the idle P3 power state 386. Next, after the timing parameter tPMIC_PWR_GOOD_OUT plus additional timing parameters are satisfied, the PMIC 100 may perform one or more power-up sequences according to registers 102a-102n and float signal PWR_GOOD. The PMIC 100 may not need to be restarted. A VR Disable command or a VR Enable command on bus 90 (e.g., register value R32[7] is set to 0 or 1) may have no effect on the PMIC 100. Configuring one or more bits (e.g., register value R2F[6,4:3]) to 0 may have no effect on the PMIC 100 (e.g., in combination with Fig.18 shown).

[0183] In another approach, when the PMIC 100 is in a safe operating mode and the register value 104 is set to 1, the regulators 106a-106n may be powered down by setting the register value R32[5] to 1, which may drive the signal PWR_GOOD low. The PMIC 100 may perform one or more of the power down sequences based on the registers 102a-102n (e.g., register R58 and / or register R5A) to maintain the voltage relationship as configured in the registers 102a-102n. The PMIC 100 may drive the signal PWR_GOOD low and only unlock the register R32. The PMIC 100 may retain the contents of all registers 102a-102n (e.g., including the MTP error log register). In the safe operating mode, the PMIC 100 may keep all write protection registers locked (except R32[7]). The PMIC 100 may not enter the static P1 power state 388.

[0184] The host 20 may re-enable the voltage regulators 106a-106n by issuing a VR Enable command on the bus 90, and, after the tPMIC_PWR_GOOD timing parameter is satisfied, the PMIC 100 may perform one or more power-up sequences and float the signal PWR_GOOD. After the host 20 issues the VR Enable command, the PMIC 100 may re-lock the register R32. The PMIC 100 may not require a reboot to re-enable the output voltage regulators 106a-106n.

[0185] The PMIC 100 may be configured to generate an internal VRDisable command at any time in response to one or more events. The PMIC 100 may perform one or more power-down sequences according to the registers 102a-102n to maintain the voltage relationship as configured in the registers 102a-102n. The PMIC 100 may not enter the static P1 power state 388. The PMIC 100 may then assert the signal PWR_GOOD to low. In the safe operating mode, the PMIC 100 may need to be restarted. The VR Enable command (e.g., provided by the bus 90 or provided by the signal VR_EN) may have no effect on the PMIC 100, and the PMIC 100 may maintain the signal PWR_GOOD to low.

[0186] It is obvious to those skilled in the relevant art that Figures 1 to 19The functions performed by the diagrams can be implemented using conventional general-purpose processors, digital computers, microprocessors, microcontrollers, RISC (reduced instruction set computer) processors, CISC (complex instruction set computer) processors, SIMD (single instruction multiple data) processors, signal processors, central processing units (CPUs), arithmetic logic units (ALUs), video digital signal processors (VDSPs), and / or similar computing machines programmed according to the teachings of this specification. It is obvious to those skilled in the relevant art that a skilled programmer can easily prepare appropriate software, firmware, coding, routines, instructions, opcodes, microcodes, and / or program modules based on the teachings of this disclosure. The software is typically executed from one or more media by one or more processors of a machine implementation.

[0187] The present invention may also be implemented by preparing an ASIC (application specific integrated circuit), a platform ASIC, an FPGA (field programmable gate array), a PLD (programmable logic device), a CPLD (complex programmable logic device), a sea of ​​gates, an RFIC (radio frequency integrated circuit), an ASSP (application specific standard product), one or more monolithic integrated circuits, one or more chips or dies arranged as a flip chip module and / or a multi-chip module, or by interconnecting an appropriate conventional component circuit network, as described herein, modifications of which will be readily apparent to those skilled in the art.

[0188] Thus, the present invention may also include a computer product, which may be one or more storage media and / or one or more transmission media, including instructions that can be used to program a machine to perform one or more processes or methods according to the present invention. The machine's execution of the instructions contained in the computer product and the operation of the surrounding circuits may transform the input data into one or more files on the storage medium and / or one or more output signals representing a physical object or substance, such as audio and / or visual depictions. The storage medium may include, but is not limited to: any type of disk, including floppy disks, hard drives, magnetic disks, optical disks, CD-ROMs, DVDs, and magneto-optical disks; and circuits such as ROM (read-only memory), RAM (random access memory), EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM), UVPROM (ultraviolet erasable programmable ROM), flash memory, magnetic cards, optical cards, and / or any type of medium suitable for storing electronic instructions.

[0189] The elements of the present invention may form part or all of one or more devices, units, components, systems, machines and / or devices. The equipment may include, but is not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, handheld computers, cloud servers, personal digital assistants, portable electronic devices, battery-powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, preprocessors, postprocessors, transmitters, receivers, transceivers, cryptographic circuits, cellular phones, digital cameras, positioning and / or navigation systems, medical equipment, head-up displays, wireless devices, audio recording, audio storage and / or audio playback equipment, video recording, video storage and / or video playback equipment, gaming platforms, peripherals and / or multi-chip modules. It will be appreciated by those skilled in the art that the elements of the present invention may be implemented in other types of equipment to meet the standards for specific applications.

[0190] The various signals of the present invention are generally "on" (e.g., digital HIGH or 1) or "off" (e.g., digital LOW or 0). However, the specific polarity of the on (e.g., asserted) and off (e.g., de-asserted) states of a signal may be adjusted (e.g., inverted) to meet the design criteria of a particular implementation. Additionally, inverters may be added to change the specific polarity of a signal.

[0191] When used in conjunction with the copula (is (are)) and verbs, the terms "may" and "usually" are intended to convey the following intention: this specification is exemplary and is considered broad enough to cover the specific examples set forth in the present disclosure as well as alternative examples that can be derived based on the present disclosure. The terms "may" and "usually" as used herein should not be interpreted as necessarily implying the expectation or possibility of omitting the corresponding elements.

[0192] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.

Claims

1. A computing device, comprising: a plurality of registers, one register of the plurality of registers being a power state entry register configured to control entry into a low power state; as well as A host interface, the host interface comprising a plurality of pins, one of the plurality of pins being an enable pin, wherein (i) the apparatus is configured to enter the low power state in response to (a) setting the power state entry register to a first value, and (b) providing a signal having a first level to the enable pin, (ii) the apparatus is configured to exit the low power state in response to providing the signal having a second level to the enable pin, (iii) the device enters an idle state after exiting the low power state, (iv) the low power state consumes less power than the idle state, (v) the enable pin is implemented as an input configured to control the state of the plurality of regulators, (vi) in the low power state, the device is adapted to operate with (a) the plurality of regulators turned off, (b) access to a bus disabled, and (c) values ​​of three of the plurality of registers stored in a non-volatile memory, (vii) in the idle state, the apparatus is adapted to operate with (a) the plurality of voltage regulators turned on, and (b) access to the bus enabled, and (viii) One of the three registers among the plurality of registers is the power state entry register.

2. The computing device according to claim 1, wherein: The low power state operates at 25 μA current, and the idle state operates at 100 μA current.

3. The computing device according to claim 1, wherein: The apparatus implements a power management integrated circuit for an unbuffered double data rate fifth generation memory module.

4. The computing device of claim 1, wherein in the idle state the plurality of regulators are turned on at a 0A load.

5. The computing device according to claim 1, wherein: The bus is at least one of an I2C bus and an I3C bus.

6. The computing device according to claim 1, wherein: The plurality of regulators include a switching output regulator and a low dropout regulator.

7. The computing device of claim 1, further configured to enter and exit the low power state when the device is operating in (a) a secure operating mode or (b) a programmed operating mode.

8. The computing device according to claim 1, wherein: The power state entry register is configured to: (a) be initialized with a second value by default, and (b) change to the first value in response to a command from a host controller.

9. The computing device according to claim 8, wherein: When the power state entry register has the second value, the device does not enter the low power state.

10. The computing device of claim 1, wherein: The enable pin is operable to receive a VR_EN signal.

11. The computing device of claim 1, wherein: The apparatus implements a power management integrated circuit for buffering double data rate fifth generation memory modules.

12. The computing device of claim 1, wherein: The apparatus implements a power management integrated circuit for a registered double data rate fifth generation memory module.

13. The computing device of claim 1, wherein: The apparatus is configured to reuse the enable pin in conjunction with the power state entry register to control the entry into and the exit from the low power state.

14. The computing device of claim 13, wherein the enable pin is further used to control states of the plurality of voltage regulators, so that the device can be implemented without increasing the number of the plurality of pins.

15. A computing device comprising: a plurality of registers, one register of the plurality of registers being a power state entry register configured to control entry into a low power state; as well as A host interface, the host interface comprising a plurality of pins, one of the plurality of pins being an enable pin, wherein (i) the apparatus is configured to enter the low power state in response to (a) setting the power state entry register to a first value, and (b) providing a signal having a first level to the enable pin, (ii) the apparatus is configured to exit the low power state in response to providing the signal having a second level to the enable pin, (iii) the device enters an idle state after exiting the low power state, (iv) the low power state consumes less power than the idle state, (v) the enable pin is implemented as an input configured to control the state of the plurality of regulators, (vi) the device is configured to enter and exit the low power state when the device is operating in (a) a secure operating mode or (b) a programmed operating mode, (vii) one of the plurality of pins is a power good pin, and (viii) the device is configured to: when the device is in the low power state, when in the programming operation mode, enable the power good pin to have bidirectional operation.

16. The computing device of claim 15, wherein the device implements a power management integrated circuit for an unbuffered double data rate fifth generation memory module.

17. The computing device of claim 15, wherein the plurality of regulators include a switching output regulator and a low dropout regulator.

18. The computing device of claim 15, wherein the device implements a power management integrated circuit for buffering double data rate fifth generation memory modules.

19. The apparatus of claim 15, wherein the apparatus is configured to reuse the enable pin in conjunction with the power state entry register to control the entry into and the exit from the low power state.

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