Data migration method, storage control chip and flash memory device

Abstract

The embodiment of the present application relates to the application field of storage devices, and discloses a data moving method, a storage control chip and a flash memory device, wherein the to-be-moved data is read out from a source physical storage unit address of a user data area and cached in a cache space, the to-be-moved data is roughly programmed to a target physical storage unit address of the user data area, the cache space is released after the rough programming is completed, the to-be-moved data which has completed rough programming is cached to the cache space, the to-be-moved data is finely programmed to the target physical storage unit address, and the cache space is released after the fine programming is completed. The application can release the cache space in time after each programming (rough programming or fine programming) is completed, reduce the occupation time of the cache resource, enable other tasks to use the cache space, and thus improve the resource use efficiency of the cache space.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage devices, and in particular to a data migration method, a storage control chip and a flash memory device. BACKGROUND

[0002] A flash memory device, for example, a solid state drive (SSD), is a storage device that uses a semiconductor flash memory (NAND Flash) as a medium. When performing a write operation, the flash memory device is prone to overwrite conflicts. Due to the limited storage capacity of the flash memory device and the characteristic of the flash memory medium that requires erasing before writing, in garbage collection (GC) and other scenarios, storage space needs to be released through data migration.

[0003] Currently, in the process of data migration, valid data stored in the flash memory medium needs to be stored in a cache space first, and then the valid data is written from the cache space to the flash memory medium, and the corresponding cache space is released after the write operation is completed.

[0004] In the process of implementing the present application, the inventors have found that at least the following problem exists in the prior art: For a flash memory device that requires two programming operations for a write operation, for example, a flash memory device in a quad-level cell (QLC) mode, during the time from when the data completes coarse programming to when fine programming begins, the corresponding cache space is not further utilized or released, resulting in idle resources and low utilization efficiency of the cache space. SUMMARY

[0005] Embodiments of the present application provide a data migration method, a storage control chip and a flash memory device to improve the resource utilization efficiency of the cache space.

[0006] Embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, a data migration method is provided. The data migration method is applied to a flash memory device, the flash memory device includes a cache space and a flash memory medium, the flash memory medium includes a user data area, the cache space is used to cache to-be-migrated data, and the data migration method includes:

[0008] reading the to-be-migrated data from a source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space;

[0009] performing coarse programming of the to-be-migrated data to a target physical storage unit address of the user data area, and releasing the cache space after the coarse programming is completed;

[0010] caching the to-be-migrated data that has completed the coarse programming to the cache space;

[0011] fine programming the to-be-moved data to the target physical storage unit addresses, and releasing the cache space after the fine programming is completed.

[0012] In some embodiments, the flash media further comprises a first target super block;

[0013] reading out the to-be-moved data from the source physical storage unit addresses of the user data area and caching the to-be-moved data in the cache space, comprising:

[0014] traversing the first mapping table entries of the first target super block and the second mapping table entries in the cache space;

[0015] determining the source physical storage unit addresses corresponding to the to-be-moved data according to the first mapping table entries and the second mapping table entries;

[0016] reading the first target super block based on the source physical storage unit addresses to obtain the to-be-moved data;

[0017] constructing write units based on the to-be-moved data, and storing each write unit to the cache space.

[0018] In some embodiments, the method further comprises:

[0019] caching the first management structure constructed in the process of reading out the to-be-moved data from the source physical storage unit addresses of the user data area in the cache space.

[0020] In some embodiments, the method further comprises:

[0021] after determining the source physical storage unit addresses corresponding to the to-be-moved data, recording the source physical storage unit addresses based on the first management structure;

[0022] recording the construction relationship between each write unit and the to-be-moved data based on the first management structure;

[0023] when performing the coarse programming on the to-be-moved data, determining the programming order of each write unit based on the first management structure;

[0024] after the coarse programming is completed, releasing the storage area corresponding to the to-be-moved data of each write unit in the cache space based on the first management structure.

[0025] In some embodiments, caching the to-be-moved data that has completed the coarse programming to the cache space, comprising:

[0026] obtaining the first management structure cached in the cache space;

[0027] obtaining the to-be-moved data and storing the to-be-moved data to the cache space;

[0028] Fine programming the to-be-moved data to the target physical storage unit addresses, and releasing the cache space after the fine programming is completed, comprising:

[0029] Fine programming the to-be-moved data to the target physical storage unit addresses according to the first management structure, and releasing the cache space based on the first management structure after the fine programming is completed.

[0030] In some embodiments, the to-be-moved data is obtained and stored to the cache space, comprising:

[0031] Reading the first target super block based on the source physical storage unit address recorded by the first management structure to obtain the to-be-moved data;

[0032] Building the write unit based on the build relationship recorded by the first management structure, and storing the write unit to the cache space.

[0033] In some embodiments, fine programming the to-be-moved data to the target physical storage unit addresses according to the first management structure, and releasing the cache space based on the first management structure after the fine programming is completed, comprising:

[0034] Determining the programming order and the target physical storage unit address of each write unit based on the first management structure;

[0035] Fine programming each write unit according to the programming order, and storing each write unit to the corresponding target physical storage unit address;

[0036] Releasing the first management structure after each write unit is fine programmed.

[0037] In some embodiments, the method further comprises:

[0038] Calculating the number of write units based on the write bandwidth threshold of the flash device, the bandwidth threshold of the cache space, and the write bandwidth threshold of the single die;

[0039] Calculating the cache capacity used by the programming operation based on the number of write units and the capacity of the cache unit;

[0040] The programming operation comprises coarse programming or fine programming, and the cache capacity is the product of the number of write units and the capacity of the cache unit.

[0041] The number of write units is the maximum of a first number and a second number, the first number is the ratio of the write bandwidth threshold of the flash device and the write bandwidth threshold of the single die, and the second number is the ratio of the bandwidth threshold of the cache space and the write bandwidth threshold of the single die.

[0042] In a second aspect, the embodiments of the present application provide a storage control chip, comprising:

[0043] at least one processor; and

[0044] a memory in communication connection with the at least one processor; wherein

[0045] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the data migration method as in the first aspect.

[0046] In a third aspect, an embodiment of the present application provides a flash memory device, comprising:

[0047] The storage control chip as in the second aspect;

[0048] At least one flash memory medium, in communication connection with the storage control chip.

[0049] In a fourth aspect, an embodiment of the present application further provides a non-volatile computer readable storage medium, which stores computer executable instructions, and when the computer executable instructions are executed by a processor, the processor performs the data migration method as in the first aspect.

[0050] The beneficial effects of the embodiments of the present application are that, different from the prior art, the data migration method provided by the embodiments of the present application is applied to a flash memory device, the flash memory device comprises a cache space and a flash memory medium, the flash memory medium comprises a user data area, the cache space is used to cache to-be-migrated data, and the data migration method comprises the following steps: reading the to-be-migrated data from a source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space; performing coarse programming on the to-be-migrated data to a target physical storage unit address of the user data area, and releasing the cache space after the coarse programming is completed; caching the to-be-migrated data that has completed the coarse programming to the cache space; performing fine programming on the to-be-migrated data to the target physical storage unit address, and releasing the cache space after the fine programming is completed.

[0051] By reading the to-be-migrated data from the source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space, performing coarse programming on the to-be-migrated data to the target physical storage unit address of the user data area, releasing the cache space after the coarse programming is completed, caching the to-be-migrated data that has completed the coarse programming to the cache space, performing fine programming on the to-be-migrated data to the target physical storage unit address, and releasing the cache space after the fine programming is completed, the present application can release the cache space in time after each programming (coarse programming or fine programming) is completed, reduce the occupation time of the cache resource, enable other tasks to use the cache space, and thus improve the resource use efficiency of the cache space. BRIEF DESCRIPTION OF DRAWINGS

[0052] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the embodiments presented. The embodiments disclosed herein are not intended to be exhaustive or to limit the claims to the precise form disclosed. Many variations and modifications are possible in light of the disclosure. The drawings can not be to scale. Any representational or process flow diagrams can have some of the representations and / or flows omitted, exaggerated, emphasized, interpreted, and / or generalized for educational purposes.

[0053] Figure 1 is a structural schematic diagram of a flash memory device provided by an embodiment of the present application;

[0054] Figure 2 is a structural schematic diagram of a master control system of a flash memory device provided by an embodiment of the present application;

[0055] Figure 3 is a flow schematic diagram of a data moving method provided by an embodiment of the present application;

[0056] Figure 4 is a schematic diagram of a cache space occupation duration provided by an embodiment of the present application;

[0057] Figure 5 is another schematic diagram of a cache space occupation duration provided by an embodiment of the present application;

[0058] Figure 6 is a structural schematic diagram of a storage control chip provided by an embodiment of the present application;

[0059] Figure 7 is a structural schematic diagram of another flash memory device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0061] It should be noted that the various features of the embodiments of the present application can be combined with each other without conflict, and are within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Furthermore, the "first", "second", "third" and the like used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0062] The technical scheme of the present application will be described in detail below in combination with the drawings of the specification:

[0063] Referring to Figure 1 , Figure 1 is a structural schematic diagram of a flash memory device provided by an embodiment of the present application;

[0064] As Figure 1 shown, the flash memory device 100 includes a connector 101, a storage control chip 102, other peripheral units 103, a cache unit 104, and a flash memory medium 105.

[0065] The connector 101 connects the storage control chip 102 and a host, and is configured to communicate with the host, for example, a computer or a server; the storage control chip 102 is connected to the connector 101, the other peripheral units 103, the cache unit 104, and the flash memory medium 105, and is configured to serve as a control operation unit to manage the internal system of the flash memory device. The storage control chip 102 includes, but is not limited to, a solid state disk controller; the peripheral units 103 are connected to the storage control chip 102, and include components such as a serial port, a sensor, a register, and a power supply chip; and the cache unit 104 is connected to the storage control chip 102, and serves as a cache and an algorithm table storage unit. The cache unit 104 is generally a dynamic random access memory (DRAM).

[0066] The flash memory medium 105 serves as a storage medium of the flash memory device 100, and is also referred to as a flash memory, a Flash, a Flash memory, or a Flash grain. As a storage unit, the flash memory medium 105 is configured to store user data and system data. The storage control chip 102 and the flash memory medium 105 present a plurality of channels. One channel is independently connected to one flash memory medium. For example, channel 0 is connected to one flash memory medium, channel 1 is connected to one flash memory medium, and channel x is connected to one flash memory medium.

[0067] Referring to Figure 2 , Figure 2 is a structural schematic diagram of a master control system of a flash memory device provided by an embodiment of the present application;

[0068] It can be understood that the storage control chip of the flash memory device includes a master control system. The master control system is configured to connect a host and a flash memory array, and implement input and output (IO) processing of data.

[0069] As Figure 2 shown, the master control system 210 includes:

[0070] A front end module 211 (FE) is configured to acquire a host command to generate an IO operation. The front end module 211 is further configured to be responsible for a communication protocol of the host 200, and operations such as analysis of a host command and a flash memory device command.

[0071] The flash algorithm module 212, i.e., a flash translation layer (FTL), is used to map the IO operation to determine the flash array to be issued.

[0072] The flash algorithm module 212 sends the IO operation to the back end module 213 (BE) of the storage control chip, so that the back end module 213 receives the IO operation sent by the flash algorithm module 212.

[0073] The back end module 213 (BE) is connected to the flash algorithm module 212, and is used to receive the IO operation sent by the flash algorithm module 212 to control the hardware module 214 to perform read / write / erase operations on the flash array.

[0074] The hardware module 214 (HW Op Nand Mode) refers to a module for operating the flash memory, which is connected to the back end module 213 and controlled by the back end module 213, and is used to operate the flash memory, for example, according to the IO operation, to operate the corresponding flash array or flash medium, i.e., to complete the operation of data to the flash memory, and the operation includes read operation, write operation or erase operation.

[0075] Due to the limited storage capacity of the flash device, and the characteristic of the flash medium that it is erased before writing, in the garbage collection (GC) and other scenarios, it is necessary to release the storage space by data migration. The data migration refers to the process of moving data from one physical storage location to another location.

[0076] The data migration mainly consists of three sub-tasks: mapping table scanning, migration read operation and migration write operation. The mapping table scanning task is to compare the P2L table item in the node with the logical address to physical address (L2P) table item by cyclically scanning all physical address to logical address mapping nodes (P2L nodes) to determine whether the data stored in the flash medium is valid.

[0077] The moveRead task is to scan the valid physical storage unit address (PMA) obtained from the mapping table, read the data stored in the address, and store the data to the cache space. The moveWrite task is to write the data read by the moveRead task from the cache space to the flash medium, and release the corresponding cache space after the write operation is completed. Each subtask is continuously looped until all the data to be moved is moved.

[0078] As can be seen, the moveRead operation needs to store the valid data in the flash medium to the cache space, which will occupy a large amount of cache resources.

[0079] For flash devices that need to perform two programming operations for write operations, such as Quad-Level Cell (QLC) flash devices, during the data moving process, the moveWrite operation needs to complete two programming operations, that is, after the first write command is issued, the data is transmitted from the cache space to the flash medium for coarse programming (first programming), and then after the second write command is issued, the data is transmitted from the cache space to the flash medium again for fine programming (second programming), and the corresponding cache space is released after the fine programming is completed.

[0080] QLC flash, each storage unit of which can store 4 bits of information, has higher storage density than Single Level Cell (SLC), Multiple Level Cell (MLC), or Triple Level Cell (TLC) flash devices, and can provide larger storage capacity in the same physical space, but this high storage density is achieved by implementing more potential states in a single storage unit, and two programming operations are needed to ensure that the data is accurately written to the flash medium.

[0081] The first programming, also known as coarse programming, is used to preliminarily store data to the flash medium, and at this time the storage unit has not reached the final voltage state. The second programming, also known as fine programming, adjusts the voltage level to ensure that the storage unit accurately reaches its corresponding voltage state, so that the data is accurately stored in the flash medium and can be correctly read.

[0082] It can be seen that for the flash memory device requiring two programming operations for the write operation, the data read from the migration read operation is written to the cache space, and the cache space can be released only after the migration write operation completes the coarse programming and the fine programming. In this process, the cache space is occupied all the time, but there is a long period of time when no operation is performed on the cache space, for example, the corresponding cache space is not further utilized or released from the time when the data completes the coarse programming to the time before the fine programming starts. The corresponding cache space cannot be used or reused by other tasks during this period, resulting in idle resources and low use efficiency.

[0083] Based on this, the embodiment of the present application provides a data migration method, which can release the cache space in time by releasing the cache space after completing the coarse programming and releasing the cache space after completing the fine programming, so that other tasks can use the cache space, thereby improving the resource use efficiency of the cache space.

[0084] Please refer to Figure 3 , Figure 3 is a flowchart of a data migration method provided by the embodiment of the present application;

[0085] The data migration method is applied to a flash memory device, specifically, to a flash memory device requiring two programming operations for a write operation, for example, to a QLC flash, and the two programming operations include coarse programming and fine programming.

[0086] In the embodiment of the present application, the flash memory device includes a cache space and a flash memory medium, the cache space is used to cache to-be-migrated data, the to-be-migrated data is data that needs to be migrated in the data migration process, and the to-be-migrated data needs to be subjected to coarse programming and fine programming. The flash memory medium includes a user data area, and the user data area is used to store to-be-migrated data, that is, the user data area is used to store to-be-migrated data that has not been subjected to coarse programming and fine programming, and / or to store to-be-migrated data that has completed coarse programming and / or fine programming.

[0087] The storage location of the to-be-migrated data that has not been subjected to coarse programming and fine programming in the user data area is different from the storage location of the same to-be-migrated data that has completed coarse programming and / or fine programming. The cache space includes but is not limited to a dynamic random access memory (DRAM). Preferably, the cache space is a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0088] As shown in Figure 3 , the data migration method comprises:

[0089] Step S301: reading out the data to be migrated from a source physical storage unit address of a user data area and caching in a cache space;

[0090] The source physical storage unit address is a physical storage unit address of the data to be migrated in the user data area without rough programming and fine programming, i.e., a physical storage unit address of the data to be migrated before data migration.

[0091] Specifically, the data to be migrated is read from the user data area of the flash medium according to the source physical storage unit address of the data to be migrated, and the data to be migrated is cached in the cache space.

[0092] In the embodiment of the present application, the flash medium includes a first target super block. The first target super block is located in the metadata area and can be an SLC type flash medium.

[0093] In the embodiment of the present application, step S301 specifically includes steps S311-S314:

[0094] Step S311: traversing a first mapping table item of the first target super block and a second mapping table item in the cache space;

[0095] The first mapping table item is a P2L table item, and the second mapping table item is an L2P table item. Each super block corresponds to a plurality of mapping nodes, and the mapping node is a physical address to logical address mapping node (P2L Node). The mapping node is used to store the P2L table item of each storage unit.

[0096] Specifically, each mapping node of the first target super block is traversed by a mapping table scanning task to obtain the first mapping table item stored in each mapping node, and the second mapping table item of the first target super block stored in the cache space is read.

[0097] Step S312: determining the source physical storage unit address corresponding to the data to be migrated according to the first mapping table item and the second mapping table item;

[0098] Specifically, whether the first mapping table item and the second mapping table item of each storage unit are the same is determined by the mapping table scanning task. If the first mapping table item and the second mapping table item of any storage unit are the same, the data stored in the storage unit is valid data, and data migration of the data stored in the storage unit is required; if the first mapping table item and the second mapping table item of any storage unit are different, the data stored in the storage unit is invalid data, and data migration of the data stored in the storage unit is not required.

[0099] Further, when the first mapping table entry and the second mapping table entry of any storage unit are the same, the data stored in the storage unit is taken as the data to be moved, and the current physical storage unit address of the storage unit is taken as the source physical storage unit address.

[0100] Step S313: reading the first target super block based on the source physical storage unit address to obtain the data to be moved.

[0101] Specifically, the first target super block is read based on each source physical storage unit address determined in step S312 by the move read operation task to obtain a plurality of data to be moved.

[0102] Before reading the first target super block, the method further comprises: allocating a reading node and a corresponding storage area in the cache space by the move read operation task. The reading node refers to a specific node responsible for processing and responding to data reading requests.

[0103] Step S314: constructing a write unit based on the plurality of data to be moved, and storing each write unit to the cache space.

[0104] The write unit is composed of a plurality of data to be moved, and the write unit is a basic data unit for programming operation (coarse programming or fine programming). The size of the write unit can be set by those skilled in the art according to the type of flash medium, which is not limited herein.

[0105] Specifically, the read data to be moved is constructed into a write unit by the move read operation task, and each write unit is stored in the corresponding storage area in the cache space.

[0106] In the embodiment of the present application, the method further comprises: caching the first management structure constructed in the process of reading the data to be moved from the source physical storage unit address of the user data area in the cache space.

[0107] The first management structure is a management structure of the move read operation task. The management structure is used to manage the related information of the move read operation, so as to coordinate the processes of reading, writing and mapping updating of data. The related information of the move read operation includes but is not limited to the logical address (readLma) of the P2L table read from the metadata area of the SLC flash medium and stored in the cache, the logical address (readLma) read from the P2L table in the cache, the physical address (readPma) read from the L2P table in the cache, and the context management structure (readloCtx). The first management structure can be set by those skilled in the art according to the type of flash device, which is not limited herein.

[0108] Specifically, in the process of reading data from the source physical storage unit address, a first management structure is needed to be constructed to manage and record the related information of the whole moving read operation, and the first management structure is cached in the cache space. When the second fine programming is needed, the second write unit is reconstructed according to the first management structure and the rule of constructing the first fine programming write unit, and the cache space resource containing the data to be moved and the first management structure is released after the second fine programming is completed.

[0109] In the embodiments of the present application, the flash memory device further comprises a front-end module, a flash memory algorithm module, a back-end module and a hardware module, and the functions and connection modes of these modules can be referred to Figure 2 , which will not be repeated here.

[0110] Step S302: Roughly programming the data to be moved to the target physical storage unit address of the user data area, and releasing the cache space after completing the rough programming.

[0111] The target physical storage unit address is the physical storage unit address of the data to be moved in the user data area after completing the rough programming and / or fine programming, i.e. the physical storage unit address to which the data to be moved needs to be moved.

[0112] Specifically, each data to be moved cached in the cache space is read, and each data to be moved is sequentially roughly programmed and stored to the target physical storage unit address of the user data area, and the storage area corresponding to any data to be moved in the cache space is released after completing the rough programming of the data to be moved.

[0113] In the embodiments of the present application, step S302 specifically comprises steps S321-S323:

[0114] Step S321: generating a rough programming instruction based on the front-end module, and sending the rough programming instruction to the flash memory algorithm module, so that the flash memory algorithm module and the back-end module transmit the write unit corresponding to the rough programming instruction from the cache space to the flash memory medium;

[0115] The rough programming instruction is used to instruct the flash memory algorithm module, the back-end module and the hardware module to perform corresponding programming operations.

[0116] Specifically, the rough programming instruction is generated by the front-end module through the moving write operation task, and is sent to the flash memory algorithm module, and the flash memory algorithm module determines the target physical storage unit address according to the rough programming instruction, and the back-end module transmits the write unit corresponding to the rough programming instruction from the cache space to the flash memory medium.

[0117] Step S322: roughly programming the write unit based on the hardware module;

[0118] Specifically, by moving the write operation task, the scheduling hardware module coarsely programs the write unit, and initially stores the write unit to the target physical storage unit address of the user data area. At this time, the storage unit in the flash medium does not reach the final voltage state.

[0119] Step S323: After the coarse programming is completed, the storage area corresponding to the write unit in the cache space is released.

[0120] Specifically, after the coarse programming of any write unit is completed, the storage area corresponding to the to-be-moved data of the write unit in the cache space is released by moving the read operation task.

[0121] In the embodiments of the present application, the method further includes steps S1-S4:

[0122] Step S1: After determining the source physical storage unit address corresponding to the to-be-moved data, record the source physical storage unit address based on the first management structure.

[0123] Specifically, after the mapping table scanning task obtains the scanning result, the scanning result of the mapping table scanning task, i.e., the source physical storage unit address corresponding to the to-be-moved data, is recorded by the first management structure.

[0124] Step S2: Record the construction relationship between each write unit and the to-be-moved data based on the first management structure.

[0125] The construction relationship includes but is not limited to the data allocation relationship between the write unit and the to-be-programmed data. The data allocation relationship includes the number of to-be-programmed data contained in a write unit and the storage order of different to-be-moved data in the write unit.

[0126] Specifically, when the write unit is constructed based on the plurality of to-be-moved data in step S314, the construction relationship between each write unit and the to-be-moved data is recorded by the first management structure.

[0127] In some embodiments, the method further includes recording the storage address of each write unit in the cache space based on the first management structure, and managing the cache space based on the first management structure.

[0128] Specifically, when the corresponding storage area in the cache space is allocated by moving the read operation task, the storage address of each write unit in the cache space is recorded, and the cache space is managed by the first management structure.

[0129] Step S3: When the to-be-moved data is coarsely programmed, determine the programming order of each write unit based on the first management structure.

[0130] Specifically, the write rule of the migration write operation task is constructed by the first management structure, and when the data to be migrated is roughly programmed, the programming order of each write unit is determined according to the first management structure. Wherein, the write rule of the migration write operation task can be set by those skilled in the art according to the first management structure, which is not limited herein.

[0131] In some embodiments, when the data to be migrated is roughly programmed, the first management structure is also used to record the target physical storage unit address.

[0132] Step S4: After the rough programming is completed, the storage area corresponding to the data to be migrated of the write unit in the cache space is released based on the first management structure.

[0133] Specifically, after any write unit completes rough programming, the storage area corresponding to the data to be migrated of the write unit in the cache space is released by the first management structure.

[0134] Step S303: cache the data to be migrated which has completed rough programming to the cache space;

[0135] Specifically, since the storage area of the data to be migrated in the cache space has been released after the rough programming is completed, the data to be migrated which has completed rough programming needs to be cached to the cache space before fine programming.

[0136] In the embodiments of the present application, step S303 specifically includes steps S331-S332:

[0137] Step S331: obtain the first management structure cached in the cache space;

[0138] Specifically, the first management structure cached in the cache space is obtained to store the data to be migrated to the cache space again according to the first management structure.

[0139] Step S332: obtain the data to be migrated and store the data to be migrated to the cache space.

[0140] Specifically, the data to be migrated is obtained according to the first management structure, and the data to be migrated is stored to the cache space.

[0141] In the embodiments of the present application, step S332 specifically includes steps S3321-S3322:

[0142] Step S3321: read the first target super block based on the source physical storage unit address recorded by the first management structure to obtain the data to be migrated;

[0143] Specifically, a source physical storage unit address of the first management structure record is obtained, and a first target super block is read according to the source physical storage unit address to obtain a plurality of to-be-moved data.

[0144] Step S3322: A write unit is constructed based on the construction relationship of the first management structure record, and the write unit is stored in the cache space.

[0145] Specifically, the read to-be-moved data is reconstructed into a write unit according to the construction relationship used during rough programming (i.e., the construction relationship of the first management structure record) through a move read operation task, and each write unit is stored in a corresponding storage area in the cache space.

[0146] Step S304: Fine programming is performed on the to-be-moved data to the target physical storage unit address, and the cache space is released after the fine programming is completed.

[0147] Specifically, fine programming is performed on the to-be-programmed data, and the storage area of the to-be-programmed data in the cache space is released after the fine programming is completed.

[0148] In some embodiments, step S304 specifically includes steps S341-S343:

[0149] Step S341: Fine programming instructions are generated based on the front-end module, and the fine programming instructions are sent to the flash algorithm module, so that the flash algorithm module and the back-end module transmit the write unit corresponding to the fine programming instructions from the cache space to the flash medium;

[0150] The fine programming instructions are used to instruct the flash algorithm module, the back-end module, and the hardware module to perform corresponding programming operations.

[0151] Specifically, a move write operation task is constructed through the first management structure, the front-end module is dispatched to generate fine programming instructions, and the fine programming instructions are sent to the flash algorithm module. The flash algorithm module determines the target physical storage unit address according to the fine programming instructions, and the back-end module transmits the write unit corresponding to the fine programming instructions from the cache space to the flash medium.

[0152] Step S342: Fine programming is performed on the write unit based on the hardware module;

[0153] Specifically, the hardware module is dispatched to perform rough programming on the write unit through a move write operation task, and a plurality of write units are stored in the target physical storage unit address of the user data area. At this time, the storage unit in the flash medium reaches the final voltage state.

[0154] Step S343: After the fine programming is completed, the storage area of the to-be-moved data corresponding to the write unit in the cache space is released.

[0155] Specifically, after the fine programming of any write unit is completed, the corresponding storage area of the write unit in the cache space is released by moving the read operation task.

[0156] In some embodiments, the step S304 comprises: fine programming the data to be moved to the target physical storage unit address according to the first management structure, and releasing the cache space based on the first management structure after the fine programming is completed.

[0157] The step of fine programming the data to be moved to the target physical storage unit address according to the first management structure and releasing the cache space based on the first management structure after the fine programming is completed comprises steps S344-S346.

[0158] Step S344: determining the programming order of each write unit and the target physical storage unit address based on the first management structure;

[0159] Specifically, the write rule of the moving write operation task is constructed by the first management structure. Since the first management structure is not released from the cache space after the coarse programming is completed, the write rule in the process of fine programming is the same as the write rule in the process of coarse programming, that is, the programming order of each write unit in the process of fine programming and coarse programming is the same. According to the target physical storage unit address recorded by the first management structure in the process of coarse programming, the target physical storage unit address corresponding to each write unit is determined.

[0160] It can be understood that the first management structure is not released from the cache space, and the related information of the moving read operation is retained, so that the first management structure used in the coarse programming can be reused in the fine programming to construct the same write order and related rules, so as to quickly complete the fine programming.

[0161] Step S345: fine programming each write unit according to the programming order and storing each write unit to the corresponding target physical storage unit address;

[0162] Specifically, the hardware module is dispatched to fine program each write unit according to the programming order and store each write unit to the corresponding target physical storage unit address by the moving write operation task.

[0163] Step S346: releasing the first management structure after each write unit is fine programmed.

[0164] Specifically, the first management structure is released after each write unit is fine programmed, so that the corresponding storage area of the data to be moved corresponding to each write unit in the cache space can be released, and the two programming (coarse programming and fine programming) is finally completed.

[0165] It can be understood that, since the first management structure body reserves all the management structures except the data to be moved in the coarse programming, when fine programming is needed, the same moving write operation task is re-constructed according to the first management structure body, the rule of moving write operation task in coarse programming is re-constructed, and the first management structure bodies of the management cache space and the moving read operation task are released after the fine programming is completed, that is, two programming of the moving write operation task is completed.

[0166] In the embodiment of the present application, the flash memory device further comprises a die, the super block writes data to the die in parallel when performing the programming operation, the die comprises a cache unit, and the method further comprises: calculating the cache capacity used by the programming operation according to the write bandwidth threshold of the flash memory device and the bandwidth threshold of the cache space.

[0167] The step of calculating the cache capacity used by the programming operation specifically comprises: calculating the number of write units based on the write bandwidth threshold of the flash memory device, the bandwidth threshold of the cache space and the write bandwidth threshold of a single die; and calculating the cache capacity used by the programming operation based on the number of write units and the capacity of the cache unit.

[0168] The programming operation comprises coarse programming or fine programming, the cache capacity used by the programming operation is the capacity of the cache space used by the programming operation, the write bandwidth threshold of the flash memory device is the maximum value of the total write bandwidth of the flash memory device, the bandwidth threshold of the cache space is the maximum bandwidth of the cache space, and the write bandwidth threshold of a single die is the maximum write bandwidth of a single die. The write bandwidth threshold of the flash memory device, the bandwidth threshold of the cache space and the write bandwidth threshold of a single die can be set by those skilled in the art according to the actual model of the flash memory device, the actual product type of the memory serving as the cache space and the type of the flash memory medium, and are not limited herein.

[0169] The cache capacity is the product of the number of write units and the capacity of the cache unit, the number of write units is the number of write units that need to be cached without breaking the bandwidth limit, and the capacity of the cache unit is the size of the storage space corresponding to a write unit on the die. The number of write units is the maximum value of a first number and a second number, the first number is the ratio of the write bandwidth threshold of the flash memory device to the write bandwidth threshold of a single die, and the second number is the ratio of the bandwidth threshold of the cache space to the write bandwidth threshold of a single die.

[0170] When a cache unit stores only one write unit, the capacity of the cache unit is the same as the size of the write unit; when a cache unit stores multiple write units, the capacity of the cache unit is an integer multiple of the size of the write unit. The capacity of the cache unit is set by those skilled in the art according to the actual type of the flash memory medium and the size of the write unit, and is not limited herein.

[0171] Specifically, the write bandwidth threshold of the flash device is divided by the write bandwidth threshold of a single die to obtain a first quantity. The bandwidth threshold of the cache space is divided by the write bandwidth threshold of a single die to obtain a second quantity. The maximum of the first quantity and the second quantity is taken as the write unit quantity. The write unit quantity is multiplied by the capacity of the cache unit to obtain the cache capacity used by the programming operation.

[0172] In the embodiments of the present application, the method further comprises: after the cache capacity used by the programming operation is calculated, allocating cache space for the to-be-moved data according to the cache capacity.

[0173] Compared with the prior art which takes the product of the number of dies, the size of a write unit and the number of super pages contained in a word line as the total cache data amount, the present application can more accurately calculate the cache capacity used by the programming operation by taking the maximum of the first quantity and the second quantity as the write unit quantity and taking the product of the write unit quantity and the capacity of the cache unit as the cache capacity used by the programming operation, thereby improving the resource utilization rate of the cache space.

[0174] For example: when the flash device has 8 dies, a word line contains 9 super pages, and the size of each QLC write unit is 128KB, the total cache data amount is 8*9*128KB=9216KB. Under the same conditions, the write unit quantity is 16, which is equivalent to when the flash device has 8 dies, a word line only has 2 super pages participating in the programming operation, and when the capacity of the cache unit is 128KB, the cache capacity used by the programming operation is 8*2*128KB=2048KB, which is reduced by 7168KB compared with the total cache data amount.

[0175] By calculating the write unit quantity based on the write bandwidth threshold of the flash device, the bandwidth threshold of the cache space and the write bandwidth threshold of a single die, and calculating the cache capacity used by the programming operation based on the write unit quantity and the capacity of the cache unit, the present application can consider the cache capacity used by the programming operation according to the total read-write bandwidth of the flash and the size of the cache space, thereby improving the accuracy of cache capacity calculation and reducing resource idling.

[0176] Compared with the prior art which writes the data read from the moving read operation into the cache space until the cache space is released after the moving write operation completes the coarse programming and fine programming, the present application can make the cache space available to other tasks during the time period from when the data completes the coarse programming to when the fine programming starts by releasing the cache space after the coarse programming is completed. And by reasonably releasing the cache space within the effective time, the consumption of the cache space can be reduced without affecting the performance, thereby saving computing power.

[0177] Please refer to Figure 4 , Figure 4is a cache space occupation time length diagram provided by an embodiment of the present application;

[0178] Figure 4 Take a scenario that the cache space is released after the completion of the coarse programming and the fine programming.

[0179] As shown in Figure 4 , the total time from the start of writing the read data into the cache space to the completion of the coarse programming and the fine programming is T0, that is, the cache space occupation time length is T0.

[0180] Please refer to Figure 5 , Figure 5 is another cache space occupation time length diagram provided by an embodiment of the present application;

[0181] Figure 5 Take a scenario that the cache space is released after the completion of the coarse programming.

[0182] As shown in Figure 5 , the time length from the start of writing the read data into the cache space to the release of the cache space after the completion of the coarse programming is T1, and the time length from the start of writing the read data into the cache space again to the release of the cache space after the completion of the fine programming is T2.

[0183] The cache space occupation time length T3 is the sum of the time length T1 from the start of writing the read data into the cache space to the release of the cache space after the completion of the coarse programming and the time length T2 from the start of writing the read data into the cache space again to the release of the cache space after the completion of the fine programming.

[0184] For the existing scheme, the total time from the start of writing the read data into the cache space to the completion of the coarse programming and the fine programming is T0, that is, the cache space occupation time length is T0, and the total usage bandwidth in the T0 time is the ratio of the cache space capacity and the cache space occupation time length T0.

[0185] In the scenario that the cache space is released after the completion of the coarse programming, the cache space occupation time length T3 is the sum of the time length from the start of writing the read data into the cache space to the release of the cache space after the completion of the coarse programming and the time length from the start of writing the read data into the cache space again to the release of the cache space after the completion of the fine programming. The usage bandwidth in the T3 time is the ratio of the cache capacity used by the programming operation and the cache space occupation time length T3.

[0186] Since the cache capacity used by the programming operation is less than the capacity of the cache space, and the occupation time T0 of the cache space is greater than T3, the usage bandwidth in T3 time is less than the total usage bandwidth in T0 time, that is, by releasing the cache space after completing the coarse programming, the application can reduce the usage bandwidth of the cache space.

[0187] The released computing power is the product of the difference between the occupation time of the cache space (that is, T3-T0) and the cache capacity used by the programming operation, and the saved computing power is the difference between the first computing power and the second computing power. The first computing power is the product of the capacity of the cache space and the occupation time T0 of the cache space, and the second computing power is the product of the cache capacity used by the programming operation and the occupation time T3 of the cache space.

[0188] In the embodiment of the application, a data migration method is provided, which is applied to a flash memory device including a cache space and a flash memory medium, the flash memory medium including a user data area, and the cache space being used to cache to-be-migrated data. The data migration method includes: reading the to-be-migrated data from a source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space; performing coarse programming on the to-be-migrated data to a target physical storage unit address of the user data area, and releasing the cache space after completing the coarse programming; caching the to-be-migrated data that has completed the coarse programming to the cache space; performing fine programming on the to-be-migrated data to the target physical storage unit address, and releasing the cache space after completing the fine programming.

[0189] By reading the to-be-migrated data from the source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space, performing coarse programming on the to-be-migrated data to the target physical storage unit address of the user data area, and releasing the cache space after completing the coarse programming, and caching the to-be-migrated data that has completed the coarse programming to the cache space, performing fine programming on the to-be-migrated data to the target physical storage unit address, and releasing the cache space after completing the fine programming, the application can release the cache space in time after completing each programming (coarse programming or fine programming), reduce the occupation time of the cache resource, and enable other tasks to use the cache space, thereby improving the resource usage efficiency of the cache space.

[0190] Please refer to Figure 6 , Figure 6 is a structural schematic diagram of a storage control chip provided by the embodiment of the application;

[0191] As Figure 6 indicated, the storage control chip 102 includes one or more processors 121 and a memory 122. Among them, Figure 6 In the embodiment, the processor 121 is taken as an example.

[0192] The processor 121 and the memory 122 can be connected through a bus or other means,Figure 6 The bus connection is taken as an example.

[0193] The processor 121 is configured to provide computing and control capabilities to control the flash memory device 100 to perform corresponding tasks, for example, to control the flash memory device 100 to perform the data migration method in any of the above method embodiments. The flash memory device includes a cache space and a flash memory medium, and the flash memory medium includes a user data area. The cache space is used to cache to-be-migrated data. The data migration method includes: reading the to-be-migrated data from a source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space; performing coarse programming of the to-be-migrated data to a target physical storage unit address of the user data area, and releasing the cache space after the coarse programming is completed; caching the to-be-migrated data that has completed the coarse programming to the cache space; performing fine programming of the to-be-migrated data to the target physical storage unit address, and releasing the cache space after the fine programming is completed.

[0194] By reading the to-be-migrated data from the source physical storage unit address of the user data area and caching the to-be-migrated data in the cache space, performing coarse programming of the to-be-migrated data to the target physical storage unit address of the user data area, and releasing the cache space after the coarse programming is completed, and caching the to-be-migrated data that has completed the coarse programming to the cache space, performing fine programming of the to-be-migrated data to the target physical storage unit address, and releasing the cache space after the fine programming is completed, the application can release the cache space in time after each programming (coarse programming or fine programming) is completed, reduce the occupation time of the cache resource, and enable other tasks to use the cache space, thereby improving the resource use efficiency of the cache space.

[0195] The processor 121 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The processor 121 can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0196] The memory 122, as a non-transitory computer readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the data migration method in the embodiments of the present application. The processor 121 can implement the data migration method in any of the method embodiments described above by running the non-transitory software programs, instructions and modules stored in the memory 122. Specifically, the memory 122 can include a volatile memory (VM), such as a random access memory (RAM); the memory 122 can also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 122 can also include a combination of the above types of memories.

[0197] The memory 122 can include a high-speed random access memory and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 122 can optionally include a memory disposed remotely relative to the processor 121, and these remote memories can be connected to the processor 121 through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0198] One or more modules are stored in the memory 122, and when executed by the one or more processors 121, perform the data migration method in any of the method embodiments described above, for example, perform the above-described Figure 3 each of the steps shown.

[0199] Please refer to Figure 7 , Figure 7 is another structure diagram of a flash memory device provided by the embodiments of the present application;

[0200] As Figure 7 shown, the flash memory device 100 includes a storage control chip 102 and at least one flash memory medium 105. Among them, the flash memory medium 105 is in communication connection with the storage control chip 102, Figure 7 The flash memory device 100 also includes a cache space (not shown in the figure), which is used to store data to be migrated, and the flash memory medium 105 includes a user data area (not shown in the figure).

[0201] The storage control chip 102 is configured to execute the data migration method in any of the above embodiments, and includes: reading the to-be-migrated data from a source physical storage unit address of a user data area and caching the to-be-migrated data in a cache space; performing coarse programming of the to-be-migrated data to a target physical storage unit address of the user data area, and releasing the cache space after the coarse programming is completed; caching the to-be-migrated data that has completed the coarse programming to the cache space; and performing fine programming of the to-be-migrated data to the target physical storage unit address, and releasing the cache space after the fine programming is completed.

[0202] The flash medium 105 is communicatively connected to the storage control chip 102, and is configured to store data.

[0203] By including the storage control chip in the flash device, the storage control chip is configured to execute the data migration method in any of the above embodiments, and the application can release the cache space in time after each programming (coarse programming or fine programming) is completed, reduce the occupation time of the cache resource, enable other tasks to use the cache space, and thus improve the resource use efficiency of the cache space.

[0204] The application also provides a non-volatile computer storage medium, which stores computer executable instructions. The computer executable instructions are executed by one or more processors, for example, the one or more processors can execute the data migration method in any of the above method embodiments, for example, execute the above-described steps.

[0205] The device or equipment embodiments described above are merely illustrative, and the unit modules described as separate components can or can not be physically separated, and the components described as module units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network module units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0206] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be implemented by means of software plus a general hardware platform, and of course can also be implemented by hardware. Based on such understanding, the above technical solutions or the part that contributes to the related art can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of the embodiments or some parts of the embodiments.

[0207] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, but not to limit them; under the idea of the present application, the technical features in the above examples or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the present application as described above. In order to be brief, they are not provided in detail; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data migration method, characterized by, The application is applied to a flash memory device, the flash memory device includes a cache space and a flash memory medium, the flash memory medium includes a user data area, the cache space is used for caching to-be-moved data, and the flash memory medium further includes a first target super block; The method comprises: reading the to-be-moved data from a source physical storage unit address of a user data area and caching the to-be-moved data in the cache space; coarsely programming the to-be-moved data to a target physical storage unit address of the user data area, and releasing the cache space after the coarse programming is completed; caching the to-be-moved data that has completed the coarse programming to the cache space; finely programming the to-be-moved data to the target physical storage unit address, and releasing the cache space after the fine programming is completed; The reading of the to-be-moved data from a source physical storage unit address of a user data area and the caching of the to-be-moved data in the cache space comprises: traversing a first mapping table item of the first target super block and a second mapping table item in the cache space; determining a source physical storage unit address corresponding to the to-be-moved data according to the first mapping table item and the second mapping table item; reading a first target super block based on the source physical storage unit address to obtain to-be-moved data; and constructing a write unit based on a plurality of the to-be-moved data, and storing each write unit to the cache space; The method further comprises: calculating a write unit quantity based on a write bandwidth threshold of a flash memory device, a bandwidth threshold of a cache space, and a write bandwidth threshold of a single die; calculating a cache capacity used by a programming operation based on the write unit quantity and a capacity of a cache unit; wherein the programming operation comprises coarse programming or fine programming, and the cache capacity is a product of the write unit quantity and the capacity of the cache unit; the write unit quantity is a maximum value in a first quantity and a second quantity, the first quantity is a ratio of the write bandwidth threshold of the flash memory device and the write bandwidth threshold of the single die, and the second quantity is a ratio of the bandwidth threshold of the cache space and the write bandwidth threshold of the single die.

2. The method of claim 1, wherein, The method further comprises: caching a first management structure constructed in the process of reading the to-be-moved data from a source physical storage unit address of a user data area to the cache space.

3. The method of claim 2, wherein, The method further comprises: recording the source physical storage unit address based on the first management structure after the source physical storage unit address corresponding to the to-be-moved data is determined; recording a construction relationship between each write unit and the to-be-moved data based on the first management structure; determining a programming order of each write unit based on the first management structure when the to-be-moved data is coarsely programmed; releasing a storage area corresponding to the to-be-moved data in the cache space corresponding to the write unit based on the first management structure after the coarse programming is completed.

4. The method according to claim 3, wherein the caching of the to-be-moved data that has completed the coarse programming to the cache space comprises: obtaining the first management structure cached in the cache space; obtaining to-be-moved data and storing the to-be-moved data to the cache space; The fine programming of the data to be moved to the target physical storage unit address, and releasing the cache space after the fine programming is completed, comprises: Fine programming of the data to be moved to the target physical storage unit address according to the first management structure, and releasing the cache space based on the first management structure after the fine programming is completed.

5. The method of claim 4, wherein, The obtaining of the data to be moved and the storing of the data to be moved to the cache space, comprises: Reading a first target super block based on the source physical storage unit address recorded by the first management structure to obtain data to be moved; Building a write unit based on the construction relationship recorded by the first management structure, and storing the write unit to the cache space.

6. The method of claim 4, wherein the fine programming of the data to be moved to the target physical storage unit address according to the first management structure, and releasing the cache space based on the first management structure after the fine programming is completed, comprises: Determining the programming order and the target physical storage unit address of each write unit based on the first management structure; Fine programming of each write unit according to the programming order, and storing each write unit to the corresponding target physical storage unit address; Releasing the first management structure after the fine programming of each write unit is completed. Comprise:

7. A memory control chip, characterized by At least one processor; And The memory is in communication connection with the at least one processor; wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the data moving method of any one of claims 1-6. Comprise:

8. A flash memory device, comprising: The storage control chip of claim 7; At least one flash medium in communication connection with the storage control chip. ​

Images