An instruction dispatch method and apparatus, an electronic device, and a readable storage medium

Abstract

Embodiments of the present application provide an instruction dispatching method and device, electronic equipment and readable storage medium, which are applied to the technical field of computer. In the method, the number of target instructions of the same instruction type in each first transmission queue can be obtained; based on the number of target instructions, the load order of each first transmission queue for the instruction type is determined; based on the priority between the load order and the queue entrance of the first transmission queue, the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction is determined, so as to dispatch each to-be-dispatched instruction through the corresponding queue entrance. According to the load order of the first transmission queue and the priority of the queue entrance, the to-be-dispatched instruction of the corresponding instruction type can be dispatched to the queue entrance of the first transmission queue, the to-be-dispatched instructions of each instruction type can be evenly dispatched to the queue entrance of the transmission queue of the corresponding instruction type, and the balance degree of instruction dispatching can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to an instruction dispatching method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] At present, with the continuous development of instruction set, the type and number of functional units required in the execution stage are increasing, which leads to the expansion of the number of transmission queues serving the functional units.

[0003] In the related art, a transmission queue cache is usually added in front of the transmission queue, a small number of transmission queues are managed through the transmission queue cache, and the dispatching operation is completed in two cycles, that is, in the first cycle, each to-be-dispatched instruction is distributed to multiple transmission queue caches, and in the second cycle, the to-be-dispatched instructions in the transmission queue cache are dispatched to the specific transmission queue managed by each transmission queue cache.

[0004] However, the above-mentioned instruction dispatching method needs to set a transmission queue cache in the processor and increases the number of processor pipeline stages, which leads to poor instruction dispatching balance and affects the instruction processing performance of the processor. SUMMARY

[0005] Embodiments of the present application provide an instruction dispatching method, device, electronic equipment and readable storage medium, which can solve the problems in the related art.

[0006] In order to solve the above-mentioned problems, an instruction dispatching method is disclosed in the embodiments of the present application, and the method comprises:

[0007] obtaining the number of target instructions of the same instruction type in each first transmission queue; wherein the first transmission queue is used to transmit instructions to the functional unit corresponding to the instruction type;

[0008] determining the load sequence of each first transmission queue for the instruction type based on the number of target instructions;

[0009] determining the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction based on the priority between the load sequence and the queue entrance of the first transmission queue, so as to dispatch each to-be-dispatched instruction through the corresponding queue entrance; wherein the to-be-dispatched instruction corresponds to the instruction type.

[0010] Optionally, the determination of the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction based on the priority between the load sequence and the queue entrance of the first transmission queue comprises:

[0011] determining the one-hot encoding corresponding to each dispatching sequence based on the load sequence; wherein the valid bit of the one-hot encoding is used to indicate the first transmission queue corresponding to the corresponding dispatching sequence.

[0012] determine the one-hot encoding corresponding to each to-be-issued instruction according to the dispatch order corresponding to the one-hot encoding, and generate a first encoding matrix used as a basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-issued instruction;

[0013] determine the queue entry of the first transmission queue corresponding to each to-be-issued instruction according to the matrix row number and the matrix column number corresponding to each effective bit in the first encoding matrix.

[0014] Optionally, the determination of the queue entry of the first transmission queue corresponding to each to-be-issued instruction according to the matrix row number and the matrix column number corresponding to each effective bit in the first encoding matrix comprises:

[0015] perform bit-by-bit addition on each matrix row in the first encoding matrix and all previous matrix rows to obtain a target matrix row corresponding to the matrix row, and the target matrix rows constitute a second encoding matrix;

[0016] determine the queue entry of the first transmission queue corresponding to each to-be-issued instruction according to the matrix row number, the matrix column number and the effective bit value corresponding to each effective bit in the second encoding matrix; the effective bit represents the first element bit matching a target value in each column of the second encoding matrix, and the target value has a corresponding relationship with the priority.

[0017] Optionally, the determination of the one-hot encoding corresponding to each to-be-issued instruction according to the dispatch order corresponding to the one-hot encoding, and the generation of the first encoding matrix used as a basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-issued instruction comprise:

[0018] determine an instruction index corresponding to each to-be-issued instruction based on the number of previous instructions of each to-be-issued instruction;

[0019] determine the one-hot encoding corresponding to each to-be-issued instruction based on the instruction index and the dispatch order;

[0020] arrange the one-hot encoding corresponding to each to-be-issued instruction according to the instruction index to obtain the first encoding matrix.

[0021] Optionally, the determination of the one-hot encoding corresponding to each to-be-issued instruction based on the instruction index and the dispatch order comprises:

[0022] in a case where the number of instructions in the set of to-be-issued instructions is greater than the total number of queues of the first transmission queue, expand the one-hot encoding sequence constituted by the one-hot encoding to obtain a target one-hot encoding sequence according to the number of instructions in the set of to-be-issued instructions; the number of encodings in the target one-hot encoding sequence is equal to the number of instructions, and the one-hot encodings in the one-hot encoding sequence are arranged based on the corresponding dispatch order;

[0023] Based on the instruction index, sequentially select the one-hot encoding corresponding to each to-be-dispatched instruction from the target one-hot encoding sequence.

[0024] Optionally, the generating, based on the one-hot encoding corresponding to each to-be-dispatched instruction, of a first encoding matrix used as a basis for instruction dispatching comprises:

[0025] Based on the queue index corresponding to each transmission queue other than the first transmission queue in the full-quantity transmission queue sequence, add a zero bit in the one-hot encoding corresponding to each to-be-dispatched instruction to obtain a target one-hot encoding corresponding to each to-be-dispatched instruction; wherein the number of encoding bits of the target one-hot encoding is equal to the number of queues of the full-quantity transmission queue sequence.

[0026] According to the dispatching order corresponding to the target one-hot encoding, determine the target one-hot encoding corresponding to each to-be-dispatched instruction, and based on the target one-hot encoding corresponding to each to-be-dispatched instruction, generate a first encoding matrix used as a basis for instruction dispatching, so as to determine the transmission queue corresponding to each to-be-dispatched instruction from the full-quantity transmission queue sequence through the matrix number of the first encoding matrix.

[0027] Optionally, the determining, based on the target instruction quantity, of the load order of each first transmission queue for the instruction type comprises:

[0028] Compare the target instruction quantity of each first transmission queue with each other to obtain a comparison result corresponding to each first transmission queue;

[0029] Based on the comparison result, determine that the target instruction quantity is less than the number of queues of the first transmission queue.

[0030] According to the number of queues corresponding to each first transmission queue, determine the load order of each first transmission queue for the instruction type.

[0031] Optionally, the method further comprises:

[0032] In a case where the queue state of the first transmission queue is a ready state, according to the instruction order of each to-be-dispatched instruction, select a target to-be-dispatched instruction from the to-be-dispatched instruction corresponding to the first transmission queue and dispatch the target to-be-dispatched instruction to the first transmission queue, and block the to-be-dispatched instruction after the target to-be-dispatched instruction to dispatch the blocked to-be-dispatched instruction in a subsequent clock cycle; wherein the instruction quantity of the target to-be-dispatched instruction is the same as the number of queue entries of the first transmission queue.

[0033] In a case where the queue state of the first transmission queue is a full state, block each to-be-dispatched instruction and the to-be-dispatched instruction after the to-be-dispatched instruction to dispatch the blocked to-be-dispatched instruction in a subsequent clock cycle.

[0034] In another aspect, the embodiments of the present application disclose an instruction dispatching device, which comprises:

[0035] an acquisition module, configured to acquire a target instruction quantity of the same instruction type in each first transmission queue, wherein the first transmission queue is used to transmit instructions to a functional unit corresponding to the instruction type;

[0036] a load sequence module, configured to determine a load sequence of each first transmission queue for the instruction type based on the target instruction quantity;

[0037] a dispatching module, configured to determine a queue entry of each first transmission queue corresponding to a to-be-dispatched instruction based on a priority between the load sequence and the queue entry of the first transmission queue, so as to dispatch each to-be-dispatched instruction through the corresponding queue entry, wherein the to-be-dispatched instruction corresponds to the instruction type.

[0038] In still another aspect, the embodiments of the present application further disclose an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the foregoing instruction dispatching method.

[0039] The embodiments of the present application further disclose a readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the foregoing instruction dispatching method.

[0040] The embodiments of the present application have the following advantages: in the instruction dispatching method provided by the embodiments of the present application, a target instruction quantity of the same instruction type in each first transmission queue is acquired, wherein the first transmission queue is used to transmit instructions to a functional unit corresponding to the instruction type; a load sequence of each first transmission queue for the instruction type is determined based on the target instruction quantity; a queue entry of each first transmission queue corresponding to a to-be-dispatched instruction is determined based on a priority between the load sequence and the queue entry of the first transmission queue, so as to dispatch each to-be-dispatched instruction through the corresponding queue entry, wherein the to-be-dispatched instruction corresponds to the instruction type. In the embodiments of the present application, the load sequence of each first transmission queue for the same instruction type is determined, and the to-be-dispatched instruction of the corresponding instruction type is dispatched to the queue entry of each first transmission queue according to the load sequence of the first transmission queue and the priority of the queue entry. In this way, the to-be-dispatched instruction of each instruction type can be evenly dispatched to the transmission queue of the corresponding instruction type, and the transmission queue can evenly dispatch the to-be-dispatched instruction through different queue entries, which helps to improve the balance degree of instruction dispatching, so that the efficiency of the processor in processing instructions can be improved to a certain extent.

[0041] And in the embodiment of the present application, the setting of the transmit queue cache in the processor for instruction dispatching is avoided, the circuit area of the processor for setting the transmit queue cache can be saved, the number of the processor pipeline can be reduced, and the instruction processing performance of the processor can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of the drawings.

[0043] Figure 1 is a step flow chart of an embodiment of the instruction dispatching method of the present application;

[0044] Figure 2 is a transmit queue schematic diagram provided by the embodiment of the present application;

[0045] Figure 3 is a transmit queue set schematic diagram provided by the embodiment of the present application;

[0046] Figure 4 is a structural block diagram of an instruction dispatching device of the present application;

[0047] Figure 5 is a structural block diagram of an electronic device for instruction dispatching provided by the example of the present application. DETAILED DESCRIPTION

[0048] The technical solutions of the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0049] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0050] The instruction dispatch method provided by the embodiments of the present application can be applied to a processor. The instruction pipeline of the processor can generally include the steps of fetching, decoding, renaming, dispatching, issuing, executing, and writing back. Among them, the fetching operation can be used to obtain the instructions to be executed; the decoding operation can be used to analyze the instructions obtained in the fetching stage, determine the operation type and operand position information corresponding to the instructions, and prepare the control signals required for executing the instructions; the renaming operation can be used to map the logical register number required by the instructions to the physical register number, so as to explicitly implement the physical register of the instructions; the dispatching operation can be used to dispatch the renamed instructions (i.e. the instructions to be dispatched) to the corresponding issue queue; the issuing operation can be used to temporarily store the instructions, and the instructions can be issued to the corresponding functional unit after being awakened in the issue queue; the executing operation is used to perform related calculations through the functional unit to actually execute the instructions; and the writing back operation can be used to write the execution result of the instructions back to the register file.

[0051] Method embodiments

[0052] Reference Figure 1 The method can include the following steps:

[0053] Step 101, obtaining the number of target instructions of the same instruction type in each first issue queue; wherein the first issue queue is used to issue instructions to the functional unit corresponding to the instruction type.

[0054] In the embodiment of the present application, the issue queue (IQ) in the processor can contain one or more queue entries and one or more queue exits. The queue entries can be used to receive and add instructions to the issue queue, and the queue exits can be used to issue instructions in the issue queue to functional units (FUs) connected to the queue exits. The functional units can include, but are not limited to, arithmetic logic units (ALUs), floating point units (FPUs), multipliers (MULs), branch jump units (BJUs), and the like, and the instruction types can include, but are not limited to, arithmetic logic types, floating point operation types, multiplication types, branch jump types, and the like, without specific limitation in the embodiment of the present application.

[0055] With reference to Figure 2 , Figure 2 A schematic diagram of an issue queue is shown in the embodiment of the present application, as shown in Figure 2 The issue queue IQ0 can have two queue entries enq0 and enq1 and two queue exits deq0 and deq1. Each queue exit of the issue queue can correspond to one or more execution units (EXUs), and each execution unit can include one or more functional units. As shown in Figure 2 The issue queue IQ0 can have two execution units, the first execution unit containing two functional units: an arithmetic logic unit and a multiplier unit, and the second execution unit including one functional unit: a branch jump unit. The instructions related to the three functional units of the issue queue IQ0 can enter the issue queue IQ0 from the queue entries enq0 or enq1, but since the queue exits are bound to the execution units, the instructions related to the arithmetic logic unit or the multiplier unit can only be dequeued from the queue exit deq0, and the instructions related to the branch jump unit can only be dequeued from the queue exit deq1.

[0056] In the embodiment of the present application, the issue queue with the same functional unit for the same instruction type in all issue queues of the processor can be regarded as the first issue queue corresponding to the instruction type. For all first issue queues of the same instruction type, the target instruction quantity corresponding to each first issue queue can be obtained. The target instruction quantity represents the number of instructions in the first issue queue corresponding to the above instruction type.

[0057] It should be noted that the instruction corresponding to the above instruction type can represent the instruction through a specific functional unit, so that the number of target instructions determined through the corresponding relationship can more accurately reflect the load situation of the first transmission queue for a certain functional unit; the instruction corresponding to the above instruction type can also represent all instructions that need to be transmitted through the queue outlet connected to the functional unit corresponding to the instruction type, so that when determining the number of target instructions through the corresponding relationship, it is not necessary to accurately identify the specific category of each instruction in the first transmission queue, but only to identify the transmission outlet of each instruction in the first transmission queue, so that the number of target instructions can be determined more quickly and efficiently, which helps to reduce the processing delay. Therefore, the number of target instructions of the first transmission queue can also be equal to the number of instructions of the above instruction type actually contained in the first transmission queue, or can be greater than the number of instructions of the above instruction type actually contained in the first transmission queue, and the statistical method of the number of target instructions can be flexibly set according to actual business needs, and the embodiments of the application are not limited specifically.

[0058] Referring to Figure 3 , Figure 3 A transmission queue set provided by an embodiment of the application is shown, as shown in Figure 3 The processor can include four transmission queues, namely transmission queue IQ0, transmission queue IQ1, transmission queue IQ2 and transmission queue IQ3, wherein each transmission queue can include two queue entrances enq0 and enq1, and each transmission queue can include two queue exits deq0 and deq1. The queue exit deq0 of the transmission queue IQ0, the queue exit deq0 of the transmission queue IQ1, the queue exit deq0 of the transmission queue IQ2 and the queue exit deq0 of the transmission queue IQ3 all include an arithmetic logic unit ALU, so that the transmission queues IQ0-IQ3 can be determined as a group of first transmission queues of the arithmetic logic unit type; and the queue exit deq0 of the transmission queue IQ0 and the queue exit deq0 of the transmission queue IQ1 both include a multiplication unit MUL, so that the transmission queues IQ0 and IQ1 can be determined as a group of first transmission queues of the multiplication unit type; and the queue exit deq1 of the transmission queue IQ0, the queue exit deq1 of the transmission queue IQ1 and the queue exit deq1 of the transmission queue IQ2 all include a branch jump unit BJU, so that the transmission queues IQ0, IQ1 and IQ2 can be determined as a group of first transmission queues of the branch jump unit type.

[0059] As Figure 3As shown, for a group of first issue queues IQ0-IQ3 of the arithmetic logic unit type, if the first issue queue IQ0 contains 4 instructions corresponding to the arithmetic logic type, the first issue queue IQ1 contains 5 instructions corresponding to the arithmetic logic type, the first issue queue IQ2 contains 6 instructions corresponding to the arithmetic logic type, and the first issue queue IQ3 contains 3 instructions corresponding to the arithmetic logic type. Then, for the arithmetic logic type, the target instruction quantity of the first issue queue IQ0 is 4, the target instruction quantity of the first issue queue IQ1 is 5, the target instruction quantity of the first issue queue IQ2 is 6, and the target instruction quantity of the first issue queue IQ3 is 3. It should be noted that the first issue queue IQ0 contains 5 instructions corresponding to the arithmetic logic type, which can represent that the first issue queue IQ0 contains 4 instructions that need to be executed by the arithmetic logic unit, or that the first issue queue IQ0 contains 4 instructions that need to be transmitted by the corresponding queue exit deq0 of the arithmetic logic unit. The statistical manner of the target instruction quantity can be flexibly set according to actual business requirements, and the embodiment of the present application does not make specific limitation.

[0060] In step 102, based on the target instruction quantity, a load order of each first issue queue for the instruction type is determined.

[0061] In the embodiment of the present application, after the target instruction quantity of each first issue queue for a certain instruction type is determined, the load order of each first issue queue for the instruction type can be determined according to the target instruction quantity of each first issue queue.

[0062] Specifically, the first issue queue can be sorted directly according to the target instruction quantity, and the sorting result is taken as the load order of the corresponding first issue queue.

[0063] In step 103, based on the load order and the priority between the queue entrance of the first issue queue, the queue entrance of the corresponding first issue queue of each to-be-issued instruction is determined, so as to issue each to-be-issued instruction through the corresponding queue entrance; wherein the to-be-issued instruction corresponds to the instruction type.

[0064] In the renaming stage, the processor will decode the instructions to obtain the functional unit information corresponding to the instructions, that is, to determine the instruction type corresponding to the instructions.

[0065] In this embodiment of the invention, instructions of the same type as the instruction corresponding to the first issue queue from all instructions decoded during the renaming phase or all instructions not yet dispatched can be considered as the set of instructions to be dispatched in the first issue queue. The instructions to be dispatched in this set are then dispatched based on the load order of the first issue queue for that instruction type. It should be noted that "all instructions decoded during the renaming phase" can represent all instructions decoded by the processor in one clock cycle or one clock tick, and the number of these instructions can be equal to the processor's rename width. Instructions not yet dispatched can include all instructions decoded during the renaming phase, as well as instructions that were not successfully dispatched in the previous cycle. Therefore, the number of instructions to be dispatched can be less than or equal to the processor's rename width, or it can be greater than the processor's rename width.

[0066] In this embodiment of the invention, the first launch queue may have multiple queue entries, and different queue entries may have different priorities. For example, such as... Figure 3 As shown, each of the first launch queues IQ0-IQ3 has two queue entries, enq0 and enq1. Each first launch queue's queue entry enq0 can have a high priority, and each first launch queue's queue entry enq1 can have a low priority. It should be noted that multiple queue entries of different first launch queues can have the same priority order; for example, the priority of queue entry enq0 for all first launch queues can be higher than the priority of queue entry enq1. Conversely, queue entries of different first launch queues can also have different priority orders; for example, the priority of queue entry enq0 for first launch queues IQ0 and IQ1 can be higher than the priority of queue entry enq1, while the priority of queue entry enq1 for first launch queues IQ2 and IQ3 can be higher than the priority of queue entry enq0. This embodiment of the invention does not impose specific limitations on this.

[0067] Specifically, instructions can be assigned in ascending order of load, prioritizing the first launch queue with lower load. Then, instructions are assigned in descending order of priority, prioritizing the higher-priority queue entries within the first launch queue. The assignment process can involve multiple rounds. In the first round, instructions are assigned sequentially to the first-priority queue entries of each first launch queue, following the load order from lowest to highest. In the second round, the remaining instructions are assigned sequentially to the second-priority queue entries of each first launch queue, again following the load order from lowest to highest, and so on, until all instructions have been assigned. The first priority is higher than the second priority. Once the queue entry of the first launch queue corresponding to an instruction is determined, the instruction can be assigned to that first launch queue through that queue entry.

[0068] For example, such as Figure 3 As shown, if the first transmit queues are arranged in ascending order of ALU instruction type load as IQ2, IQ1, IQ0, and IQ3, and the queue entry enq0 of each first transmit queue has the first priority and the queue entry enq1 has the second priority, and there are 6 instructions to be assigned in the current set of instructions to be assigned [instruction 0, instruction 1, instruction 2, instruction 3, instruction 4, instruction 5], then in the first round of allocation, instruction 0 is assigned to the queue entry enq0 of the first transmit queue IQ2, instruction 1 is assigned to the queue entry enq0 of the first transmit queue IQ1, instruction 2 is assigned to the queue entry enq0 of the first transmit queue IQ0, and instruction 3 is assigned to the queue entry enq0 of the first transmit queue IQ3; in the second round of allocation, instruction 4 is assigned to the queue entry enq1 of the first transmit queue IQ2, and instruction 5 is assigned to the queue entry enq1 of the first transmit queue IQ1.

[0069] Optionally, the instruction dispatch process in this embodiment of the invention can be set in the renaming stage of the processor instruction pipeline. That is, after the instruction type corresponding to the instruction is determined in the renaming stage, the dispatch operation of the instruction to be dispatched is performed, thereby optimizing the processing timing and helping to improve processor performance.

[0070] It should be noted that, in this embodiment of the invention, for each set of first launch queues corresponding to different instruction types, this method can be used to perform the dispatch operation of the corresponding instruction type's pending instructions. The pending instructions of different instruction types can be dispatched independently, thereby achieving the dispatch operation of all instructions, which helps to improve the utilization rate of the execution unit and the launch queue. The above-mentioned instruction dispatch process for different instruction types can be performed serially or in parallel; this embodiment of the invention does not impose specific limitations.

[0071] In conclusion, the instruction dispatching method provided by the embodiment of the present application comprises the following steps: obtaining the target instruction quantity of the same instruction type in each first transmission queue; the first transmission queue is used for transmitting instructions to the functional unit corresponding to the instruction type; determining the load sequence of each first transmission queue for the instruction type based on the target instruction quantity; determining the queue entry of the first transmission queue corresponding to each to-be-dispatched instruction based on the priority between the load sequence and the queue entry of the first transmission queue, so as to dispatch each to-be-dispatched instruction through the corresponding queue entry; the to-be-dispatched instruction corresponds to the instruction type. In the embodiment of the present application, the load sequence of each first transmission queue for the same instruction type is determined, and the to-be-dispatched instruction of the corresponding instruction type is dispatched to the queue entry of each first transmission queue according to the load sequence of the first transmission queue and the priority of the queue entry. In this way, the to-be-dispatched instructions of each instruction type can be evenly dispatched to the transmission queue of the corresponding instruction type, and the transmission queue can also evenly dispatch the to-be-dispatched instructions through different queue entries, which helps to improve the balance of instruction dispatching, thereby improving the efficiency of the processor in processing instructions to a certain extent.

[0072] In the embodiment of the present application, the transmission queue cache is avoided in the processor for instruction dispatching, which can save the circuit area of the transmission queue cache of the processor and reduce the number of processor pipeline stages, thereby further improving the instruction processing performance of the processor.

[0073] Optionally, in some embodiments, the step of determining the load sequence of each first transmission queue for the instruction type based on the target instruction quantity can specifically comprise:

[0074] In step 1021, the target instruction quantity of each first transmission queue is compared with each other to obtain the comparison result corresponding to each first transmission queue.

[0075] In the embodiment of the present application, each first transmission queue can be compared with each other to obtain the comparison result corresponding to each first transmission queue, which can indicate the size relationship between the target instruction quantity of the first transmission queue and the target instruction quantity of each other transmission queue. The above comparison process can be realized by a corresponding comparator in the processor.

[0076] For example, if the target instruction quantity corresponding to the first transmission queue IQ0-IQ3 is 4, 5, 6 and 3 respectively, the first transmission queue IQ0-IQ3 is compared with each other for a total of 6 times, the comparison result corresponding to the first transmission queue IQ0 can comprise IQ0<IQ1, IQ0<IQ2 and IQ0>IQ3; the comparison result corresponding to the first transmission queue IQ1 can comprise IQ1>IQ0, IQ1<IQ2 and IQ1>IQ3, and so on.

[0077] Further, the comparison results of each first transmission queue can be embodied in the form of a table or a matrix, and the comparison process can be shown in Table 1 as follows:

[0078] IQ0 IQ1 IQ2 IQ3 IQ0 0 IQ0 < IQ1 IQ0 < IQ2 IQ0 < IQ3 IQ1 ~ IQ0 < IQ1 0 IQ1 < IQ2 IQ1 < IQ3 IQ2 ~ IQ0 < IQ2 ~ IQ1 < IQ2 0 IQ2 < IQ3 IQ3 ~ IQ0 < IQ3 ~ IQ1 < IQ3 ~ IQ2 < IQ3 0

[0079] Table 1

[0080] wherein, IQ0<IQ1 represents judging whether the target instruction quantity of the first transmission queue IQ1 for the instruction type is greater than the target instruction quantity of the first transmission queue IQ0 for the instruction type, ~IQ0<IQ1 represents taking the inverse of the comparison result of IQ0<IQ1, and the rest is filled with zero. Therefore, by setting 6 comparators, it can be judged whether IQ0<IQ1, IQ0<IQ2, IQ0<IQ3, IQ1<IQ2, IQ1<IQ3, IQ2<IQ3 are true, if true, the result of the corresponding position is 1, if not true, the result of the corresponding position is 0, and the entire table can be filled by taking the inverse and filling with zero, and the complete comparison result of each first transmission queue can be obtained, wherein each column corresponds to the comparison result of a first transmission queue.

[0081] For example, if the target instruction quantities of the first transmission queues IQ0-IQ3 in Table 1 above are 4, 5, 6, and 3 respectively, the comparison results can be shown in Table 2 as follows:

[0082] IQ0 IQ1 IQ2 IQ3 IQ0 0 0 0 1 IQ1 1 0 0 1 IQ2 1 1 0 1 IQ3 0 0 0 0

[0083] Table 2

[0084] In step 1022, the target instruction quantity is determined to be less than the number of the first transmission queues based on the comparison results.

[0085] In the embodiment of the present application, according to the comparison results of each first transmission queue, the number of the first transmission queues whose target instruction quantity is less than the target instruction quantity of the first transmission queue can be counted.

[0086] Further, in the case of using the comparison method shown in Table 1 above, the comparison results of each first transmission queue (each column in Table 2) can be directly summed to obtain the number of the first transmission queues whose target instruction quantity is less than the target instruction quantity of the first transmission queue.

[0087] For example, the sum of each column in Table 2 can be obtained, and the number of the first transmission queue corresponding to IQ0 is 2, the number of the first transmission queue corresponding to IQ1 is 1, the number of the first transmission queue corresponding to IQ2 is 0, and the number of the first transmission queue corresponding to IQ3 is 3.

[0088] In step 1023, the load order of each first transmission queue for the instruction type is determined according to the number of queues corresponding to each first transmission queue.

[0089] In the embodiment of the present application, the number of queues corresponding to the first transmission queue can directly reflect the position of the target instruction number of the first transmission queue in the small-to-large order, and the number of queues of the first transmission queue can be directly used as the load order of the first transmission queue for the above instruction type.

[0090] For example, if the number of queues corresponding to IQ0 is 2, the number of queues corresponding to IQ1 is 1, the number of queues corresponding to IQ2 is 0, and the number of queues corresponding to IQ3 is 3, the above number of queues can be directly used as the load order of the corresponding first transmission queue, that is, the first transmission queue is arranged in the order of IQ2, IQ1, IQ0, and IQ3 from small to large.

[0091] In the embodiment of the present application, the target instruction number of each first transmission queue is compared with each other to obtain the comparison result corresponding to each first transmission queue, the number of queues of the first transmission queue is determined to be smaller than the target instruction number based on the comparison result, and the load order of each first transmission queue for the instruction type is determined according to the number of queues corresponding to each first transmission queue. The efficiency of determining the load order of the first transmission queue for the same instruction type can be improved, which helps to reduce the delay of the process of determining the load order and reduce the required processor area.

[0092] Optionally, in some embodiments, the step of determining the queue entry of the first transmission queue corresponding to each to-be-issued instruction based on the load order and the priority between the queue entry of the first transmission queue can specifically include:

[0093] In step 1031, the one-hot encoding corresponding to each issue order is determined based on the load order, and the valid bit of the one-hot encoding is used to indicate the first transmission queue corresponding to the corresponding issue order.

[0094] In the embodiment of the present application, one-hot encoding corresponding to each dispatch order can be generated to improve the efficiency of subsequent determination of the correspondence between the to-be-dispatched instruction and the queue entry. The one-hot encoding can represent the first transmission queue that needs to be dispatched according to the corresponding dispatch order. Therefore, the one-hot encoding can indicate the first transmission queue corresponding to the corresponding dispatch order in the first transmission queue sequence through the position of the valid bit in the one-hot encoding, thereby indicating the first transmission queue corresponding to the corresponding dispatch order. In the one-hot encoding, only one position is 1 and the rest are 0. The position that is 1 can be referred to as a valid bit, which can be used to indicate the load order of the corresponding first transmission queue in the load order. The dispatch order represents the order in one round of dispatching for the first transmission queue, that is, the total amount of the dispatch order can be the same as the number of the first transmission queue.

[0095] For example, if the first transmission queue loads are arranged from small to large as follows: IQ2, IQ1, IQ0, IQ3, based on the principle of preferentially assigning instructions to first transmission queues with lower loads, the one-hot encoding corresponding to the assignment order 1 can be set to 0010, that is, the third bit of the valid bit indicates the third first transmission queue IQ2 in the first transmission queue sequence. The one-hot encoding corresponding to the assignment order 2 can be set to 0100, that is, the second bit of the valid bit indicates the second first transmission queue IQ1 in the first transmission queue sequence. The one-hot encoding corresponding to the assignment order 3 can be set to 1000, that is, the first bit of the valid bit indicates the first first transmission queue IQ0 in the first transmission queue sequence. The one-hot encoding corresponding to the assignment order 4 can be set to 0001, that is, the fourth bit of the valid bit indicates the fourth first transmission queue IQ3 in the first transmission queue sequence.

[0096] In the embodiment of the present application, each group of first transmission queues can correspond to a group of one-hot encodings for balanced dispatching of instructions of the corresponding instruction type. The one-hot encodings can be stored in a register for subsequent use.

[0097] In step 1032, the one-hot encoding corresponding to the dispatch order is determined for each to-be-dispatched instruction, and a first encoding matrix used as a basis for instruction dispatching is generated based on the one-hot encoding corresponding to each to-be-dispatched instruction.

[0098] In the embodiment of the present application, one one-hot encoding can be assigned to each to-be-dispatched instruction in the to-be-dispatched instruction set. The assignment process can be multiple rounds, and the one-hot encoding is not repeated in each round.

[0099] Specifically, the sequential assignment can be performed according to the corresponding dispatching order of the one-hot encoding. For example, if the one-hot encoding is arranged as 0010, 0100, 1000, and 0001 according to the corresponding dispatching order, and there are 6 instructions 0-5 to be dispatched in the instruction set to be dispatched, the corresponding relationship can be established in sequence in the first round of allocation, i.e., instruction 0-0010, instruction 1-0100, instruction 2-1000, and instruction 3-0001, and the corresponding relationship can also be established in sequence in the second round of allocation, i.e., instruction 4-0010 and instruction 5-0100.

[0100] According to the above example, if the corresponding relationship between the 6 instructions to be dispatched and the 4 one-hot encodings is instruction 0-0010, instruction 1-0100, instruction 2-1000, instruction 3-0001, instruction 4-0010, and instruction 5-0100, the first encoding matrix shown in Table 3 can be generated as follows:

[0101] IQ0 IQ1 IQ2 IQ3 Instruction 0 0 0 1 0 Instruction 1 0 1 0 0 Instruction 2 1 0 0 0 Instruction 3 0 0 0 1 Instruction 4 0 0 1 0 Instruction 5 0 1 0 0

[0102] Table 3

[0103] In the above first encoding matrix, the matrix rows are composed of the one-hot encodings corresponding to the dispatching orders, the number of matrix rows is equal to the number of instructions in the instruction set to be dispatched, and each matrix row corresponds to one instruction to be dispatched, and each matrix column corresponds to one first transmission queue.

[0104] In step 1033, the queue entry of the first transmission queue corresponding to each instruction to be dispatched is determined according to the number of matrix rows and the number of matrix columns corresponding to each valid bit in the first encoding matrix.

[0105] In the embodiment of the present application, the first encoding matrix can be traversed to determine the number of matrix rows and the number of matrix columns in which each valid bit in the first encoding matrix is located. The valid bit can represent a matrix element with an element value of 1. Since each matrix row in the first encoding matrix can correspond to one instruction to be dispatched, and each matrix column can correspond to one first transmission queue, the corresponding relationship between one instruction to be dispatched and one first transmission queue can be determined according to the number of matrix rows and the number of matrix columns in which a valid bit is located.

[0106] After determining the instructions to be dispatched corresponding to each first transmission queue, the instructions to be dispatched can be allocated to each queue entry in turn according to the queue entry priority of the first transmission queue, so as to determine the corresponding relationship between the instructions to be dispatched and the transmission queues of the first transmission queue.

[0107] For example, in the first encoding matrix shown in Table 3, there are 6 valid bits. The valid bit of the first row of the matrix corresponds to the matrix row number and the matrix column number, which are 1 and 3 respectively, and instruction 0 is assigned to IQ2; the valid bit of the second row of the matrix corresponds to the matrix row number and the matrix column number, which are 2 and 2 respectively, and instruction 1 is assigned to IQ1, and so on. According to the first encoding matrix shown in Table 3, the corresponding relationship shown in Table 4 can be obtained:

[0108] First transmit queue Pending instructions IQ0 Instruction 2 IQ1 Instruction 1, Instruction 5 IQ2 Instruction 0, Instruction 4 IQ3 Instruction 3

[0109] Table 4

[0110] For each first transmission queue corresponding to the to-be-assigned instruction, the queue entry priority can be assigned. If the first transmission queue IQ0-IQ3 includes two queue entries enq0 and enq1, where enq0 is the first priority and enq1 is the second priority, in the case that the to-be-assigned instruction corresponding to the first transmission queue IQ0 includes instruction 2, instruction 2 can be assigned to the queue entry enq0 of the first transmission queue IQ0; in the case that the to-be-assigned instruction corresponding to the first transmission queue IQ1 includes instruction 1 and instruction 5, instruction 1 can be assigned to the queue entry enq0 of the first transmission queue IQ1, and instruction 5 can be assigned to the queue entry enq1 of the first transmission queue IQ1, and so on.

[0111] Further, in order to further improve the allocation efficiency, the valid bit order of each valid bit in the matrix column can also be obtained, so as to directly determine the queue entry of the first transmission queue corresponding to each to-be-assigned instruction according to the matrix row number, the matrix column number and the valid bit order of each valid bit in the first encoding matrix. The valid bit order indicates that the valid bit belongs to the first valid bit in the matrix column.

[0112] Specifically, the first transmission queue corresponding to the to-be-assigned instruction can be determined according to the matrix row number and the matrix column number corresponding to each valid bit, and the priority corresponding to the corresponding to-be-assigned instruction can be determined according to the valid bit order corresponding to each valid bit, so as to directly determine the first transmission queue corresponding to the to-be-assigned instruction and the corresponding queue entry in the first transmission queue. The queue entry corresponding to the to-be-assigned instruction is the queue entry matched with the priority thereof.

[0113] In the embodiment of the present application, the one-hot encoding corresponding to each dispatch order is determined based on the load sequence; wherein the valid bits of the one-hot encoding are used to indicate the first transmission queue corresponding to the corresponding dispatch order; the one-hot encoding corresponding to each to-be-dispatched instruction is determined according to the dispatch order corresponding to the one-hot encoding, and the first encoding matrix used as the basis for instruction dispatch is generated based on the one-hot encoding corresponding to each to-be-dispatched instruction; the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction is determined according to the matrix row number and the matrix column number corresponding to each valid bit in the first encoding matrix. The to-be-dispatched instruction can be preferentially allocated to the first transmission queue with smaller load through the bit operation of the one-hot encoding, which not only helps to improve the processing efficiency of the instruction, but also reduces the calculation amount and the chip area required in the instruction dispatch process, and improves the efficiency of the instruction dispatch process.

[0114] Optionally, in some embodiments, the step of determining the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction according to the matrix row number and the matrix column number corresponding to each valid bit in the first encoding matrix can specifically include:

[0115] In step 10331, each matrix row in the first encoding matrix is added to the previous all matrix rows to obtain the target matrix row corresponding to the corresponding matrix row, and each target matrix row constitutes a second encoding matrix.

[0116] In the embodiment of the present application, in order to further improve the instruction dispatch efficiency, each matrix row in the first encoding matrix can be added to the previous all matrix rows to obtain the target matrix row corresponding to the corresponding matrix row, and the second encoding matrix constituted by each target matrix row can be obtained, and the correspondence between the to-be-dispatched instruction and the queue entrance can be directly determined through different element values in the second encoding matrix. Wherein, the previous all matrix rows of the matrix row in the first encoding matrix include all matrix rows with a row number less than the matrix row.

[0117] It should be noted that if the matrix row is the first row, there is no previous matrix row, and the matrix row can be directly used as the target matrix row corresponding to the matrix row; or the matrix row can be added to 0 to obtain the target matrix row corresponding to the matrix row, and the embodiment of the present application is not limited in this regard.

[0118] For example, for the first encoding matrix shown in Table 3, the second row can be added to the first row to obtain the target matrix row (0, 1, 1, 0) corresponding to the second row, and the third row can be added to the first row and the second row to obtain the target matrix row (1, 1, 1, 0) corresponding to the third row. Thus, the target matrix row obtained after each matrix row performs the above operation can constitute the second encoding matrix shown in Table 5 as follows:

[0119]

[0120]

[0121] Table 5

[0122] Since the size of the second encoding matrix does not change, i.e., the number of matrix rows and the number of matrix columns do not change, the second encoding matrix can still inherit the correspondence between the matrix rows and the to-be-assigned instructions in the first encoding matrix, and the correspondence between the matrix columns and the first transmission queue.

[0123] In step 10332, the queue entry of the first transmission queue corresponding to each to-be-assigned instruction is determined according to the number of matrix rows, the number of matrix columns, and the value of the effective bit corresponding to each effective bit in the second encoding matrix. The effective bit represents the first element bit in each column of the second encoding matrix that matches the target value, and the target value has a corresponding relationship with the priority.

[0124] In the embodiment of the application, a plurality of target values having a corresponding relationship with the priority can be preset. For example, if the priority includes a first priority and a second priority, target values 1 and 2 can be preset, wherein the target value 1 and the target value 2 correspond to the first priority and the second priority, respectively. Target values 1, 2, 3, 4, 5, 6, 7, 8, etc. can also be preset, wherein the target values 1, 3, 5, and 7 correspond to the first priority, and the target values 2, 4, 6, and 8 correspond to the second priority. The embodiment of the application is not limited in this regard.

[0125] The effective bit can be the first element bit in each matrix column of the second encoding matrix that matches the target value. Specifically, the element values of each matrix column in the second encoding matrix can be traversed, and the first matrix element in each matrix column that matches the target value is taken as the effective bit. The first matrix element in the matrix column that matches the target value means that the first matrix element that matches the target value is found by traversing from the matrix element at the 0th row of the matrix column. It should be noted that if there are multiple target values, the corresponding effective bits in each matrix column can be matched for each target value, i.e., each matrix column can contain multiple effective bits that match different target values.

[0126] Further, the target value corresponding to the priority can also indicate that the target value corresponds to the queue entry of the corresponding priority. In the embodiment of the present application, the queue entry identifier can be directly used as the priority, that is, the queue entry can use different entry identifiers to distinguish the priority, and the target value can directly correspond to the corresponding queue entry identifier. For example, each first transmission queue can include a queue entry enq0 and a queue entry enq1, where the queue entry identifier enq0 can indicate that it is the first priority, and the queue entry identifier enq1 can indicate that it is the second priority. The target value 0 can be set to correspond to the queue entry identifier enq0, and the target value 1 can be set to correspond to the queue entry identifier enq1, thereby improving the efficiency of matching the queue entry according to the target value.

[0127] In the embodiment of the present application, the first transmission queue corresponding to each to-be-issued instruction can be determined according to the matrix row number and the matrix column number corresponding to each valid bit, and the queue entry corresponding to each to-be-issued instruction can be determined according to the valid bit value corresponding to each valid bit, thereby determining the queue entry of the first transmission queue corresponding to each to-be-issued instruction.

[0128] For example, if the target value includes 1 and 2, the six valid bits can be determined according to the second encoding matrix shown in Table 5, the non-valid bits in Table 5 are hidden, and only the valid bits are retained to obtain the following

[0129] Table 6:

[0130] IQ0 IQ1 IQ2 IQ3 Instruction 0 1 Instruction 1 1 Instruction 2 1 Instruction 3 1 Instruction 4 2 Instruction 5 2

[0131] Table 6

[0132] In the embodiment of the present application, the matrix row number and the matrix column number corresponding to each valid bit are used to indicate the first transmission queue corresponding to the to-be-issued instruction, and the valid bit value corresponding to each valid bit is used to indicate the queue entry corresponding to the to-be-issued instruction. If the target value 1 corresponds to the queue entry enq0 of the first priority, and the target value 2 corresponds to the queue entry enq1 of the second priority, then according to Table 6, instruction 0 can correspond to the queue entry enq0 of the first transmission queue IQ2, instruction 1 can correspond to the queue entry enq0 of the first transmission queue IQ1, instruction 2 can correspond to the queue entry enq0 of the first transmission queue IQ0, instruction 3 can correspond to the queue entry enq0 of the first transmission queue IQ3, instruction 4 can correspond to the queue entry enq1 of the first transmission queue IQ2, and instruction 5 can correspond to the queue entry enq1 of the first transmission queue IQ1.

[0133] Further, each queue entrance of each first transmission queue can also be configured with a corresponding priority selector, which is used to select a corresponding to-be-dispatched instruction from the to-be-dispatched instruction set and the second encoding matrix according to the effective bit, and transmit the selected to-be-dispatched instruction into the queue entrance corresponding to the priority selector. The above-mentioned priority selector can also select to-be-dispatched instructions in parallel, thereby improving the instruction dispatching efficiency. Wherein, the priority selectors of different priority queue entrances select effective bits from the matrix array corresponding to the first transmission queue to which the priority selector belongs in the second encoding matrix according to the corresponding target value, and determine the corresponding to-be-dispatched instruction according to the matrix row in which the selected effective bit is located.

[0134] For example, as shown in Table 6 above, the priority selector of the queue entrance enq0 of the first transmission queue IQ2 can select the effective bit matching the target value 1 (the matrix element of the first row in the matrix array corresponding to IQ2) from the second encoding matrix, so as to select instruction 0 through the effective bit and transmit instruction 0 into the first transmission queue IQ2 through the queue entrance enq0; the priority selector of the queue entrance enq1 of the first transmission queue IQ2 can select the effective bit matching the target value 2 (the matrix element of the fifth row in the matrix array corresponding to IQ2) from the second encoding matrix, so as to select instruction 4 through the effective bit and transmit instruction 4 into the first transmission queue IQ2 through the queue entrance enq1.

[0135] In the embodiment of the application, by performing bit-by-bit addition on each matrix row in the first encoding matrix and all the preceding matrix rows, a target matrix row corresponding to each matrix row is obtained, and each target matrix row constitutes the second encoding matrix; according to the number of matrix rows, the number of matrix arrays and the number of effective bits corresponding to each effective bit in the second encoding matrix, the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction is determined. The efficiency of the instruction dispatching process can be effectively improved.

[0136] Optionally, in some embodiments, the step of determining the one-hot encoding corresponding to each to-be-dispatched instruction according to the dispatching order corresponding to the one-hot encoding, and generating the first encoding matrix used as the basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-dispatched instruction, can specifically include:

[0137] In step S21, the instruction index corresponding to each to-be-dispatched instruction is determined based on the number of preceding instructions of each to-be-dispatched instruction.

[0138] In the embodiment of the present application, in order to ensure that the to-be-dispatched instructions can be dispatched in sequence, the instruction index corresponding to each to-be-dispatched instruction can be determined, so as to indicate the dispatching sequence of the corresponding to-be-dispatched instruction by the instruction index. Wherein, the number of the precedent instructions of a to-be-dispatched instruction can represent the number of the instructions whose execution sequence is in front of the to-be-dispatched instruction among all the to-be-dispatched instructions of the instruction type corresponding to the first emission queue; or can represent the number of the instructions whose execution sequence is in front of the to-be-dispatched instruction among all the to-be-dispatched instructions of all the instruction types.

[0139] Specifically, the number of the precedent instructions of each to-be-dispatched instruction can be directly taken as the instruction index corresponding to the corresponding to-be-dispatched instruction; or the number of the precedent instructions of each to-be-dispatched instruction can be added or subtracted by a fixed value (for example, 1) to obtain the instruction index corresponding to the corresponding to-be-dispatched instruction; or each to-be-dispatched instruction can be sorted according to the number of the precedent instructions of each to-be-dispatched instruction, and the sorting result can be taken as the instruction index of each to-be-dispatched instruction, which is not limited in the embodiment of the present application.

[0140] In step S22, the one-hot encoding corresponding to each to-be-dispatched instruction is determined based on the instruction index and the dispatching sequence.

[0141] In the embodiment of the present application, the one-hot encoding can correspond to the dispatching sequence, and the to-be-dispatched instruction can correspond to the instruction index. The correspondence between the to-be-dispatched instruction and the one-hot encoding can be established according to the instruction index and the dispatching sequence, so that the to-be-dispatched instruction with a higher instruction index can be dispatched earlier.

[0142] In the embodiment of the present application, each to-be-dispatched instruction can be traversed in ascending order of the instruction index, and the one-hot encoding corresponding to each to-be-dispatched instruction can be allocated in ascending order of the dispatching sequence. If the number of the to-be-dispatched instructions is greater than the number of the dispatching sequence, the one-hot encoding corresponding to the dispatching sequence can be allocated in multiple rounds. In each round of allocation, the one-hot encoding can be allocated to the corresponding to-be-dispatched instruction in descending order of the dispatching sequence.

[0143] For example, if there are 6 instructions A-F to be dispatched, the number of preceding instructions of the instruction A to be dispatched is 3, the number of preceding instructions of the instruction B to be dispatched is 2, the number of preceding instructions of the instruction C to be dispatched is 4, the number of preceding instructions of the instruction D to be dispatched is 1, the number of preceding instructions of the instruction E to be dispatched is 0, and the number of preceding instructions of the instruction F to be dispatched is 5, it can be determined that the instruction indexes corresponding to the instructions A-F to be dispatched are 3, 2, 4, 1, 0, and 5 respectively. If the one-hot encoding is arranged in ascending order of the dispatching order as [0010, 0100, 1000, 0001], the corresponding relationship between the instructions to be dispatched and the one-hot encodings can be obtained by the above-mentioned manner as follows: instruction E-0010, instruction D-0100, instruction B-1000, instruction A-0001, instruction C-0010, and instruction F-0100.

[0144] In step S23, the one-hot encodings corresponding to the instructions to be dispatched are arranged according to the instruction indexes to obtain the first encoding matrix.

[0145] In the embodiment of the present application, the one-hot encodings corresponding to the instructions to be dispatched can be arranged according to the instruction indexes to obtain the corresponding first encoding matrix. In the above-mentioned example, the first encoding matrix shown in Table 7 can be generated by the corresponding relationship between the instructions A-F and the one-hot encodings in the above-mentioned example and the instruction indexes of the instructions A-F.

[0146] IQ0 IQ1 IQ2 IQ3 Instruction E 0 0 1 0 Instruction D 0 1 0 0 Instruction B 1 0 0 0 Instruction A 0 0 0 1 Instruction C 0 0 1 0 Instruction F 0 1 0 0

[0147] Table 7

[0148] In the embodiment of the present application, the instruction indexes corresponding to the instructions to be dispatched are determined based on the number of preceding instructions of each instruction to be dispatched, the one-hot encodings corresponding to the instructions to be dispatched are determined based on the instruction indexes and the dispatching order, and the one-hot encodings corresponding to the instructions to be dispatched are arranged according to the instruction indexes to obtain the first encoding matrix. The one-hot encodings corresponding to the instructions to be dispatched which are executed in the earlier order can be assigned to the smaller dispatching order, the order of the instructions to be dispatched can be ensured to be executed, and the dispatching efficiency can be improved to a certain extent.

[0149] Optionally, in some embodiments, the step of determining the one-hot encodings corresponding to the instructions to be dispatched based on the instruction indexes and the dispatching order can specifically include:

[0150] S221, in the case that the number of instructions of the set of instructions to be dispatched is greater than the total number of the first transmission queue, the one-hot encoding sequence formed by the one-hot encodings is expanded according to the number of instructions of the set of instructions to be dispatched to obtain a target one-hot encoding sequence, wherein the number of encodings of the target one-hot encoding sequence is equal to the number of instructions, and the one-hot encodings in the one-hot encoding sequence are arranged based on the corresponding dispatching order.

[0151] In the embodiment of the present application, in order to further improve the matching efficiency of the to-be-issued instruction and the one-hot encoding, when the number of instructions in the to-be-issued instruction set is greater than the total number of the first transmission queue, the one-hot encoding sequence constituted by the one-hot encoding is expanded according to the number of instructions in the to-be-issued instruction set, so that the number of one-hot encodings contained in the expanded target one-hot encoding sequence is equal to the number of instructions. Thus, the matching process can be completed in one round of traversal process, which helps to improve the matching efficiency.

[0152] Specifically, the one-hot encodings can be arranged in the dispatching order corresponding to the one-hot encodings first to obtain a one-hot encoding sequence, and then the one-hot encodings corresponding to the dispatching order are sequentially copied from the first one-hot encoding in the one-hot encoding sequence and concatenated at the end of the one-hot encoding sequence until the target one-hot encoding sequence with the same number of one-hot encodings as the number of instructions is obtained.

[0153] For example, if the one-hot encoding sequence obtained by arranging the one-hot encodings in the dispatching order from small to large is [0010, 0100, 1000, 0001], and the number of instructions is 6, the one-hot encoding sequence can be expanded to obtain the target one-hot encoding sequence [0010, 0100, 1000, 0001, 0010, 0100].

[0154] S222, sequentially selecting the one-hot encoding corresponding to each to-be-issued instruction from the target one-hot encoding sequence based on the instruction index.

[0155] In the embodiment of the present application, each to-be-issued instruction can be sequentially traversed based on the instruction index, and the one-hot encodings are sequentially selected from the target one-hot encoding sequence for pairing, so that the one-hot encoding corresponding to each to-be-issued instruction can be determined through one traversal, which helps to improve the efficiency of determining the one-hot encoding corresponding to the to-be-issued instruction.

[0156] Optionally, in some embodiments, the step of determining the one-hot encoding corresponding to each to-be-issued instruction according to the dispatching order corresponding to the one-hot encoding, and generating the first encoding matrix used as the basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-issued instruction can specifically include:

[0157] S31, based on the queue index corresponding to the transmission queue other than the first transmission queue in the full-quantity transmission queue sequence, adding zero bits in the one-hot encoding corresponding to each to-be-issued instruction to obtain the target one-hot encoding corresponding to each to-be-issued instruction; wherein the number of encoding bits of the target one-hot encoding is equal to the number of queues of the full-quantity transmission queue sequence.

[0158] In the embodiment of the present application, in order to further improve the instruction dispatch efficiency, the zero bits can be added to the one-hot encoding corresponding to each to-be-dispatched instruction, and the one-hot encoding is expanded to the same number of bits as the number of queues in the full-quantity launch queue sequence, so as to obtain a target one-hot encoding, so that each bit in the target one-hot encoding can correspond to one launch queue in the full-quantity launch queue sequence, and the effective bit in the target one-hot encoding can still correspond to the first launch queue corresponding to the effective bit of the corresponding one-hot encoding in the full-quantity launch queue sequence. The full-quantity launch queue sequence represents a launch queue sequence formed by all launch queues in the processor, and the queue index of the first launch queue is used to indicate the position of the first launch queue in the full-quantity launch queue sequence.

[0159] For example, if the full-quantity launch queue sequence is [queue 1, queue 2, queue 3, queue 4, queue 5, queue 6], the first launch queue includes queue 1-4, and the one-hot encoding corresponding to one to-be-dispatched instruction is 0010, then it can be determined that the launch queues in the full-quantity launch queue sequence except the first launch queue are queue 5 and queue 6, and the corresponding queue indexes are 5 and 6, then the zero bits can be added to the 5th bit and the 6th bit of the one-hot encoding to obtain the corresponding target one-hot encoding 001000.

[0160] In step S32, the target one-hot encoding corresponding to each to-be-dispatched instruction is determined according to the dispatch order corresponding to the target one-hot encoding, and the first encoding matrix used as the basis for instruction dispatch is generated based on the target one-hot encoding corresponding to each to-be-dispatched instruction, so as to determine the launch queue corresponding to each to-be-dispatched instruction from the full-quantity launch queue sequence through the matrix row number of the first encoding matrix.

[0161] In the example of the present application, the first encoding matrix or the second encoding matrix in each step can be generated based on the target one-hot encoding, and in this case, the corresponding first launch queue can be directly determined from the full-quantity launch queue sequence based on the matrix row number corresponding to the effective bit in the first encoding matrix or the second encoding matrix, and the corresponding relationship with the to-be-dispatched instruction corresponding to the matrix row number where the effective bit is located is determined.

[0162] In the embodiment of the present application, based on the queue indexes corresponding to the transmission queues except the first transmission queue in the full transmission queue sequence, zero bits can be added in the one-hot encoding corresponding to each to-be-dispatched instruction to obtain the target one-hot encoding corresponding to each to-be-dispatched instruction, and the target one-hot encoding corresponding to each to-be-dispatched instruction is determined according to the dispatch order corresponding to the target one-hot encoding, and the first encoding matrix used as the basis for instruction dispatch is generated based on the target one-hot encoding corresponding to each to-be-dispatched instruction, so as to determine the transmission queue corresponding to each dispatched instruction from the full transmission queue sequence through the matrix row number of the first encoding matrix. Since the first transmission queue belongs to part of the transmission queues in the full transmission queue sequence, the corresponding first transmission queue can be directly located in the full transmission queue sequence through the matrix row number of the effective bits in the first encoding matrix or the second encoding matrix in the subsequent process by adding zero bits to the one-hot encoding, which can effectively improve the efficiency of locating the first transmission queue and further improve the dispatch efficiency.

[0163] Optionally, in some embodiments, the following steps can also be included:

[0164] In step S41, in the case where the queue state of the first transmission queue is the ready state, the target to-be-dispatched instruction is selected from the to-be-dispatched instructions corresponding to the first transmission queue according to the instruction order of each to-be-dispatched instruction and dispatched to the first transmission queue, and the to-be-dispatched instructions after the target to-be-dispatched instruction are blocked to be dispatched in the subsequent clock cycle; wherein the number of instructions of the target dispatched instruction is the same as the number of queue entries of the first transmission queue.

[0165] In the embodiment of the present application, in order to further improve the stability of the sequential execution of instructions, the queue state of the first transmission queue can be obtained before the actual dispatch of the to-be-dispatched instruction. The queue state can at least include the ready state and the full state. The ready state means that all queue entries of the transmission queue can receive new instructions, and the full state means that all queue entries of the transmission queue are occupied and cannot receive new instructions.

[0166] In the case where the queue state of the first transmission queue is the ready state, the target to-be-dispatched instruction can be selected from the to-be-dispatched instructions corresponding to the first transmission queue according to the instruction order of each to-be-dispatched instruction, and the number of instructions of the target to-be-dispatched instruction can be the same as the number of queue entries of the first transmission queue, and then the remaining to-be-dispatched instructions corresponding to the first transmission queue are blocked in the current clock cycle.

[0167] Specifically, in the to-be-dispatched instructions corresponding to the first transmission queue determined by the first encoding matrix or the second encoding matrix, the to-be-dispatched instructions corresponding to the effective bits of the front queue entry quantity can be selected from the matrix array corresponding to the first transmission queue, and dispatched to the first transmission queue, and the to-be-dispatched instructions corresponding to the remaining effective bits are blocked.

[0168] Specifically, the above blocking operation can be realized by the priority selector configured in the queue entry. The next to-be-dispatched instruction of the target to-be-dispatched instruction can be selected by the priority selector, so that the next to-be-dispatched instruction cannot enter the corresponding queue entry, so as to achieve the purpose of blocking the to-be-dispatched instruction and the subsequent to-be-dispatched instruction. In addition, the to-be-dispatched instructions other than the target to-be-dispatched instruction can also be blocked in other ways, which is not limited in the embodiment of the application.

[0169] Specifically, in the instruction dispatching based on the second encoding matrix shown in Table 5, if the matrix array corresponding to the first transmission queue IQ2 in the second encoding matrix further includes effective bits 3 and 4, the to-be-dispatched instructions corresponding to the effective bits 1 and 2 in the matrix array corresponding to the first transmission queue IQ2 can be dispatched by the first transmission queue IQ2 in the case that the first transmission queue IQ2 is in an idle state, and the priority selector corresponding to the first transmission queue selects the to-be-dispatched instruction corresponding to the effective bit 3 to block the to-be-dispatched instruction corresponding to the effective bit 3 and the subsequent to-be-dispatched instruction corresponding to the effective bit 4.

[0170] In step S42, in the case that the queue state of the first transmission queue is in a full state, each to-be-dispatched instruction and the subsequent to-be-dispatched instruction are blocked, so as to dispatch the blocked to-be-dispatched instruction in the subsequent clock cycle.

[0171] In the embodiment of the application, if the queue state of the first transmission queue is in a full state, it indicates that the first transmission queue cannot receive to-be-dispatched instructions, and all to-be-dispatched instructions and the subsequent to-be-dispatched instructions can be directly blocked.

[0172] Specifically, in the instruction dispatching based on the second encoding matrix shown in Table 5, the to-be-dispatched instruction corresponding to the effective bit 1 can be selected by the priority selector corresponding to the first transmission queue IQ2 in the case that the first transmission queue IQ2 is in a full state, so as to block the to-be-dispatched instruction corresponding to the effective bit 1, the to-be-dispatched instruction corresponding to the effective bit 2, and all the subsequent to-be-dispatched instructions.

[0173] In the embodiment of the present application, the blocked to-be-issued instruction in the current clock cycle can be regarded as a to-be-issued instruction in the subsequent clock cycle, and is issued together with the to-be-issued instruction generated in the next cycle. The specific issuing process is the same as the instruction issuing mode of the embodiment of the present application, which will not be described here. For example, in the case of using the second encoding matrix to issue instructions, the second encoding matrix can be updated based on the blocked to-be-issued instruction in the current clock cycle and the to-be-issued instruction generated in the subsequent clock cycle, and the blocked to-be-issued instruction in the current cycle can be continuously issued in the subsequent clock cycle based on the updated second encoding matrix.

[0174] In the embodiment of the present application, in the case that the queue state of the first transmission queue is the ready state, a target to-be-issued instruction is selected from the to-be-issued instructions corresponding to the first transmission queue according to the instruction order of each to-be-issued instruction, and the target to-be-issued instruction is issued to the first transmission queue, and the to-be-issued instructions after the target to-be-issued instruction are blocked. In the case that the queue state of the first transmission queue is the full state, each to-be-issued instruction and the subsequent to-be-issued instruction are blocked, and the blocked to-be-issued instruction is issued in the subsequent clock cycle. The stability of the to-be-issued instruction in order can be further improved.

[0175] It should be noted that, for the method embodiment, in order to simply describe, all are expressed as a series of action combinations, but those skilled in the art should know that the embodiment of the present application is not limited by the action order described, because according to the embodiment of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily required by the embodiment of the present application.

[0176] Device embodiment

[0177] Reference Figure 4 , a structural block diagram of an instruction issuing device of the present application is shown, which specifically can include:

[0178] The acquisition module 201 is configured to acquire the number of target instructions of the same instruction type in each first transmission queue; wherein the first transmission queue is configured to transmit instructions to the functional unit corresponding to the instruction type.

[0179] The load order module 202 is configured to determine the load order of each first transmission queue for the instruction type based on the number of target instructions.

[0180] The issuing module 203 is configured to determine the queue entrance of the first transmission queue corresponding to each to-be-issued instruction based on the priority between the load order and the queue entrance of the first transmission queue, so as to issue each to-be-issued instruction through the corresponding queue entrance; wherein the to-be-issued instruction corresponds to the instruction type.

[0181] Optionally, the dispatching module comprises:

[0182] a one-hot encoding submodule configured to determine one-hot encoding corresponding to each dispatching order based on the load sequence; wherein a valid bit of the one-hot encoding is configured to indicate a first transmission queue corresponding to the corresponding dispatching order;

[0183] an encoding matrix submodule configured to determine one-hot encoding corresponding to each to-be-dispatched instruction according to the dispatching order corresponding to the one-hot encoding, and generate a first encoding matrix used as a basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-dispatched instruction;

[0184] a queue entry submodule configured to determine a queue entry of the first transmission queue corresponding to each to-be-dispatched instruction according to a matrix row number and a matrix column number corresponding to each valid bit in the first encoding matrix.

[0185] Optionally, the queue entry submodule comprises:

[0186] an encoding matrix unit configured to add each matrix row in the first encoding matrix to all previous matrix rows to obtain a target matrix row corresponding to the corresponding matrix row, and each target matrix row constitutes a second encoding matrix;

[0187] a queue entry determination unit configured to determine a queue entry of the first transmission queue corresponding to each to-be-dispatched instruction according to a matrix row number, a matrix column number and a valid bit number corresponding to each valid bit in the second encoding matrix; wherein the valid bit represents a first element bit matching a target value in each column in the second encoding matrix, and the target value has a corresponding relationship with the priority.

[0188] Optionally, the encoding matrix submodule comprises:

[0189] an instruction index unit configured to determine an instruction index corresponding to each to-be-dispatched instruction based on a number of previous instructions of each to-be-dispatched instruction;

[0190] a one-hot encoding corresponding relationship unit configured to determine one-hot encoding corresponding to each to-be-dispatched instruction based on the instruction index and the dispatching order;

[0191] a first encoding matrix generation unit configured to arrange the one-hot encoding corresponding to each to-be-dispatched instruction according to the instruction index to obtain the first encoding matrix.

[0192] Optionally, the one-hot encoding corresponding relationship unit comprises:

[0193] a target one-hot encoding sequence subunit configured to, in a case where the number of instructions in the set of instructions to be dispatched is greater than the total number of the first transmission queues, expand the one-hot encoding sequence constituted by the one-hot encodings according to the number of instructions in the set of instructions to be dispatched to obtain a target one-hot encoding sequence; wherein the number of encodings in the target one-hot encoding sequence is equal to the number of instructions, and the one-hot encodings in the one-hot encoding sequence are arranged based on the corresponding dispatching order;

[0194] a one-hot encoding selection subunit configured to sequentially select the one-hot encoding corresponding to each instruction to be dispatched from the target one-hot encoding sequence based on the instruction index.

[0195] Optionally, the encoding matrix sub-module comprises:

[0196] a target one-hot encoding unit configured to add zero bits to the one-hot encoding corresponding to each instruction to be dispatched based on the queue index corresponding to the transmission queue other than each first transmission queue in the full-quantity transmission queue sequence to obtain the target one-hot encoding corresponding to each instruction to be dispatched; wherein the number of encoding bits of the target one-hot encoding is equal to the number of queues in the full-quantity transmission queue sequence;

[0197] a second encoding matrix generation unit configured to determine the target one-hot encoding corresponding to each instruction to be dispatched according to the dispatching order corresponding to the target one-hot encoding, generate a first encoding matrix used as a basis for instruction dispatching based on the target one-hot encoding corresponding to each instruction to be dispatched, and determine the transmission queue corresponding to each dispatched instruction from the full-quantity transmission queue sequence through the number of matrix rows of the first encoding matrix.

[0198] Optionally, the load order module comprises:

[0199] a comparison result sub-module configured to compare the target instruction number of each first transmission queue with each other to obtain the comparison result corresponding to each first transmission queue;

[0200] a queue number sub-module configured to determine the number of queues of the first transmission queue based on the comparison result in which the target instruction number is less than the first transmission queue;

[0201] a load order determination sub-module configured to determine the load order of each first transmission queue for the instruction type according to the number of queues corresponding to each first transmission queue.

[0202] Optionally, the apparatus further comprises:

[0203] The first blocking module is configured to, when the queue state of the first transmission queue is the ready state, select a target to-be-issued instruction from the to-be-issued instructions corresponding to the first transmission queue according to the instruction sequence of the to-be-issued instructions, and block the to-be-issued instructions after the target to-be-issued instruction, so as to issue the blocked to-be-issued instructions in a subsequent clock cycle; wherein the number of the target to-be-issued instructions is the same as the number of the queue entries of the first transmission queue.

[0204] The second blocking module is configured to, when the queue state of the first transmission queue is the full state, block the to-be-issued instructions and the subsequent to-be-issued instructions, so as to issue the blocked to-be-issued instructions in a subsequent clock cycle.

[0205] In summary, in the instruction issuing device provided by the embodiment of the present application, the number of target instructions of the same instruction type in each first transmission queue is obtained; wherein the first transmission queue is configured to transmit instructions to a functional unit corresponding to the instruction type; the load sequence of each first transmission queue for the instruction type is determined based on the number of target instructions; and the queue entry of the first transmission queue corresponding to each to-be-issued instruction is determined based on the priority between the load sequence and the queue entry of the first transmission queue, so as to issue each to-be-issued instruction through the corresponding queue entry; wherein the to-be-issued instruction corresponds to the instruction type. In the embodiment of the present application, the load sequence of each first transmission queue for the same instruction type is determined, and the to-be-issued instructions of the corresponding instruction type are assigned to the queue entries of each first transmission queue according to the load sequence of the first transmission queue and the priority of the queue entry. In this way, the to-be-issued instructions of each instruction type can be evenly assigned to the transmission queue of the corresponding instruction type, and the transmission queue can also evenly assign the to-be-issued instructions through different queue entries, which helps to improve the balance of instruction issuing, so as to improve the efficiency of the processor in processing instructions to a certain extent.

[0206] In the embodiment of the present application, the transmission queue cache is avoided to be set in the processor for instruction issuing, which can save the circuit area of the processor for setting the transmission queue cache, and can also reduce the number of processor pipeline stages, which helps to further improve the instruction processing performance of the processor.

[0207] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts are described in the part of the method embodiment.

[0208] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0209] As to the processor in the above-mentioned embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and thus will not be described in detail here.

[0210] With reference to Figure 5 is a structural block diagram of an electronic device for instruction dispatch provided by an embodiment of the present application. As shown in Figure 5 , the electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions, and the executable instructions make the processor execute the instruction dispatch method of the foregoing embodiments.

[0211] The processor can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable device, transistor logic device, hardware component or any combination thereof. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0212] The communication bus can include a channel for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect, peripheral component interconnect) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 only one line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0213] The memory can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), magnetic tape, a floppy disk, an optical data storage device, and the like.

[0214] The embodiment of the present application also provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), the processor can execute the instruction dispatch method shown in the embodiment of the present application. Figure 1 The instruction dispatch method shown in the embodiment of the present application.

[0215] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between each embodiment can be referred to each other.

[0216] Those skilled in the art should understand that the embodiments of the embodiment of the present application can be provided as a method, device or computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0217] The embodiments of the present application are described with reference to flowcharts and / or block diagrams according to the method, terminal device (system) and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of the flows and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the computer or other programmable data processing terminal device produce a machine that implements the functions specified in the flowchart and / or block diagram. Figure One The device that implements the functions specified in one flow or multiple flows and / or blocks Figure One The device that implements the functions specified in one flow or multiple flows and / or blocks

[0218] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a predetennined manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart or flowsheets Figure One of the flowchart or flowsheets and / or blocks Figure One of the flowchart or flowsheets and / or blocks

[0219] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the function specified in the flowchart or flowsheets Figure One of the flowchart or flowsheets and / or blocks Figure One Figure One of the flowchart or flowsheets and / or blocks

[0220] While preferred embodiments of the application have been described, modifications and alterations thereto can occur to those skilled in the art upon reading the preceding description. It is intended to include all such modifications and alterations insofar as they come within the scope of the embodiments of the application. Accordingly, the following claims are intended to cover all such modifications and alterations.

[0221] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to nomenclature different components to distinguish one component from another component and do not necessarily imply or require any such actual relationship or order. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0222] The above provides a kind of instruction dispatching method, device, electronic equipment and readable storage medium provided by the present application, detailed introduction is carried out, the principle and implementation mode of the present application are described in this paper with specific examples, the above example is only for helping understanding the method of the present application and its core idea;For the person skilled in the art, according to the idea of the present application, there will be changes in specific implementation mode and application range, and the above description should not be understood as the limitation of the present application.

Claims

1. An instruction dispatch method, characterized by, The method comprises: acquiring a target instruction quantity of a same instruction type in each first transmission queue, wherein the first transmission queue is used for transmitting instructions to a functional unit corresponding to the instruction type; determining a load sequence of each first transmission queue for the instruction type based on the target instruction quantity; determining a queue entrance of a first transmission queue corresponding to each to-be-dispatched instruction based on a priority between the load sequence and the queue entrance of the first transmission queue, so as to dispatch each to-be-dispatched instruction through the corresponding queue entrance; wherein the to-be-dispatched instruction corresponds to the instruction type; the determining of the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction based on the priority between the load sequence and the queue entrance of the first transmission queue comprises: determining a one-hot encoding corresponding to each dispatching sequence based on the load sequence; wherein an effective bit of the one-hot encoding is used to indicate the first transmission queue corresponding to the corresponding dispatching sequence; determining a one-hot encoding corresponding to each to-be-dispatched instruction according to a dispatching sequence corresponding to the one-hot encoding, and generating a first encoding matrix used as a basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-dispatched instruction; determining the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction according to a matrix row number and a matrix column number corresponding to each effective bit in the first encoding matrix.

2. The method of claim 1, wherein, the determining of the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction according to the matrix row number and the matrix column number corresponding to each effective bit in the first encoding matrix comprises: bit-by-bit adding each matrix row in the first encoding matrix to all previous matrix rows to obtain a target matrix row corresponding to the corresponding matrix row, and each target matrix row constitutes a second encoding matrix; determining the queue entrance of the first transmission queue corresponding to each to-be-dispatched instruction according to a matrix row number, a matrix column number and an effective bit value corresponding to each effective bit in the second encoding matrix; wherein the effective bit represents a first element bit matching a target value in each column in the second encoding matrix, and the target value has a corresponding relationship with the priority.

3. The method of claim 1, wherein, the determining of the one-hot encoding corresponding to each to-be-dispatched instruction according to the dispatching sequence corresponding to the one-hot encoding, and the generating of the first encoding matrix used as the basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-dispatched instruction comprises: determining an instruction index corresponding to each to-be-dispatched instruction based on a previous instruction quantity of each to-be-dispatched instruction; determining the one-hot encoding corresponding to each to-be-dispatched instruction based on the instruction index and the dispatching sequence; arranging the one-hot encoding corresponding to each to-be-dispatched instruction according to the instruction index to obtain the first encoding matrix.

4. The method of claim 3, wherein, the determining of the one-hot encoding corresponding to each to-be-dispatched instruction based on the instruction index and the dispatching sequence comprises: in a case where an instruction quantity of the to-be-dispatched instruction set is greater than a total quantity of the first transmission queues, expanding a one-hot encoding sequence constituted by the one-hot encoding to obtain a target one-hot encoding sequence according to the instruction quantity of the to-be-dispatched instruction set; wherein a code quantity of the target one-hot encoding sequence is equal to the instruction quantity, and the one-hot encoding in the one-hot encoding sequence is arranged based on the corresponding dispatching sequence. The target one-hot encoding corresponding to each to-be-dispatched instruction is determined according to the dispatch order corresponding to the target one-hot encoding, and a first encoding matrix used as a basis for instruction dispatch is generated based on the target one-hot encoding corresponding to each to-be-dispatched instruction, so as to determine the transmission queue corresponding to each dispatched instruction from the full-transmission queue sequence through the matrix number of the first encoding matrix.

5. The method of claim 1, wherein, The target one-hot encoding corresponding to each to-be-dispatched instruction is determined according to the dispatch order corresponding to the target one-hot encoding, and a first encoding matrix used as a basis for instruction dispatch is generated based on the target one-hot encoding corresponding to each to-be-dispatched instruction, so as to determine the transmission queue corresponding to each dispatched instruction from the full-transmission queue sequence through the matrix number of the first encoding matrix. The method further includes: In a case where the queue state of the first transmission queue is a ready state, a target to-be-dispatched instruction is selected from the to-be-dispatched instructions corresponding to the first transmission queue according to the instruction order of each to-be-dispatched instruction, and the to-be-dispatched instructions after the target to-be-dispatched instruction are blocked, so that the blocked to-be-dispatched instructions are dispatched in a subsequent clock cycle; wherein the instruction number of the target to-be-dispatched instruction is the same as the queue entry number of the first transmission queue.

6. The method of claim 1, wherein, In a case where the queue state of the first transmission queue is a full state, each to-be-dispatched instruction and the subsequent to-be-dispatched instructions are blocked, so that the blocked to-be-dispatched instructions are dispatched in a subsequent clock cycle. The apparatus includes: The obtaining module is configured to obtain the target instruction number of the same instruction type in each first transmission queue; wherein the first transmission queue is configured to transmit instructions to a functional unit corresponding to the instruction type. The load sequence module is configured to determine the load sequence of each first transmission queue for the instruction type based on the target instruction number.

7. The method of claim 1, wherein, The dispatch module is configured to determine the queue entry of the first transmission queue corresponding to each to-be-dispatched instruction based on the priority between the load sequence and the queue entry of the first transmission queue, so as to dispatch each to-be-dispatched instruction through the corresponding queue entry; wherein the to-be-dispatched instruction corresponds to the instruction type. The dispatch module includes: The one-hot encoding submodule is configured to determine the one-hot encoding corresponding to each dispatch order based on the load sequence; wherein the valid bit of the one-hot encoding is used to indicate the first transmission queue corresponding to the corresponding dispatch order.

8. An instruction dispatch apparatus, characterized by, ​ ​ ​ ​ ​ ​ The encoding matrix submodule is configured to determine a one-hot encoding corresponding to each to-be-issued instruction according to a corresponding dispatch order of the one-hot encoding, and generate a first encoding matrix used as a basis for instruction dispatching based on the one-hot encoding corresponding to each to-be-issued instruction. The queue entry submodule is configured to determine a queue entry of a first transmission queue corresponding to each to-be-issued instruction according to a matrix row number and a matrix column number corresponding to each valid bit in the first encoding matrix.

9. An electronic device, comprising: The electronic device includes a processor, a memory, a communication interface, and a communication bus, the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction dispatching method in any one of claims 1 to 7.

10. A readable storage medium, characterized by, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor can execute the instruction dispatching method in any one of claims 1 to 7.

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