Semiconductor system for reducing operation time and operation method thereof

Abstract

A semiconductor system includes: a memory for storing data; a first master intellectual property (IP) block configured to generate a first wake-up signal; a first bus block configured to generate a second wake-up signal when a wake-up operation is performed in response to the first wake-up signal; a second bus block configured to generate a third wake-up signal when a wake-up operation is performed in response to the second wake-up signal; and a third bus block configured to perform data communication with the memory and perform a wake-up operation in response to a third wake-up signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0153097 filed in the Korean Intellectual Property Office on November 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor system and an operating method thereof, and more particularly, to a semiconductor system and an operating method thereof for reducing an operating time. Background Art

[0004] A semiconductor system may include one or more blocks, each of which may include one or more intellectual property (IP) blocks, a clock management unit (CMU), and a power management unit (PMU). To reduce idle power consumption of a block, the system may perform a power-off operation of the IP block, which typically involves stopping the delivery of a clock signal from the CMU to the IP block when the IP block is not in use.

[0005] When a power-off operation is performed and a power-on operation is performed for a specific IP block that is currently in a power-off state, if other blocks are interconnected via a hierarchical bus, the power-on operation needs to be performed sequentially across the related blocks. Therefore, the time required to perform the power-on operation may increase with the number of related blocks, thereby potentially impairing the performance of the semiconductor system. Therefore, a technology that can reduce the time required to perform the power-on operation is needed. Summary of the invention

[0006] The inventive concept provides a semiconductor system for reducing a power-on operation time and an operating method thereof.

[0007] According to an embodiment of the present invention, there is provided a semiconductor system, including: a memory for storing data; a first master intellectual property (IP) block configured to generate a first wake-up signal; a first bus block configured to generate a second wake-up signal when a wake-up operation is performed in response to the first wake-up signal; a second bus block configured to generate a third wake-up signal when a wake-up operation is performed in response to the second wake-up signal; and a third bus block configured to perform data communication with the memory and to perform a wake-up operation in response to the third wake-up signal.

[0008] According to an embodiment conceived in the present invention, a semiconductor system is provided, including: a memory for storing data; a first level bus block configured to perform data communication with the memory; a second level bus block configured to perform data communication with the first level bus block; and a third level bus block configured to perform data communication with the second level bus block, wherein when a wake-up operation is performed on the third level bus block, the first level bus block and the second level bus block are configured to perform the wake-up operation.

[0009] According to an embodiment conceived in the present invention, there is provided an operating method of a semiconductor system including a bus block and a plurality of intellectual property (IP) blocks, the operating method comprising: when performing a wake-up operation on a first bus block, sending a first wake-up signal to a second bus block among the bus blocks that performs data communication with the first bus block; when performing a wake-up operation on the second bus block in response to the first wake-up signal, sending a second wake-up signal to a third bus block that performs data communication with the second bus block; and performing a wake-up operation on the third bus block in response to the second wake-up signal, wherein the second bus block is a bus block of a higher level than the first bus block, and the third bus block is a bus block of a higher level than the second bus block. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing a semiconductor system according to an embodiment;

[0012] Figure 2 is a flowchart illustrating an operating method of a semiconductor system according to an embodiment;

[0013] Figure 3 is a graph illustrating an operating method of a semiconductor system according to an embodiment;

[0014] Figure 4 is a block diagram showing a semiconductor system according to an embodiment;

[0015] Figure 5 is a block diagram showing a semiconductor system according to an embodiment;

[0016] Figure 6 is a graph illustrating an operating method of a semiconductor system according to an embodiment;

[0017] Figure 7 is a block diagram showing a semiconductor system according to an embodiment;

[0018] Figure 8 is a block diagram showing an address decoder of a semiconductor system according to an embodiment;

[0019] Fig. 9 is a graph illustrating an operating method of a semiconductor system according to an embodiment;

[0020] Fig.10 is a block diagram showing a semiconductor system according to an embodiment;

[0021] Fig.11 is a block diagram showing an electronic device according to an embodiment; and

[0022] Fig.12 is a block diagram illustrating an electronic device according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram showing a semiconductor system 1 a according to an embodiment.

[0025] refer to Figure 1 , the semiconductor system 1a may be implemented as a personal computer (PC) or a mobile device. For example, the mobile device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, or an e-book, but is not limited thereto.

[0026] The semiconductor system 1a may refer to a semiconductor device, and the semiconductor system 1a may be implemented as an integrated circuit (IC), a mainboard, a system on chip (SoC), a microprocessor, an application processor (AP), a mobile AP, a chipset, or a collection of semiconductor chips, but is not limited thereto.

[0027] The semiconductor system 1a may include a first master intellectual property (IP) block 110a, a second master IP block 120a, and a third master IP block 130a, a first bus block 210a, a second bus block 220a, and a third bus block 230a, and a memory 300a. Although the semiconductor system 1a is shown to include the first to third master IP blocks 110a, 120a, and 130a and the first to third bus blocks 210a, 220a, and 230a, the semiconductor system 1a may include more master IP blocks and bus blocks.

[0028] The first to third main IP blocks 110a, 120a, and 130a are functional blocks that perform specific functions, and each may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), a communication processor (CP), a digital signal processor (DSP), a video module (e.g., a camera interface, a joint photographic experts group (JPEG) processor, a video processor or a mixer, etc.), a 3D graphics core, an audio system or a driver. At least one of the first to third main IP blocks 110a, 120a, and 130a may include at least one core that executes instructions, but the inventive concept is not limited thereto.

[0029] The first bus block to the third bus block 210a, 220a and 230a can have different levels (or hierarchies). For example, the first bus block 210a can be a third-level bus block, the second bus block 220a can be a second-level bus block, and the third bus block 230a can be a first-level bus block. The lower the level, the higher the level that can be referenced, and the higher the bus block level, the higher the accessibility to the memory 300a. In other words, this structure means that the low-level block can reference the high-level block, and the higher the bus block level is positioned, the more access it has to the memory.

[0030] The first power management unit (PMU) 211a, the second PMU 221a, and the third PMU 231a may control or supply a power supply voltage supplied to a specific block (eg, the first to third bus blocks 210a, 220a, and 230a).

[0031] The first clock management unit (CMU) 212a, the second CMU 222a, and the third CMU 232a may control or supply a clock signal supplied to a specific block (e.g., the first bus block to the third bus block 210a, 220a, and 230a), and transmit and receive control signals to and from the first PMU to the third PMU 211a, 221a, and 231a to perform a clock gating operation on each specific block (e.g., the first bus block to the third bus block 210a, 220a, and 230a). The clock gating operation may be an operation of reducing power consumption (e.g., switching power consumption) of a specific block by not providing a clock signal to the block when the operation of the block is not required. In other words, the clock gating operation involves reducing power consumption of a specific block by withholding a clock signal from the block when its operation is not required, such as switching power management.

[0032] The first bus 213a, the second bus 223a, and the third bus 233a can perform data communication between blocks including the first bus to the third bus 213a, 223a, and 233a, respectively, and other blocks. For example, the first bus 213a can perform data communication with the first master IP block 110a, the second bus 223a can perform data communication with the second master IP block 120a, and the third bus 233a can perform data communication with the third master IP block 130a. The first bus to the third bus 213a, 223a, and 233a can each be implemented as an advanced microcontroller bus architecture (AMBA), an advanced high-performance bus (AHB), an advanced peripheral bus (APB), an advanced extensible interface (AXI), an advanced system bus (ASB), an AXI consistency extension (ACE) or a combination thereof, but is not limited thereto.

[0033] The first bus block 210a may include a first PMU 211a, a first CMU 212a, and a first bus 213a. The second bus block 220a may include a second PMU 221a, a second CMU 222a, and a second bus 223a. The third bus block 230a may include a third PMU 231a, a third CMU 232a, and a third bus 233a.

[0034] The first PMU 211a may receive a wake-up signal from the first main IP block 110a, and send the wake-up signal to the second PMU 221a when performing a wake-up operation on the first bus block 210a in response to the received wake-up signal. The wake-up operation refers to a power-on operation that starts a specific block that is currently in a power-off state. The power-off state refers to a state of a specific block to which a power gating operation has been applied to block its power supply voltage. The power-on operation involves applying a blocked power supply voltage to a block in a power-off state. The power-on state refers to a state of a specific block after a power-on operation has been performed on the specific block.

[0035] In some embodiments, the first master IP block 110a may generate a first wake-up signal to access the memory 300a, and the first PMU 211a may perform a wake-up operation on the first bus block 210a in response to the first wake-up signal. The first PMU 211a may send a second wake-up signal to the second PMU 221a when performing the wake-up operation on the first bus block 210a.

[0036] The second PMU 221a may receive a wake-up signal from the first PMU 211a and transmit the wake-up signal to the third PMU 231a when performing a wake-up operation on the second bus block 220a in response to the received wake-up signal. In some embodiments, the second PMU 221a may perform a wake-up operation on the second bus block 220a in response to the second wake-up signal. The second PMU 221a may transmit a third wake-up signal to the third PMU 231a when performing a wake-up operation on the second bus block 220a.

[0037] The third PMU 231a may receive a wake-up signal from the second PMU 221a and perform a wake-up operation on the third bus block 230a in response to the received wake-up signal. In some embodiments, the third PMU 231a may perform a wake-up operation on the third bus block 230a in response to the third wake-up signal.

[0038] In some embodiments, the first PMU 211a may further include a hierarchical register that masks a wake-up signal sent to the second PMU 221a, and the second PMU 221a may further include a hierarchical register that masks a wake-up signal sent to the third PMU 231a. Figures 4 to 6 Embodiments related to hierarchical registers are described.

[0039] The third level bus block or the second level bus block may also include a hierarchical register that masks a wake-up signal sent to a higher level bus block. Figures 4 to 6 Embodiments related to hierarchical registers are described.

[0040] The memory 300a is a storage device for storing data and can be electrically connected to the third bus block 230a. In this specification, the memory 300a is described as a dynamic random access memory (DRAM), but is not limited thereto. For example, the memory 300a may include a volatile memory such as a static RAM (SRAM) or a non-volatile memory such as a phase change RAM (PRAM), a resistive RAM (ReRAM), and a magnetic RAM (MRAM) flash memory.

[0041] In a comparative example, when a master IP block that performs data communication with a low-level bus block accesses a memory that performs data communication with a high-level bus block, the master IP block may perform a wake-up operation on the blocks sequentially from the low-level bus block to the high-level bus block. For example, after completing the wake-up operation on the third-level bus block, the master IP block may send a wake-up signal to the second-level bus block, and after completing the wake-up operation on the second-level bus block in response to the wake-up signal received by the second-level bus block, send the wake-up signal to the first-level bus block. The wake-up operation time may increase in proportion to the number of blocks from the low-level bus block to the high-level bus block. In other words, the time required for the wake-up operation may increase in proportion to the number of blocks from the low-level bus block to the high-level bus block. For example, assuming that the number of blocks from the low-level bus block to the high-level bus block is 3 and the wake-up operation time of one bus block is t, the wake-up operation time may be 3*t.

[0042] On the other hand, according to the semiconductor system 1a conceived of the present invention, when the first master IP block 110a accesses the memory 300a, the first master IP block 110a can send a wake-up signal to the second bus block 220a when performing a wake-up operation on the first bus block 210a, and send a wake-up signal to the third bus block 230a when performing a wake-up operation on the second bus block 220a. Therefore, the wake-up operation time of the first bus block 210a, the second bus block 220a, and the third bus block 230a can be less than 3*t. Therefore, the semiconductor system 1a conceived of the present invention can perform a power-on operation on each of the multiple blocks together, and reduce the time required to perform the power-on operation, thereby enhancing the performance of the semiconductor system 1a. For example, the semiconductor system 1a is capable of performing a power-on operation across multiple blocks at the same time.

[0043] Figure 2 1 is a flow chart showing an operating method 10 of a semiconductor system 1a according to an embodiment. Figure 2 As shown, the operating method 10 of the semiconductor system 1 a may include a plurality of operations S210 to S230 .

[0044] refer to Figure 1 and Figure 2 In operation S210, a wake-up operation on the third-level bus block may be performed and a first wake-up signal may be sent. In some embodiments, the first bus block 210a may be a third-level bus block, the second bus block 220a may be a second-level bus block, and the third bus block 230a may be a first-level bus block. The first bus block 210a may send a first wake-up signal to the second bus block 220a when performing a wake-up operation on the first bus block 210a.

[0045] In operation S220, a wake-up operation on the second level bus block may be performed and a second wake-up signal may be transmitted. In some embodiments, the second bus block 220a may transmit the second wake-up signal to the third bus block 230a when a wake-up operation is performed on the second bus block 220a in response to the first wake-up signal.

[0046] In operation S230, a wake-up operation may be performed on the first level bus block. In some embodiments, the third bus block 230a may perform a wake-up operation on the third bus block 230a in response to the second wake-up signal.

[0047] In some embodiments, the low-level bus block may also include a hierarchical register for masking a wake-up signal sent to the high-level bus block. Figures 4 to 6 Embodiments related to hierarchical registers are described.

[0048] Figure 3 is a first graph 20 illustrating an operating method of a semiconductor system 1 a according to an embodiment.

[0049] refer to Figure 1 and Figure 3 The first graph 20 may be a graph illustrating an operating method of the semiconductor system 1a and is used to explain a process in which a master IP block performing data communication with a low-level bus block performs a wake-up operation on a high-level bus block.

[0050] In some embodiments, the first period T1 may represent a process in which the first master IP block 110a accesses the memory 300a when each of the first to third bus blocks 210a, 220a, and 230a is in a power-off state. For example, the first bus block 210a may enter a power-off state at time t1, the second bus block 220a may enter a power-off state at time t2, and the third bus block 230a may enter a power-off state at time t3. After time t3, the first master IP block 110a may generate a first wake-up signal to access the memory 300a. The first bus block 210a may send a second wake-up signal to the second bus block 220a when performing a wake-up operation in response to the first wake-up signal at time t4. The second bus block 220a may send a third wake-up signal to the third bus block 230a when performing a wake-up operation in response to the second wake-up signal at time t5. The third bus block 230a may perform a wake-up operation in response to the third wake-up signal at time t6. After time t6, the first to third bus blocks 210a, 220a, and 230a may each be in a power-on state, and the first master IP block 110a may access the memory 300a through the first to third bus blocks 210a, 220a, and 230a.

[0051] In some embodiments, the second period T2 may represent a process in which the second master IP block 120a accesses the memory 300a when each of the first to third bus blocks 210a, 220a, and 230a is in a power-off state. For example, the first bus block 210a may enter a power-off state at time t7, the second bus block 220a may enter a power-off state at time t8, and the third bus block 230a may enter a power-off state at time t9. After time t9, the second master IP block 120a may generate a fourth wake-up signal to access the memory 300a. The second bus block 220a may send a fifth wake-up signal to the third bus block 230a when performing a wake-up operation in response to the fourth wake-up signal at time t10. The third bus block 230a may perform a wake-up operation in response to the fifth wake-up signal at time t11. After time t11, the second bus block 220a and the third bus block 230a may each be in a power-on state, and the second master IP block 120a may access the memory 300a through the second bus block 220a and the third bus block 230a. When the second master IP block 120a accesses the memory 300a, the first bus block 210a may maintain a power-off state.

[0052] Figure 4 is a block diagram showing a semiconductor system 1 b according to the embodiment.

[0053] refer to Figure 4 , the semiconductor system 1b may include a first main IP block 110b and a second main IP block 120b, a first bus block 210b, a second bus block 220b and a third bus block 230b, a memory 300b, an address decoder 400b, and a first sub-IP block 510b and a second sub-IP block 520b. Although the semiconductor system 1b is shown to include the first main IP block 110b and the second main IP block 120b, the first to third bus blocks 210b, 220b and 230b, and the first sub-IP block 510b and the second sub-IP block 520b, the semiconductor system 1b may include more main IP blocks, more bus blocks, and more sub-IP blocks.

[0054] The first and second master IP blocks 110b and 120b, the first to third bus blocks 210b, 220b, and 230b, and the memory 300b may correspond to Figure 1 The first master IP block 110a and the second master IP block 120a, the first to third bus blocks 210a, 220a and 230a, and the memory 300a are omitted. Figure 1 The redundant descriptions given in .

[0055] The address decoder 400b may generate an address wake-up signal based on the addresses of the first sub-IP block 510b and the second sub-IP block 520b. The address wake-up signal may include a wake-up signal sent to at least one block. For example, when the first main IP block 110b attempts to access the second sub-IP block 520b, the address decoder 400b may send a wake-up signal to the first bus block 210b and the second bus block 220b and the second sub-IP block 520b respectively based on the signal received from the first main IP block 110b. Figure 8 An embodiment of the address decoder 400b is described.

[0056] The first sub-IP block 510b and the second sub-IP block 520b may be functional blocks that perform specific functions. The first sub-IP block 510b may perform data communication with the first bus block 210b, and the second sub-IP block 520b may perform data communication with the second bus block 220b.

[0057] The first PMU 211b may include a first hierarchical register 211_1b. In some embodiments, the first hierarchical register 211_1b may mask a wake-up signal sent from the first PMU 211b to the second PMU 221b in response to an address wake-up signal generated by the address decoder 400. Masking may refer to an operation of blocking a signal sent. For example, when the first main IP block 110b accesses the first sub-IP block 510b, the address decoder 400b may generate an address wake-up signal including a wake-up signal sent to the first bus block 210b and the first sub-IP block 510b in response to a signal received from the first main IP block 110b. Because the first sub-IP block 510b is a block at the same level as the first bus block 210b, a wake-up operation on a block at a higher level than the first bus block 210b may be unnecessary. Therefore, the first hierarchical register 211_1b may mask the wake-up signal transmitted from the first PMU 211b to the second PMU 221b in response to the generated address wake-up signal, and the second bus block 220b may maintain a power-off state.

[0058] The second PMU 221b may include a second hierarchical register 221_1b. In some embodiments, the second hierarchical register 221_1b may mask a wake-up signal sent from the second PMU 221b to the third PMU 231b in response to an address wake-up signal generated by the address decoder 400. For example, when the first main IP block 110b accesses the second sub-IP block 520b, the address decoder 400b may generate an address wake-up signal including a wake-up signal sent to the first bus block 210b, the second bus block 220b, and the second sub-IP block 520b in response to a signal received from the first main IP block 110b. Because the second sub-IP block 520b is a block at the same level as the second bus block 220b, a wake-up operation on a block at a higher level than the second bus block 220b may be unnecessary. Therefore, the second hierarchical register 221_1b may mask the wake-up signal transmitted from the second PMU 221b to the third PMU 231b in response to the generated address wake-up signal, and the third bus block 230b may maintain a power-off state.

[0059] Figure 5 is a block diagram showing a semiconductor system 1c according to the embodiment.

[0060] refer to Figure 5 , the semiconductor system 1c may include first main IP blocks 111c and 112c, first and second bus blocks 210c and 220c, and address decoders 410c and 420c. Although the semiconductor system 1c is shown to include the first main IP blocks 111c and 112c, the first and second bus blocks 210c and 220c, and address decoders 410c and 420c, the semiconductor system 1c may include more first main IP blocks, more bus blocks, and more address decoders.

[0061] The first main IP blocks 111c and 112c may correspond to Figure 4 In the first master IP block 110b, the address decoders 410c and 420c may correspond to Figure 4 The address decoder 400b in the embodiment of the present invention and the first bus block 210c and the second bus block 220c may correspond to Figure 4 The first bus block 210b and the second bus block 220b in the embodiment of the present invention are omitted. Figure 4 The redundant descriptions given in .

[0062] The first PMU 211 c may include first hierarchical registers 211_1 c and 211_2 c , enable registers 211_3 c , 211_4 c , 211_5 c , and 211_6 c , a plurality of AND gates, and a plurality of OR gates.

[0063] The first layer registers 211_1c and 211_2c may correspond to Figure 4 The first layer register 211_1b in the Figure 4 In some embodiments, the first hierarchical registers 211_1c and 211_2c may correspond to the first master IP blocks 111c and 112c, respectively, that perform data communication with the first bus block 210c. For example, the first hierarchical register 211_1c may correspond to the first master IP block 111c, and the first hierarchical register 211_2c may correspond to the second master IP block 112c.

[0064] In some embodiments, the first hierarchical register 211_1c may mask the wake-up signal sig1 transmitted from the first PMU 211c to the second PMU 221c in response to the address wake-up signal generated by the address decoder 410c. For example, when the first master IP block 111c accesses the first sub-IP block that transmits data with the first bus block 210c, the first hierarchical register 211_1c may generate a signal of a first level (e.g., 0) in response to the address wake-up signal generated by the address decoder 410c. The wake-up signal sig1 transmitted from the first PMU 211c to the second PMU 221c may be masked based on the signal of the first level. For example, when the first master IP block 111c accesses the second sub-IP block that transmits data with the second bus block 220c, the first hierarchical register 211_1c may generate a signal of a second level (e.g., 1) in response to the address wake-up signal generated by the address decoder 410c. The wake-up signal sig1 transmitted from the first PMU 211c to the second PMU 221c may be generated based on the signal of the second level. The first tier register 211_2c may operate on the same principle as the first tier register 211_1c.

[0065] In some embodiments, the enable registers 211_3c, 211_4c, 211_5c, and 211_6c may each correspond to the first master IP block 111c or 112c or the address decoder 410c or 420c, and may control the first PMU 211c to generate a wake-up signal sig1 or sig2 based on a signal generated by the first master IP block 111c or 112c or the address decoder 410c or 420c. For example, the enable register 211_3c corresponding to the first master IP block 111c may generate a signal of a first level (e.g., 0), and the first PMU 211c may ignore a signal generated by the first master IP block 111c based on the signal of the first level. For example, the enable register 211_3c corresponding to the first master IP block 111c may generate a signal of a second level (e.g., 1), and the first PMU 211c may generate a wake-up signal sig1 or sig2 based on a signal generated by the first master IP block 111c based on the signal of the second level. In other words, the first PMU 211c may ignore the first level signal of the first master IP block 111c but generate a wake-up signal based on the second level signal of the first master IP block 111c. The enable register 211_4c, 211_5c, or 211_6c may operate on the same principle as the enable register 211_3c.

[0066] Figure 6 is a second graph 30 illustrating an operating method of the semiconductor system 1 b according to the embodiment.

[0067] refer to Figure 4 and Figure 6 The second graph 30 may be a graph illustrating an operating method of the semiconductor system 1b and is used to explain a process in which a master IP block performing data communication with a lower-level bus block performs a wake-up operation on a higher-level bus block or a same-level bus block.

[0068] In some embodiments, the third period T3 may represent a process in which the first master IP block 110b accesses the second sub IP block 520b when each of the first and second bus blocks 210b and 220b and the first and second sub IP blocks 510b and 520b is in a power-off state.

[0069] For example, the first bus block 210b may enter the power-off state at time t1a, the second bus block 220b may enter the power-off state at time t2a, the second sub-IP block 520b may enter the power-off state at time t3a, and the first sub-IP block 510b may maintain the power-off state. After time t3a, the first main IP block 110b may send a control signal to the address decoder 400b to access the second sub-IP block 520b, and send a wake-up signal to the first PMU 211b. After receiving the control signal, the address decoder 400b may generate an address wake-up signal including a wake-up signal to be sent to the second bus block 220b and the second sub-IP block 520b based on the address of the second sub-IP block 520b. At time t4a, the first PMU 211b may perform a wake-up operation on the first bus block 210b in response to the wake-up signal received from the first main IP block 110b, and the first hierarchical register 211_1b may mask the wake-up signal sent from the first PMU 211b to the second PMU 221b in response to the address wake-up signal. At time t5a, the second PMU 221b may perform a wake-up operation on the second bus block 220b in response to the address wake-up signal. At time t6a, the second sub-IP block 520b may perform a wake-up operation in response to the address wake-up signal. Because the address decoder 400b generates the wake-up signals to be sent to the second bus block 220b and the second sub-IP block 520b in parallel, the time t5a may be the same as the time t6a.

[0070] For example, after time t3a, the first main IP block 110b may send a control signal to the address decoder 400b to access the second sub-IP block 520b. After receiving the control signal, the address decoder 400b may generate an address wake-up signal including wake-up signals to be sent to the first bus block 210b, the second bus block 220b, and the second sub-IP block 520b based on the address of the second sub-IP block 520b. At time t4a, the first PMU 211b may perform a wake-up operation on the first bus block 210b in response to the address wake-up signal, and the first hierarchical register 211_1b may mask the wake-up signal sent from the first PMU 211b to the second PMU 221b in response to the address wake-up signal. The subsequent process may be the same as described above.

[0071] In some embodiments, the fourth period T4 may represent a process in which the first main IP block 110b accesses the first sub IP block 510b when each of the first and second bus blocks 210b and 220b and the first and second sub IP blocks 510b and 520b is in a power-off state.

[0072] For example, the first bus block 210b may enter a power-off state at time t7a, the second bus block 220b may enter a power-off state at time t8a, the second sub-IP block 520b may enter a power-off state at time t9a, and the first sub-IP block 510b may maintain a power-off state. Time t8a and t9a may be the same. In addition, t7a may occur after time t8a and t9a. After time t9a, the first main IP block 110b may send a control signal to the address decoder 400b to access the first sub-IP block 510b, and send a wake-up signal to the first PMU 211b. After receiving the control signal, the address decoder 400b may generate an address wake-up signal including a wake-up signal to be sent to the first sub-IP block 510b based on the address of the first sub-IP block 510b. At time t10a, the first PMU 211b may perform a wake-up operation on the first bus block 210b in response to the wake-up signal received from the first main IP block 110b, and the first hierarchical register 211_1b may mask the wake-up signal sent from the first PMU 211b to the second PMU 221b in response to the address wake-up signal. At time t11a, the first sub-IP block 510b may perform a wake-up operation in response to the address wake-up signal.

[0073] For example, after time t9a, the first main IP block 110b may send a control signal to the address decoder 400b to access the first sub-IP block 510b. After receiving the control signal, the address decoder 400b may generate an address wake-up signal including a wake-up signal to be sent to the first bus block 210b and the first sub-IP block 510b based on the address of the first sub-IP block 510b. At time t10a, the first PMU 211b may perform a wake-up operation on the first bus block 210b in response to the address wake-up signal, and the first hierarchical register 211_1b may mask the wake-up signal sent from the first PMU 211b to the second PMU 221b in response to the address wake-up signal. The subsequent process may be the same as described above. The second bus block 220b and the second sub-IP block 520b may maintain a power-off state before and after time t10a. Since the address decoder 400 b generates the wake-up signal to be transmitted to the first bus block 210 b and the first sub IP block 510 b in parallel, the time t10 a may be the same as the time t11 a .

[0074] Figure 7 is a block diagram showing a semiconductor system 1d according to the embodiment.

[0075] refer to Figure 7, the semiconductor system 1d may include a third main IP block 130d, a first bus block 210d, a second bus block 220d, and a third bus block 230d, a memory 300d, an address decoder 400d, and first sub-IP blocks 510d and 520d, second sub-IP blocks 530d and 540d, and third sub-IP blocks 550d and 560d. Although the semiconductor system 1d is shown to include the third main IP block 130d, the first to third bus blocks 210d, 220d, and 230d, the first sub-IP blocks 510d and 520d, the second sub-IP blocks 530d and 540d, and the third sub-IP blocks 550d and 560d, the semiconductor system 1d may include more main IP blocks, more bus blocks, and more sub-IP blocks.

[0076] The third master IP block 130d and the first to third bus blocks 210d, 220d, and 230d and the memory 300d may correspond to Figure 1 The third master IP block 130a, the first bus block to the third bus block 210a, 220a and 230a and the memory 300a, and the address decoder 400d may correspond to Figure 4 The address decoder 400b is therefore omitted. Figure 1 and Figure 4 The redundant descriptions given in .

[0077] The first sub-IP blocks 510d and 520d, the second sub-IP blocks 530d and 540d, and the third sub-IP blocks 550d and 560d may be function blocks that perform specific functions. The first sub-IP blocks 510d and 520d may perform data communication with the first bus block 210d, and the second sub-IP blocks 530d and 540d may perform data communication with the second bus block 220d. The third sub-IP blocks 550d and 560d may perform data communication with the third bus block 230d.

[0078] After receiving the control signal from the third main IP block 130d, the address decoder 400d may generate an address wake-up signal based on the addresses of the first sub-IP blocks 510d and 520d, the second sub-IP blocks 530d and 540d, and the third sub-IP blocks 550d and 560d. The address wake-up signal may include a wake-up signal sent to at least one block. Figure 7 and Figure 8 An embodiment of an address decoder 400d is described.

[0079] Figure 8 is a block diagram illustrating an address decoder 400 e of a semiconductor system according to an embodiment. Figure 8 The third master IP block 130e and the address decoder 400e may correspond to Figure 7The third master IP block 130d and the address decoder 400d are omitted, and therefore, Figure 7 The redundant descriptions given in .

[0080] refer to Figure 8 , the address decoder 400e may include a plurality of OR gates, and generates an address wake-up signal based on the address of the sub-IP block. In some embodiments, further reference is made to Figure 7 , each of the first sub-IP blocks 510d and 520d, the second sub-IP blocks 530d and 540d, and the third sub-IP blocks 550d and 560d may correspond to a specific address. For example, the first sub-IP block 510d may correspond to the first address 1, the first sub-IP block 520d may correspond to the second address 2, the second sub-IP block 530d may correspond to the third address 3, the second sub-IP block 540d may correspond to the fourth address 4, the third sub-IP block 550d may correspond to the fifth address 5, and the third sub-IP block 560d may correspond to the sixth address 6.

[0081] In some embodiments, the third main IP block 130e can generate a control signal, and the address decoder 400e can generate an address wake-up signal based on the first address 1 to the sixth address 6 of the first sub-IP blocks 510d and 520d, the second sub-IP blocks 530d and 540d, and the third sub-IP blocks 550d and 560d after receiving the control signal.

[0082] For example, when the third main IP block 130e accesses the third sub-IP block 560d, the address decoder 400e may generate a wake-up signal WS1 to be transmitted to the third sub-IP block 560d and a wake-up signal WS3 to be transmitted to the third bus block 230d based on the sixth address 6. When the third main IP block 130e accesses the third sub-IP block 550d, the address decoder 400e may generate a wake-up signal WS2 to be transmitted to the third sub-IP block 550d based on the fifth address 5 and the wake-up signal WS3 to be transmitted to the third bus block 230d.

[0083] For example, when the third master IP block 130e accesses the second sub-IP block 540d, the address decoder 400e may generate a wake-up signal WS4 to be transmitted to the second sub-IP block 540d, a wake-up signal WS6 to be transmitted to the second bus block 220d, and a wake-up signal WS3 to be transmitted to the third bus block 230d based on the fourth address 4. When the third master IP block 130e accesses the second sub-IP block 530d, the address decoder 400e may generate a wake-up signal WS5 to be transmitted to the second sub-IP block 530d based on the third address 3, the wake-up signal WS6 to be transmitted to the second bus block 220d, and the wake-up signal WS3 to be transmitted to the third bus block 230d.

[0084] For example, when the third master IP block 130e accesses the first sub-IP block 520d, the address decoder 400e may generate a wake-up signal WS7 to be transmitted to the first sub-IP block 520d, a wake-up signal WS9 to be transmitted to the first bus block 210d, a wake-up signal WS6 to be transmitted to the second bus block 220d, and a wake-up signal WS3 to be transmitted to the third bus block 230d based on the second address 2. When the third master IP block 130e accesses the first sub-IP block 510d, the address decoder 400e may generate a wake-up signal WS8 to be transmitted to the first sub-IP block 510d based on the first address 1, the wake-up signal WS9 to be transmitted to the first bus block 210d, the wake-up signal WS6 to be transmitted to the second bus block 220d, and the wake-up signal WS3 to be transmitted to the third bus block 230d.

[0085] Fig. 9 is a third graph 40 illustrating an operating method of the semiconductor system 1 d according to the embodiment.

[0086] refer to Figures 7 to 9 The third graph 40 may be a graph illustrating an operating method of the semiconductor system 1d and is used to explain a process in which a master IP block performing data communication with a high-level bus block performs a wake-up operation on a low-level bus block.

[0087] In some embodiments, the fifth period T5 may represent a process in which the third master IP block 130d accesses the second sub IP block 530d when each of the second and third bus blocks 220d and 230d and the second sub IP blocks 530d and 540d is in a power-off state.

[0088] For example, the third bus block 230d may enter the power-off state at time t1b, the second bus block 220d may enter the power-off state at time t2b, the second sub-IP block 530d may enter the power-off state at time t3b, and the second sub-IP block 540d may maintain the power-off state. Times t1b, t2b, and t3b may be the same as each other. After time t3b, the third main IP block 130d may send a control signal to the address decoder 400d to access the second sub-IP block 530d. After receiving the control signal, the address decoder 400d may access the second sub-IP block 530d based on the address of the second sub-IP block 530b (e.g., Figure 8 The third address 3) generates a wake-up signal (eg, Figure 8 At time t4b, the third PMU 231d may respond to the address wake-up signal (eg, Figure 8At time t5b, the second PMU 221d may respond to the address wake-up signal (eg, Figure 8 The second sub-IP block 530d may perform a wake-up operation on the second bus block 220d in response to the address wake-up signal (eg, Figure 8 The wake-up operation is performed based on the wake-up signal WS5 in the second bus block 220d. Because the address decoder 400d generates the wake-up signals (e.g., wake-up signals WS6, WS3, and WS5) to be sent to the second bus block 220d, the third bus block 230d, and the second sub-IP block 530d in parallel, the time t4b may be the same as the time t5b and the time t6b. However, in some cases, the time t4b, the time t5b, and the time t6b may be different from each other.

[0089] In some embodiments, the sixth period T6 may represent a process in which the third master IP block 130d accesses the second sub IP block 540d when each of the second and third bus blocks 220d and 230d and the second sub IP blocks 530d and 540d is in a power-off state.

[0090] For example, the third bus block 230d may enter the power-off state at time t7b, the second bus block 220d may enter the power-off state at time t8b, the second sub-IP block 530d may enter the power-off state at time t9b, and the second sub-IP block 540d may maintain the power-off state. After time t9b, the third main IP block 130d may send a control signal to the address decoder 400d to access the second sub-IP block 540d. After receiving the control signal, the address decoder 400d may access the second sub-IP block 540d based on the address of the second sub-IP block 540b (e.g., Figure 8 The fourth address 4) generates a wake-up signal (eg, Figure 8 At time t7b, the third PMU 231d may respond to the address wake-up signal (eg, Figure 8 At time t11b, the second PMU 221d may respond to the address wake-up signal (eg, Figure 8 The second sub-IP block 540d may perform a wake-up operation on the second bus block 220d in response to the address wake-up signal (eg, Figure 8Because the address decoder 400d generates the wake-up signals (e.g., the wake-up signals WS6, WS3, and WS4) to be sent to the second bus block 220d, the third bus block 230d, and the second sub-IP block 530d in parallel, the time t10b may be the same as the time t11b and the time t12b.

[0091] Fig.10 is a block diagram showing a semiconductor system 1f according to the embodiment.

[0092] refer to Fig.10 , the semiconductor system 1f may include a third main IP block 130f, a third bus block 230f, a memory 300f, a third sub-IP block 550f, a system controller 600f, and a power management integrated circuit (PMIC) 700f. Although the semiconductor system 1f is shown to include the third main IP block 130f, the third bus block 230f, the memory 300f, the third sub-IP block 550f, the system controller 600f, and the PMIC 700f, the semiconductor system 1f may include more first main IP blocks, more bus blocks, and more sub-IP blocks.

[0093] The third main IP block 130f, the third bus block 230f, the memory 300f, and the third sub-IP block 550f may correspond to Figure 7 The third main IP block 130d, the third bus block 230d, the memory 300d and the third sub-IP block 550d are omitted. Figure 7 The redundant descriptions given in .

[0094] The third main IP block 130f may include an interrupt request (IRQ) generator 131f. The IRQ generator 131f may send a wake-up signal to a block related to the third main IP block 130f before the third main IP block 130f operates. In this specification, the third main IP block 130f includes the IRQ generator 131f, but is not limited thereto. For example, the IRQ generator 131f may be located outside the third main IP block 130f.

[0095] In some embodiments, the third sub-IP block 550f may be a block related to the third main IP block 130f, and the IRQ generator 131f may send a wake-up signal to the third sub-IP block 550f before performing a wake-up operation on the third main IP block 130f. For example, when the third main IP block 130f operates, the third sub-IP block 550f may operate together. In this case, the third sub-IP block 550f may be referred to as a block related to the third main IP block 130f. The IRQ generator 131f may send a wake-up signal to the third sub-IP block 550f before performing a wake-up operation on the third main IP block 130f.

[0096] In some embodiments, when the third main IP block 130f operates, the IRQ generator 131f may send a wake-up signal faster than the period of the third sub-IP block 550f. In other words, when the third main IP block 130f operates, the IRQ generator 131f may send a wake-up signal faster than the operation period of the third sub-IP block 550f. For example, the third sub-IP block 550f may be a block that operates periodically, and the operation period of the third sub-IP block 550f may be T ms (T is a natural number). The IRQ generator 131f may send a wake-up signal to the third sub-IP block 550f faster than T ms.

[0097] In the semiconductor system 1f of the present invention, the IRQ generator 131f can perform an early wake-up operation of early waking up another block (e.g., the third sub-IP block 550f) related to a specific block (e.g., the third main IP block 130f), and thus, the time required to perform a power-on operation on each of the multiple blocks can be reduced, thereby enhancing the performance of the semiconductor system 1f.

[0098] The system controller 600f may perform a lock setting operation or an unlocking operation on a specific block. A plurality of blocks connected to a specific bus block may share a supplied power supply voltage, and the lock setting operation may be an operation of reducing the power supply voltage supplied to a specific block, which uses a shared power supply voltage exceeding the necessary. The unlocking operation may be an operation of releasing the lock setting operation. In some embodiments, the system controller 600f may perform a lock setting operation or an unlocking operation on the third sub-IP block 550f. For example, the third sub-IP block 550f may receive a control signal from the IRQ generator 131f, and may send locking information to the system controller 600f based on the received control signal. When the locking information is at a first level (e.g., a low level), the system controller 600f may perform an unlocking operation on the third sub-IP block 550f, and when the locking information is at a second level (e.g., a high level), the lock setting operation is performed on the third sub-IP block 550f.

[0099] Fig.11 is a block diagram showing an electronic device 2 according to the embodiment.

[0100] refer to Fig.11 The electronic device 2 may be implemented as a handheld device such as a mobile phone, a smart phone, a tablet PC, a PDA, an enterprise digital assistant EDA, a digital still camera, a digital video camera, a PMP, a PND, a handheld game console, or an electronic book.

[0101] The electronic device 2 may include the SoC 1000 , an external memory 1850 , a display device 1550 , and a power management integrated circuit (PMIC) 1950 .

[0102] SoC 1000 may include a central processing unit (CPU) 1100, a clock management unit (CMU) 1200, a graphics processing unit (GPU) 1300, a timer 1400, a display controller 1500, a random access memory (RAM) 1600, a read-only memory (ROM) 1700, a memory controller 1800, a power management unit (PMU) 1910, a power control circuit 1900, and a bus 1050. In addition to the components shown, SoC 1000 may also include other components. For example, electronic device 2 may also include a display device 1550, an external memory 1850, and a PMIC 1950. PMIC 1950 may be implemented outside SoC 1000. However, SoC 1000 is not limited thereto, and may include a PMU capable of performing the functions of PMIC 1950.

[0103] The CPU 1100 may also be referred to as a processor, and may process or execute a program and / or data stored in the external memory 1850. For example, the CPU 1100 may process or execute a program and / or data in response to an operation clock signal output from the CMU 1200.

[0104] The CPU 1100 may be implemented as a multi-core processor. A multi-core processor may be a computing component having two or more independent physical processors (referred to as "cores"), and each processor may read and execute program instructions. Programs and / or data stored in the ROM 1700, RAM 1600, and / or external memory 1850 may be loaded into the memory of the CPU 1100 as needed.

[0105] The CMU 1200 may generate an operation clock signal. The CMU 1200 may include a clock signal generating device such as a phase locked loop (PLL), a delay locked loop (DLL), or a crystal oscillator.

[0106] The operation clock signal may be supplied to the GPU 1300. The operation clock signal may be supplied to other components (eg, the CPU 1100 or the memory controller 1800, etc.). The CMU 1200 may change the frequency of the operation clock signal.

[0107] The GPU 1300 may convert data read from the external memory 1850 by the memory controller 1800 into a signal suitable for the display device 1550 .

[0108] The timer 1400 may output a count value indicating time based on the operation clock signal output from the CMU 1200 .

[0109] The display device 1550 may display an image signal output from the display controller 1500. For example, the display device 1550 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, or a flexible display. The display controller 1500 may control the operation of the display device 1550.

[0110] The RAM 1600 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory may be temporarily stored in the RAM 1600 by the control of the CPU 1100 or according to a booting code stored in the ROM 1700. The RAM 1600 may be implemented as a dynamic RAM (DRAM) or a static RAM (SRAM).

[0111] The ROM 1700 may store permanent programs and / or data. The ROM 1700 may be implemented as an Erasable Programmable Read Only Memory (EPROM) or an Electrically Erasable Programmable Read Only Memory (EEPROM).

[0112] The memory controller 1800 may communicate with the external memory 1850 through an interface. The memory controller 1800 may control all operations of the external memory 1850 and control data exchange between the host and the external memory 1850. For example, the memory controller 1800 may write data to the external memory 1850 or read data from the external memory 1850 at the request of the host. Here, the host may be a master device such as the CPU 1100, the GPU 1300, or the display controller 1500.

[0113] The external memory 1850 is a storage medium for storing data, and may store an operating system (OS), various programs, and / or various data. The external memory 1850 may be, for example, a DRAM, but is not limited thereto. For example, the external memory 1850 may be a non-volatile memory device (e.g., a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FeRAM) device). In another embodiment, the external memory 1850 may be an internal memory provided inside the SoC 1000. In addition, the external memory 1850 may be a flash memory, an embedded multimedia card (eMMC), or a universal flash storage (UFS).

[0114] The PMU 1910 may control the voltage required for each device connected to the SoC 1000 to operate. In some embodiments, the SoC 1000 may include a plurality of blocks (e.g., the CPU 1100, the GPU 1300, or the bus 1050), and the PMU 1910 may perform a power-on / power-off operation on each of the plurality of blocks. The PMU 1910 may be used in conjunction with the above-described Figure 1 For example, the PMU 1910 can perform a power-on operation in parallel on the CPU 1100, the GPU 1300, or the bus 1050 that is in a power-off state, which can reduce the time required to perform the power-on operation, thereby enhancing the performance of the electronic device 2.

[0115] The CPU 1100 , the CMU 1200 , the GPU 1300 , the timer 1400 , the display controller 1500 , the RAM 1600 , the ROM 1700 , the memory controller 1800 , the power control circuit 1900 , and the PMU 1910 may communicate with one another via the bus 1050 .

[0116] Fig.12 is a block diagram showing an electronic device 3 according to the embodiment.

[0117] refer to Fig.12 , the electronic device 3 can be implemented as a PC, a data server or a portable electronic device.

[0118] The electronic device 3 may include a SoC 2000 , a camera module 2100 , a display 2200 , a power supply 2300 , an input / output (I / O) port 2400 , a memory 2500 , a storage device 2600 , an external memory 2700 , and a network device 2800 .

[0119] SoC 2000 may include a plurality of blocks (e.g., Fig.11 The SoC 2000 may include the CPU 1100, GPU 1300, or bus 1050 of the embodiment of the present invention, and may perform a power-on operation on each of the plurality of blocks in parallel. Figure 1 For example, the SoC 2000 may power off a plurality of blocks ( Fig.11 The power-on operation is performed in parallel on each block in the CPU 1100, GPU 1300 or bus 1050), which can reduce the time required to perform the power-on operation on each block in the multiple blocks, thereby enhancing the performance of the electronic device 3.

[0120] The camera module 2100 may be a module capable of converting an optical image into an electrical image. Therefore, the electrical image output from the camera module 2100 may be stored in the storage device 2600, the memory 2500, or the external memory 2700. In addition, the electrical image output from the camera module 2100 may be displayed through the display 2200.

[0121] The display 2200 may display data output from the storage device 2600, the memory 2500, the I / O port 2400, the external memory 2700, or the network device 2800. The display 2200 may be Fig.11 Display device 1550 shown in .

[0122] The power supply 2300 may provide an operating voltage to at least one of the components. Fig.11 The PMIC 1950 shown in FIG.

[0123] The I / O port 2400 may include a port capable of transmitting data to the electronic device 1 or transmitting data output from the electronic device 2 to an external device. For example, the I / O port 2400 may include a port for connecting a pointing device such as a computer mouse, a port for connecting a printer, or a port for connecting a USB drive.

[0124] The memory 2500 may be implemented as a volatile memory or a nonvolatile memory. According to an embodiment, a memory controller capable of controlling data access operations on the memory 2500, such as a read operation, a write operation (or a program operation), or an erase operation, may be integrated or embedded in the SoC 2000. According to another embodiment, the memory controller may be implemented between the SoC 2000 and the memory 2500.

[0125] The storage device 2600 may be implemented as a hard disk drive or a solid state drive (SSD).

[0126] The external memory 2700 may be implemented as a secure digital (SD) card or a multimedia card (MMC). According to an embodiment, the external memory 2700 may be a subscriber identity module (SIM) card or a universal subscriber identity module (USIM) card.

[0127] The network device 2800 may be a device capable of connecting the electronic device 3 to a wired network or a wireless network.

[0128] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A semiconductor system, comprising: A memory for storing data; A first master intellectual property IP block is configured to generate a first wake-up signal; a first bus block configured to generate a second wake-up signal when performing a wake-up operation in response to the first wake-up signal; a second bus block configured to generate a third wake-up signal when performing the wake-up operation in response to the second wake-up signal; as well as The third bus block is configured to perform data communication with the memory and to perform the wake-up operation in response to the third wake-up signal.

2. The semiconductor system according to claim 1, wherein The first bus block comprises: a first bus configured to perform data communication with the first master IP block; as well as a first power management unit PMU configured to generate the second wake-up signal when performing the wake-up operation in response to the first wake-up signal, The second bus block comprises: a second bus configured to perform data communication with the first bus; and a second PMU configured to generate the third wake-up signal when performing the wake-up operation in response to the second wake-up signal, The third bus block comprises: a third bus configured to perform data communication with the second bus and the memory; and The third PMU is configured to perform the wake-up operation in response to the third wake-up signal.

3. The semiconductor system according to claim 2, further comprising: a second master IP block configured to generate a fourth wake-up signal and perform data communication with the second bus, wherein the second PMU is configured to generate a fifth wake-up signal when performing the wake-up operation in response to the fourth wake-up signal, and The third PMU is configured to perform the wake-up operation in response to the fifth wake-up signal.

4. The semiconductor system according to claim 2, further comprising: Multiple sub-IP blocks; as well as an address decoder configured to generate an address wake-up signal based on address information of each sub-IP block in the plurality of sub-IP blocks, The first PMU includes a first hierarchical register configured to mask the second wake-up signal in response to the address wake-up signal.

5. The semiconductor system according to claim 4, wherein: The second PMU includes a second hierarchy register configured to mask the third wake-up signal in response to the address wake-up signal.

6. The semiconductor system according to claim 5, wherein The address decoder is configured to generate the address wake-up signal based on address information of a first sub-IP block among the plurality of sub-IP blocks that performs data communication with the second bus block, The first PMU is configured to generate the second wake-up signal by using the first hierarchical register, the first hierarchical register generating a high level signal in response to the address wake-up signal, The second PMU is configured to mask the third wake-up signal by using the second hierarchy register, the second hierarchy register generating a low level signal in response to the address wake-up signal, and The first sub-IP block is configured to perform the wake-up operation in response to the address wake-up signal.

7. The semiconductor system according to claim 1, further comprising: a third master IP block configured to generate a sixth wake-up signal and perform data communication with the third bus block; Multiple sub-IP blocks; as well as The address decoder is configured to generate an address wake-up signal based on address information of a specific sub-IP block among the plurality of sub-IP blocks, wherein the third bus block is configured to perform the wake-up operation in response to the sixth wake-up signal, and The specific sub-IP block is configured to perform the wake-up operation in response to the address wake-up signal.

8. The semiconductor system according to claim 7, wherein The specific sub-IP block is configured to perform data communication with the second bus block, and The second bus block is configured to perform the wake-up operation in response to the address wake-up signal.

9. The semiconductor system according to claim 7, wherein The second bus block comprises: Second bus; as well as A second power management unit PMU is configured to perform the wake-up operation in response to the address wake-up signal, The third bus block comprises: a third bus configured to perform data communication with the second bus and the third master IP block; and a third PMU configured to perform the wake-up operation in response to the sixth wake-up signal, and The specific sub-IP block includes: a fourth bus configured to perform data communication with the second bus; and The fourth PMU is configured to perform the wake-up operation in response to the address wake-up signal.

10. The semiconductor system according to claim 1, further comprising: a third master IP block configured to generate a sixth wake-up signal and perform data communication with the third bus block; as well as a first sub-IP block configured to perform data communication with the third bus block, wherein the third bus block is configured to perform the wake-up operation in response to the sixth wake-up signal, and The third main IP block includes an interrupt request IRQ generator configured to send a seventh wake-up signal to the first sub-IP block before generating the sixth wake-up signal.

11. The semiconductor system according to claim 10, further comprising: a system controller configured to perform a lock setting operation or an unlocking operation on the first sub-IP block, The IRQ generator is configured to send a control signal to the first sub-IP block and control the system controller in response to the control signal.

12. The semiconductor system according to claim 11, wherein The first sub-IP block is configured to send locking information to the system controller in response to the control signal, The system controller is configured to: When the locking information is at a first level, performing the unlocking operation on the first sub-IP block, and When the lock information is at a second level, the lock setting operation is performed on the first sub-IP block.

13. A semiconductor system comprising: A memory for storing data; a first level bus block configured to perform data communications with the memory; a second level bus block configured to perform data communications with the first level bus block; as well as a third level bus block configured to perform data communication with the second level bus block, The first-level bus block and the second-level bus block are configured to perform the wake-up operation when the wake-up operation on the third-level bus block is performed.

14. The semiconductor system according to claim 13, wherein The third level bus block includes a third level power management unit PMU, the third level PMU is configured to generate a first wake-up signal when performing the wake-up operation, The second level bus block includes a second level PMU configured to generate a second wake-up signal when performing the wake-up operation in response to the first wake-up signal, and The first level bus block includes a first level PMU configured to perform the wake-up operation in response to the second wake-up signal.

15. The semiconductor system according to claim 14, further comprising: Multiple sub-intellectual property IP blocks; as well as an address decoder configured to generate an address wake-up signal based on address information of each sub-IP block in the plurality of sub-IP blocks, The third level PMU includes a hierarchical register configured to mask the first wake-up signal in response to the address wake-up signal.

16. The semiconductor system according to claim 13, further comprising: a first level master intellectual property IP block configured to perform data communication with the first level bus block; Multiple sub-IP blocks; as well as The address decoder is configured to generate an address wake-up signal based on address information of a specific sub-IP block among the plurality of sub-IP blocks, wherein the first level bus block is configured to perform the wake-up operation in response to the wake-up signal or the address wake-up signal generated by the first level master IP block, and The specific sub-IP block is configured to perform the wake-up operation in response to the address wake-up signal.

17. The semiconductor system according to claim 13, further comprising: a first-level master IP block configured to generate a fourth wake-up signal and perform data communication with the first-level bus block; as well as A first level sub-IP block is configured to perform data communication with the first level bus block, wherein the first level bus block is configured to perform the wake-up operation in response to the fourth wake-up signal, and The first-level main IP block includes an interrupt request IRQ generator configured to send a fifth wake-up signal to the first-level sub-IP block before generating the fourth wake-up signal.

18. The semiconductor system according to claim 17, further comprising: a system controller configured to perform a lock setting operation or an unlocking operation on the first-level sub-IP block, The IRQ generator is configured to send a control signal to the first-level sub-IP block, and control the lock setting operation or the unlocking operation in response to the control signal.

19. An operating method of a semiconductor system, the semiconductor system comprising a bus block and a plurality of intellectual property IP blocks, the operating method comprising: When performing a wake-up operation on the first bus block, sending a first wake-up signal to a second bus block that performs data communication with the first bus block among the bus blocks; When the wake-up operation is performed on the second bus block in response to the first wake-up signal, sending a second wake-up signal to a third bus block that performs data communication with the second bus block; as well as performing the wake-up operation on the third bus block in response to the second wake-up signal, wherein the second bus block is a bus block of a higher level than the first bus block, and The third bus block is a higher-level bus block than the second bus block.

20. The operating method according to claim 19, wherein: The transmitting of the first wake-up signal includes masking the first wake-up signal when the wake-up operation is performed on a first IP block among the plurality of IP blocks that performs data communication with the first bus block.

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