System and method for error correction code architecture with memory mapping

Abstract

Systems, apparatuses, and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile memory devices, a memory including a plurality of storage units, a mapping memory including a plurality of mapping entries to indicate an allocation state of the plurality of storage units, and a memory mapping manager. The plurality of storage units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager is configured to control allocation of the plurality of storage units and set an allocation state in the plurality of mapping entries.

Description

This application is a divisional application of the invention application with application date of December 13, 2019, application number 201911284577.9, and invention name “System and method for error correction code architecture with memory mapping”. Technical Field

[0001] The present specification relates to an error correction code (ECC) architecture, and more particularly to an ECC architecture with flexible memory mapping. Background Art

[0002] ECC has been widely used in data storage and communication systems to recover user data by a receiver or reader even when many errors (not exceeding the capabilities of the code used) are introduced during transmission or in memory due to data corruption. Conventional ECC architectures typically have an encoder path and a decoder path, which require independent encoding buffers and decoding buffers during the encoding and decoding processes. In addition, in multi-channel storage or communication systems, conventional ECC architectures also require separate channel buffers to serve each channel. Therefore, there is a need in the art for an ECC architecture that can organize and utilize resources to achieve faster throughput and lower power consumption. Summary of the invention

[0003] The subject matter disclosed in this specification relates to systems, methods and devices for providing an ECC architecture with flexible memory mapping. Flexible memory mapping can minimize the total physical memory required for the ECC architecture and can also avoid copying data from one buffer to another. Physical memory can be mapped and remapped for different purposes in different scenarios, and system performance can be improved in different use cases. By reducing or avoiding unnecessary data movement from one memory to another, ECC throughput can be increased and power consumption can be reduced. In addition, quality of service (QoS) control can be implemented in some embodiments so that memory resources can be intelligently allocated based on actual needs without affecting performance.

[0004] In an exemplary embodiment, an apparatus is provided that may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile memory devices, a memory including a plurality of storage units, a mapping memory including a plurality of mapping entries to indicate allocation states of the plurality of storage units, and a memory mapping manager. The plurality of storage units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager is configured to control allocation of the plurality of storage units and set allocation states in the plurality of mapping entries.

[0005] In another exemplary embodiment, a method is provided, comprising: receiving a storage request for a read or write task for a channel from an encoding task control or a decoding task control, checking the overall memory usage and the memory usage of the channel, determining that the storage request needs to be executed immediately and a storage unit among the multiple storage units is available, allocating the storage unit to the channel, updating a memory map entry corresponding to the storage unit, and publishing the storage unit to the encoding or decoding task control. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A nonvolatile memory controller according to an embodiment of the present disclosure is schematically shown.

[0007] Figure 2 An ECC processor according to an embodiment of the present disclosure is schematically shown.

[0008] Figure 3A The figure schematically shows a memory map according to an embodiment of the present disclosure.

[0009] Figure 3B Another memory mapping according to an embodiment of the present disclosure is schematically shown.

[0010] Figure 4 is a flowchart of a process for allocating memory according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Now, specific embodiments according to the present application will be described in detail with reference to the accompanying drawings. For consistency, the same elements in various drawings are represented by the same reference numerals.

[0012] This specification provides apparatus, systems and methods for supporting any combination of various high-speed non-volatile memories (NVMs) and various NVMs. As used herein, a non-volatile memory device can be a computer memory device that can retain stored information after power failure and can retrieve stored information after power is turned on again (turned off and reopened). Non-volatile memory devices can include floppy disks, hard disk drives, tapes, optical disks, NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), nano-RAM (Nano-RAM), etc. In the specification, NAND flash memory can be used as an example of the proposed technology. However, other types of non-volatile memory devices can be used to implement these technologies according to various embodiments disclosed in this specification.

[0013] Figure 1An exemplary non-volatile memory controller 100 according to one embodiment is schematically shown. The non-volatile memory controller 100 may include a first interface 110, a second interface 112, a microcontroller unit (MCU) 102, and an ECC processor 104. The first interface 110 may be any existing or yet to be developed interface configured to couple the non-volatile memory controller 100 to a system bus of a host computing system, and receive data from the host computing system and send data to the host computing system. In one embodiment, for example, the first interface 110 may be a host interface controller (e.g., Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), PCIe, etc.). The second interface 112 may be any existing or yet to be developed interface configured to couple the memory controller to one or more non-volatile memory devices. In one embodiment, the second interface 112 may be a multi-channel interface that may be configured to transmit encoded data (e.g., ECC codewords) on multiple channels in parallel. For example, the second interface 112 may be an open NAND flash interface (ONFI), which may support different protocols (eg, non-volatile double data rate (NVDDR), NVDDR type 2 (NVDDR2), NVDDR type 3 (NVDDR3), and Toggle protocol) and operate at different transmission speeds.

[0014] The MCU 102 may be a computer processor configured to execute executable instructions (e.g., software or firmware). In various embodiments, the MCU 102 may be a microprocessor, a microcontroller, a field programmable gate array (FPGA), or an application specific IC (ASIC). The ECC processor 104 may include one or more ECC encoders for encoding data into codewords to be stored in the NVM, and one or more ECC decoders for decoding codewords read from the NVM.

[0015] Figure 2An ECC processor 200 according to an embodiment of the present disclosure is schematically shown. The ECC processor 200 may be an embodiment of the ECC processor 104, and the various components of the ECC processor 200 described herein may be implemented in an FPGA, an ASIC, or a combination of an FPGA and an ASIC. The ECC processor 200 may include an ECC engine 201, as well as a memory mapping component 206, a memory (Memory) 208, and a QoS monitor 210. The ECC engine 201 may include an encoder 202 and a decoder 204. The encoder 202 may represent one or more encoders in the ECC processor 200, and the decoder 204 may represent one or more decoders in the ECC processor 200. The memory 208 may include a plurality of storage units. In some embodiments, the size of the storage unit may be selected to be at least the size of the ECC codeword. For example, if the encoder 202 and the decoder 204 are configured for a codeword of a specific size, the size of the storage unit may be the specific size. If there are multiple encoders 202 and multiple decoders 204 configured for codewords of two or more different sizes, the maximum codeword size among the codewords of different sizes may be selected for the size of the storage unit. Although in Figure 2 In the illustrated embodiment, the ECC engine 201 may include an encoder 202 and a decoder 204, but in some embodiments, the ECC engine 201 may include only one or more encoders or one or more decoders, but not both.

[0016] In one embodiment, the storage cells of memory 208 can be logically divided into two parts: NAND data part 220 and error recovery data buffer part 222. NAND data part 220 can include K storage cells, and error recovery data buffer part 222 can include R storage cells. K and R can be any suitable number and can be determined based on the number of channels. For example, an embodiment of the ECC processor 200 for a 4-channel NAND storage system can have a memory 208 with K of 12 and R of 8 (a total of 20 storage cells). It should be noted that the logical partitioning can be optional, and a memory 208 without such logical partitioning can implement all the techniques described herein in one embodiment.

[0017] The memory mapping component 206 may include a mapping memory 216 and a memory mapping manager 218. The memory 208 may be coupled to the encoder 202 and the decoder 204 via the memory mapping component 206. The mapping memory 216 may include a data structure having a plurality of mapping entries indicating the allocation status of the memory 208. The data structure may be implemented in any suitable format, such as but not limited to a mapping table. In one embodiment, each mapping entry in the data structure may correspond to a storage unit of the memory 208, such that the value in the mapping entry may indicate the allocation status of the corresponding storage unit. In another embodiment, each mapping entry in the data structure may correspond to two or more storage units of the memory 208, such that the value in the mapping entry may indicate the allocation status of two or more corresponding storage units. Some examples herein may use a mapping entry corresponding to a storage unit to illustrate the features of various embodiments. These features are also applicable to embodiments in which a mapping entry may correspond to multiple storage units.

[0018] The allocation state maintained in each mapping entry may include a plurality of information, including, but not limited to, which channel the corresponding storage unit is used for, and whether the corresponding storage unit is used in an encoding, decoding, or error recovery operation mode. For example, during operation, when a write task is to be performed on a channel, a storage unit may be allocated to the channel for encoding, and the storage unit may store the codeword generated by the encoder 202 and to be written to the channel. When there is a read task (or a retry task when there is an error in the previous decoding process), the storage unit or another storage unit may be allocated to the channel for decoding, and the storage unit may store the codeword read from the channel and decoded by the decoder 204.

[0019] In some embodiments, the codeword may be cross-channel. As used herein, a cross-channel codeword may be divided into multiple fragments and allocated to multiple channels during a programming (write) operation, wherein one fragment is allocated to a separate channel, and the fragments read from the multiple channels are assembled together during a read operation. In these embodiments, the allocation state may also include information indicating whether the codeword in the corresponding storage unit is cross-channel.

[0020] The memory map entry format may vary from application to application. In an embodiment that supports cross-channel, an exemplary mapping entry may include three fields: FMT, MODE, CH. The FMT field may indicate the cross-channel status. An exemplary FMT field may have two bits, for example, 00 indicates a single channel (for example, there is no cross-channel for the codeword in the corresponding storage unit), 01 indicates that the codeword in the corresponding storage unit can be distributed in two channels, 10 indicates that the codeword in the corresponding storage unit can be distributed in four channels, and 11 indicates that the codeword in the corresponding storage unit can be distributed in all channels. The MODE field may indicate the operation mode. An exemplary MODE field may have two bits, for example, 00 indicates decoding, 01 indicates encoding, 10 indicates error recovery, and 11 indicates a reserved state. In one embodiment, MODE "11" is reserved for future use. For example, a storage unit may be fixed for a specific purpose (for example, decoding / encoding / error recovery) without reallocation. In some embodiments, the MODE field may have more than 2 bits. The CH field may include a channel identifier (CH ID) indicating the channel associated with the codeword in the corresponding storage unit. The width of the CH field may depend on the number of channels in a multi-channel NAND memory system. For example, in some embodiments, the CH field may have a width of 2 bits for a four-channel NAND memory system and a width of 3 bits for an eight-channel NAND memory system.

[0021] Each storage unit of the memory 208 can be allocated to any channel for any operating mode, and the allocation state can be changed dynamically during operation. The allocation and change of the allocation state can be referred to as physical memory mapping and remapping, which can be equivalent to and performed by updating the mapping entry. The memory mapping manager 218 can be a control submodule that can allocate and release storage units and also control memory mapping.

[0022] In some embodiments, the ECC processor 200 may further include a quality of service (QoS) monitor 210, an encoding task control 212, and a decoding task control 214. The memory mapping component 206 may allocate storage units and publish the allocated storage units to the encoding task control 212 and the decoding task control 214. The encoding task control 212 may be a write control block that is configured to control all write tasks and provide the allocated storage units (e.g., in the encoding operation mode) to the encoder 202 and the NAND interface 112 to complete the write task. The decoding task control 214 may be a read control block that is configured to control all read tasks and provide the allocated storage units (e.g., in the encoding operation mode and the error recovery mode) to the decoder 204 and the NAND interface 112 to complete the read task. It should be noted that in an embodiment with only an encoder, the decoding task control 214 may not be necessary. In addition, in an embodiment with only a decoder, the encoding task control 212 may not be necessary.

[0023] Each storage unit can have an idle or busy state, which can be maintained by the memory mapping component 206. In one embodiment, in addition to the mapping information, the idle or busy state can also be stored in the memory mapping memory 216. In another embodiment, the idle or busy state can be stored in a separate memory state table. Once a storage unit is allocated for a storage request (e.g., an encoding / decoding task control allocation request), the memory mapping manager 218 can set the state of the storage unit to busy. Before a busy storage unit becomes idle, it cannot be reallocated. The memory mapping manager 218 can set the state of a storage unit to idle when a release request (e.g., an encoding / decoding release request) is received. In some embodiments, the memory allocation of the memory mapping manager 218 can be a priority allocation. For example, if a storage unit is pre-set for decoding, the priority of the decoding task to use the storage unit may be higher than that of the encoding task.

[0024] In one embodiment, the encoding task control 212 may have a queue for all pending write tasks, and the decoding task control 214 may have a queue for all pending read tasks and a queue for pending retry tasks. The QoS monitor 210 may be configured to determine memory map updates. In one embodiment, the QoS monitor 210 may determine memory map updates based on one or more criteria. Exemplary criteria may include, but are not limited to, the total number of pending read tasks, the total number of pending write tasks, the next expected task from NAND (read or write), pending retry tasks, idle channels, 4K random reads, traffic congestion, and sequential writes, etc. It should be noted that if certain conditions are met in the QoS monitor 210, if the status of the storage unit is idle, the storage unit can be reallocated from the decoding task to the encoding task, and vice versa.

[0025] Setting or modifying the values ​​in the mapping entries may be accomplished by a variety of operations. An "initialization" operation may be an exemplary operation that initializes the entire data structure by assigning respective initial values ​​to each mapping entry. This may be equivalent to allocating memory 208 according to an initial configuration. For example, in an initial configuration, all storage units of memory 208 may be divided among all channels, with each channel having one or more storage units for encoding, one or more storage units for decoding, and one or more storage units for error recovery.

[0026] After a storage unit has been assigned a certain purpose (e.g., after initialization), its allocation state can be changed on the fly, and some operations can be performed to achieve memory mapping and remapping on the fly. A "set" operation can be an exemplary operation of instant remapping to set a specific value to a mapping entry. For example, a specific purpose can be initially assigned to each storage unit of memory 208 (e.g., when the system is just powered on), and an "initialize" operation can set an initial value for each mapping entry according to the allocation state of the corresponding storage unit. During operation, it often happens that the initial allocation needs to be changed. Some example situations may be related to read and write traffic requirements. For example, there may be a read operation to read data from a channel, and the data to be transmitted in the channel may exceed the memory initially allocated to the channel. One or more storage units originally allocated for other purposes (e.g., encoding or error recovery of the channel, or any operating mode of other channels) can be dynamically reallocated to the channel for reading, thereby avoiding the channel from being stuck and can "set" the mapping entry corresponding to the one or more dynamically reallocated storage units to read (e.g., decoding operating mode) the channel. In some embodiments, dynamic reallocation can depend on whether the storage unit is free. In one embodiment, if a read command is followed by a program command (e.g., writing data to the NVM), then one or more storage cells assigned to the channel read may be immediately mapped to the channel's encoding operation mode and used for the codeword to be written to the channel. In an embodiment where "reservation" is implemented for certain uses, then the storage cells may be reserved for that particular use. For example, one embodiment may implement "reservation" by having a bit in the mapping entry indicating that "reserved" state, and the storage cells may be fixed for that particular use and cannot be reallocated to a different use.

[0027] Sometimes, a read command and a write command may be issued for a channel at the same time. In one embodiment, the read command can be satisfied first so that the entire system appears to be responsive, and the write command can be executed after the read command. That is, the storage unit can be allocated first to execute the read command, and then the storage unit can be reallocated to execute the write command. In addition, some read tasks or write tasks may have some specific memory usage requirements. For example, a 4K read task may need to allocate some storage units to the decoding operation mode so that the codewords received from the channel interface can be buffered without blocking. On the contrary, a sequential write task may need to allocate some storage units to the encoding operation mode so that the encoder-generated codewords can be buffered without obstacles. In these use cases, a "set" operation can be used on the mapping entry to complete the mapping and remapping of each storage unit.

[0028] The "swap" operation can be another exemplary operation of remapping on the fly to exchange the values ​​of two mapping entries. For example, after the "initialization" operation, the first storage unit can be assigned to the decoding operation mode of a specific channel, and the second storage unit can be assigned to the error recovery mode of a specific channel. During operation, the decoder 204 may not be able to successfully decode the codeword stored in the first storage unit in the first attempt, and the codeword may have to be decoded again via an error recovery process (e.g., retrying with a more powerful decoder). Then, the first storage unit can be remapped to the error recovery mode without actually copying the codeword from the first storage unit to another storage unit (e.g., the second storage unit), and the second storage unit can be allocated for decoding, so that the first storage unit and the second storage unit can exchange their operation modes without actually moving data between them. In general, because the memory 208 is shared by all channels and all encoders and decoders, it is possible to avoid moving codewords from one decoder buffer to another decoder buffer when switching from one decoder to another. In an embodiment of the logical partitioning of the memory 208, the first storage unit can be allocated from the NAND data portion 220, and the second storage unit can be allocated from the error recovery data buffer portion 222.

[0029] Another exemplary operation may be a "reset" operation to reset the value of a map entry to an initial allocation state. In one embodiment, some operations (e.g., initialization, setting, and resetting) may be batch operations, such that one operation may be applied to two or more map entries in a batch.

[0030] An exemplary allocation workflow may begin when the memory mapping manager 218 receives a storage request for a memory resource when there is a read or write task for a channel. The memory mapping manager 218 may check the overall memory usage and the memory usage of the channel. The channel memory usage may refer to active memory usage, such as a busy storage unit assigned to the channel. The overall memory usage may be the sum of all channel memory usages. It should be noted that when a storage unit is in a busy state, the mapping information indicates the current memory usage of the storage unit. However, if a storage unit is reserved, it can only be used according to the mapping information. In addition, in some cases, the mapping entry may be different from the active state. For example, the memory map may indicate the pre-allocated state of the storage unit (e.g., pre-allocating CH0 for decoding). Then, unless the QoS monitor 210 or the memory mapping manager 218 changes the mapping entry, the decoding task (e.g., CH0 decoding task) has a higher priority and can use the storage unit.

[0031] In some embodiments, a queue may be implemented in the memory mapping component 206 so that when a request is received, the memory mapping manager 218 may compare the storage request with any existing request in the queue. If the storage request does not need to be executed immediately (e.g., not a high priority), the memory mapping manager 218 may add the request to the queue. If the memory mapping manager 218 determines that the request needs to be executed immediately (e.g., a high priority), one or more storage units may be allocated to the channel in view of the availability of one or more empty storage units. In some embodiments, the memory mapping component 206 may also maintain an active status (Active Status) for each of the multiple storage units of the memory 208. For example, in one embodiment, the memory mapping manager 218 may maintain a data store including multiple active status entries. Each active status entry may be an active bit corresponding to a storage unit to indicate whether the storage unit is idle or busy. If there are available storage units to be allocated, the memory mapping manager 218 may allocate one or more storage units to the channel and update the mapping entries corresponding to the one or more allocated storage units. The allocated one or more storage units may be issued to a read control block or a write control block (e.g., an encoding task control 212 and a decoding task control 214).

[0032] An exemplary memory release workflow implemented by the memory mapping manager 218 may begin with the memory mapping manager 218 receiving a storage release request for an allocated storage unit from a read control block or a write control block. The memory mapping manager 218 may clear the memory mapping entry corresponding to the allocated storage unit and update the overall memory availability.

[0033] Figure 3ASchematically illustrates a single channel memory map according to one embodiment of the present disclosure. Memory cells 302.1 to 302.4 may be part of memory 208. Two memory cells 302.1 and 302.2 may be assigned to a channel for read tasks, denoted as CH_0 306. Memory cell 302.1 may hold a codeword denoted as CW1 CH_0 from CH_0 306, and memory cell 302.2 may hold another codeword denoted as CW2 CH_0 from CH_0. Two memory cells 302.3 and 302.4 may be assigned to another channel for read tasks, denoted as CH_1 308. Memory cell 302.3 may hold a codeword denoted as CW1 CH_1 from CH_1 308, and memory cell 302.4 may hold another codeword denoted as CW2 CH_1 from CH_1. The allocation status of the memory cells 302.1 to 302.4 can be indicated by the mapping entries 304.1 to 304.4, respectively. In an embodiment with an exemplary mapping entry structure {FMT, MODE, CH}, the memory mapping entries 304.1 and 304.2 can have an FMT field indicating a single channel with "00", a decoded MODE field with "00", and a CH field indicating CH_0 306 with "00". The memory mapping entries 304.3 and 304.4 can have an FMT field indicating a single channel with "00", a decoded MODE field with "00", and a CH field indicating CH_1 308 with "01". Therefore, the codewords in the memory cells 302.1 to 302.4 are single channel codewords. That is, each codeword in the memory cells 302.1 to 302.4 is from a channel.

[0034] Figure 3B Schematically illustrates cross-channel memory mapping according to an embodiment of the present disclosure. Figure 3A on the contrary, Figure 3B Each memory cell 302.1 to 302.4 in may be assigned a read task from a virtual channel, which may include physical channels CH_0 306 and CH_1 308. Figure 3B As shown, each of the memory cells 302.1 to 302.4 can accommodate a codeword, half of which is read from CH_0 306 and the other half is read from CH_1 308. For example, Figure 3B The storage unit 302.1 shown in FIG. 3 may contain a code word CW3, wherein half of the code word CW3 comes from CH_0 306 and the other half comes from CH_1 308; Figure 3B The storage unit 302.3 shown may contain a codeword CW4, half of which comes from CH_0 306 and the other half from CH_1 308; Figure 3BThe storage unit 302.2 shown may contain a codeword CW5, half of which comes from CH_0 306 and the other half from CH_1 308; Figure 3B The illustrated memory cell 302 . 4 may contain a codeword CW6 , half of which comes from CH_0 306 and the other half from CH_1 308 .

[0035] In addition, if Figure 3B As shown, memory map entries 304.1 to 304.4 may each have an FMT field indicating a two-channel cross-channel codeword with "01", a MODE field indicating a decoded with "00", and a CH field indicating a channel ID of a virtual channel with "00". Therefore, the codewords in storage units 302.1 to 302.4 may be cross-channel codewords. That is, each codeword in storage units 302.1 to 302.4 is from a virtual channel that may include two channels. It should be noted that similar to the example of two channel codewords, 4-channel and all channel cross-channel codewords may be stored in a storage unit.

[0036] Figure 3A Single channel mapping and Figure 3B The cross-channel mapping can also be used for write tasks similar to read tasks, where codeword data enters the channel (or virtual channel) rather than coming out of the channel (or virtual channel).

[0037] Figure 44 is a flow chart of a process 400 for allocating memory according to one embodiment of the present disclosure. The process 400 may be implemented by an embodiment of the ECC processor 200 using hardware (e.g., a field programmable gate array (FPGA) or an application specific IC (ASIC)), firmware, or any suitable combination. In block 402, a storage request may be received. For example, when there is a read task or a write task for a channel, a storage request may be generated at a read control block or a write control block (e.g., an encoding task control 212 and a decoding task control 214) and sent to a mapping manager 218. In one embodiment, the storage request may be received at a QoS monitor 210, and the QoS monitor 210 may apply a quality of service check before the storage request may be forwarded to the mapping manager 218. In block 404, the overall memory usage and the memory usage of the channel associated with the storage request may be checked. In one embodiment, the memory mapping manager 218 may check the overall memory usage and the memory usage of the channel. In block 406, it may be determined that the storage request needs to be executed immediately and that a storage unit is available. For example, the memory mapping manager 218 may check with the QoS monitor 210 to determine that the storage request has a high priority and needs to be executed immediately and at least one storage unit may be available (e.g., free). In box 408, the available storage unit may be allocated. In box 410, the memory mapping entry corresponding to the allocated storage unit may be updated. In box 412, the allocated storage unit may be issued to a read control block or a write control block (e.g., an encoding task control 212 and a decoding task control 214). In one embodiment, the encoding task control 212 and the decoding task control 214 may have queues for pending read tasks and write tasks, and the issued storage unit may be used to complete one of the read tasks or the write tasks.

[0038] According to the embodiments of the present disclosure, flexible memory mapping can be implemented to minimize the total physical memory required in the ECC architecture. For example, in a traditional ECC architecture with an n-stage (n is a positive integer greater than 1) pipeline design, in order to support the throughput required for reading and writing, the encoding or decoding path of each channel requires n codeword (CW) buffers (e.g., n storage units), so each channel of the traditional ECC architecture requires a total of 2n CW buffers. However, an embodiment using flexible memory mapping may only require n CW buffers to support the read and write throughput required for each channel. For example, the NVM may be in a read or write state, but not in both states at the same time. These n CW buffers can be mapped to the encoding path or the decoding path according to usage requirements, and a 50% memory usage saving for each channel can be achieved.

[0039] In some embodiments, usage requirements can be determined and met through QoS monitoring. Through flexible memory mapping, physical memory can be mapped and remapped for different purposes in different scenarios. Performance can be improved based on usage and usage priority. In addition, data movement from one memory location to another in a conventional ECC architecture is made unnecessary and can be completely avoided. ECC throughput can be increased and power consumption can be reduced. For example, in an ECC architecture with multiple decoders, a codeword that fails to be decoded by one decoder is typically retried by another decoder, and the codeword must be moved to the corresponding decoder buffer to continue decoding in the conventional ECC architecture. At a CW decoding failure rate of 10%, this data movement may result in a throughput loss of approximately 2-3% in a conventional ECC architecture. In an embodiment according to the present disclosure, data movement due to switching between different decoders is unnecessary and avoidable.

[0040] In an exemplary embodiment, an apparatus is provided that may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile memory devices, a memory including a plurality of storage units, a mapping memory including a plurality of mapping entries to indicate allocation status of the plurality of storage units, and a memory mapping manager. The plurality of storage units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager is configured to control allocation of the plurality of storage units and set allocation status in the plurality of mapping entries.

[0041] In one embodiment, the device may further include an encoding task control. The ECC engine includes at least one ECC encoder, and the encoding task control is configured to control a write task and provide a set of one or more storage units in the plurality of storage units to the at least one ECC encoder and the multi-channel interface to complete the write task.

[0042] In one embodiment, the apparatus may further include a decoding task control. The ECC engine includes at least one ECC decoder, and the decoding task control is configured to control a read task and provide a set of one or more storage units in the plurality of storage units to the at least one ECC encoder and the multi-channel interface to complete the read task.

[0043] In one embodiment, the apparatus may further include an encoding task control, a decoding task control, and a QoS monitor configured to determine a memory map update. The ECC engine includes at least one ECC encoder and at least one ECC decoder, the encoding task control is configured to control a write task and provide a first set of one or more storage units in the plurality of storage units to the at least one ECC encoder and the multi-channel interface to complete the write task, and the decoding task control is configured to control a read task and provide a second set of one or more storage units in the plurality of storage units to the at least one ECC decoder and the multi-channel interface to complete the read task.

[0044] In one embodiment, the QoS monitor is configured to determine the memory mapping update based on one or more conditions selected from the following group of conditions: the total number of pending read tasks, the total number of pending write tasks, the next expected task from the one or more non-volatile memory devices, pending retry tasks, idle channels, 4K random reads, traffic congestion, and sequential writes.

[0045] In one embodiment, the memory mapping manager can be further configured to receive a storage request for a read task or a write task of a channel, check the overall memory usage and the memory usage of the channel, determine that the storage request needs to be executed immediately and one of the multiple storage units is available, and allocate the storage unit to the channel; update the memory mapping entry corresponding to the storage unit and publish the storage unit to the encoding or decoding task control.

[0046] In one embodiment, the memory mapping manager may be further configured to receive a storage release request for an already allocated storage unit from the encoding or decoding task control, clear the memory mapping entry corresponding to the already allocated storage unit, and update the overall memory usage.

[0047] In one embodiment, a memory map entry of the plurality of memory map entries includes a first field indicating a cross-channel status, a second field indicating an operation mode, and a third field indicating a channel.

[0048] In one embodiment, the cross-channel status indicates whether a codeword in a corresponding storage unit is stored in one or more channels of the one or more non-volatile memory devices.

[0049] In one embodiment, when the codewords in the corresponding storage unit are stored in a plurality of channels, the third field indicates a virtual channel including two or more channels.

[0050] In one embodiment, the apparatus may further include an activity state memory for storing an activity state of each of the plurality of storage units, wherein the memory mapping manager is further configured to allocate storage units among the plurality of storage units based on the activity state of the storage unit.

[0051] In one embodiment, the ECC engine includes a first ECC decoder and a second ECC decoder, and the memory mapping manager is further configured to dynamically map storage units allocated to the first ECC decoder to the second ECC decoder by setting corresponding memory mapping entries.

[0052] In another exemplary embodiment, a method is provided, comprising: receiving a storage request for a read task or a write task for a channel from an encoding task control or a decoding task control, checking the overall memory usage and the memory usage of the channel, determining that the storage request needs to be executed immediately and a storage unit among the multiple storage units is available, allocating the storage unit to the channel, updating a memory map entry corresponding to the storage unit, and publishing the storage unit to the encoding task control or the decoding task control.

[0053] In one embodiment, the method may further include: maintaining a write task queue for write tasks, maintaining a read task queue for read tasks, and determining a memory mapping update by using one or more conditions selected from the following group of conditions, the criteria including: a total number of pending read tasks, a total number of pending write tasks, a next expected task from one or more non-volatile memory devices, a pending retry task, an idle channel, 4K random reads, traffic congestion, and sequential writes.

[0054] In one embodiment, the method may further include: receiving a storage release request for an already allocated storage unit from the encoding task control or the decoding task control, clearing a memory map entry corresponding to the already allocated storage unit, and updating overall memory usage.

[0055] In one embodiment, the memory map entry includes a first field indicating a cross-channel status, a second field indicating an operation mode, and a third field indicating an identifier of the channel.

[0056] In one embodiment, the cross-channel status indicates whether the codeword in the storage unit is stored in one or more channels of the one or more non-volatile memory devices.

[0057] In one embodiment, when the codewords in the storage unit are stored in a plurality of channels, the third field indicates a virtual channel including two or more channels.

[0058] In one embodiment, the method may further include: maintaining an activity state of the storage unit, wherein the storage unit is available when its activity state is idle.

[0059] In one embodiment, the method may further include: dynamically mapping the storage unit allocated to the first ECC decoder to the second ECC decoder by setting a corresponding memory mapping entry.

[0060] In one embodiment, the method may further include: determining that the channel is blocked in read data transfer or write data transfer due to insufficient memory, and mapping more storage units to the channel to reduce channel blocking.

[0061] In one embodiment, the method may further include determining that the channel releases one or more allocated storage units to reduce channel congestion, and remapping the one or more storage units to another task to allow the other task to start transmission immediately.

[0062] Any disclosed methods and operations may be implemented as computer-executable instructions (e.g., software code of the operations described herein) stored on one or more computer-readable storage media (e.g., non-transitory computer-readable media, such as one or more optical disk media, volatile storage components (e.g., DRAM or SRAM), or non-volatile storage components (e.g., hard disk drives)) and executed on a device controller (e.g., firmware executed by an ASIC). Any computer-executable instructions for implementing the disclosed techniques and any data created and used during implementation of the disclosed embodiments may be stored on one or more computer-readable media (e.g., non-transitory computer-readable media).

[0063] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

Claims

1. A method, characterized in that include: receiving a storage request for a read task or a write task of a channel from an encoding task control or a decoding task control; Check overall memory usage and memory usage of said channel; determining that the storage request needs to be executed immediately and a storage unit in the plurality of storage units is available; assigning the storage unit to the channel; Updating a memory map entry corresponding to the storage unit; as well as The storage unit is published to the encoding task control or the decoding task control.

2. The method according to claim 1, characterized in that Also includes: Maintain the write task queue for write tasks; Maintain the read task queue for read tasks; as well as A memory map update is determined by using one or more conditions selected from the following group of conditions: a total number of pending read tasks, a total number of pending write tasks, a next expected task from one or more non-volatile memory devices, a pending retry task, an idle channel, 4K random reads, traffic congestion, and sequential writes.

3. The method according to claim 1, characterized in that Also includes: receiving a storage release request for an already allocated storage unit from the encoding task control or the decoding task control; clearing the memory map entry corresponding to the allocated storage unit; and Updates overall memory usage.

4. The method according to claim 1, characterized in that The memory map entry includes a first field indicating a cross-channel status, a second field indicating an operation mode, and a third field indicating an identifier of the channel.

5. The method according to claim 4, characterized in that The cross-channel status indicates whether a codeword in the storage unit is stored in one or more channels of the one or more non-volatile memory devices.

6. The method according to claim 5, characterized in that When the codewords in the storage unit are stored in a plurality of channels, the third field indicates a virtual channel including two or more channels.

7. The method according to claim 1, characterized in that Also includes: An activity state of the storage unit is maintained, wherein the storage unit is available when its activity state is idle.

8. The method according to claim 1, characterized in that Also includes: The storage unit allocated to the first ECC decoder is dynamically mapped to the second ECC decoder by setting the corresponding memory mapping entry.

9. The method according to claim 1, characterized in that Also includes: determining that the channel is blocked on a read data transfer or a write data transfer due to insufficient memory; as well as More memory cells are mapped to the channel to reduce channel congestion.

10. The method according to claim 9, characterized in that Also includes: determining that the channel releases one or more allocated storage units to reduce channel congestion; as well as The one or more storage units are remapped to another task to allow the other task to immediately begin transferring.

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