Debugging subsystem and method based on JTAG interface
By dividing the control interface and data interface on the JTAG interface and adopting a high bandwidth debugging mode, the problem of low data transmission rate in FPGA debugging is solved, efficient data transmission and resource conservation is achieved, and security in complex environments is enhanced.
Patent Information
- Application Number
- CN202510003281.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-09
AI Technical Summary
During the FPGA debugging process, due to the speed limitations of the standard JTAG interface and the host polling model, the debugging data transmission rate is low, which cannot meet the real-time transmission requirements. The use of too much SRAM resources will reduce the clock frequency, resulting in unsatisfied timing or exhausted resources.
By dividing the control interface and data interface on the JTAG interface, the special rate and encoding optimization of the data interface are used to switch to the high bandwidth debugging mode, efficient transmission of the data interface is achieved, and high-frequency clock is provided through the data multiplexing module and the phase-locking loop.
It improves the transmission rate and efficiency of debugging data, decouples the timing of the serial interface and the JTAG timing, reduces the occupation of SRAM resources, and enhances the security in complex electromagnetic environments.
Smart Images
Figure CN119962451A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip debugging technology, and in particular to a debugging subsystem and method based on a JTAG interface. Background Art
[0002] As chip integration and clock speed increase, the amount of data that needs to be processed during FPGA debugging also increases. For FPGA debugging conditions, if a circuit operates at a frequency of 100MHz and captures a single-bit signal, a data stream of up to 100Mbps will be generated. However, due to the dual-edge design and single-ended signal transmission limitations of the standard JTAG interface, its communication rate is usually limited to less than 50Mbps. In addition, the JTAG debug access point (TAP) cannot actively send requests to the debug host (DebugHost), which means that the host must constantly poll the debug interface to obtain the latest status information of the device under test, which causes a large overhead on the host processor resources and I / O bus bandwidth.
[0003] At present, the on-chip logic analyzer (CWC) of FPGA can only transmit debug data through the JTAG interface. However, due to the speed limitation of the JTAG interface mentioned above, it cannot meet the demand for real-time transmission of debug data. Therefore, the traditional on-chip logic analyzer of FPGA must occupy the static random access memory (SRAM) on the chip to buffer the captured data and send this data to the host when the debug host requests it. In order to expand the observation window, more SRAM resources are required. However, since the SRAM in FPGA is designed in blocks, occupying too many SRAM resources will reduce the clock frequency of the logic under test. If the timing requirements or resource occupancy in the design are already in a tight state, then the integrated CWC may cause the timing to fail to meet the requirements or exhaust all available on-chip SRAM resources. This may cause the circuit to not work properly or the layout and routing stage to fail. For the traditional virtual IO interface (VIO), all control signals related to IO flipping are sent down through the JTAG interface by the host computer, and the flip rate of virtual IO will also be limited by the bandwidth of the JTAG interface. This will limit the rate at which users can use virtual IO to send debug signal vectors to the device under test. Summary of the invention
[0004] To this end, the embodiments of the present application provide a debugging subsystem and method based on a JTAG interface, thereby improving the transmission rate of debugging data.
[0005] In a first aspect, the present application provides a debugging subsystem based on a JTAG interface.
[0006] This application is achieved through the following technical solutions:
[0007] JTAG interface-based debugging subsystem, including:
[0008] A serial debug controller, a JTAG master state machine, a JTAG interface, a data multiplexing module and an IO function selector; the JTAG interface includes a control interface and a data interface, the control interface is a fixed-function interface, and the data interface is an interface that supports configuration switching; the JTAG master state machine is used to control the state of the JTAG interface;
[0009] The serial debug controller is configured to receive a debug configuration transmitted by a debug host, and send the debug configuration to the data multiplexing module during the debugging process;
[0010] The data multiplexing module is configured to receive debug data and transmit the debug data according to the debug configuration assigned by the serial debug controller;
[0011] The IO function selector is configured to determine a characteristic configuration of the data interface based on a debug mode.
[0012] In a preferred example of the present application, it can be further configured that the data multiplexing module includes: a debugging data hub, a serial encoder, a serial shifter, a serial decoder and a phase-locked loop;
[0013] The debug data hub is configured to receive debug control signals from the serial debug controller, collect debug data from the user debug controller, and transmit the debug data to the serial encoder;
[0014] The serial encoder is configured to encode the debug data and transmit the encoded debug data to the serial shifter;
[0015] The serial shifter is configured to transmit the encoded debug data to the serial decoder;
[0016] The serial decoder is configured to decode the debug data and transmit the decoded debug data to the virtual IO TAP;
[0017] The phase-locked loop is configured to provide a high-frequency clock to the debug data hub, serial encoder, serial shifter, and serial decoder.
[0018] In a preferred example of the present application, it can be further configured that the data clock source of the data interface link includes the on-link clock of the JTAG link, the clock of the processor subsystem, the clock driving the digital logic in the FPGA, a high-frequency homologous clock generated by multiplying the on-link clock of the JTAG link, or a user-defined clock.
[0019] In a preferred example of the present application, it can be further configured that the link coding strategy of the data multiplexing module adopts a DC-free component coding strategy.
[0020] In a preferred example of the present application, it can be further configured that the link coding strategy of the data multiplexing module includes at least one of an 8b / 10b coding strategy, a 64 / 66b coding strategy, a 128 / 130b coding strategy or a Manchester coding strategy.
[0021] In a preferred example of the present application, it can be further configured that the IO function selector is configured to determine the characteristic configuration of the data interface based on the debugging mode, including:
[0022] The device is configured to select functional characteristics of the data interface, wherein the functional characteristics are selected from at least one of traditional JTAG functions, logic analyzer capture data output, processor trace signal output, virtual IO interface signal input, and processor core semi-hosting interface input and output.
[0023] In a preferred example of the present application, it can be further configured that the IO function selector is configured to determine the characteristic configuration of the data interface based on the debugging mode, including:
[0024] The device is configured to select an electrical characteristic of a data interface, wherein the electrical characteristic is selected from at least one of a single-ended signal, a low voltage differential signal, a bidirectional low voltage differential signal, or a multi-level differential signal.
[0025] In a second aspect, the present application provides a debugging method based on a JTAG interface.
[0026] This application is achieved through the following technical solutions:
[0027] Writing the debugging configuration into the serial debugging controller of the debugged chip, the debugging configuration includes the configuration of the data pin, the frequency configuration of the phase-locked loop, the configuration of the data packaging format, the configuration of the data encoding format, the configuration of the debug bus transceiver time slot and the configuration of the bandwidth allocation strategy;
[0028] After the debug configuration is written, the debug host initiates a transfer task to the debugged chip through the JTAG interface;
[0029] After the internal phase-locked loop is locked and the data of the data recovery circuit is locked, the JTAG interface is switched to the high-bandwidth debugging mode through the JTAG master state machine, and the debugging subsystem exchanges data with the debugging software in the host computer through the high-bandwidth debugging mode according to the debugging configuration;
[0030] After debugging is completed, the debugging host sends an instruction to exit the high-bandwidth debugging mode through the JTAG interface to restore the debugged chip to a normal debugging state.
[0031] On the third aspect, the present application is realized through the following technical solutions:
[0032] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements any step of the above-mentioned debugging method based on a JTAG interface when executing the computer program.
[0033] In a fourth aspect, the present application provides a computer-readable storage medium.
[0034] This application is achieved through the following technical solutions:
[0035] A computer-readable storage medium stores a computer program, wherein the computer program implements any of the steps of the above-mentioned debugging method based on a JTAG interface when executed by a processor.
[0036] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:
[0037] The debugging subsystem provided in the present application divides the JTAG interface into a control interface and a data interface, and can perform special rate and coding optimization on the data interface, which is not restricted by the host polling transmission model in the JTAG protocol, thereby improving the transmission rate and efficiency; the timing of the serial interface and the JTAG timing are partially or completely decoupled, so the timing and data of the debugging interface do not need to be restricted by the timing of the JTAG interface; in addition, a DC-free encoding method is selected to facilitate clock recovery at the receiving end and electrical isolation, thereby improving safety in complex electromagnetic environments. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A schematic diagram of the structure of a debugging subsystem based on a JTAG interface provided in an embodiment of the present application;
[0039] Figure 2 A schematic diagram of the structure of a debugging subsystem based on a JTAG interface provided in yet another embodiment of the present application;
[0040] Figure 3 A flowchart of a debugging method based on a JTAG interface is provided as another embodiment of the present application. DETAILED DESCRIPTION
[0041] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make modifications to the present embodiment without any creative contribution as needed. However, as long as it is within the scope of the claims of the present application, it shall be protected by the patent law.
[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0043] In addition, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application, unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.
[0044] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with basically the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity and execution order.
[0045] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
[0046] First, the technical terms used in this application are explained:
[0047] FPGA (Field Programmable Gate Array): is an integrated circuit that allows users to configure and reconfigure hardware logic as needed;
[0048] JTAG (Joint Test Action Group) is an international standard test protocol mainly used for internal chip testing;
[0049] TDI (Test Data Input), used for inputting test data;
[0050] TDO (test data output), used for output of test data;
[0051] TMS (Test Mode Selection), used to select different test modes;
[0052] TCK (test clock input) is used to input the clock signal.
[0053] The embodiments of the present application are further described in detail below in conjunction with the drawings in the specification.
[0054] like Figure 1 As shown, a debugging subsystem based on a JTAG interface is provided for a first exemplary embodiment of the present application, and the debugging subsystem includes:
[0055] A serial debug controller, a JTAG master state machine, a JTAG interface, a data multiplexing module and an IO function selector; wherein the JTAG interface includes a control interface and a data interface, the control interface is a fixed-function interface, and the data interface is an interface that supports configuration switching; the JTAG master state machine is used to control the state of the JTAG interface; the serial debug controller is configured to receive a debug configuration transmitted by a debug host, and to send the debug configuration to the data multiplexing module during the debugging process; the data multiplexing module is configured to receive debug data, and to transmit debug data according to the debug configuration assigned by the serial debug controller; the IO function selector is configured to determine the characteristic configuration of the data interface based on the debug mode.
[0056] Specifically, in order to be compatible with the original JTAG interface solution, the JTAG interface in this application has four signal interfaces of the traditional JTAG interface: test clock interface (TCK), test mode selection interface (TMS), test data input interface (TDI), and test data output interface (TDO). At the same time, these four interfaces support the control timing of the traditional JTAG interface, ensuring that the traditional debugging host can communicate with the JTAG interface of this application without obstacles. In order to solve the problem that the existing interface limits the debugging signal transmission rate, the JTAG interface in this application is improved on the basis of the existing traditional interface and divided into two interfaces, one of which is a control interface, which is a fixed-function interface and cannot change its function, including a test clock interface (TCK) and a test mode selection interface (TMS); the second is a data interface, which is uniformly used as a data interface for debugging data transmission, outputting the debugging data specified by the user in a specific format, and the data interface supports configuration switching, including a test data input interface (TDI), a test data output interface (TDO) and a spare interface. Specifically, after the data interface completes the interface feature configuration through JTAG signaling and enters a specific debugging mode, it will switch from being controlled by the JTAG master state machine to being controlled by the debug data controller. The corresponding data interface will conduct bidirectional interaction of debugging data with the debugging host at a rate higher than the JTAG JTCK clock (several to dozens of times).
[0057] In the debugging subsystem of the present application, the JTAG interface is divided into a control interface and a data interface, and the data interface can be specially optimized for rate and encoding, and is not limited by the host polling transmission model in the JTAG protocol, thereby improving the transmission rate and efficiency.
[0058] The second exemplary embodiment of the present application provides a debugging subsystem based on the JTAG interface, which is further improved on the basis of the first exemplary embodiment, such as Figure 2 As shown, the specific improvements are as follows: the data multiplexing module includes: a debugging data hub, a serial encoder, a serial shifter, a serial decoder and a phase-locked loop;
[0059] The debug data hub is configured to receive debug control signals from the serial debug controller, collect debug data from the user debug controller, and transmit the debug data to the serial encoder; the serial encoder encodes the debug data and transmits the encoded debug data to the serial shifter; the serial shifter transmits the encoded debug data to the serial decoder, which decodes the debug data and transmits it to the virtual IO TAP (Test Access Port); the phase-locked loop is configured to provide a high-frequency clock for the debug data hub, the serial encoder, the serial shifter, and the serial decoder. Typically, under the condition of using 8b / 10b encoding, the phase-locked loop in the system generates clocks according to the ratio of JTCK: debug parallel clock: high-speed serial clock (1:N:10*N).
[0060] The third exemplary embodiment of the present application provides a debugging subsystem based on a JTAG interface, which is further improved on the basis of the first exemplary embodiment of the present application, and the specific improvements are as follows: the data clock source of the data interface link includes the JTAG link's on-link clock, the processor subsystem's clock, the clock driving the digital logic in the FPGA, a high-frequency homologous clock generated by multiplying the JTAG link's on-link clock, or a user-defined clock. The above improvements can make the debugging subsystem more flexible to adapt to different debugging requirements and debugging environments, and select a more suitable clock source according to specific application scenarios. When debugging tasks need to process large amounts of data, a high-frequency clock can be used to provide a higher data transmission rate. The serial interface timing of the debugging subsystem is partially or completely decoupled from the JTAG timing, so the timing and data of the debugging interface do not need to be limited by the JTAG interface timing.
[0061] The fourth exemplary embodiment of the present application provides a debugging subsystem based on the JTAG interface, which is further improved on the basis of the second exemplary embodiment of the present application, and the specific improvements are as follows: the link coding strategy of the data multiplexing module adopts a DC-free coding strategy. The DC-free coding strategy helps to reduce the DC component in the signal and can reduce the dependence on clock synchronization. Since the traditional JTAG uses a clock-associated design that requires the delay of the entire system link to be no greater than half of the clock cycle, the traditional JTAG has a low tolerance for delays. At the same time, inserting a digital isolator in the link will insert a delay, which will greatly reduce the communication rate. In the face of this situation, the use of a DC-free coding strategy facilitates the recovery of the clock and signal transformer at the receiving end for digital isolation, while also reducing system complexity and providing an easy electrical isolation solution for systems that require electrical isolation.
[0062] The fifth exemplary embodiment of the present application provides a debugging subsystem based on the JTAG interface, which is further improved on the basis of the fourth exemplary embodiment of the present application, and the specific improvements are as follows: the link coding strategy of the data multiplexing module adopts at least one of the 8b / 10b coding strategy, the 64 / 66b coding strategy, the 128 / 130b coding strategy or the Manchester coding strategy. The 8b / 10b coding strategy encodes 8 bits of data into 10 bits by adding an additional 2 bits of coding, so as to facilitate clock recovery and data error detection in high-speed serial communication. The 64 / 66b coding strategy is to add 2 bits of data to the front of the 64-bit data or control information and encode it into 66 bits of data. The 128 / 130b coding strategy is to add a 2-bit synchronization header to the front of the 128-bit Payload to form a 130-bit data block. This coding method can significantly improve bandwidth utilization. Another feasible way is that the link coding strategy in the data multiplexing module adopts the Manchester coding strategy. There is a level jump in the middle of each data bit of the Manchester coding, which allows the receiving end to use these jumps to recover the clock signal and achieve clock synchronization. During the debugging process, in the case of a waiting state or the need for a master-slave handshake or when the user selects multiple alternative functions in the same debugging interface, in order to distinguish different debugging data sources or logic states in these cases, a DC-free encoding strategy is used to encode different data boundary codewords. Selecting a DC-free encoding method facilitates clock recovery at the receiving end, facilitates electrical isolation, and improves safety in complex electromagnetic environments.
[0063] Preferably, the serial encoder may use 8b / 10b coded K code when encoding the debug data.
[0064] Preferably, the serial encoder may use XYZ encoding of Manchester encoding when encoding the debugging data.
[0065] The sixth exemplary embodiment of the present application provides a debugging subsystem based on a JTAG interface, which is further improved on the basis of the first exemplary embodiment of the present application, and the specific improvements are as follows:
[0066] The IO function selector is configured to determine the characteristic configuration of the data interface based on the debugging mode, including: being configured to select the functional characteristics of the data interface, the functional characteristics being selected from at least one of the traditional JTAG function, the logic analyzer capture data output, the processor trace signal output, the virtual IO interface signal input, and the processor core semi-hosted interface input and output. The processor may be a hard processor core that has been solidified, or a soft processor core that exists in the form of FPGA soft logic.
[0067] The seventh exemplary embodiment of the present application provides a debugging subsystem based on the JTAG interface, which is further improved on the basis of the first exemplary embodiment of the present application, and the specific improvements are as follows: the IO function selector is configured to determine the characteristic configuration of the data interface based on the debugging mode, including: being configured to select the electrical characteristics of the data interface, and the electrical characteristics are selected from at least one of a single-ended signal, a low-voltage differential signal, a bidirectional low-voltage differential signal or a multi-level differential signal. Among them, the low-voltage differential signal includes but is not limited to LVDS, LVPECL (low voltage positive emitter coupled logic), and a low-voltage differential signal of the CML level standard, the bidirectional low-voltage differential signal includes but is not limited to a bidirectional low-voltage differential signal with echo cancellation, and the multi-level differential signal includes but is not limited to a multi-level differential signal of MLT-3 and PAM4. The data interface can select a single-ended data transmission scheme or a differential data transmission scheme. The former can reduce the requirements for debugging cables and circuit board drawing, and the latter can achieve maximized debugging bandwidth and easy-to-implement interface electrical isolation.
[0068] The eighth exemplary embodiment of the present application provides a debugging method based on a JTAG interface, which is executed based on the debugging subsystem provided by the first to seventh exemplary embodiments described above. Figure 3 As shown, the method includes:
[0069] S10: writing the debugging configuration into the serial debugging controller of the debugged chip, the debugging configuration including the configuration of the data pin, the frequency configuration of the phase-locked loop, the configuration of the data packaging format, the configuration of the data encoding format, the configuration of the debug bus transceiver time slot and the configuration of the bandwidth allocation strategy;
[0070] Specifically, the debugging host writes the debugging configuration into the serial debugging controller of the debugged chip through the debugging cable according to the JTAG specific access sequence. The debugging configuration includes but is not limited to selecting the interface for input and output of debugging data, specifically the multiplexing of the test data input interface (TDI) and the test data output interface (TDO), the selection of the spare interface, and setting the level standard adopted by each interface, setting the output frequency of the phase-locked loop, setting the data packaging format during the debugging data transmission process, setting the data encoding format, setting the debug bus receiving and transmitting time slot, and setting the bandwidth allocation strategy. It should be noted that the chip to be debugged can be an FPGA chip or an FPSoC chip.
[0071] S20: After the debugging configuration is written, the debugging host initiates a transmission task to the debugged chip through the JTAG interface.
[0072] Specifically, after completing the configuration of the debugging subsystem, the debugging host can initiate a transmission task to the debugged chip through the JTAG interface, including but not limited to downloading the code stream of the FPGA subsystem inside the debugged chip, debugging control of the processor subsystem, and firmware downloading. This step only involves the interaction between the JTAG master state machine and the traditional TAP, which can be regarded as an operation of waiting for the phase-locked loop inside the debugging subsystem to lock to a frequency that is a multiple of the JTCK signal. In this step, any JTAG operation on the target chip is completed except for the operation on the serial debugging controller.
[0073] S30: After the internal phase-locked loop is locked and the data of the data recovery circuit is locked, the JTAG interface is switched to the high-bandwidth debugging mode through the JTAG master state machine, and the debugging subsystem exchanges data with the debugging software in the host computer through the high-bandwidth debugging mode according to the debugging configuration.
[0074] Specifically, after the phase-locked loop inside the debugging subsystem is locked to a frequency that is a multiple of the JTCK signal and the data of the data recovery circuit is locked, the JTAG interface is switched to high-bandwidth debugging mode through the JTAG master state machine, and the debugging subsystem interacts with the debugging software in the host computer according to the allocated time slots and bandwidth allocation strategy in the debugging configuration.
[0075] In step S30, the serial debug controller collects the debug data uploaded by the user debug controller from the debug data hub according to the bandwidth allocation strategy given by the user, adds the debug data frame header for marking the data source and data format to the debug data, obtains the debug data packaged with the header, and transmits it to the serial encoder through the debug data FIFI memory. The serial encoder encodes the debug data according to the DC-free encoding strategy specified by the serial debug controller to generate a DC-balanced data stream, and transmits the data stream to the serial decoder through the serial shifter. The serial decoder decodes the data stream according to the inverse process of the specified DC-free encoding strategy, and transmits it to the virtual IO TAP after decoding. In this step, the user completes the transfer of debug data between the debug host (also called the host computer) and the debugged chip through the debug subsystem. For example, the software debug tracking program of the debug host transfers the tracking data, sends the waveform capture data to the CWC host computer, and sends the virtual IO waveform data to the debugged chip.
[0076] S40: After the debugging is completed, the debugging host sends an instruction to exit the high-bandwidth debugging mode through the JTAG interface to restore the debugged chip to a normal debugging state.
[0077] Specifically, the high-bandwidth debugging mode of the debugged chip is exited through JTAG signaling, and the debugging subsystem is reconfigured. After the debugging subsystem is closed, the JTAG clock output can be safely stopped and the access to the JTAG TAP and the high-bandwidth debugging subsystem can be terminated. This process is the reverse process of step S10, and is also implemented by the debugging host (host computer) operating JTAG through the debugging cable.
[0078] The specific definition of the debugging method based on the JTAG interface provided in this embodiment can be found in the embodiment of the debugging subsystem based on the JTAG interface above, and will not be repeated here. Each module in the above debugging subsystem can be implemented in whole or in part by software, hardware, and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.
[0079] An embodiment of the present application provides a computer device, which may include a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the processor executes the steps of the debugging method based on the JTAG interface as in any of the above embodiments.
[0080] The embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the debugging method based on the JTAG interface as in any of the above embodiments are implemented. Wherein, the computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive and / or a memory stick (Memory Stick), etc., and the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The working process, working details and technical effects of the computer-readable storage medium provided in this embodiment can be found in the above embodiment of the debugging method based on the JTAG interface, which will not be repeated here.
[0081] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
[0082] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0083] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system described in the present application is divided into different functional units or modules to complete all or part of the functions described above.
Claims
1. A debugging subsystem based on the JTAG interface, characterized in that: include: A serial debug controller, a JTAG master state machine, a JTAG interface, a data multiplexing module and an IO function selector; the JTAG interface includes a control interface and a data interface, the control interface is a fixed-function interface, and the data interface is an interface that supports configuration switching; the JTAG master state machine is used to control the state of the JTAG interface; The serial debug controller is configured to receive a debug configuration transmitted by a debug host, and send the debug configuration to the data multiplexing module during the debugging process; The data multiplexing module is configured to receive debug data and transmit the debug data according to the debug configuration assigned by the serial debug controller; The IO function selector is configured to determine a characteristic configuration of the data interface based on a debug mode.
2. The JTAG interface-based debugging subsystem according to claim 1, characterized in that: The data multiplexing module includes: a debugging data hub, a serial encoder, a serial shifter, a serial decoder and a phase-locked loop; The debug data hub is configured to receive debug control signals from the serial debug controller, collect debug data from the user debug controller, and transmit the debug data to the serial encoder; The serial encoder is configured to encode the debugging data and transmit the encoded debugging data to the serial shifter; The serial shifter is configured to transmit the encoded debug data to the serial decoder; The serial decoder is configured to decode the debug data and transmit the decoded debug data to the virtual IOTAP; The phase-locked loop is configured to provide a high-frequency clock to the debug data hub, serial encoder, serial shifter, and serial decoder.
3. The debugging subsystem based on the JTAG interface according to claim 1, characterized in that: The data clock sources of the data interface link include the JTAG link clock, the processor subsystem clock, the clock driving the digital logic in the FPGA, the high-frequency homologous clock generated by multiplying the JTAG link clock, or the user-defined clock.
4. The JTAG interface-based debugging subsystem according to claim 2, characterized in that: The link coding strategy of the data multiplexing module adopts a DC-free coding strategy.
5. The JTAG interface-based debugging subsystem according to claim 4, characterized in that: The link coding strategy of the data multiplexing module includes at least one of an 8b / 10b coding strategy, a 64 / 66b coding strategy, a 128 / 130b coding strategy or a Manchester coding strategy.
6. The JTAG interface-based debugging subsystem according to claim 1, characterized in that: The IO function selector is configured to determine a characteristic configuration of the data interface based on the debugging mode, including: The device is configured to select functional characteristics of the data interface, wherein the functional characteristics are selected from at least one of traditional JTAG functions, logic analyzer capture data output, processor trace signal output, virtual IO interface signal input, and processor core semi-hosting interface input and output.
7. The JTAG interface-based debugging subsystem according to claim 1, characterized in that: The IO function selector is configured to determine a characteristic configuration of the data interface based on the debugging mode, including: The device is configured to select an electrical characteristic of a data interface, wherein the electrical characteristic is selected from at least one of a single-ended signal, a low voltage differential signal, a bidirectional low voltage differential signal, or a multi-level differential signal.
8. A debugging method based on a JTAG interface, characterized in that: The debugging method is applied to the debugging subsystem based on the JTAG interface according to any one of claims 1 to 7, comprising: Writing the debugging configuration into the serial debugging controller of the debugged chip, the debugging configuration includes the configuration of the data pin, the frequency configuration of the phase-locked loop, the configuration of the data packaging format, the configuration of the data encoding format, the configuration of the debug bus transceiver time slot and the configuration of the bandwidth allocation strategy; After the debug configuration is written, the debug host initiates a transfer task to the debugged chip through the JTAG interface; After the internal phase-locked loop is locked and the data of the data recovery circuit is locked, the JTAG interface is switched to the high-bandwidth debugging mode through the JTAG master state machine, and the debugging subsystem exchanges data with the debugging software in the host computer through the high-bandwidth debugging mode according to the debugging configuration; After debugging is completed, the debugging host sends an instruction to exit the high-bandwidth debugging mode through the JTAG interface to restore the debugged chip to a normal debugging state.
9. A computer device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method according to claim 8.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to claim 8 are implemented.