Mask generation model training method and device, computer equipment and storage medium

Abstract

The invention discloses a mask generation model training method and device, computer equipment and a storage medium, and belongs to the technical field of computers. The method comprises the following steps: acquiring a first sample chip layout and a level set of the first sample chip layout, wherein the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout; inputting the level set of the first sample chip layout into a mask generation model to obtain a level set of a first prediction mask output by the mask generation model; determining a first prediction mask based on the level set of the first prediction mask, and determining a wafer pattern obtained by photoetching by using the first prediction mask; and training a mask generation model based on the difference between the wafer pattern and the first sample chip layout. The photoetching knowledge can be learned in the training process of the mask generation model, and the accuracy of the mask generation model is ensured. And the mask can be predicted only by calling the trained mask generation model, so that the efficiency of the mask generation process is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a training method, apparatus, computer equipment, and storage medium for a mask generation model. Background Art

[0002] Photolithography technology refers to the process of transferring the pattern on the mask to the wafer. As the feature size of integrated circuits continues to shrink, the optical diffraction and optical proximity effects in the photolithography process become more and more obvious, resulting in a large difference between the pattern on the wafer etched through the mask and the pattern on the chip layout, which in turn affects the performance, production capacity and yield of the chip.

[0003] In the related art, the mask is optimized using pixel-based level set inverse lithography technology so that the pattern etched on the wafer by the optimized mask is consistent with the pattern on the chip layout. However, due to the large amount of pixel-level data, the complexity of this method is high and the mask generation process is inefficient. Summary of the invention

[0004] The embodiments of the present application provide a method, apparatus, computer device and storage medium for training a mask generation model, which can improve the efficiency of the mask generation process. The technical solution is as follows:

[0005] In one aspect, a method for training a mask generation model is provided, the method comprising:

[0006] Acquire a first sample chip layout and a level set of the first sample chip layout, wherein the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout;

[0007] Inputting the level set of the first sample chip layout into a mask generation model to obtain a level set of a first prediction mask output by the mask generation model, wherein the level set of the first prediction mask represents a contour line of a pattern in the first prediction mask;

[0008] Determine the first prediction mask based on the level set of the first prediction mask, and determine a wafer pattern obtained by performing lithography using the first prediction mask;

[0009] The mask generation model is trained based on the difference between the wafer pattern and the first sample chip layout.

[0010] On the other hand, a training device for a mask generation model is provided, the device comprising:

[0011] A first acquisition module is used to acquire a first sample chip layout and a level set of the first sample chip layout, wherein the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout;

[0012] A level set generation module, used for inputting the level set of the first sample chip layout into a mask generation model to obtain a level set of a first prediction mask output by the mask generation model, wherein the level set of the first prediction mask represents a contour line of a pattern in the first prediction mask;

[0013] a mask determination module, configured to determine the first prediction mask based on the level set of the first prediction mask;

[0014] A wafer pattern determination module, used to determine a wafer pattern obtained by photolithography using the first prediction mask;

[0015] The first training module is used to train the mask generation model based on the difference between the wafer pattern and the first sample chip layout.

[0016] Optionally, the first acquisition module is used to:

[0017] Obtaining the first sample chip layout;

[0018] For any coordinate point on the first sample chip layout, a level set value of the coordinate point is determined according to the positional relationship between the coordinate point and the pattern in the first sample chip layout, and the level set values ​​of multiple coordinate points on the first sample chip layout constitute the level set of the first sample chip layout.

[0019] Optionally, the first acquisition module is used to:

[0020] In the case where the coordinate point is located inside the pattern in the first sample chip layout, the inverse of the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout is determined as the level set value of the coordinate point;

[0021] In the case where the coordinate point is located outside the pattern in the first sample chip layout, determining the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout as the level set value of the coordinate point;

[0022] In the case where the coordinate point is located on the contour line of the pattern in the first sample chip layout, a target value is determined as the level set value of the coordinate point, and the target value is equal to 0.

[0023] Optionally, the level set of the first prediction mask includes level set values ​​of a plurality of coordinate points on the first prediction mask, and the mask determination module is configured to:

[0024] For any coordinate point on the first prediction mask, when the level set value of the coordinate point is not greater than 0, the pixel value of the coordinate point is determined to be 1; when the level set value of the coordinate point is greater than 0, the pixel value of the coordinate point is determined to be 0.

[0025] Optionally, the wafer pattern determination module is used to:

[0026] determining light intensity distribution parameters of the first prediction mask;

[0027] According to a lithography physical model, calculating the light intensity distribution parameters of the wafer pattern obtained under the condition of the light intensity distribution parameters of the first prediction mask, the lithography physical model is an algorithm model used to describe the lithography process; or, inputting the light intensity distribution parameters of the first prediction mask into a light intensity prediction model to obtain the light intensity distribution parameters on the wafer pattern output by the light intensity prediction model, the light intensity prediction model is a deep learning model used to predict the light intensity distribution in the lithography process;

[0028] The wafer pattern is determined based on the light intensity distribution parameter on the wafer pattern.

[0029] Optionally, the first training module is used to:

[0030] determining a first loss value based on a difference between the wafer pattern and the first sample chip layout;

[0031] Based on the first loss value, the mask generation model is trained so that the first loss value obtained based on the trained mask generation model is reduced.

[0032] Optionally, the first training module is used to:

[0033] Determine a defocus error, an exposure dose error, and an imaging error, wherein the defocus error represents an error between a focus and a standard focus during a photolithography process, the exposure dose error represents an error between an exposure dose of a photoresist during a photolithography process and a standard exposure dose, and the imaging error represents a difference between the wafer pattern and the first sample chip layout;

[0034] Based on the defocus error, the exposure dose error and the imaging error, the first loss value is determined, and the first loss value is positively correlated with the defocus error, the exposure dose error and the imaging error.

[0035] Optionally, the device further comprises:

[0036] The second acquisition module is used to acquire a level set of a first sample mask, where the first sample mask is used to obtain a level set corresponding to the first sample chip version through photolithography. Figure 1a wafer pattern consistent with the first sample mask, wherein the level set of the first sample mask represents the contour line of the pattern in the first sample mask;

[0037] The first training module is used to:

[0038] The mask generation model is trained based on the difference between the wafer pattern and the first sample chip layout, and the difference between the level set of the first predicted mask and the level set of the first sample mask.

[0039] Optionally, the first training module is used to:

[0040] Determining a first loss value based on a difference between the wafer pattern and the first sample chip layout;

[0041] determining a second loss value based on a difference between a level set of the first prediction mask and a level set of the first sample mask;

[0042] Performing a weighted summation of the first loss value and the second loss value to obtain a third loss value;

[0043] Based on the third loss value, the mask generation model is trained so that the third loss value obtained based on the trained mask generation model is reduced.

[0044] Optionally, the second acquisition module is used to:

[0045] Determining the level set of the first sample chip layout as a reference level set;

[0046] The following iterative process is performed on the reference level set: a reference mask is determined based on the reference level set, and a reference wafer pattern obtained by photolithography using the reference mask is determined; based on the difference between the reference wafer pattern and the first sample chip layout, the reference level set is adjusted so that the difference between the reference wafer pattern obtained based on the adjusted reference level set and the first sample chip layout is reduced;

[0047] In response to the iteration process satisfying an iteration end condition, the iteration process is stopped to obtain a level set of the first sample mask.

[0048] Optionally, the second acquisition module is used to:

[0049] determining a fourth loss value based on a difference between the reference wafer pattern and the first sample chip layout;

[0050] Based on the fourth loss value, the reference level set is adjusted so that a fourth loss value obtained based on the adjusted reference level set is reduced.

[0051] Optionally, the mask generation model is a pre-trained model, and the apparatus further includes a second training module, which is used to:

[0052] Obtain a level set of a second sample chip layout and a level set of a second sample mask, wherein the second sample mask is used to obtain a level set corresponding to the second sample chip layout by photolithography. Figure 1 The level set of the second sample chip layout represents the contour line of the pattern in the second sample chip layout, and the level set of the second sample mask represents the contour line of the pattern in the second sample mask;

[0053] Inputting the level set of the second sample chip layout into the mask generation model to obtain the level set of the second prediction mask output by the mask generation model, wherein the level set of the second prediction mask represents the contour of the pattern in the second prediction mask;

[0054] The mask generation model is pre-trained based on a difference between a level set of the second prediction mask and a level set of the second sample mask.

[0055] Optionally, the device further comprises a model using module, configured to:

[0056] Obtaining a level set of the target chip layout;

[0057] Inputting the level set of the target chip layout into the trained mask generation model to obtain the level set of the target mask output by the mask generation model;

[0058] The target mask is determined based on the level set of the target mask, and the target mask is used to obtain a target chip version through photolithography. Figure 1 Unique wafer patterning.

[0059] On the other hand, a computer device is provided, comprising a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the training method of the mask generation model as described in the above aspects.

[0060] On the other hand, a computer-readable storage medium is provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor to implement the operations performed by the training method of the mask generation model as described in the above aspects.

[0061] On the other hand, a computer program product is provided, including a computer program, wherein the computer program is loaded and executed by a processor to implement the operations performed by the training method of the mask generation model as described in the above aspects.

[0062] The solution provided by the embodiment of the present application is that during the training process of the mask generation model, the level set of the sample chip layout is input into the mask generation model, and the level set of the predicted mask is output. The predicted mask can be determined according to the level set of the predicted mask, and the predicted mask is the mask corresponding to the sample chip layout predicted by the model. Then, the wafer pattern obtained when the predicted mask is used for lithography is determined. The smaller the difference between the wafer pattern and the sample chip layout, the more accurate the mask predicted by the mask generation model. Therefore, the mask generation model can be trained based on the difference between the wafer pattern and the sample chip layout. Since the determination process of the wafer pattern depends on the lithography knowledge in the lithography process, the mask generation model can learn the lithography knowledge during the training process, thereby ensuring the accuracy of the mask generation model. Moreover, compared with the pixelated level set reverse lithography technology, the present application only needs to call the trained mask generation model to predict the mask, which reduces the complexity and improves the efficiency of the mask generation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0064] Figure 1 It is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0065] Figure 2 It is a flowchart of a method for training a mask generation model provided in an embodiment of the present application;

[0066] Figure 3 is a flowchart of another method for training a mask generation model provided in an embodiment of the present application;

[0067] Figure 4 It is a structural schematic diagram of a mask generation model provided in an embodiment of the present application;

[0068] Figure 5 It is a schematic diagram of the structure of an embedded network provided in an embodiment of the present application;

[0069] Figure 6 is a schematic diagram of the structure of an attention network provided in an embodiment of the present application;

[0070] Figure 7 is a flowchart of another method for training a mask generation model provided in an embodiment of the present application;

[0071] Figure 8 It is a flowchart of a pre-training method of a mask generation model provided in an embodiment of the present application;

[0072] Fig. 9 It is a system architecture diagram of a method for training a mask generation model provided in an embodiment of the present application;

[0073] Fig.10 is a flow chart of a mask generation method provided in an embodiment of the present application;

[0074] Fig.11 is a comparison diagram of a fault tolerance window of a photolithography process provided in an embodiment of the present application;

[0075] Fig.12 It is a structural schematic diagram of a training device for a mask generation model provided in an embodiment of the present application;

[0076] Fig.13 It is a structural schematic diagram of another mask generation model training device provided in an embodiment of the present application;

[0077] Fig.14 is a schematic diagram of the structure of a terminal provided in an embodiment of the present application;

[0078] Fig.15 It is a structural diagram of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0080] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of this application, a first sample chip layout may be referred to as a second sample chip layout, and similarly, a second sample chip layout may be referred to as a first sample chip layout.

[0081] Among them, at least one refers to one or more than one, for example, at least one coordinate point can be one coordinate point, two coordinate points, three coordinate points, or any other integer greater than or equal to one. Multiple refers to two or more than two, for example, multiple coordinate points can be two coordinate points, three coordinate points, or any other integer greater than or equal to two. Each refers to each of at least one, for example, each coordinate point refers to each coordinate point in the multiple coordinate points. If the multiple coordinate points are 3 coordinate points, each coordinate point refers to each coordinate point in the 3 coordinate points.

[0082] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals (including but not limited to signals transmitted between user terminals and other devices, etc.) involved in this application are all fully authorized by users or relevant parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0083] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0084] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0085] Computer vision (CV) is a science that studies how to make machines "see". To be more specific, it refers to using cameras and computers to replace human eyes to identify and measure targets, and further perform image processing so that the computer processes the images into images that are more suitable for human observation or transmission to instruments for detection. As a scientific discipline, computer vision studies related theories and technologies, and attempts to establish an artificial intelligence system that can obtain information from images or multi-dimensional data. Large model technology has brought important changes to the development of computer vision technology. Pre-trained models in the field of vision such as Swin-Transformer, ViT (Vision Transformer), V-MoE (Vision MoE), and MAE (Masked Auto Encoder) can be quickly and widely applied to downstream specific tasks after fine-tuning (Fine Tune). Computer vision technology generally includes image processing, image recognition, image semantic understanding, image retrieval, OCR (Optical Character Recognition), video processing, video semantic understanding, video content / behavior recognition, three-dimensional object reconstruction, 3D (3 Dimensions) technology, virtual reality, augmented reality, simultaneous positioning and mapping, and also includes common biometric recognition technology.

[0086] Machine Learning (ML) is a multi-disciplinary interdisciplinary subject involving probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory and other disciplines. It specializes in studying how computers simulate or implement human learning behavior to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental way to make computers intelligent. Its applications are spread across all areas of artificial intelligence. Machine learning and deep learning usually include artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and teaching learning. The pre-trained model is the latest development of deep learning, which integrates the above technologies.

[0087] Pre-training model (PTM), also known as cornerstone model or big model, refers to a deep neural network (DNN) with large parameters. It is trained on massive unlabeled data, and uses the function approximation ability of large-parameter DNN to extract common features from the data. After fine-tuning (Fine Tune), parameter-efficient fine-tuning (Parameter-Efficient Fine-Tuning, PEFT), prompt tuning (Prompt-Tuning) and other technologies, it is suitable for downstream tasks. Therefore, the pre-training model can achieve ideal results in few-shot or zero-shot scenarios. PTM can be divided into language models (ELMO, BERT, GPT), visual models (Swin-Transformer, ViT, V-MOE), speech models (VALL-E), multimodal models (ViBERT, CLIP, Flamingo, Gato), etc. according to the data modality processed. Among them, the multimodal model refers to a model that establishes two or more data modality feature representations. Pre-trained models are important tools for outputting artificial intelligence generated content (AIGC), and can also be used as a general interface to connect multiple specific task models.

[0088] The following will describe the training method of the mask generation model provided in the embodiment of the present application based on artificial intelligence technology and computer vision technology.

[0089] As the feature size of integrated circuits continues to shrink, optical diffraction and optical proximity effects in the lithography process become more and more obvious, resulting in a large difference between the pattern lithography on the wafer and the pattern on the chip layout through mask lithography, which in turn affects the performance, production capacity and yield of the chip. Resolution enhancement technology based on optical proximity correction (OPC) is an effective means to solve this problem. In order to further improve the imaging quality of the chip process, it is necessary to correct the mask of the chip. The level set inverse lithography technology (ILT) pixelates the mask pattern and optimizes the pixel value of the mask through optimization methods such as conjugate gradient descent to further improve the fidelity of the pattern on the wafer. The level set inverse lithography technology optimizes the pixel points of the mask. The amount of mask pixel data that needs to be optimized is large, and the calculation is also very time-consuming, which makes it difficult to directly apply it to the full chip mask optimization. In particular, as the process size of the chip is further shortened and the pattern becomes more complex, the required calculation time increases sharply, which becomes a major challenge for the widespread application of the level set inverse lithography technology. With the rapid development of artificial intelligence technology, machine learning methods have been applied to level set reverse lithography technology. The initial mask is generated using machine learning methods and then fine-tuned using level set reverse lithography. However, there is no embedded knowledge of lithography physics in the training process of the machine learning method, which results in low imaging quality of the generated initial mask, affecting the fidelity of the wafer pattern and the process window.

[0090] In an embodiment of the present application, the correction layer of the level set inverse lithography technology is integrated into the training framework of the mask generation model. In the forward propagation process of the mask generation model, the correction layer of the level set inverse lithography technology iteratively corrects the mask generated by the mask generation model according to the lithography knowledge. In the reverse propagation process, the weight of the mask generation model is corrected according to the gradient of the level set inverse lithography technology through the chain rule, so the trained mask generation model contains the lithography knowledge, improves the accuracy of the mask, and can achieve hundreds or thousands of times of acceleration compared to the level set inverse lithography technology.

[0091] The training method of the mask generation model provided in the embodiment of the present application can be used in a computer device. Optionally, the computer device is a terminal or a server. Optionally, the server is an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network) and big data and artificial intelligence platforms. Platform. Optionally, the terminal is a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, a smart terminal, etc., but is not limited to this.

[0092] In one possible implementation, the computer program involved in the embodiments of the present application may be deployed and executed on a computer device, or on multiple computer devices located at one location, or on multiple computer devices distributed at multiple locations and interconnected through a communication network. Multiple computer devices distributed at multiple locations and interconnected through a communication network can constitute a blockchain system.

[0093] In one possible implementation, the computer device used to train the mask generation model in the embodiment of the present application is a node in the blockchain system, which can store the trained mask generation model in the blockchain. Thereafter, the node or the node corresponding to other devices in the blockchain can generate a mask corresponding to the chip layout through the mask generation model.

[0094] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application, see Figure 1 , the implementation environment includes: a terminal 101 and a server 102. The terminal 101 and the server 102 are connected via a wireless or wired network. Optionally, the server 102 is used to train a mask generation model using the method provided in an embodiment of the present application, and send the trained mask generation model to the terminal 101, and the mask generation model is used to generate a mask corresponding to the chip layout. Subsequently, the terminal 101 generates a level set of the mask corresponding to the level set of the chip layout through the mask generation model, determines the mask according to the level set of the mask, and then uses the mask for lithography. Alternatively, after completing the training of the mask generation model, the server 102 generates a level set of the mask corresponding to the level set of the chip layout through the mask generation model, determines the mask according to the level set of the mask, and sends the generated mask to the terminal 101.

[0095] The training method of the mask generation model provided in the embodiment of the present application can be applied to any scenario where a mask generation model needs to be used to generate a mask.

[0096] For example, in the context of chip lithography, the training method of the mask generation model provided in the embodiment of the present application can be installed in computational lithography software. After designing the chip layout, the chip mask manufacturer calculates the level set of the chip layout, inputs the level set of the chip layout into the trained mask generation model, and the mask generation model outputs the predicted level set of the mask. The mask can be determined based on the level set of the mask, and then the mask is used to perform lithography on the wafer to obtain the same level set as the chip layout. Figure 1 The wafer pattern is consistent, and the wafer is subsequently cut and packaged into chips. The method provided in the embodiment of the present application can significantly improve the process window for generating masks. The process window can be understood as the tolerance for exposure dose and defocus during the lithography process, which significantly reduces the mask optimization time and computing cost, and provides a high-quality mask for the chip lithography process. The training method of the mask generation model provided in the embodiment of the present application can also be expanded to other aspects of integrated circuit design, such as chip performance detection, chip bad point detection, image segmentation and other fields.

[0097] Figure 2 is a flowchart of a method for training a mask generation model provided in an embodiment of the present application. The embodiment of the present application is executed by a computer device. Figure 2 , the method comprising:

[0098] 201. A computer device obtains a first sample chip layout and a level set of the first sample chip layout, where the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout.

[0099] The computer device obtains a first sample chip layout and a level set of the first sample chip layout, the first sample chip layout is a pattern expected to be obtained by photolithography, and the level set of the first sample chip layout represents a contour line of the pattern in the first sample chip layout.

[0100] 202. The computer device inputs the level set of the first sample chip layout into the mask generation model to obtain the level set of the first prediction mask output by the mask generation model, where the level set of the first prediction mask represents the contour of the pattern in the first prediction mask.

[0101] The mask generation model is used to generate a level set of masks based on a level set of a chip layout. A computer device inputs a level set of a first sample chip layout into the mask generation model, and the mask generation model processes the level set of the first sample chip layout to obtain a level set of a first predicted mask. The first predicted mask refers to a predicted mask of the first sample chip layout, and the level set of the first predicted mask represents the contour of a pattern in the first predicted mask.

[0102] 203. The computer device determines a first prediction mask based on the level set of the first prediction mask, and determines a wafer pattern obtained by performing lithography using the first prediction mask.

[0103] Since the level set of the first prediction mask can represent the contour of the pattern in the first prediction mask, the computer device can determine the first prediction mask based on the level set of the first prediction mask. The first prediction mask is used for photolithography to obtain a wafer pattern, so based on photolithography knowledge, the wafer pattern obtained by photolithography using the first stored mask can be determined. It should be noted that the wafer pattern obtained here is not obtained by using a photolithography machine to perform real photolithography on the first prediction mask, but rather by using photolithography knowledge to perform photolithography simulation or photolithography simulation to determine the wafer pattern obtained by photolithography using the first stored mask.

[0104] 204. The computer device trains the mask generation model based on the difference between the wafer pattern and the first sample chip layout.

[0105] The first sample chip layout is a pattern expected to be obtained by photolithography. The wafer pattern in the above step 203 is a pattern obtained by photolithography using the first prediction mask. The more similar the wafer pattern is to the first sample chip layout, the more accurate the first prediction mask is. Therefore, the training goal of the mask generation model is to reduce the difference between the wafer pattern corresponding to the first prediction mask and the first sample chip layout. Therefore, the computer device trains the mask generation model based on the difference between the wafer pattern and the first sample chip layout, so that the mask generation model is optimized in the direction of reducing the difference between the wafer pattern and the first sample chip layout, so that the mask generation model learns how to generate a more accurate mask level set for the wafer pattern obtained after photolithography, which is equivalent to embedding photolithography knowledge in the mask generation model, which is conducive to improving the precision and accuracy of the mask generation model.

[0106] The method provided by the embodiment of the present application, during the training process of the mask generation model, the level set of the sample chip layout is input into the mask generation model, and the level set of the predicted mask is output. The predicted mask can be determined according to the level set of the predicted mask, and the predicted mask is the mask corresponding to the sample chip layout predicted by the model. Then, the wafer pattern obtained when the predicted mask is used for lithography is determined. The smaller the difference between the wafer pattern and the sample chip layout, the more accurate the mask predicted by the mask generation model. Therefore, the mask generation model can be trained based on the difference between the wafer pattern and the sample chip layout. Since the determination process of the wafer pattern depends on the lithography knowledge in the lithography process, the mask generation model can learn the lithography knowledge during the training process, thereby ensuring the accuracy of the mask generation model. Moreover, compared with the pixelated level set reverse lithography technology, the present application only needs to call the trained mask generation model to predict the mask, which reduces the complexity and improves the efficiency of the mask generation process.

[0107] Above Figure 2 The embodiment of the present invention is only a brief description of the training method of the mask generation model. For a more detailed process, please refer to the following Figure 3 Embodiment of the invention. Figure 3 is a flowchart of another method for training a mask generation model provided in an embodiment of the present application. The embodiment of the present application is executed by a computer device. Figure 3 , the method comprising:

[0108] 301. A computer device obtains a first sample chip layout.

[0109] The computer device obtains a first sample chip layout, where the first sample chip layout may be data in a published mask data set. For example, the first sample chip layout meets 32 nm process requirements and certain design rules.

[0110] After obtaining the first sample chip layout, the computer device determines a level set of the first sample chip layout. The process of determining the level set of the first sample chip layout is described in step 302 below.

[0111] 302. The computer device determines, for any coordinate point on the first sample chip layout, a level set value of the coordinate point according to the positional relationship between the coordinate point and the pattern in the first sample chip layout. The level set values ​​of multiple coordinate points on the first sample chip layout constitute a level set of the first sample chip layout. The level set of the first sample chip layout represents the contour of the pattern in the first sample chip layout.

[0112] The first sample chip layout has a pattern, which is also the direction of the circuit on the chip. For any coordinate point on the first sample chip layout, the computer device determines the positional relationship between the coordinate point and the pattern in the first sample chip layout, for example, the positional relationship indicates whether the coordinate point is located inside, outside, or on the contour line of the pattern. The computer device determines the level set value of the coordinate point based on the positional relationship, and the level set values ​​of multiple coordinate points on the first sample chip layout constitute the level set of the first sample chip layout. It can be understood that the level set value of the coordinate point can represent the positional relationship between the coordinate point and the pattern in the first sample chip layout, so the level set composed of the level set values ​​of the multiple coordinate points can represent the contour line of the pattern in the first sample chip layout.

[0113] In a possible implementation, the computer device determines the level set value of the coordinate point according to the positional relationship between the coordinate point and the pattern in the first sample chip layout, including the following three situations:

[0114] (1) When the coordinate point is located inside the pattern in the first sample chip layout, the computer device determines the inverse of the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout as the level set value of the coordinate point.

[0115] That is, if the coordinate point is located inside the pattern, the level set value of the coordinate point is negative.

[0116] (2) When the coordinate point is located outside the pattern in the first sample chip layout, the computer device determines the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout as the level set value of the coordinate point.

[0117] That is, if a coordinate point is outside the pattern, the level set value of the coordinate point is positive.

[0118] (3) When the coordinate point is located on the contour line of the pattern in the first sample chip layout, the computer device determines the target value as the level set value of the coordinate point, and the target value is equal to 0.

[0119] That is to say, if a coordinate point is located on the contour line of the pattern, the level set value of the coordinate point is 0.

[0120] Then, the level set value of the coordinate point in the first sample chip layout can be expressed by the following formula (1).

[0121]

[0122] Wherein, (x, y) represents the coordinate point in the first sample chip layout, ψ(x, y) represents the level set value of the coordinate point (x, y), C represents the contour line of the pattern in the first sample chip layout, and d(x, y) represents the minimum distance between the coordinate point (x, y) and the contour line of the pattern in the first sample chip layout, for example, the minimum distance refers to the minimum Euclidean distance. if(x, y)∈inside(C) means that the coordinate point (x, y) is located inside the pattern in the first sample chip layout, if(x, y)∈C means that the coordinate point (x, y) is located on the contour line of the pattern in the first sample chip layout, and if(x, y)∈outside(C) means that the coordinate point (x, y) is located outside the pattern in the first sample chip layout.

[0123] 303. The computer device inputs the level set of the first sample chip layout into the mask generation model to obtain the level set of the first prediction mask output by the mask generation model, where the level set of the first prediction mask represents the contour of the pattern in the first prediction mask.

[0124] After obtaining the level set of the first sample chip layout, the computer device inputs the level set of the first sample chip layout into the mask generation model, and the mask generation model processes the level set of the first sample chip layout to obtain the level set of the first predicted mask, the first predicted mask refers to the predicted mask of the first sample chip layout, and the level set of the first predicted mask represents the contour of the pattern in the first predicted mask.

[0125] In one possible implementation, Figure 4 As shown, the mask generation model includes an encoding network, an embedding network, an attention network, a feature conversion network and a decoding network. The encoding network is also connected to the decoding network, and the output of the encoding network is also the input of the decoding network. The embedding network is connected to the attention network, and the output of the embedding network is the input of the attention network. The attention network is connected to the feature conversion network, and the output of the attention network is the input of the feature conversion network. The feature conversion network is connected to the decoding network, and the output of the feature conversion network is the input of the decoding network. The computer device inputs the level set of the first sample chip layout into the encoding network and the embedding network in the mask generation model respectively. After being processed in sequence by the encoding network, the embedding network, the attention network, the feature conversion network and the decoding network, the decoding network outputs the level set of the first prediction mask.

[0126] Alternatively, if Figure 4As shown in the figure, the coding network includes 4 coding layers, which are used to extract the local detail features of the level set of the chip layout. The coding layer consists of a convolution layer, a normalization layer, and an activation function. The convolution layers in the 4 coding layers are composed of 8, 16, 32, and 64 3×3 convolution kernels, respectively, and the convolution step is 2. The convolution layer is connected to the normalization layer, and the activation function can use ReLU (rectified linear unit). Among them, the dimension of the level set of the chip layout input into the coding network is (1, 256, 256), and the dimension of the feature output in the coding network is (64, 16, 16).

[0127] Optionally, the embedding network is used to segment and sample the level set of the chip layout to extract features, which are then flattened into sequence features and input into the attention network. Figure 5 As shown in the figure, the embedding network includes a convolutional layer, a normalization layer, a flattening layer, and a transposition layer. The convolutional layer consists of 1024 1×1 convolution kernels, and the convolution step is 16. The dimension of the feature output by the normalization layer is (1024, 16, 16). After being processed by the flattening layer and the transposition layer, the dimension of the feature output by the embedding network is (256, 1024).

[0128] Optionally, the attention network is used to extract global features of the level set of the chip layout. Figure 6 As shown in the figure, the attention network consists of two parts. The first part includes a normalization layer and a multi-head attention layer (e.g., an 8-head attention layer). The first part is used to extract high-level features of the correlation information between different positions on the sequence features. The second part includes a normalization layer and a multilayer perceptron (MLP). The multilayer perceptron includes two fully connected layers. The activation function used in the fully connected layer can be ReLU. The second part is used to perform nonlinear transformation on the features of each position in the sequence features to obtain higher-level features. After the sequence features output by the embedding network are input into the attention network, the dimension of the features output by the attention network is (256, 1024).

[0129] Optionally, the feature conversion network includes a transposition layer and a Reshape layer. After the sequence features output by the attention network are input into the feature conversion network, the dimension of the features output by the feature conversion network is (1024, 16, 16).

[0130] Alternatively, if Figure 4As shown in the figure, the decoding network includes 5 decoding layers, which are composed of deconvolution layers, normalization layers and activation functions. The first 4 deconvolution layers of the 5 decoding layers are composed of 512, 256, 128 and 64 3×3 convolution kernels respectively, and the deconvolution step size is 2. The last deconvolution layer is a 3×3 convolution kernel. The convolution layer is connected to the normalization layer, and the activation function can be Leaky-ReLU (rectified linear unit). Among them, the features output by the feature conversion network and the encoding network are concatenated and input into the decoding network. The dimension of the level set of the mask finally output by the decoding network is (1, 256, 256).

[0131] 304. The computer device determines a first prediction mask based on the level set of the first prediction mask.

[0132] Since the level set of the first prediction mask can represent the contour of the pattern in the first prediction mask, the computer device can determine the first prediction mask based on the level set of the first prediction mask.

[0133] In a possible implementation, the level set of the first prediction mask includes level set values ​​of multiple coordinate points on the first prediction mask. For any coordinate point on the first prediction mask, the computer device determines the pixel value of the coordinate point as 1 if the level set value of the coordinate point is not greater than 0, and determines the pixel value of the coordinate point as 0 if the level set value of the coordinate point is greater than 0, thereby obtaining a binary first prediction mask.

[0134] Then, the pixel value of the coordinate point in the first prediction mask can be expressed by the following formula (2).

[0135]

[0136] Among them, (x, y) represents the coordinate point in the first prediction mask, M(x, y) represents the pixel value of the coordinate point (x, y), ψ(x, y) represents the level set value of the coordinate point (x, y), if ψ(x, y) ≤ 0 means that the level set value of the coordinate point (x, y) is not greater than 0, if ψ(x, y) > 0 means that the level set value of the coordinate point (x, y) is greater than 0.

[0137] 305. The computer device determines a wafer pattern obtained by performing lithography using the first predicted mask.

[0138] The first predicted mask is used for performing photolithography to obtain a wafer pattern, so based on photolithography knowledge, the wafer pattern obtained by performing photolithography using the first stored mask can be determined.

[0139] In one possible implementation, a computer device determines the light intensity distribution parameters of a first prediction mask, and calculates the light intensity distribution parameters of a wafer pattern obtained under the light intensity distribution parameters of the first prediction mask according to a lithography physical model, wherein the lithography physical model is an algorithm model for describing a lithography process. The computer device determines the wafer pattern based on the light intensity distribution parameters on the wafer pattern.

[0140] Optionally, the lithography physical model is a Hopkins optical model. The Hopkins optical model can be decomposed into a sum of coherent optical kernels through singular value decomposition. The light source and the optical projection process can be represented by a series of coherent optical kernels. Therefore, the light intensity distribution parameter I(x, y; h μ ) can be obtained by convolving the light intensity distribution parameters of the mask with a series of coherent optical kernels, see the following formula (3).

[0141]

[0142] Among them, I(x,y;h μ ) represents the coordinate point (x, y) on the wafer at the defocus h μ The light intensity distribution parameter under the influence of , K represents the number of a series of coherent optical cores, k is a positive integer not greater than K, for example, K is equal to 24. k (x,y;h μ ) represents the Hopkins optical model with defocus h obtained by singular value decomposition μ The kth order coherent optical kernel, ω k (h μ ) means h k (x,y;h μ ), M(x,y) represents the light intensity distribution parameter of the coordinate point (x,y) on the mask, Represents a convolution operation.

[0143] Optionally, the computer device determines the process of the wafer pattern based on the light intensity distribution parameters on the wafer pattern, which is represented by the following formula (4).

[0144]

[0145] Among them, Z1(x,y;h μ ,t q ) indicates that at defocus h μ and exposure dose t q The wafer pattern obtained by lithography under the influence of μ ) represents the coordinate point (x, y) on the wafer at the defocus h μ The light intensity distribution parameter under the influence of , sig(·) is the sigmoid function, θ Zis an adjustable parameter that controls the steepness of the sigmoid function. th Represents the threshold function of the photoresist on the wafer.

[0146] In another possible implementation, the computer device determines the light intensity distribution parameters of the first prediction mask; the light intensity distribution parameters of the first prediction mask are input into the light intensity prediction model to obtain the light intensity distribution parameters on the wafer pattern output by the light intensity prediction model, and the light intensity prediction model is a deep learning model for predicting the light intensity distribution in the lithography process. The computer device determines the wafer pattern based on the light intensity distribution parameters on the wafer pattern.

[0147] It should be noted that the above-mentioned lithography physical model is an algorithmic model used to describe the lithography process, rather than an artificial intelligence model trained using a deep learning algorithm. The light intensity prediction model is a deep learning model used to predict light intensity distribution, that is, an artificial intelligence model trained using a deep learning algorithm. Compared with the lithography physical model, the use of the light intensity prediction model to predict the light intensity distribution parameters on the wafer pattern can avoid the time-consuming process caused by a large number of convolution calculations, thereby improving processing efficiency.

[0148] 306. The computer device determines a first loss value based on a difference between the wafer pattern and the first sample chip layout.

[0149] The first sample chip layout is a pattern expected to be obtained through photolithography, and the wafer pattern is a pattern obtained by photolithography using the first prediction mask. The more similar the wafer pattern is to the first sample chip layout, the more accurate the first prediction mask is. Therefore, the training goal of the mask generation model is to reduce the difference between the wafer pattern corresponding to the first prediction mask and the first sample chip layout. Therefore, the computer device determines the first loss value of the mask generation model based on the difference between the wafer pattern and the first sample chip layout. The training goal of the mask generation model is to reduce the first loss value.

[0150] The greater the difference between the wafer pattern and the first sample chip layout, the greater the first loss value, and the smaller the difference between the wafer pattern and the first sample chip layout, the smaller the first loss value.

[0151] In one possible implementation, the computer device determines a defocus error, an exposure dose error, and an imaging error, wherein the defocus error indicates an error between a focus and a standard focus during a photolithography process, the exposure dose error indicates an error between an exposure dose of a photoresist during a photolithography process and a standard exposure dose, and the imaging error indicates a difference between a wafer pattern and a first sample chip layout. The computer device determines a first loss value based on the defocus error, the exposure dose error, and the imaging error, and the first loss value is positively correlated with the defocus error, the exposure dose error, and the imaging error.

[0152] The defocus error and exposure dose error can be flexibly set according to actual needs, and the imaging error is determined based on the difference between the wafer pattern and the first sample chip layout.

[0153] Optionally, the computer device determines a first loss value process based on a defocus error, an exposure dose error and an imaging error, see the following formula (5).

[0154]

[0155] Among them, L LS1 represents the first loss value, h μ represents the μth defocused sampling value, t q represents the sampling value of the qth exposure dose, U represents the number of defocus samples, μ is a positive integer not greater than U, Q represents the number of exposure dose samples, and q is a positive integer not greater than Q. ξ(h μ ) represents the statistical distribution function of the defocus sampling value, that is, the defocus error, ζ(t q ) represents the statistical distribution function of the exposure dose sampling value, that is, the exposure dose error. Aerial1 Represents imaging error.

[0156] Optionally, σ h Indicates that the distribution function broadens. σ q represents the broadening of the distribution function. Alternatively, if the effects of defocus and exposure dose during photolithography are considered, h μ The value of can be [-80nm, 0nm, 80nm], σ h The value of can be 80, t q The value of can be [-0.1, 0.0, 0.1], σ q The value of h can be 0.1. If the influence of defocus and exposure dose in the photolithography process is not considered, μ and t q The value of can be 0nm and 0.

[0157] Optionally, the imaging error L Aerial1 It can be expressed by the following formula (6).

[0158]

[0159] Among them, Z1(x,y;h μ ,t q ) indicates that at defocus h μ and exposure dose t q The wafer pattern obtained by photolithography under the influence of Z t(x, y) represents the first sample chip layout, N represents the wafer pattern or the range of the first sample chip layout, x and y represent the coordinate values ​​of the coordinate points in the wafer pattern or the first sample chip layout, and γ is an adjustable parameter.

[0160] 307. The computer device trains the mask generation model based on the first loss value to reduce the first loss value obtained based on the trained mask generation model.

[0161] The training goal of the mask generation model is to reduce the first loss value, so the computer device trains the mask generation model based on the first loss value to reduce the first loss value obtained based on the trained mask generation model.

[0162] In one possible implementation, the computer device may use a gradient descent method to adjust the model parameters of the mask generation model so that the mask generation model is optimized in a direction of reducing the loss value. The computer device determines a gradient of the first loss value with respect to the model parameters of the mask generation model, and updates the model parameters of the mask generation model in an optimization direction of reducing the gradient.

[0163] Optionally, the gradient of the first loss value with respect to the model parameters of the mask generation model can be expressed by the following formula (7).

[0164]

[0165] in, represents the gradient of the first loss value with respect to the model parameters of the mask generation model, L LS1 represents the first loss value, w represents the model parameters of the mask generation model, ψ ML represents the level set of the first predicted mask predicted by the mask generation model, and ML represents the first predicted mask.

[0166] Optionally, the gradient of the first loss value with respect to the model parameters of the mask generation model can be numerically calculated using automatic differentiation technology, and the model parameters of the mask generation model are updated based on the gradient using the Adam gradient optimization method. Therefore, during the training process of the mask generation model, lithography knowledge (lithography physics model or light intensity prediction model) is integrated into the model parameters of the mask generation model, so that the mask corresponding to the level set generated by the mask generation model has higher fidelity.

[0167] The method provided by the embodiment of the present application, during the training process of the mask generation model, the level set of the sample chip layout is input into the mask generation model, and the level set of the predicted mask is output. The predicted mask can be determined according to the level set of the predicted mask, and the predicted mask is the mask corresponding to the sample chip layout predicted by the model. Then, the wafer pattern obtained when the predicted mask is used for lithography is determined. The smaller the difference between the wafer pattern and the sample chip layout, the more accurate the mask predicted by the mask generation model. Therefore, the mask generation model can be trained based on the difference between the wafer pattern and the sample chip layout. Since the determination process of the wafer pattern depends on the lithography knowledge in the lithography process, the mask generation model can learn the lithography knowledge during the training process, thereby ensuring the accuracy of the mask generation model. Moreover, compared with the pixelated level set reverse lithography technology, the present application only needs to call the trained mask generation model to predict the mask, which reduces the complexity and improves the efficiency of the mask generation process.

[0168] Above Figure 3 In an embodiment, the mask generation model is trained according to the difference between the wafer pattern and the first sample chip layout. In another embodiment, in addition to this, the mask generation model can also be trained according to the difference between the level set of the first prediction mask and the level set of the first sample mask. The detailed process is shown below. Figure 7 Embodiment of the invention. Figure 7 is a flowchart of another method for training a mask generation model provided in an embodiment of the present application. The embodiment of the present application is executed by a computer device, see Figure 7 , the method comprising:

[0169] 701. A computer device obtains a first sample chip layout and a level set of the first sample chip layout, where the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout.

[0170] The process of obtaining the first sample chip layout and the level set of the first sample chip layout in step 701 is the same as the process of obtaining the first sample chip layout and the level set of the first sample chip layout in steps 301-302, and will not be repeated here.

[0171] 702. The computer device obtains a level set of a first sample mask, where the first sample mask is used to obtain a level set corresponding to the first sample chip version by photolithography. Figure 1 The level set of the first sample mask represents the contour lines of the pattern in the first sample mask.

[0172] It can be understood that the first sample mask is an ideal mask, that is, the mask can be obtained by photolithography in the same manner as the first sample chip version. Figure 1Therefore, it is hoped that the level set generated by the mask generation model is consistent with the level set of the first sample mask. The level set of the first sample mask can be obtained based on the level set inverse lithography technology.

[0173] In one possible implementation, the computer device determines the level set of the first sample chip layout as the reference level set. The computer device performs the following iterative process on the reference level set: determining a reference mask based on the reference level set, and determining a reference wafer pattern obtained by photolithography using the reference mask; adjusting the reference level set based on the difference between the reference wafer pattern and the first sample chip layout, so that the difference between the reference wafer pattern obtained based on the adjusted reference level set and the first sample chip layout is reduced. In response to the iterative process satisfying the iterative end condition, the computer device stops the iterative process and obtains the level set of the first sample mask.

[0174] In the embodiment of the present application, the computer device needs to adjust the level set of the first sample chip layout to obtain the level set of the first sample mask, so that the first sample mask can be photolithographically obtained in accordance with the first sample chip layout. Figure 1 The computer device first determines the level set of the first sample chip layout as the reference level set. At this time, the reference level set can be understood as the initial level set of the entire adjustment process. Then the computer device determines the reference wafer pattern that can be obtained by lithography according to the reference level set. The purpose of the embodiment of the present application is to make the determined reference wafer pattern consistent with the first sample chip layout. Figure 1 Therefore, the computer device can determine the difference between the reference wafer pattern and the first sample chip layout, and adjust the reference level set according to the difference, so that the reference level set changes in the direction of reducing the difference. Similar to the iterative training process of the deep learning model, the computer device iteratively performs the above adjustment process until the iteration end condition is met, stops the iteration process, and determines the reference level set obtained by the last adjustment as the level set of the first sample mask.

[0175] The process of determining the reference mask based on the reference level set is the same as the process of determining the first prediction mask based on the level set of the first prediction mask in step 304, which is not described in detail here. The process of determining the reference wafer pattern obtained by lithography using the reference mask is the same as the process of determining the wafer pattern obtained by lithography using the first prediction mask in step 305, which is not described in detail here.

[0176] Optionally, the iteration end condition is that the number of iterations reaches a target number, or the iteration end condition is that the difference between the currently obtained reference wafer pattern and the first sample chip layout is less than a target value, etc.

[0177] In a possible implementation, a computer device adjusts a reference level set based on a difference between a reference wafer pattern and a first sample chip layout so as to reduce a difference between a reference wafer pattern obtained based on the adjusted reference level set and the first sample chip layout, including: determining a fourth loss value based on the difference between the reference wafer pattern and the first sample chip layout, and adjusting the reference level set based on the fourth loss value so as to reduce a fourth loss value obtained based on the adjusted reference level set. The greater the difference between the reference wafer pattern and the first sample chip layout, the greater the fourth loss value, and the smaller the difference between the reference wafer pattern and the first sample chip layout, the smaller the fourth loss value.

[0178] Optionally, the computer device determines a defocus error, an exposure dose error, and an imaging error, wherein the defocus error represents the error between the focus and the standard focus during the photolithography process, the exposure dose error represents the error between the exposure dose of the photoresist during the photolithography process and the standard exposure dose, and the imaging error represents the difference between the reference wafer pattern and the first sample chip layout. The computer device determines a fourth loss value based on the defocus error, the exposure dose error, and the imaging error, and the fourth loss value is positively correlated with the defocus error, the exposure dose error, and the imaging error. The defocus error and the exposure dose error can be flexibly set according to actual needs, and the imaging error is determined based on the difference between the reference wafer pattern and the first sample chip layout.

[0179] Optionally, the computer device determines a fourth loss value process based on the defocus error, the exposure dose error and the imaging error, see the following formula (8).

[0180]

[0181] Among them, L LS2 represents the fourth loss value, h μ represents the μth defocused sampling value, t q represents the sampling value of the qth exposure dose, U represents the number of defocus samples, μ is a positive integer not greater than U, Q represents the number of exposure dose samples, and q is a positive integer not greater than Q. ξ(h μ ) represents the statistical distribution function of the defocus sampling value, that is, the defocus error, ζ(t q ) represents the statistical distribution function of the exposure dose sampling value, that is, the exposure dose error. Aerial2 Represents imaging error.

[0182] Optionally, σ h Indicates that the distribution function broadens. σ q represents the broadening of the distribution function. Alternatively, if the effects of defocus and exposure dose during photolithography are considered, hμ The value of can be [-80nm, 0nm, 80nm], σ h The value of can be 80, t q The value of can be [-0.1, 0.0, 0.1], σ q The value of h can be 0.1. If the influence of defocus and exposure dose in the photolithography process is not considered, μ and t q The value of can be 0nm and 0.

[0183] Optionally, L Aerial2 It can be expressed by the following formula (9).

[0184]

[0185] Among them, Z2(x,y;h μ ,t q ) indicates that at defocus h μ and exposure dose t q The reference wafer pattern obtained by lithography under the influence of t (x, y) represents the first sample chip layout, N represents the range of the reference wafer pattern or the first sample chip layout, x and y represent the coordinate values ​​of the coordinate points in the reference wafer pattern or the first sample chip layout, and γ is an adjustable parameter.

[0186] In a possible implementation, the computer device may use a gradient descent method to adjust the reference level set based on the fourth loss value, so that the reference level set is optimized in a direction of reducing the fourth loss value. The computer device determines a gradient of the fourth loss value with respect to the reference level set, and updates the reference level set in an optimization direction of reducing the gradient.

[0187] Optionally, the computer device determines a gradient of the imaging error of the reference wafer pattern, and the gradient of the imaging error of the reference wafer pattern can be expressed by the following formula (10).

[0188]

[0189] Where L represents the perimeter of the reference wafer pattern contour, γ is an adjustable parameter, Z2 represents the reference wafer pattern, and Z t represents the first sample chip layout, M represents the light intensity distribution parameter of the reference mask corresponding to the reference level set, θ Z is an adjustable parameter that controls the steepness of the sigmoid function, H represents K coherent optical kernels, and H * is the complex conjugate of H, H flip is H rotated 180 degrees, and ⊙ represents the matrix dot product.

[0190] Optionally, the computer device determines the evolution speed of the reference mask boundary, and the evolution speed of the reference mask boundary can be expressed by the following formula (11).

[0191]

[0192] Among them, ve represents the evolution speed of the reference mask boundary, h μ represents the μth defocused sampling value, t q represents the sampling value of the qth exposure dose, U represents the number of defocus samples, μ is a positive integer not greater than U, Q represents the number of exposure dose samples, and q is a positive integer not greater than Q. ξ(h μ ) represents the statistical distribution function of the defocus sampling value, that is, the defocus error, ζ(t q ) represents the statistical distribution function of the exposure dose sampling value, that is, the exposure dose error. Aerial2 represents the imaging error of the reference wafer pattern, and M represents the light intensity distribution parameter of the reference mask.

[0193] Optionally, the computer device determines the evolution equation of the reference level set according to the above formula (11), and the evolution equation of the reference level set can be expressed by the following formula (12).

[0194]

[0195] Among them, ψ i (x,y) represents the reference level set after the i-th iteration, ψ i+1 (x,y) represents the reference level set after the i+1th iteration.

[0196] According to the above formula (12), the gradient of the fourth loss value with respect to the reference level set can be determined as However, in order to control the smoothness of the reference mask and eliminate noise, a penalty function R is also introduced in the gradient TV , penalty function R TV It can be expressed by the following formula (13).

[0197]

[0198] Among them, R TV represents the penalty term, ψ represents the reference level set, and x and y represent the coordinate values ​​of the coordinate points.

[0199] According to the above formula (13), it can be determined that the evolution speed of the penalty function boundary can be expressed by the following formula (14).

[0200]

[0201] Among them, κ represents the evolution speed of the penalty function boundary, R TVrepresents the penalty term, and ψ represents the reference level set.

[0202] After introducing the penalty function, the gradient of the fourth loss value with respect to the reference level set can be expressed by the following formula (15).

[0203]

[0204] in, represents the gradient of the fourth loss value with respect to the reference level set, L LS2 represents the fourth loss value, ψ represents the reference level set, and h μ represents the μth defocused sampling value, t q represents the sampling value of the qth exposure dose, U represents the number of defocus samples, μ is a positive integer not greater than U, Q represents the number of exposure dose samples, and q is a positive integer not greater than Q. ξ(h μ ) represents the statistical distribution function of the defocus sampling value, that is, the defocus error, ζ(t q ) represents the statistical distribution function of the exposure dose sampling value, that is, the exposure dose error. Aerial2 represents the imaging error of the reference wafer pattern. M represents the light intensity distribution parameter of the reference mask, and λ is an adjustable parameter, for example, it can take a value of 0.01.

[0205] 703. The computer device inputs the level set of the first sample chip layout into the mask generation model to obtain the level set of the first prediction mask output by the mask generation model, where the level set of the first prediction mask represents the contour of the pattern in the first prediction mask.

[0206] The process of generating the level set of the first prediction mask in step 703 is the same as the process of generating the level set of the first prediction mask in step 303 above, and will not be described in detail here.

[0207] 704. The computer device determines a first prediction mask based on the level set of the first prediction mask, and determines a wafer pattern obtained by performing lithography using the first prediction mask.

[0208] The process of determining the wafer pattern in step 704 is the same as the process of determining the wafer pattern in steps 304 to 305 above, and will not be described in detail here.

[0209] 705. The computer device trains a mask generation model based on the difference between the wafer pattern and the first sample chip layout, and the difference between the level set of the first predicted mask and the level set of the first sample mask.

[0210] The first sample chip layout is a pattern expected to be obtained through photolithography, and the wafer pattern is a pattern obtained by photolithography using the first prediction mask. The more similar the wafer pattern is to the first sample chip layout, the more accurate the first prediction mask is. The level set of the first sample mask is the level set expected to be generated. The level set of the first prediction mask is a level set generated using the mask generation model. The more similar the level set of the first prediction mask is to the level set of the first sample mask, the more accurate the level set of the first prediction mask is. Therefore, the training goal of the mask generation model is to reduce the difference between the wafer pattern corresponding to the first prediction mask and the first sample chip layout, and the difference between the level set of the first prediction mask and the level set of the first sample mask. Therefore, the computer device trains the mask generation model based on these two differences, so that the mask generation model is optimized in the direction of reducing these two differences, so that the mask generation model learns how to generate a more accurate mask level set for the wafer pattern obtained after photolithography.

[0211] In one possible implementation, a computer device determines a first loss value based on a difference between a wafer pattern and a first sample chip layout; determines a second loss value based on a difference between a level set of a first prediction mask and a level set of a first sample mask; performs a weighted summation of the first loss value and the second loss value to obtain a third loss value; and trains a mask generation model based on the third loss value so that a third loss value obtained based on the trained mask generation model is reduced.

[0212] Optionally, the first loss value is the same as the first loss value in step 306, which is not described again. Optionally, the second loss value is the Euclidean norm between the level set of the first prediction mask and the level set of the first sample mask, etc., which is not limited in this embodiment of the present application.

[0213] In one possible implementation, the third loss value can be expressed by the following formula (16).

[0214] Loss = αL LS1 +L fit ;

[0215]

[0216] L fit =||ψ ML (Z t ;w)-ψ|| 2 ;Formula (16)

[0217] Among them, Loss represents the third loss value, L LS1 Represents the first loss value, L fit represents the second loss value, α is an adjustable parameter, for example, the value is 0.001. μrepresents the μth defocused sampling value, t q represents the sampling value of the qth exposure dose, U represents the number of defocus samples, μ is a positive integer not greater than U, Q represents the number of exposure dose samples, and q is a positive integer not greater than Q. ξ(h μ ) represents the statistical distribution function of the defocus sampling value, that is, the defocus error, ζ(t q ) represents the statistical distribution function of the exposure dose sampling value, that is, the exposure dose error. Aerial1 Represents the imaging error of the wafer pattern. ML (Z t ; w) represents the level set of the first prediction mask, and ψ represents the level set of the first sample mask.

[0218] In a possible implementation, the computer device may use a gradient descent method to adjust the model parameters of the mask generation model based on the third loss value, so that the model parameters of the mask generation model are optimized in a direction of reducing the third loss value. The computer device determines the gradient of the third loss value with respect to the model parameters of the mask generation model, and updates the model parameters of the mask generation model in an optimization direction of reducing the gradient.

[0219] Optionally, the gradient of the third loss value with respect to the model parameters of the mask generation model can be expressed by the following formula (17).

[0220]

[0221] in, represents the gradient of the third loss value with respect to the model parameters of the mask generation model, Loss represents the third loss value, and w represents the model parameters of the mask generation model. ψ ML represents the level set of the first predicted mask, M ML represents the first prediction mask, L LS1 Represents the first loss value, L fit represents the second loss value, α is an adjustable parameter, λ is an adjustable parameter, ξ(h μ ) represents the statistical distribution function of the defocus sampling value, that is, the defocus error, ζ(t q ) represents the statistical distribution function of the exposure dose sampling value, that is, the exposure dose error. Aerial1 Represents the imaging error of the wafer pattern. and It can be calculated using automatic differentiation technology. In the embodiment of the present application, the model parameters of the mask generation model are updated based on the gradient using the Adam gradient optimization method. Therefore, during the training process of the mask generation model, the lithography knowledge (lithography physics model or light intensity prediction model) is integrated into the model parameters of the mask generation model, so that the fidelity of the mask corresponding to the level set generated by the mask generation model is higher.

[0222] The method provided by the embodiment of the present application, during the training process of the mask generation model, the level set of the sample chip layout is input into the mask generation model, and the level set of the predicted mask is output. The predicted mask can be determined according to the level set of the predicted mask, and the predicted mask is the mask corresponding to the sample chip layout predicted by the model. Then, the wafer pattern obtained when the predicted mask is used for lithography is determined. The smaller the difference between the wafer pattern and the sample chip layout, the more accurate the mask predicted by the mask generation model. Therefore, the mask generation model can be trained based on the difference between the wafer pattern and the sample chip layout. Since the determination process of the wafer pattern depends on the lithography knowledge in the lithography process, the mask generation model can learn the lithography knowledge during the training process, thereby ensuring the accuracy of the mask generation model. Moreover, compared with the pixelated level set reverse lithography technology, the present application only needs to call the trained mask generation model to predict the mask, which reduces the complexity and improves the efficiency of the mask generation process.

[0223] The above embodiments illustrate the training process of the mask generation model. In other embodiments, the mask generation model is a pre-trained model, that is, the above embodiments are obtained by continuing to train on the basis of the pre-trained mask generation model. The pre-training process of the mask generation model can be found in the following Figure 8 Embodiment of the invention. Figure 8 is a flowchart of a pre-training method for a mask generation model provided in an embodiment of the present application. The embodiment of the present application is executed by a computer device, see Figure 8 , the method comprising:

[0224] 801. A computer device obtains a level set of a second sample chip layout and a level set of a second sample mask, wherein the second sample mask is used to obtain a level set of a second sample chip layout by photolithography. Figure 1 The level set of the second sample chip layout represents the contour lines of the pattern in the second sample chip layout, and the level set of the second sample mask represents the contour lines of the pattern in the second sample mask.

[0225] The process of obtaining the second sample chip layout in step 801 is the same as the process of obtaining the first sample chip layout in step 301, and will not be repeated here. The process of obtaining the level set of the second sample mask in step 801 is the same as the process of obtaining the level set of the first sample mask in step 702, and will not be repeated here.

[0226] 802. The computer device inputs the level set of the second sample chip layout into the mask generation model to obtain the level set of the second prediction mask output by the mask generation model, where the level set of the second prediction mask represents the contour of the pattern in the second prediction mask.

[0227] The process of obtaining the level set of the second prediction mask in step 802 is the same as the process of obtaining the level set of the first prediction mask in step 303 , and will not be described again.

[0228] 803. The computer device pre-trains the mask generation model based on the difference between the level set of the second prediction mask and the level set of the second sample mask.

[0229] The level set of the second sample mask is the level set expected to be generated, and the level set of the second prediction mask is the level set generated using the mask generation model. The more similar the level set of the second prediction mask is to the level set of the second sample mask, the more accurate the level set of the second prediction mask is. Therefore, the training goal of the mask generation model is to reduce the difference between the level set of the second prediction mask and the level set of the second sample mask. Therefore, the computer device trains the mask generation model based on the difference between the level set of the second prediction mask and the level set of the second sample mask, so that the mask generation model is optimized in the direction of reducing the difference.

[0230] In one possible implementation, the computer device determines a fifth loss value based on the difference between the level set of the second prediction mask and the level set of the second sample mask, and pre-trains the mask generation model based on the fifth loss value so that the fifth loss value obtained based on the pre-trained mask generation model is reduced.

[0231] Optionally, the fifth loss value is the Euclidean norm between the level set of the second prediction mask and the level set of the second sample mask, etc., which is not limited in the embodiment of the present application. The calculation method of the fifth loss value is the same as the calculation method of the second loss value in the above step 705, which will not be repeated here.

[0232] The method provided in the embodiment of the present application, during the pre-training process of the mask generation model, inputs the level set of the sample chip layout into the mask generation model, outputs the level set of the predicted mask, and trains the mask generation model based on the difference between the level set of the predicted mask and the level set of the sample mask corresponding to the sample chip layout. Therefore, the mask generation model can preliminarily learn how to generate the level set of the mask based on the level set of the chip layout during the pre-training process, thereby ensuring the accuracy of the mask generation model.

[0233] In addition, the pre-training process of the mask generation model does not involve the loss of lithography knowledge, that is, no lithography simulation is required, thereby reducing the processing complexity and improving the efficiency of pre-training. After the pre-training is completed, a mask generation model that can predict the level set of the mask based on the level set of the chip layout is initially obtained, and then the above Figure 3 or Figure 7The training method in the embodiment continues to train the mask generation model, that is, embedding losses related to lithography knowledge during the training process, so that the mask generation model can predict a mask level set that better meets the lithography requirements, thereby achieving refined adjustment of the mask generation model and improving the overall training efficiency of the mask generation model and the accuracy of the trained mask generation model.

[0234] Fig. 9 : is a system architecture diagram of a training method for a mask generation model provided in an embodiment of the present application. The system architecture includes three parts. The specific contents are as follows: Fig. 9 shown.

[0235] The first part is to determine the level set of the sample mask based on the level set reverse lithography mask optimization algorithm. The computer device obtains the second sample chip layout and the level set of the second sample chip layout, and determines the level set of the second sample mask corresponding to the second sample chip layout based on the level set reverse lithography mask optimization algorithm (see the process of obtaining the level set of the sample mask in step 702 above for details).

[0236] The second part is the process of pre-training the mask generation model, wherein the mask generation model generates a level set of a second prediction mask according to the level set of the second sample chip layout, and then pre-trains the mask generation model based on the difference between the level set of the second prediction mask and the level set of the second sample mask obtained in the first part.

[0237] The third part is the process of training the mask generation model based on lithography physics knowledge. The computer device obtains the first sample chip layout and the level set of the first sample chip layout, and determines the level set of the first sample mask corresponding to the first sample chip layout based on the level set inverse lithography mask optimization algorithm. The pre-trained mask generation model generates a level set of the first prediction mask according to the level set of the first sample chip layout, binarizes the level set of the first prediction mask, and obtains the first prediction mask. The first prediction mask is subjected to lithography simulation (using a lithography physics model or a light intensity prediction model) to obtain a wafer pattern. Then, the lithography loss (first loss value) is determined based on the difference between the wafer pattern and the first sample chip layout, and the mask loss (second loss value) is determined based on the difference between the level set of the first prediction mask and the level set of the first sample mask, and the mask generation model is trained. Among them, a level set ILT correction layer can be added to the system architecture. The level set ILT correction layer is used to determine the lithography loss. The mask generation model is trained under the guidance of the lithography loss, so that the model parameters of the trained mask generation model contain implicit lithography physics knowledge, thereby improving the process window of the predicted mask.

[0238] The above embodiments are all descriptions of the training process of the mask generation model. After the trained mask generation model is obtained, the mask generation model can be used to determine the mask corresponding to the chip layout. For detailed process, see the following Fig.10 The embodiment shown. Fig.10 is a flowchart of a mask generation method provided in an embodiment of the present application. The embodiment of the present application is executed by a computer device. Fig.10 , the method comprising:

[0239] 1001. A computer device obtains a level set of a target chip layout.

[0240] The purpose of the embodiment of the present application is to determine the target mask corresponding to the target chip layout when the target chip layout is known, so that the wafer pattern obtained by lithography through the target mask is consistent with the target chip layout. Figure 1 After obtaining the target chip layout, the computer device can determine the level set of the target chip layout based on the target chip layout, wherein the process of determining the level set of the target chip layout is the same as the process of determining the level set of the first sample chip layout in the above step 302, and will not be repeated here.

[0241] 1002. The computer device inputs the level set of the target chip layout into the trained mask generation model to obtain the level set of the target mask output by the mask generation model.

[0242] The process of obtaining the level set of the target mask in step 1002 is the same as the process of obtaining the level set of the first predicted mask in step 303 above, and will not be repeated here.

[0243] 1003. The computer device determines a target mask based on a level set of the target mask, and the target mask is used to obtain a target chip version by photolithography. Figure 1 Unique wafer patterning.

[0244] The process of determining the target mask in step 1003 is the same as the process of determining the first prediction mask in step 304, which will not be described in detail here. After obtaining the target mask, the computer device can subsequently perform photolithography using the target mask to obtain a target chip version. Figure 1 Unique wafer patterning.

[0245] In the embodiment of the present application, a trained mask generation model is used to quickly predict the chip layout to obtain a mask, which simplifies the process of generating the mask and thus improves the efficiency of the mask generation process.

[0246] Moreover, since the trained mask generation model implicitly contains the physical knowledge of the lithography process, the training process of the mask generation model also takes into account the defocus error and exposure dose error. Therefore, the mask generation model has a higher accuracy and a higher tolerance to the defocus error and exposure dose error.

[0247] like Fig.11 As shown, Fig.11 The process window for photolithography using the methods of the embodiments of the present application and related technologies is shown in FIG. 1 , which can be understood as the tolerance for defocus error and exposure dose error during the photolithography process. Fig.11 It can be seen that, compared with the related art, the method provided in the embodiment of the present application can significantly improve the process window of lithography.

[0248] Fig.12 is a structural diagram of a training device for a mask generation model provided in an embodiment of the present application. Fig.12 , the device comprises:

[0249] A first acquisition module 1201 is used to acquire a first sample chip layout and a level set of the first sample chip layout, where the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout;

[0250] The level set generation module 1202 is used to input the level set of the first sample chip layout into the mask generation model to obtain the level set of the first prediction mask output by the mask generation model, where the level set of the first prediction mask represents the contour of the pattern in the first prediction mask;

[0251] A mask determination module 1203, configured to determine a first prediction mask based on a level set of the first prediction mask;

[0252] The wafer pattern determination module 1204 is used to determine the wafer pattern obtained by photolithography using the first prediction mask;

[0253] The first training module 1205 is used to train the mask generation model based on the difference between the wafer pattern and the first sample chip layout.

[0254] The training device of the mask generation model provided by the embodiment of the present application, during the training process of the mask generation model, the level set of the sample chip layout is input into the mask generation model, and the level set of the predicted mask is output. The predicted mask can be determined according to the level set of the predicted mask, and the predicted mask is the mask corresponding to the sample chip layout predicted by the model. Then the wafer pattern obtained when the predicted mask is used for lithography is determined. The smaller the difference between the wafer pattern and the sample chip layout, the more accurate the mask predicted by the mask generation model. Therefore, the mask generation model can be trained based on the difference between the wafer pattern and the sample chip layout. Since the determination process of the wafer pattern depends on the lithography knowledge in the lithography process, the mask generation model can learn the lithography knowledge during the training process, thereby ensuring the accuracy of the mask generation model. Moreover, compared with the pixelated level set reverse lithography technology, the present application only needs to call the trained mask generation model to predict the mask, which reduces the complexity and improves the efficiency of the mask generation process.

[0255] Alternatively, see Fig.13 , the first acquisition module 1201 is used to:

[0256] Obtaining a first sample chip layout;

[0257] For any coordinate point on the first sample chip layout, the level set value of the coordinate point is determined according to the positional relationship between the coordinate point and the pattern in the first sample chip layout. The level set values ​​of multiple coordinate points on the first sample chip layout constitute the level set of the first sample chip layout.

[0258] Alternatively, see Fig.13 , the first acquisition module 1201 is used to:

[0259] When the coordinate point is located inside the pattern in the first sample chip layout, the inverse of the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout is determined as the level set value of the coordinate point;

[0260] When the coordinate point is located outside the pattern in the first sample chip layout, the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout is determined as the level set value of the coordinate point;

[0261] When the coordinate point is located on the contour line of the pattern in the first sample chip layout, the target value is determined as the level set value of the coordinate point, and the target value is equal to 0.

[0262] Alternatively, see Fig.13 , the level set of the first prediction mask includes the level set values ​​of multiple coordinate points on the first prediction mask, and the mask determination module 1203 is used to:

[0263] For any coordinate point on the first prediction mask, when the level set value of the coordinate point is not greater than 0, the pixel value of the coordinate point is determined to be 1; when the level set value of the coordinate point is greater than 0, the pixel value of the coordinate point is determined to be 0.

[0264] Alternatively, see Fig.13 , the wafer pattern determination module 1204 is used to:

[0265] determining light intensity distribution parameters of a first prediction mask;

[0266] According to the lithography physical model, the light intensity distribution parameters of the wafer pattern obtained under the condition of the light intensity distribution parameters of the first prediction mask are calculated. The lithography physical model is an algorithm model used to describe the lithography process; or, the light intensity distribution parameters of the first prediction mask are input into the light intensity prediction model to obtain the light intensity distribution parameters on the wafer pattern output by the light intensity prediction model. The light intensity prediction model is a deep learning model used to predict the light intensity distribution in the lithography process;

[0267] The wafer pattern is determined based on the light intensity distribution parameters on the wafer pattern.

[0268] Alternatively, see Fig.13 , the first training module 1205 is used to:

[0269] determining a first loss value based on a difference between the wafer pattern and the first sample chip layout;

[0270] Based on the first loss value, the mask generation model is trained so that the first loss value obtained based on the trained mask generation model is reduced.

[0271] Alternatively, see Fig.13 , the first training module 1205 is used to:

[0272] Determine a defocus error, an exposure dose error, and an imaging error, wherein the defocus error represents an error between a focus during a photolithography process and a standard focus, the exposure dose error represents an error between an exposure dose of a photoresist during a photolithography process and a standard exposure dose, and the imaging error represents a difference between a wafer pattern and a first sample chip layout;

[0273] Based on the defocus error, the exposure dose error and the imaging error, a first loss value is determined, and the first loss value is positively correlated with the defocus error, the exposure dose error and the imaging error.

[0274] Alternatively, see Fig.13 , the device further comprises:

[0275] The second acquisition module 1206 is used to acquire a level set of a first sample mask, where the first sample mask is used to obtain a level set corresponding to the first sample chip version through photolithography. Figure 1The level set of the first sample mask represents the contour line of the pattern in the first sample mask;

[0276] The first training module 1205 is used to:

[0277] The mask generation model is trained based on the difference between the wafer pattern and the first sample chip layout, and the difference between the level set of the first predicted mask and the level set of the first sample mask.

[0278] Alternatively, see Fig.13 , the first training module 1205 is used to:

[0279] Determining a first loss value based on a difference between the wafer pattern and the first sample chip layout;

[0280] Determining a second loss value based on a difference between a level set of the first prediction mask and a level set of the first sample mask;

[0281] Perform a weighted summation of the first loss value and the second loss value to obtain a third loss value;

[0282] Based on the third loss value, the mask generation model is trained so that the third loss value obtained based on the trained mask generation model is reduced.

[0283] Alternatively, see Fig.13 , the second acquisition module 1206 is used to:

[0284] determining a level set of the first sample chip layout as a reference level set;

[0285] The following iterative process is performed on the reference level set: a reference mask is determined based on the reference level set, and a reference wafer pattern obtained by photolithography using the reference mask is determined; based on the difference between the reference wafer pattern and the first sample chip layout, the reference level set is adjusted so that the difference between the reference wafer pattern obtained based on the adjusted reference level set and the first sample chip layout is reduced;

[0286] In response to the iteration process satisfying the iteration end condition, the iteration process is stopped to obtain the level set of the first sample mask.

[0287] Alternatively, see Fig.13 , the second acquisition module 1206 is used to:

[0288] determining a fourth loss value based on a difference between the reference wafer pattern and the first sample chip layout;

[0289] Based on the fourth loss value, the reference level set is adjusted so that the fourth loss value obtained based on the adjusted reference level set is reduced.

[0290] Alternatively, see Fig.13 , the mask generation model is a pre-trained model, and the apparatus further includes a second training module 1207, which is used to:

[0291] Obtain a level set of a second sample chip layout and a level set of a second sample mask, the second sample mask being used to obtain a level set of a second sample chip layout by photolithography. Figure 1 The level set of the second sample chip layout represents the contour of the pattern in the second sample chip layout, and the level set of the second sample mask represents the contour of the pattern in the second sample mask;

[0292] Inputting the level set of the second sample chip layout into the mask generation model to obtain the level set of the second prediction mask output by the mask generation model, wherein the level set of the second prediction mask represents the contour line of the pattern in the second prediction mask;

[0293] The mask generation model is pre-trained based on the difference between the level set of the second predicted mask and the level set of the second sample mask.

[0294] Alternatively, see Fig.13 The device further includes a model using module 1208, which is used to:

[0295] Obtaining a level set of the target chip layout;

[0296] Inputting the level set of the target chip layout into the trained mask generation model to obtain the level set of the target mask output by the mask generation model;

[0297] The target mask is determined based on the level set of the target mask, and the target mask is used to obtain the target chip version through lithography. Figure 1 Unique wafer patterning.

[0298] It should be noted that the training device for the mask generation model provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device is divided into different functional modules to complete all or part of the functions described above. In addition, the training device for the mask generation model provided in the above embodiment and the training method embodiment of the mask generation model belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0299] An embodiment of the present application also provides a computer device, which includes a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor to implement the operations performed in the training method of the mask generation model of the above embodiment.

[0300] Optionally, the computer device is provided as a terminal. Fig.14 A schematic diagram of the structure of a terminal 1400 provided by an exemplary embodiment of the present application is shown.

[0301] The terminal 1400 includes a processor 1401 and a memory 1402 .

[0302] The processor 1401 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1401 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1401 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1401 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1401 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0303] The memory 1402 may include one or more computer-readable storage media, which may be non-transitory. The memory 1402 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1402 is used to store at least one computer program, which is used by the processor 1401 to implement the training method of the mask generation model provided in the method embodiment of the present application.

[0304] In some embodiments, the terminal 1400 may further optionally include: a peripheral device interface 1403 and at least one peripheral device. The processor 1401, the memory 1402 and the peripheral device interface 1403 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 1403 via a bus, a signal line or a circuit board. Optionally, the peripheral device includes: at least one of a radio frequency circuit 1404, a display screen 1405, a camera assembly 1406, an audio circuit 1407 and a power supply 1408.

[0305] The peripheral device interface 1403 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 1401 and the memory 1402. In some embodiments, the processor 1401, the memory 1402, and the peripheral device interface 1403 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1401, the memory 1402, and the peripheral device interface 1403 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0306] The radio frequency circuit 1404 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 1404 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 1404 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 1404 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The radio frequency circuit 1404 can communicate with other devices through at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 1404 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0307] The display screen 1405 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1405 is a touch display screen, the display screen 1405 also has the ability to collect touch signals on the surface or above the surface of the display screen 1405. The touch signal can be input to the processor 1401 as a control signal for processing. At this time, the display screen 1405 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 1405 can be one, set on the front panel of the terminal 1400; in other embodiments, the display screen 1405 can be at least two, respectively set on different surfaces of the terminal 1400 or in a folding design; in other embodiments, the display screen 1405 can be a flexible display screen, set on a curved surface or a folding surface of the terminal 1400. Even, the display screen 1405 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 1405 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0308] The camera assembly 1406 is used to capture images or videos. Optionally, the camera assembly 1406 includes a front camera and a rear camera. The front camera is arranged on the front panel of the terminal 1400, and the rear camera is arranged on the back of the terminal 1400. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize the panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1406 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0309] The audio circuit 1407 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 1401 for processing, or input them into the radio frequency circuit 1404 to achieve voice communication. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 1400. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 1401 or the radio frequency circuit 1404 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 1407 may also include a headphone jack.

[0310] The power supply 1408 is used to power various components in the terminal 1400. The power supply 1408 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 1408 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0311] Those skilled in the art will understand that Fig.14 The structure shown in the figure does not constitute a limitation on the terminal 1400, and the terminal 1400 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0312] Optionally, the computer device is provided as a server. Fig.15 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server 1500 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1501 and one or more memories 1502, wherein the memory 1502 stores at least one computer program, and the at least one computer program is loaded and executed by the processor 1501 to implement the methods provided in the above-mentioned various method embodiments. Of course, the server may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the server may also include other components for implementing device functions, which will not be described in detail here.

[0313] An embodiment of the present application further provides a computer-readable storage medium, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor to implement the operations performed by the training method of the mask generation model of the above embodiment.

[0314] An embodiment of the present application further provides a computer program product, including a computer program, wherein the computer program is loaded and executed by a processor to implement the operations performed by the training method of the mask generation model in the above embodiment.

[0315] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0316] The above description is only an optional embodiment of the embodiments of the present application and is not intended to limit the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A method for training a mask generation model, characterized in that: The method comprises: Acquire a first sample chip layout and a level set of the first sample chip layout, wherein the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout; Inputting the level set of the first sample chip layout into a mask generation model to obtain a level set of a first prediction mask output by the mask generation model, wherein the level set of the first prediction mask represents a contour line of a pattern in the first prediction mask; Determine the first prediction mask based on the level set of the first prediction mask, and determine a wafer pattern obtained by performing lithography using the first prediction mask; The mask generation model is trained based on the difference between the wafer pattern and the first sample chip layout.

2. The method according to claim 1, characterized in that: The obtaining of a first sample chip layout and a level set of the first sample chip layout comprises: Obtaining the first sample chip layout; For any coordinate point on the first sample chip layout, a level set value of the coordinate point is determined according to the positional relationship between the coordinate point and the pattern in the first sample chip layout, and the level set values ​​of multiple coordinate points on the first sample chip layout constitute the level set of the first sample chip layout.

3. The method according to claim 2, characterized in that Determining the level set value of the coordinate point according to the positional relationship between the coordinate point and the pattern in the first sample chip layout includes: In the case where the coordinate point is located inside the pattern in the first sample chip layout, the inverse of the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout is determined as the level set value of the coordinate point; In the case where the coordinate point is located outside the pattern in the first sample chip layout, determining the minimum distance between the coordinate point and the contour line of the pattern in the first sample chip layout as the level set value of the coordinate point; In the case where the coordinate point is located on the contour line of the pattern in the first sample chip layout, a target value is determined as the level set value of the coordinate point, and the target value is equal to 0.

4. The method according to claim 1, characterized in that: The level set of the first prediction mask includes level set values ​​of a plurality of coordinate points on the first prediction mask, and determining the first prediction mask based on the level set of the first prediction mask includes: For any coordinate point on the first prediction mask, when the level set value of the coordinate point is not greater than 0, the pixel value of the coordinate point is determined to be 1; when the level set value of the coordinate point is greater than 0, the pixel value of the coordinate point is determined to be 0.

5. The method according to claim 1, characterized in that The determining of a wafer pattern obtained by performing lithography using the first predicted mask includes: determining light intensity distribution parameters of the first prediction mask; According to a lithography physical model, calculating the light intensity distribution parameters of the wafer pattern obtained under the condition of the light intensity distribution parameters of the first prediction mask, the lithography physical model is an algorithm model used to describe the lithography process; or, inputting the light intensity distribution parameters of the first prediction mask into a light intensity prediction model to obtain the light intensity distribution parameters on the wafer pattern output by the light intensity prediction model, the light intensity prediction model is a deep learning model used to predict the light intensity distribution in the lithography process; The wafer pattern is determined based on the light intensity distribution parameter on the wafer pattern.

6. The method according to claim 1, characterized in that The step of training the mask generation model based on the difference between the wafer pattern and the first sample chip layout includes: determining a first loss value based on a difference between the wafer pattern and the first sample chip layout; Based on the first loss value, the mask generation model is trained so that the first loss value obtained based on the trained mask generation model is reduced.

7. The method according to claim 6, characterized in that The determining of a first loss value based on a difference between the wafer pattern and the first sample chip layout comprises: Determine a defocus error, an exposure dose error, and an imaging error, wherein the defocus error represents an error between a focus and a standard focus during a photolithography process, the exposure dose error represents an error between an exposure dose of a photoresist during a photolithography process and a standard exposure dose, and the imaging error represents a difference between the wafer pattern and the first sample chip layout; Based on the defocus error, the exposure dose error and the imaging error, the first loss value is determined, and the first loss value is positively correlated with the defocus error, the exposure dose error and the imaging error.

8. The method according to claim 1, characterized in that: The method further comprises: Acquire a level set of a first sample mask, where the first sample mask is used to obtain a wafer pattern consistent with the first sample chip layout through photolithography, and the level set of the first sample mask represents a contour line of the pattern in the first sample mask; The step of training the mask generation model based on the difference between the wafer pattern and the first sample chip layout includes: The mask generation model is trained based on the difference between the wafer pattern and the first sample chip layout, and the difference between the level set of the first predicted mask and the level set of the first sample mask.

9. The method according to claim 8, characterized in that The training of the mask generation model based on the difference between the wafer pattern and the first sample chip layout, and the difference between the level set of the first predicted mask and the level set of the first sample mask, comprises: Determining a first loss value based on a difference between the wafer pattern and the first sample chip layout; determining a second loss value based on a difference between a level set of the first prediction mask and a level set of the first sample mask; Performing a weighted summation of the first loss value and the second loss value to obtain a third loss value; Based on the third loss value, the mask generation model is trained so that the third loss value obtained based on the trained mask generation model is reduced.

10. The method according to claim 8, characterized in that The step of obtaining a level set of a first sample mask includes: Determining the level set of the first sample chip layout as a reference level set; The following iterative process is performed on the reference level set: a reference mask is determined based on the reference level set, and a reference wafer pattern obtained by photolithography using the reference mask is determined; based on the difference between the reference wafer pattern and the first sample chip layout, the reference level set is adjusted so that the difference between the reference wafer pattern obtained based on the adjusted reference level set and the first sample chip layout is reduced; In response to the iteration process satisfying an iteration end condition, the iteration process is stopped to obtain a level set of the first sample mask.

11. The method according to claim 10, characterized in that The step of adjusting the reference level set based on the difference between the reference wafer pattern and the first sample chip layout so as to reduce the difference between the reference wafer pattern obtained based on the adjusted reference level set and the first sample chip layout comprises: determining a fourth loss value based on a difference between the reference wafer pattern and the first sample chip layout; Based on the fourth loss value, the reference level set is adjusted so that a fourth loss value obtained based on the adjusted reference level set is reduced.

12. The method according to any one of claims 1 to 11, characterized in that: The mask generation model is a pre-trained model, and the pre-training process of the mask generation model includes: Obtaining a level set of a second sample chip layout and a level set of a second sample mask, wherein the second sample mask is used to obtain a wafer pattern consistent with the second sample chip layout by photolithography, the level set of the second sample chip layout represents the contour of the pattern in the second sample chip layout, and the level set of the second sample mask represents the contour of the pattern in the second sample mask; Inputting the level set of the second sample chip layout into the mask generation model to obtain the level set of the second prediction mask output by the mask generation model, wherein the level set of the second prediction mask represents the contour of the pattern in the second prediction mask; The mask generation model is pre-trained based on a difference between a level set of the second prediction mask and a level set of the second sample mask.

13. The method according to any one of claims 1 to 11, characterized in that: After training the mask generation model based on the difference between the wafer pattern and the first sample chip layout, the method further includes: Obtaining a level set of the target chip layout; Inputting the level set of the target chip layout into the trained mask generation model to obtain the level set of the target mask output by the mask generation model; The target mask is determined based on the level set of the target mask, and the target mask is used to obtain a wafer pattern consistent with the target chip layout through photolithography.

14. A training device for a mask generation model, characterized in that: The device comprises: A first acquisition module is used to acquire a first sample chip layout and a level set of the first sample chip layout, wherein the level set of the first sample chip layout represents a contour line of a pattern in the first sample chip layout; A level set generation module, used for inputting the level set of the first sample chip layout into a mask generation model to obtain a level set of a first prediction mask output by the mask generation model, wherein the level set of the first prediction mask represents a contour line of a pattern in the first prediction mask; a mask determination module, configured to determine the first prediction mask based on the level set of the first prediction mask; A wafer pattern determination module, used to determine a wafer pattern obtained by photolithography using the first prediction mask; The first training module is used to train the mask generation model based on the difference between the wafer pattern and the first sample chip layout.

15. A computer device, characterized in that: The computer device includes a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the training method for the mask generation model according to any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the training method for the mask generation model according to any one of claims 1 to 13.

17. A computer program product comprising a computer program, characterized in that The computer program is loaded and executed by a processor to implement the operations performed by the training method for a mask generation model according to any one of claims 1 to 13.

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